Change _U to _u as _U exists in ctype.h
diff --git a/src/host/pico_platform/include/hardware/platform_defs.h b/src/host/pico_platform/include/hardware/platform_defs.h
index c1451be..6d0aa84 100644
--- a/src/host/pico_platform/include/hardware/platform_defs.h
+++ b/src/host/pico_platform/include/hardware/platform_defs.h
@@ -21,8 +21,8 @@
#define NUM_SPIN_LOCKS 32u
-#ifndef _U
-#define _U(x) x ## u
+#ifndef _u
+#define _u(x) x ## u
#endif
#endif
diff --git a/src/rp2040/hardware_regs/include/hardware/platform_defs.h b/src/rp2040/hardware_regs/include/hardware/platform_defs.h
index 9d503fe..d88a566 100644
--- a/src/rp2040/hardware_regs/include/hardware/platform_defs.h
+++ b/src/rp2040/hardware_regs/include/hardware/platform_defs.h
@@ -9,8 +9,6 @@
// This header is included from C and assembler - only define macros
-#include "hardware/regs/addressmap.h"
-
#define NUM_CORES 2u
#define NUM_DMA_CHANNELS 12u
#define NUM_IRQS 32u
@@ -40,11 +38,11 @@
#define PICO_NO_RAM_VECTOR_TABLE 0
#endif
-#ifndef _U
+#ifndef _u
#ifdef __ASSEMBLER__
-#define _U(x) x
+#define _u(x) x
#else
-#define _U(x) x ## u
+#define _u(x) x ## u
#endif
#endif
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/adc.h b/src/rp2040/hardware_regs/include/hardware/regs/adc.h
index 03da29e..47510be 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/adc.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/adc.h
@@ -14,9 +14,9 @@
// =============================================================================
// Register : ADC_CS
// Description : ADC Control and Status
-#define ADC_CS_OFFSET _U(0x00000000)
-#define ADC_CS_BITS _U(0x001f770f)
-#define ADC_CS_RESET _U(0x00000000)
+#define ADC_CS_OFFSET _u(0x00000000)
+#define ADC_CS_BITS _u(0x001f770f)
+#define ADC_CS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_CS_RROBIN
// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to
@@ -27,202 +27,202 @@
// indicated by AINSEL.
// AINSEL will be updated after each conversion with the
// newly-selected channel.
-#define ADC_CS_RROBIN_RESET _U(0x00)
-#define ADC_CS_RROBIN_BITS _U(0x001f0000)
-#define ADC_CS_RROBIN_MSB _U(20)
-#define ADC_CS_RROBIN_LSB _U(16)
+#define ADC_CS_RROBIN_RESET _u(0x00)
+#define ADC_CS_RROBIN_BITS _u(0x001f0000)
+#define ADC_CS_RROBIN_MSB _u(20)
+#define ADC_CS_RROBIN_LSB _u(16)
#define ADC_CS_RROBIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_AINSEL
// Description : Select analog mux input. Updated automatically in round-robin
// mode.
-#define ADC_CS_AINSEL_RESET _U(0x0)
-#define ADC_CS_AINSEL_BITS _U(0x00007000)
-#define ADC_CS_AINSEL_MSB _U(14)
-#define ADC_CS_AINSEL_LSB _U(12)
+#define ADC_CS_AINSEL_RESET _u(0x0)
+#define ADC_CS_AINSEL_BITS _u(0x00007000)
+#define ADC_CS_AINSEL_MSB _u(14)
+#define ADC_CS_AINSEL_LSB _u(12)
#define ADC_CS_AINSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_ERR_STICKY
// Description : Some past ADC conversion encountered an error. Write 1 to
// clear.
-#define ADC_CS_ERR_STICKY_RESET _U(0x0)
-#define ADC_CS_ERR_STICKY_BITS _U(0x00000400)
-#define ADC_CS_ERR_STICKY_MSB _U(10)
-#define ADC_CS_ERR_STICKY_LSB _U(10)
+#define ADC_CS_ERR_STICKY_RESET _u(0x0)
+#define ADC_CS_ERR_STICKY_BITS _u(0x00000400)
+#define ADC_CS_ERR_STICKY_MSB _u(10)
+#define ADC_CS_ERR_STICKY_LSB _u(10)
#define ADC_CS_ERR_STICKY_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_CS_ERR
// Description : The most recent ADC conversion encountered an error; result is
// undefined or noisy.
-#define ADC_CS_ERR_RESET _U(0x0)
-#define ADC_CS_ERR_BITS _U(0x00000200)
-#define ADC_CS_ERR_MSB _U(9)
-#define ADC_CS_ERR_LSB _U(9)
+#define ADC_CS_ERR_RESET _u(0x0)
+#define ADC_CS_ERR_BITS _u(0x00000200)
+#define ADC_CS_ERR_MSB _u(9)
+#define ADC_CS_ERR_LSB _u(9)
#define ADC_CS_ERR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_CS_READY
// Description : 1 if the ADC is ready to start a new conversion. Implies any
// previous conversion has completed.
// 0 whilst conversion in progress.
-#define ADC_CS_READY_RESET _U(0x0)
-#define ADC_CS_READY_BITS _U(0x00000100)
-#define ADC_CS_READY_MSB _U(8)
-#define ADC_CS_READY_LSB _U(8)
+#define ADC_CS_READY_RESET _u(0x0)
+#define ADC_CS_READY_BITS _u(0x00000100)
+#define ADC_CS_READY_MSB _u(8)
+#define ADC_CS_READY_LSB _u(8)
#define ADC_CS_READY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_CS_START_MANY
// Description : Continuously perform conversions whilst this bit is 1. A new
// conversion will start immediately after the previous finishes.
-#define ADC_CS_START_MANY_RESET _U(0x0)
-#define ADC_CS_START_MANY_BITS _U(0x00000008)
-#define ADC_CS_START_MANY_MSB _U(3)
-#define ADC_CS_START_MANY_LSB _U(3)
+#define ADC_CS_START_MANY_RESET _u(0x0)
+#define ADC_CS_START_MANY_BITS _u(0x00000008)
+#define ADC_CS_START_MANY_MSB _u(3)
+#define ADC_CS_START_MANY_LSB _u(3)
#define ADC_CS_START_MANY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_START_ONCE
// Description : Start a single conversion. Self-clearing. Ignored if start_many
// is asserted.
-#define ADC_CS_START_ONCE_RESET _U(0x0)
-#define ADC_CS_START_ONCE_BITS _U(0x00000004)
-#define ADC_CS_START_ONCE_MSB _U(2)
-#define ADC_CS_START_ONCE_LSB _U(2)
+#define ADC_CS_START_ONCE_RESET _u(0x0)
+#define ADC_CS_START_ONCE_BITS _u(0x00000004)
+#define ADC_CS_START_ONCE_MSB _u(2)
+#define ADC_CS_START_ONCE_LSB _u(2)
#define ADC_CS_START_ONCE_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : ADC_CS_TS_EN
// Description : Power on temperature sensor. 1 - enabled. 0 - disabled.
-#define ADC_CS_TS_EN_RESET _U(0x0)
-#define ADC_CS_TS_EN_BITS _U(0x00000002)
-#define ADC_CS_TS_EN_MSB _U(1)
-#define ADC_CS_TS_EN_LSB _U(1)
+#define ADC_CS_TS_EN_RESET _u(0x0)
+#define ADC_CS_TS_EN_BITS _u(0x00000002)
+#define ADC_CS_TS_EN_MSB _u(1)
+#define ADC_CS_TS_EN_LSB _u(1)
#define ADC_CS_TS_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_EN
// Description : Power on ADC and enable its clock.
// 1 - enabled. 0 - disabled.
-#define ADC_CS_EN_RESET _U(0x0)
-#define ADC_CS_EN_BITS _U(0x00000001)
-#define ADC_CS_EN_MSB _U(0)
-#define ADC_CS_EN_LSB _U(0)
+#define ADC_CS_EN_RESET _u(0x0)
+#define ADC_CS_EN_BITS _u(0x00000001)
+#define ADC_CS_EN_MSB _u(0)
+#define ADC_CS_EN_LSB _u(0)
#define ADC_CS_EN_ACCESS "RW"
// =============================================================================
// Register : ADC_RESULT
// Description : Result of most recent ADC conversion
-#define ADC_RESULT_OFFSET _U(0x00000004)
-#define ADC_RESULT_BITS _U(0x00000fff)
-#define ADC_RESULT_RESET _U(0x00000000)
-#define ADC_RESULT_MSB _U(11)
-#define ADC_RESULT_LSB _U(0)
+#define ADC_RESULT_OFFSET _u(0x00000004)
+#define ADC_RESULT_BITS _u(0x00000fff)
+#define ADC_RESULT_RESET _u(0x00000000)
+#define ADC_RESULT_MSB _u(11)
+#define ADC_RESULT_LSB _u(0)
#define ADC_RESULT_ACCESS "RO"
// =============================================================================
// Register : ADC_FCS
// Description : FIFO control and status
-#define ADC_FCS_OFFSET _U(0x00000008)
-#define ADC_FCS_BITS _U(0x0f0f0f0f)
-#define ADC_FCS_RESET _U(0x00000000)
+#define ADC_FCS_OFFSET _u(0x00000008)
+#define ADC_FCS_BITS _u(0x0f0f0f0f)
+#define ADC_FCS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_FCS_THRESH
// Description : DREQ/IRQ asserted when level >= threshold
-#define ADC_FCS_THRESH_RESET _U(0x0)
-#define ADC_FCS_THRESH_BITS _U(0x0f000000)
-#define ADC_FCS_THRESH_MSB _U(27)
-#define ADC_FCS_THRESH_LSB _U(24)
+#define ADC_FCS_THRESH_RESET _u(0x0)
+#define ADC_FCS_THRESH_BITS _u(0x0f000000)
+#define ADC_FCS_THRESH_MSB _u(27)
+#define ADC_FCS_THRESH_LSB _u(24)
#define ADC_FCS_THRESH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_LEVEL
// Description : The number of conversion results currently waiting in the FIFO
-#define ADC_FCS_LEVEL_RESET _U(0x0)
-#define ADC_FCS_LEVEL_BITS _U(0x000f0000)
-#define ADC_FCS_LEVEL_MSB _U(19)
-#define ADC_FCS_LEVEL_LSB _U(16)
+#define ADC_FCS_LEVEL_RESET _u(0x0)
+#define ADC_FCS_LEVEL_BITS _u(0x000f0000)
+#define ADC_FCS_LEVEL_MSB _u(19)
+#define ADC_FCS_LEVEL_LSB _u(16)
#define ADC_FCS_LEVEL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_OVER
// Description : 1 if the FIFO has been overflowed. Write 1 to clear.
-#define ADC_FCS_OVER_RESET _U(0x0)
-#define ADC_FCS_OVER_BITS _U(0x00000800)
-#define ADC_FCS_OVER_MSB _U(11)
-#define ADC_FCS_OVER_LSB _U(11)
+#define ADC_FCS_OVER_RESET _u(0x0)
+#define ADC_FCS_OVER_BITS _u(0x00000800)
+#define ADC_FCS_OVER_MSB _u(11)
+#define ADC_FCS_OVER_LSB _u(11)
#define ADC_FCS_OVER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_UNDER
// Description : 1 if the FIFO has been underflowed. Write 1 to clear.
-#define ADC_FCS_UNDER_RESET _U(0x0)
-#define ADC_FCS_UNDER_BITS _U(0x00000400)
-#define ADC_FCS_UNDER_MSB _U(10)
-#define ADC_FCS_UNDER_LSB _U(10)
+#define ADC_FCS_UNDER_RESET _u(0x0)
+#define ADC_FCS_UNDER_BITS _u(0x00000400)
+#define ADC_FCS_UNDER_MSB _u(10)
+#define ADC_FCS_UNDER_LSB _u(10)
#define ADC_FCS_UNDER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_FULL
// Description : None
-#define ADC_FCS_FULL_RESET _U(0x0)
-#define ADC_FCS_FULL_BITS _U(0x00000200)
-#define ADC_FCS_FULL_MSB _U(9)
-#define ADC_FCS_FULL_LSB _U(9)
+#define ADC_FCS_FULL_RESET _u(0x0)
+#define ADC_FCS_FULL_BITS _u(0x00000200)
+#define ADC_FCS_FULL_MSB _u(9)
+#define ADC_FCS_FULL_LSB _u(9)
#define ADC_FCS_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_EMPTY
// Description : None
-#define ADC_FCS_EMPTY_RESET _U(0x0)
-#define ADC_FCS_EMPTY_BITS _U(0x00000100)
-#define ADC_FCS_EMPTY_MSB _U(8)
-#define ADC_FCS_EMPTY_LSB _U(8)
+#define ADC_FCS_EMPTY_RESET _u(0x0)
+#define ADC_FCS_EMPTY_BITS _u(0x00000100)
+#define ADC_FCS_EMPTY_MSB _u(8)
+#define ADC_FCS_EMPTY_LSB _u(8)
#define ADC_FCS_EMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_DREQ_EN
// Description : If 1: assert DMA requests when FIFO contains data
-#define ADC_FCS_DREQ_EN_RESET _U(0x0)
-#define ADC_FCS_DREQ_EN_BITS _U(0x00000008)
-#define ADC_FCS_DREQ_EN_MSB _U(3)
-#define ADC_FCS_DREQ_EN_LSB _U(3)
+#define ADC_FCS_DREQ_EN_RESET _u(0x0)
+#define ADC_FCS_DREQ_EN_BITS _u(0x00000008)
+#define ADC_FCS_DREQ_EN_MSB _u(3)
+#define ADC_FCS_DREQ_EN_LSB _u(3)
#define ADC_FCS_DREQ_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_ERR
// Description : If 1: conversion error bit appears in the FIFO alongside the
// result
-#define ADC_FCS_ERR_RESET _U(0x0)
-#define ADC_FCS_ERR_BITS _U(0x00000004)
-#define ADC_FCS_ERR_MSB _U(2)
-#define ADC_FCS_ERR_LSB _U(2)
+#define ADC_FCS_ERR_RESET _u(0x0)
+#define ADC_FCS_ERR_BITS _u(0x00000004)
+#define ADC_FCS_ERR_MSB _u(2)
+#define ADC_FCS_ERR_LSB _u(2)
#define ADC_FCS_ERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_SHIFT
// Description : If 1: FIFO results are right-shifted to be one byte in size.
// Enables DMA to byte buffers.
-#define ADC_FCS_SHIFT_RESET _U(0x0)
-#define ADC_FCS_SHIFT_BITS _U(0x00000002)
-#define ADC_FCS_SHIFT_MSB _U(1)
-#define ADC_FCS_SHIFT_LSB _U(1)
+#define ADC_FCS_SHIFT_RESET _u(0x0)
+#define ADC_FCS_SHIFT_BITS _u(0x00000002)
+#define ADC_FCS_SHIFT_MSB _u(1)
+#define ADC_FCS_SHIFT_LSB _u(1)
#define ADC_FCS_SHIFT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_EN
// Description : If 1: write result to the FIFO after each conversion.
-#define ADC_FCS_EN_RESET _U(0x0)
-#define ADC_FCS_EN_BITS _U(0x00000001)
-#define ADC_FCS_EN_MSB _U(0)
-#define ADC_FCS_EN_LSB _U(0)
+#define ADC_FCS_EN_RESET _u(0x0)
+#define ADC_FCS_EN_BITS _u(0x00000001)
+#define ADC_FCS_EN_MSB _u(0)
+#define ADC_FCS_EN_LSB _u(0)
#define ADC_FCS_EN_ACCESS "RW"
// =============================================================================
// Register : ADC_FIFO
// Description : Conversion result FIFO
-#define ADC_FIFO_OFFSET _U(0x0000000c)
-#define ADC_FIFO_BITS _U(0x00008fff)
-#define ADC_FIFO_RESET _U(0x00000000)
+#define ADC_FIFO_OFFSET _u(0x0000000c)
+#define ADC_FIFO_BITS _u(0x00008fff)
+#define ADC_FIFO_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_FIFO_ERR
// Description : 1 if this particular sample experienced a conversion error.
// Remains in the same location if the sample is shifted.
#define ADC_FIFO_ERR_RESET "-"
-#define ADC_FIFO_ERR_BITS _U(0x00008000)
-#define ADC_FIFO_ERR_MSB _U(15)
-#define ADC_FIFO_ERR_LSB _U(15)
+#define ADC_FIFO_ERR_BITS _u(0x00008000)
+#define ADC_FIFO_ERR_MSB _u(15)
+#define ADC_FIFO_ERR_LSB _u(15)
#define ADC_FIFO_ERR_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : ADC_FIFO_VAL
// Description : None
#define ADC_FIFO_VAL_RESET "-"
-#define ADC_FIFO_VAL_BITS _U(0x00000fff)
-#define ADC_FIFO_VAL_MSB _U(11)
-#define ADC_FIFO_VAL_LSB _U(0)
+#define ADC_FIFO_VAL_BITS _u(0x00000fff)
+#define ADC_FIFO_VAL_MSB _u(11)
+#define ADC_FIFO_VAL_LSB _u(0)
#define ADC_FIFO_VAL_ACCESS "RF"
// =============================================================================
// Register : ADC_DIV
@@ -231,84 +231,84 @@
// at regular intervals rather than back-to-back.
// The divider is reset when either of these fields are written.
// Total period is 1 + INT + FRAC / 256
-#define ADC_DIV_OFFSET _U(0x00000010)
-#define ADC_DIV_BITS _U(0x00ffffff)
-#define ADC_DIV_RESET _U(0x00000000)
+#define ADC_DIV_OFFSET _u(0x00000010)
+#define ADC_DIV_BITS _u(0x00ffffff)
+#define ADC_DIV_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_DIV_INT
// Description : Integer part of clock divisor.
-#define ADC_DIV_INT_RESET _U(0x0000)
-#define ADC_DIV_INT_BITS _U(0x00ffff00)
-#define ADC_DIV_INT_MSB _U(23)
-#define ADC_DIV_INT_LSB _U(8)
+#define ADC_DIV_INT_RESET _u(0x0000)
+#define ADC_DIV_INT_BITS _u(0x00ffff00)
+#define ADC_DIV_INT_MSB _u(23)
+#define ADC_DIV_INT_LSB _u(8)
#define ADC_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_DIV_FRAC
// Description : Fractional part of clock divisor. First-order delta-sigma.
-#define ADC_DIV_FRAC_RESET _U(0x00)
-#define ADC_DIV_FRAC_BITS _U(0x000000ff)
-#define ADC_DIV_FRAC_MSB _U(7)
-#define ADC_DIV_FRAC_LSB _U(0)
+#define ADC_DIV_FRAC_RESET _u(0x00)
+#define ADC_DIV_FRAC_BITS _u(0x000000ff)
+#define ADC_DIV_FRAC_MSB _u(7)
+#define ADC_DIV_FRAC_LSB _u(0)
#define ADC_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : ADC_INTR
// Description : Raw Interrupts
-#define ADC_INTR_OFFSET _U(0x00000014)
-#define ADC_INTR_BITS _U(0x00000001)
-#define ADC_INTR_RESET _U(0x00000000)
+#define ADC_INTR_OFFSET _u(0x00000014)
+#define ADC_INTR_BITS _u(0x00000001)
+#define ADC_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTR_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
-#define ADC_INTR_FIFO_RESET _U(0x0)
-#define ADC_INTR_FIFO_BITS _U(0x00000001)
-#define ADC_INTR_FIFO_MSB _U(0)
-#define ADC_INTR_FIFO_LSB _U(0)
+#define ADC_INTR_FIFO_RESET _u(0x0)
+#define ADC_INTR_FIFO_BITS _u(0x00000001)
+#define ADC_INTR_FIFO_MSB _u(0)
+#define ADC_INTR_FIFO_LSB _u(0)
#define ADC_INTR_FIFO_ACCESS "RO"
// =============================================================================
// Register : ADC_INTE
// Description : Interrupt Enable
-#define ADC_INTE_OFFSET _U(0x00000018)
-#define ADC_INTE_BITS _U(0x00000001)
-#define ADC_INTE_RESET _U(0x00000000)
+#define ADC_INTE_OFFSET _u(0x00000018)
+#define ADC_INTE_BITS _u(0x00000001)
+#define ADC_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTE_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
-#define ADC_INTE_FIFO_RESET _U(0x0)
-#define ADC_INTE_FIFO_BITS _U(0x00000001)
-#define ADC_INTE_FIFO_MSB _U(0)
-#define ADC_INTE_FIFO_LSB _U(0)
+#define ADC_INTE_FIFO_RESET _u(0x0)
+#define ADC_INTE_FIFO_BITS _u(0x00000001)
+#define ADC_INTE_FIFO_MSB _u(0)
+#define ADC_INTE_FIFO_LSB _u(0)
#define ADC_INTE_FIFO_ACCESS "RW"
// =============================================================================
// Register : ADC_INTF
// Description : Interrupt Force
-#define ADC_INTF_OFFSET _U(0x0000001c)
-#define ADC_INTF_BITS _U(0x00000001)
-#define ADC_INTF_RESET _U(0x00000000)
+#define ADC_INTF_OFFSET _u(0x0000001c)
+#define ADC_INTF_BITS _u(0x00000001)
+#define ADC_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTF_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
-#define ADC_INTF_FIFO_RESET _U(0x0)
-#define ADC_INTF_FIFO_BITS _U(0x00000001)
-#define ADC_INTF_FIFO_MSB _U(0)
-#define ADC_INTF_FIFO_LSB _U(0)
+#define ADC_INTF_FIFO_RESET _u(0x0)
+#define ADC_INTF_FIFO_BITS _u(0x00000001)
+#define ADC_INTF_FIFO_MSB _u(0)
+#define ADC_INTF_FIFO_LSB _u(0)
#define ADC_INTF_FIFO_ACCESS "RW"
// =============================================================================
// Register : ADC_INTS
// Description : Interrupt status after masking & forcing
-#define ADC_INTS_OFFSET _U(0x00000020)
-#define ADC_INTS_BITS _U(0x00000001)
-#define ADC_INTS_RESET _U(0x00000000)
+#define ADC_INTS_OFFSET _u(0x00000020)
+#define ADC_INTS_BITS _u(0x00000001)
+#define ADC_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTS_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
-#define ADC_INTS_FIFO_RESET _U(0x0)
-#define ADC_INTS_FIFO_BITS _U(0x00000001)
-#define ADC_INTS_FIFO_MSB _U(0)
-#define ADC_INTS_FIFO_LSB _U(0)
+#define ADC_INTS_FIFO_RESET _u(0x0)
+#define ADC_INTS_FIFO_BITS _u(0x00000001)
+#define ADC_INTS_FIFO_MSB _u(0)
+#define ADC_INTS_FIFO_LSB _u(0)
#define ADC_INTS_FIFO_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_ADC_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/addressmap.h b/src/rp2040/hardware_regs/include/hardware/regs/addressmap.h
index 68ff037..b39ab45 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/addressmap.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/addressmap.h
@@ -6,67 +6,69 @@
#ifndef _ADDRESSMAP_H_
#define _ADDRESSMAP_H_
+#include "hardware/platform_defs.h"
+
// Register address offsets for atomic RMW aliases
#define REG_ALIAS_RW_BITS (0x0u << 12u)
#define REG_ALIAS_XOR_BITS (0x1u << 12u)
#define REG_ALIAS_SET_BITS (0x2u << 12u)
#define REG_ALIAS_CLR_BITS (0x3u << 12u)
-#define ROM_BASE _U(0x00000000)
-#define XIP_BASE _U(0x10000000)
-#define XIP_MAIN_BASE _U(0x10000000)
-#define XIP_NOALLOC_BASE _U(0x11000000)
-#define XIP_NOCACHE_BASE _U(0x12000000)
-#define XIP_NOCACHE_NOALLOC_BASE _U(0x13000000)
-#define XIP_CTRL_BASE _U(0x14000000)
-#define XIP_SRAM_BASE _U(0x15000000)
-#define XIP_SRAM_END _U(0x15004000)
-#define XIP_SSI_BASE _U(0x18000000)
-#define SRAM_BASE _U(0x20000000)
-#define SRAM_STRIPED_BASE _U(0x20000000)
-#define SRAM_STRIPED_END _U(0x20040000)
-#define SRAM4_BASE _U(0x20040000)
-#define SRAM5_BASE _U(0x20041000)
-#define SRAM_END _U(0x20042000)
-#define SRAM0_BASE _U(0x21000000)
-#define SRAM1_BASE _U(0x21010000)
-#define SRAM2_BASE _U(0x21020000)
-#define SRAM3_BASE _U(0x21030000)
-#define SYSINFO_BASE _U(0x40000000)
-#define SYSCFG_BASE _U(0x40004000)
-#define CLOCKS_BASE _U(0x40008000)
-#define RESETS_BASE _U(0x4000c000)
-#define PSM_BASE _U(0x40010000)
-#define IO_BANK0_BASE _U(0x40014000)
-#define IO_QSPI_BASE _U(0x40018000)
-#define PADS_BANK0_BASE _U(0x4001c000)
-#define PADS_QSPI_BASE _U(0x40020000)
-#define XOSC_BASE _U(0x40024000)
-#define PLL_SYS_BASE _U(0x40028000)
-#define PLL_USB_BASE _U(0x4002c000)
-#define BUSCTRL_BASE _U(0x40030000)
-#define UART0_BASE _U(0x40034000)
-#define UART1_BASE _U(0x40038000)
-#define SPI0_BASE _U(0x4003c000)
-#define SPI1_BASE _U(0x40040000)
-#define I2C0_BASE _U(0x40044000)
-#define I2C1_BASE _U(0x40048000)
-#define ADC_BASE _U(0x4004c000)
-#define PWM_BASE _U(0x40050000)
-#define TIMER_BASE _U(0x40054000)
-#define WATCHDOG_BASE _U(0x40058000)
-#define RTC_BASE _U(0x4005c000)
-#define ROSC_BASE _U(0x40060000)
-#define VREG_AND_CHIP_RESET_BASE _U(0x40064000)
-#define TBMAN_BASE _U(0x4006c000)
-#define DMA_BASE _U(0x50000000)
-#define USBCTRL_DPRAM_BASE _U(0x50100000)
-#define USBCTRL_BASE _U(0x50100000)
-#define USBCTRL_REGS_BASE _U(0x50110000)
-#define PIO0_BASE _U(0x50200000)
-#define PIO1_BASE _U(0x50300000)
-#define XIP_AUX_BASE _U(0x50400000)
-#define SIO_BASE _U(0xd0000000)
-#define PPB_BASE _U(0xe0000000)
+#define ROM_BASE _u(0x00000000)
+#define XIP_BASE _u(0x10000000)
+#define XIP_MAIN_BASE _u(0x10000000)
+#define XIP_NOALLOC_BASE _u(0x11000000)
+#define XIP_NOCACHE_BASE _u(0x12000000)
+#define XIP_NOCACHE_NOALLOC_BASE _u(0x13000000)
+#define XIP_CTRL_BASE _u(0x14000000)
+#define XIP_SRAM_BASE _u(0x15000000)
+#define XIP_SRAM_END _u(0x15004000)
+#define XIP_SSI_BASE _u(0x18000000)
+#define SRAM_BASE _u(0x20000000)
+#define SRAM_STRIPED_BASE _u(0x20000000)
+#define SRAM_STRIPED_END _u(0x20040000)
+#define SRAM4_BASE _u(0x20040000)
+#define SRAM5_BASE _u(0x20041000)
+#define SRAM_END _u(0x20042000)
+#define SRAM0_BASE _u(0x21000000)
+#define SRAM1_BASE _u(0x21010000)
+#define SRAM2_BASE _u(0x21020000)
+#define SRAM3_BASE _u(0x21030000)
+#define SYSINFO_BASE _u(0x40000000)
+#define SYSCFG_BASE _u(0x40004000)
+#define CLOCKS_BASE _u(0x40008000)
+#define RESETS_BASE _u(0x4000c000)
+#define PSM_BASE _u(0x40010000)
+#define IO_BANK0_BASE _u(0x40014000)
+#define IO_QSPI_BASE _u(0x40018000)
+#define PADS_BANK0_BASE _u(0x4001c000)
+#define PADS_QSPI_BASE _u(0x40020000)
+#define XOSC_BASE _u(0x40024000)
+#define PLL_SYS_BASE _u(0x40028000)
+#define PLL_USB_BASE _u(0x4002c000)
+#define BUSCTRL_BASE _u(0x40030000)
+#define UART0_BASE _u(0x40034000)
+#define UART1_BASE _u(0x40038000)
+#define SPI0_BASE _u(0x4003c000)
+#define SPI1_BASE _u(0x40040000)
+#define I2C0_BASE _u(0x40044000)
+#define I2C1_BASE _u(0x40048000)
+#define ADC_BASE _u(0x4004c000)
+#define PWM_BASE _u(0x40050000)
+#define TIMER_BASE _u(0x40054000)
+#define WATCHDOG_BASE _u(0x40058000)
+#define RTC_BASE _u(0x4005c000)
+#define ROSC_BASE _u(0x40060000)
+#define VREG_AND_CHIP_RESET_BASE _u(0x40064000)
+#define TBMAN_BASE _u(0x4006c000)
+#define DMA_BASE _u(0x50000000)
+#define USBCTRL_DPRAM_BASE _u(0x50100000)
+#define USBCTRL_BASE _u(0x50100000)
+#define USBCTRL_REGS_BASE _u(0x50110000)
+#define PIO0_BASE _u(0x50200000)
+#define PIO1_BASE _u(0x50300000)
+#define XIP_AUX_BASE _u(0x50400000)
+#define SIO_BASE _u(0xd0000000)
+#define PPB_BASE _u(0xe0000000)
#endif // _ADDRESSMAP_H_
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/busctrl.h b/src/rp2040/hardware_regs/include/hardware/regs/busctrl.h
index d94d407..8be0d86 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/busctrl.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/busctrl.h
@@ -15,40 +15,40 @@
// =============================================================================
// Register : BUSCTRL_BUS_PRIORITY
// Description : Set the priority of each master for bus arbitration.
-#define BUSCTRL_BUS_PRIORITY_OFFSET _U(0x00000000)
-#define BUSCTRL_BUS_PRIORITY_BITS _U(0x00001111)
-#define BUSCTRL_BUS_PRIORITY_RESET _U(0x00000000)
+#define BUSCTRL_BUS_PRIORITY_OFFSET _u(0x00000000)
+#define BUSCTRL_BUS_PRIORITY_BITS _u(0x00001111)
+#define BUSCTRL_BUS_PRIORITY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_DMA_W
// Description : 0 - low priority, 1 - high priority
-#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _U(0x0)
-#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _U(0x00001000)
-#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _U(12)
-#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _U(12)
+#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _u(0x0)
+#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _u(0x00001000)
+#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _u(12)
+#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _u(12)
#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_DMA_R
// Description : 0 - low priority, 1 - high priority
-#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _U(0x0)
-#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _U(0x00000100)
-#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _U(8)
-#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _U(8)
+#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _u(0x0)
+#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _u(0x00000100)
+#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _u(8)
+#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _u(8)
#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_PROC1
// Description : 0 - low priority, 1 - high priority
-#define BUSCTRL_BUS_PRIORITY_PROC1_RESET _U(0x0)
-#define BUSCTRL_BUS_PRIORITY_PROC1_BITS _U(0x00000010)
-#define BUSCTRL_BUS_PRIORITY_PROC1_MSB _U(4)
-#define BUSCTRL_BUS_PRIORITY_PROC1_LSB _U(4)
+#define BUSCTRL_BUS_PRIORITY_PROC1_RESET _u(0x0)
+#define BUSCTRL_BUS_PRIORITY_PROC1_BITS _u(0x00000010)
+#define BUSCTRL_BUS_PRIORITY_PROC1_MSB _u(4)
+#define BUSCTRL_BUS_PRIORITY_PROC1_LSB _u(4)
#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_PROC0
// Description : 0 - low priority, 1 - high priority
-#define BUSCTRL_BUS_PRIORITY_PROC0_RESET _U(0x0)
-#define BUSCTRL_BUS_PRIORITY_PROC0_BITS _U(0x00000001)
-#define BUSCTRL_BUS_PRIORITY_PROC0_MSB _U(0)
-#define BUSCTRL_BUS_PRIORITY_PROC0_LSB _U(0)
+#define BUSCTRL_BUS_PRIORITY_PROC0_RESET _u(0x0)
+#define BUSCTRL_BUS_PRIORITY_PROC0_BITS _u(0x00000001)
+#define BUSCTRL_BUS_PRIORITY_PROC0_MSB _u(0)
+#define BUSCTRL_BUS_PRIORITY_PROC0_LSB _u(0)
#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW"
// =============================================================================
// Register : BUSCTRL_BUS_PRIORITY_ACK
@@ -58,11 +58,11 @@
// Arbiters update their local priority when servicing a new
// nonsequential access.
// In normal circumstances this will happen almost immediately.
-#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _U(0x00000004)
-#define BUSCTRL_BUS_PRIORITY_ACK_BITS _U(0x00000001)
-#define BUSCTRL_BUS_PRIORITY_ACK_RESET _U(0x00000000)
-#define BUSCTRL_BUS_PRIORITY_ACK_MSB _U(0)
-#define BUSCTRL_BUS_PRIORITY_ACK_LSB _U(0)
+#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _u(0x00000004)
+#define BUSCTRL_BUS_PRIORITY_ACK_BITS _u(0x00000001)
+#define BUSCTRL_BUS_PRIORITY_ACK_RESET _u(0x00000000)
+#define BUSCTRL_BUS_PRIORITY_ACK_MSB _u(0)
+#define BUSCTRL_BUS_PRIORITY_ACK_LSB _u(0)
#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO"
// =============================================================================
// Register : BUSCTRL_PERFCTR0
@@ -71,11 +71,11 @@
// Count some event signal from the busfabric arbiters.
// Write any value to clear. Select an event to count using
// PERFSEL0
-#define BUSCTRL_PERFCTR0_OFFSET _U(0x00000008)
-#define BUSCTRL_PERFCTR0_BITS _U(0x00ffffff)
-#define BUSCTRL_PERFCTR0_RESET _U(0x00000000)
-#define BUSCTRL_PERFCTR0_MSB _U(23)
-#define BUSCTRL_PERFCTR0_LSB _U(0)
+#define BUSCTRL_PERFCTR0_OFFSET _u(0x00000008)
+#define BUSCTRL_PERFCTR0_BITS _u(0x00ffffff)
+#define BUSCTRL_PERFCTR0_RESET _u(0x00000000)
+#define BUSCTRL_PERFCTR0_MSB _u(23)
+#define BUSCTRL_PERFCTR0_LSB _u(0)
#define BUSCTRL_PERFCTR0_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL0
@@ -102,32 +102,32 @@
// 0x11 -> xip_main
// 0x12 -> rom_contested
// 0x13 -> rom
-#define BUSCTRL_PERFSEL0_OFFSET _U(0x0000000c)
-#define BUSCTRL_PERFSEL0_BITS _U(0x0000001f)
-#define BUSCTRL_PERFSEL0_RESET _U(0x0000001f)
-#define BUSCTRL_PERFSEL0_MSB _U(4)
-#define BUSCTRL_PERFSEL0_LSB _U(0)
+#define BUSCTRL_PERFSEL0_OFFSET _u(0x0000000c)
+#define BUSCTRL_PERFSEL0_BITS _u(0x0000001f)
+#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f)
+#define BUSCTRL_PERFSEL0_MSB _u(4)
+#define BUSCTRL_PERFSEL0_LSB _u(0)
#define BUSCTRL_PERFSEL0_ACCESS "RW"
-#define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED _U(0x00)
-#define BUSCTRL_PERFSEL0_VALUE_APB _U(0x01)
-#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_CONTESTED _U(0x02)
-#define BUSCTRL_PERFSEL0_VALUE_FASTPERI _U(0x03)
-#define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED _U(0x04)
-#define BUSCTRL_PERFSEL0_VALUE_SRAM5 _U(0x05)
-#define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED _U(0x06)
-#define BUSCTRL_PERFSEL0_VALUE_SRAM4 _U(0x07)
-#define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED _U(0x08)
-#define BUSCTRL_PERFSEL0_VALUE_SRAM3 _U(0x09)
-#define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED _U(0x0a)
-#define BUSCTRL_PERFSEL0_VALUE_SRAM2 _U(0x0b)
-#define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED _U(0x0c)
-#define BUSCTRL_PERFSEL0_VALUE_SRAM1 _U(0x0d)
-#define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED _U(0x0e)
-#define BUSCTRL_PERFSEL0_VALUE_SRAM0 _U(0x0f)
-#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN_CONTESTED _U(0x10)
-#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN _U(0x11)
-#define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED _U(0x12)
-#define BUSCTRL_PERFSEL0_VALUE_ROM _U(0x13)
+#define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED _u(0x00)
+#define BUSCTRL_PERFSEL0_VALUE_APB _u(0x01)
+#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_CONTESTED _u(0x02)
+#define BUSCTRL_PERFSEL0_VALUE_FASTPERI _u(0x03)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED _u(0x04)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM5 _u(0x05)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED _u(0x06)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM4 _u(0x07)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED _u(0x08)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM3 _u(0x09)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED _u(0x0a)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM2 _u(0x0b)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED _u(0x0c)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM1 _u(0x0d)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED _u(0x0e)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM0 _u(0x0f)
+#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN_CONTESTED _u(0x10)
+#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN _u(0x11)
+#define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED _u(0x12)
+#define BUSCTRL_PERFSEL0_VALUE_ROM _u(0x13)
// =============================================================================
// Register : BUSCTRL_PERFCTR1
// Description : Bus fabric performance counter 1
@@ -135,11 +135,11 @@
// Count some event signal from the busfabric arbiters.
// Write any value to clear. Select an event to count using
// PERFSEL1
-#define BUSCTRL_PERFCTR1_OFFSET _U(0x00000010)
-#define BUSCTRL_PERFCTR1_BITS _U(0x00ffffff)
-#define BUSCTRL_PERFCTR1_RESET _U(0x00000000)
-#define BUSCTRL_PERFCTR1_MSB _U(23)
-#define BUSCTRL_PERFCTR1_LSB _U(0)
+#define BUSCTRL_PERFCTR1_OFFSET _u(0x00000010)
+#define BUSCTRL_PERFCTR1_BITS _u(0x00ffffff)
+#define BUSCTRL_PERFCTR1_RESET _u(0x00000000)
+#define BUSCTRL_PERFCTR1_MSB _u(23)
+#define BUSCTRL_PERFCTR1_LSB _u(0)
#define BUSCTRL_PERFCTR1_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL1
@@ -166,32 +166,32 @@
// 0x11 -> xip_main
// 0x12 -> rom_contested
// 0x13 -> rom
-#define BUSCTRL_PERFSEL1_OFFSET _U(0x00000014)
-#define BUSCTRL_PERFSEL1_BITS _U(0x0000001f)
-#define BUSCTRL_PERFSEL1_RESET _U(0x0000001f)
-#define BUSCTRL_PERFSEL1_MSB _U(4)
-#define BUSCTRL_PERFSEL1_LSB _U(0)
+#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000014)
+#define BUSCTRL_PERFSEL1_BITS _u(0x0000001f)
+#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f)
+#define BUSCTRL_PERFSEL1_MSB _u(4)
+#define BUSCTRL_PERFSEL1_LSB _u(0)
#define BUSCTRL_PERFSEL1_ACCESS "RW"
-#define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED _U(0x00)
-#define BUSCTRL_PERFSEL1_VALUE_APB _U(0x01)
-#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_CONTESTED _U(0x02)
-#define BUSCTRL_PERFSEL1_VALUE_FASTPERI _U(0x03)
-#define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED _U(0x04)
-#define BUSCTRL_PERFSEL1_VALUE_SRAM5 _U(0x05)
-#define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED _U(0x06)
-#define BUSCTRL_PERFSEL1_VALUE_SRAM4 _U(0x07)
-#define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED _U(0x08)
-#define BUSCTRL_PERFSEL1_VALUE_SRAM3 _U(0x09)
-#define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED _U(0x0a)
-#define BUSCTRL_PERFSEL1_VALUE_SRAM2 _U(0x0b)
-#define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED _U(0x0c)
-#define BUSCTRL_PERFSEL1_VALUE_SRAM1 _U(0x0d)
-#define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED _U(0x0e)
-#define BUSCTRL_PERFSEL1_VALUE_SRAM0 _U(0x0f)
-#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN_CONTESTED _U(0x10)
-#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN _U(0x11)
-#define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED _U(0x12)
-#define BUSCTRL_PERFSEL1_VALUE_ROM _U(0x13)
+#define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED _u(0x00)
+#define BUSCTRL_PERFSEL1_VALUE_APB _u(0x01)
+#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_CONTESTED _u(0x02)
+#define BUSCTRL_PERFSEL1_VALUE_FASTPERI _u(0x03)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED _u(0x04)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM5 _u(0x05)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED _u(0x06)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM4 _u(0x07)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED _u(0x08)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM3 _u(0x09)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED _u(0x0a)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM2 _u(0x0b)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED _u(0x0c)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM1 _u(0x0d)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED _u(0x0e)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM0 _u(0x0f)
+#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN_CONTESTED _u(0x10)
+#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN _u(0x11)
+#define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED _u(0x12)
+#define BUSCTRL_PERFSEL1_VALUE_ROM _u(0x13)
// =============================================================================
// Register : BUSCTRL_PERFCTR2
// Description : Bus fabric performance counter 2
@@ -199,11 +199,11 @@
// Count some event signal from the busfabric arbiters.
// Write any value to clear. Select an event to count using
// PERFSEL2
-#define BUSCTRL_PERFCTR2_OFFSET _U(0x00000018)
-#define BUSCTRL_PERFCTR2_BITS _U(0x00ffffff)
-#define BUSCTRL_PERFCTR2_RESET _U(0x00000000)
-#define BUSCTRL_PERFCTR2_MSB _U(23)
-#define BUSCTRL_PERFCTR2_LSB _U(0)
+#define BUSCTRL_PERFCTR2_OFFSET _u(0x00000018)
+#define BUSCTRL_PERFCTR2_BITS _u(0x00ffffff)
+#define BUSCTRL_PERFCTR2_RESET _u(0x00000000)
+#define BUSCTRL_PERFCTR2_MSB _u(23)
+#define BUSCTRL_PERFCTR2_LSB _u(0)
#define BUSCTRL_PERFCTR2_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL2
@@ -230,32 +230,32 @@
// 0x11 -> xip_main
// 0x12 -> rom_contested
// 0x13 -> rom
-#define BUSCTRL_PERFSEL2_OFFSET _U(0x0000001c)
-#define BUSCTRL_PERFSEL2_BITS _U(0x0000001f)
-#define BUSCTRL_PERFSEL2_RESET _U(0x0000001f)
-#define BUSCTRL_PERFSEL2_MSB _U(4)
-#define BUSCTRL_PERFSEL2_LSB _U(0)
+#define BUSCTRL_PERFSEL2_OFFSET _u(0x0000001c)
+#define BUSCTRL_PERFSEL2_BITS _u(0x0000001f)
+#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f)
+#define BUSCTRL_PERFSEL2_MSB _u(4)
+#define BUSCTRL_PERFSEL2_LSB _u(0)
#define BUSCTRL_PERFSEL2_ACCESS "RW"
-#define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED _U(0x00)
-#define BUSCTRL_PERFSEL2_VALUE_APB _U(0x01)
-#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_CONTESTED _U(0x02)
-#define BUSCTRL_PERFSEL2_VALUE_FASTPERI _U(0x03)
-#define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED _U(0x04)
-#define BUSCTRL_PERFSEL2_VALUE_SRAM5 _U(0x05)
-#define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED _U(0x06)
-#define BUSCTRL_PERFSEL2_VALUE_SRAM4 _U(0x07)
-#define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED _U(0x08)
-#define BUSCTRL_PERFSEL2_VALUE_SRAM3 _U(0x09)
-#define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED _U(0x0a)
-#define BUSCTRL_PERFSEL2_VALUE_SRAM2 _U(0x0b)
-#define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED _U(0x0c)
-#define BUSCTRL_PERFSEL2_VALUE_SRAM1 _U(0x0d)
-#define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED _U(0x0e)
-#define BUSCTRL_PERFSEL2_VALUE_SRAM0 _U(0x0f)
-#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN_CONTESTED _U(0x10)
-#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN _U(0x11)
-#define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED _U(0x12)
-#define BUSCTRL_PERFSEL2_VALUE_ROM _U(0x13)
+#define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED _u(0x00)
+#define BUSCTRL_PERFSEL2_VALUE_APB _u(0x01)
+#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_CONTESTED _u(0x02)
+#define BUSCTRL_PERFSEL2_VALUE_FASTPERI _u(0x03)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED _u(0x04)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM5 _u(0x05)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED _u(0x06)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM4 _u(0x07)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED _u(0x08)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM3 _u(0x09)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED _u(0x0a)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM2 _u(0x0b)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED _u(0x0c)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM1 _u(0x0d)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED _u(0x0e)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM0 _u(0x0f)
+#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN_CONTESTED _u(0x10)
+#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN _u(0x11)
+#define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED _u(0x12)
+#define BUSCTRL_PERFSEL2_VALUE_ROM _u(0x13)
// =============================================================================
// Register : BUSCTRL_PERFCTR3
// Description : Bus fabric performance counter 3
@@ -263,11 +263,11 @@
// Count some event signal from the busfabric arbiters.
// Write any value to clear. Select an event to count using
// PERFSEL3
-#define BUSCTRL_PERFCTR3_OFFSET _U(0x00000020)
-#define BUSCTRL_PERFCTR3_BITS _U(0x00ffffff)
-#define BUSCTRL_PERFCTR3_RESET _U(0x00000000)
-#define BUSCTRL_PERFCTR3_MSB _U(23)
-#define BUSCTRL_PERFCTR3_LSB _U(0)
+#define BUSCTRL_PERFCTR3_OFFSET _u(0x00000020)
+#define BUSCTRL_PERFCTR3_BITS _u(0x00ffffff)
+#define BUSCTRL_PERFCTR3_RESET _u(0x00000000)
+#define BUSCTRL_PERFCTR3_MSB _u(23)
+#define BUSCTRL_PERFCTR3_LSB _u(0)
#define BUSCTRL_PERFCTR3_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL3
@@ -294,31 +294,31 @@
// 0x11 -> xip_main
// 0x12 -> rom_contested
// 0x13 -> rom
-#define BUSCTRL_PERFSEL3_OFFSET _U(0x00000024)
-#define BUSCTRL_PERFSEL3_BITS _U(0x0000001f)
-#define BUSCTRL_PERFSEL3_RESET _U(0x0000001f)
-#define BUSCTRL_PERFSEL3_MSB _U(4)
-#define BUSCTRL_PERFSEL3_LSB _U(0)
+#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000024)
+#define BUSCTRL_PERFSEL3_BITS _u(0x0000001f)
+#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f)
+#define BUSCTRL_PERFSEL3_MSB _u(4)
+#define BUSCTRL_PERFSEL3_LSB _u(0)
#define BUSCTRL_PERFSEL3_ACCESS "RW"
-#define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED _U(0x00)
-#define BUSCTRL_PERFSEL3_VALUE_APB _U(0x01)
-#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_CONTESTED _U(0x02)
-#define BUSCTRL_PERFSEL3_VALUE_FASTPERI _U(0x03)
-#define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED _U(0x04)
-#define BUSCTRL_PERFSEL3_VALUE_SRAM5 _U(0x05)
-#define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED _U(0x06)
-#define BUSCTRL_PERFSEL3_VALUE_SRAM4 _U(0x07)
-#define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED _U(0x08)
-#define BUSCTRL_PERFSEL3_VALUE_SRAM3 _U(0x09)
-#define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED _U(0x0a)
-#define BUSCTRL_PERFSEL3_VALUE_SRAM2 _U(0x0b)
-#define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED _U(0x0c)
-#define BUSCTRL_PERFSEL3_VALUE_SRAM1 _U(0x0d)
-#define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED _U(0x0e)
-#define BUSCTRL_PERFSEL3_VALUE_SRAM0 _U(0x0f)
-#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN_CONTESTED _U(0x10)
-#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN _U(0x11)
-#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED _U(0x12)
-#define BUSCTRL_PERFSEL3_VALUE_ROM _U(0x13)
+#define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED _u(0x00)
+#define BUSCTRL_PERFSEL3_VALUE_APB _u(0x01)
+#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_CONTESTED _u(0x02)
+#define BUSCTRL_PERFSEL3_VALUE_FASTPERI _u(0x03)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED _u(0x04)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM5 _u(0x05)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED _u(0x06)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM4 _u(0x07)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED _u(0x08)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM3 _u(0x09)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED _u(0x0a)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM2 _u(0x0b)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED _u(0x0c)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM1 _u(0x0d)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED _u(0x0e)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM0 _u(0x0f)
+#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN_CONTESTED _u(0x10)
+#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN _u(0x11)
+#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED _u(0x12)
+#define BUSCTRL_PERFSEL3_VALUE_ROM _u(0x13)
// =============================================================================
#endif // HARDWARE_REGS_BUSCTRL_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/clocks.h b/src/rp2040/hardware_regs/include/hardware/regs/clocks.h
index 353e187..c0d2eab 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/clocks.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/clocks.h
@@ -14,52 +14,52 @@
// =============================================================================
// Register : CLOCKS_CLK_GPOUT0_CTRL
// Description : Clock control, can be changed on-the-fly (except for auxsrc)
-#define CLOCKS_CLK_GPOUT0_CTRL_OFFSET _U(0x00000000)
-#define CLOCKS_CLK_GPOUT0_CTRL_BITS _U(0x00131de0)
-#define CLOCKS_CLK_GPOUT0_CTRL_RESET _U(0x00000000)
+#define CLOCKS_CLK_GPOUT0_CTRL_OFFSET _u(0x00000000)
+#define CLOCKS_CLK_GPOUT0_CTRL_BITS _u(0x00131de0)
+#define CLOCKS_CLK_GPOUT0_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT0_CTRL_NUDGE
// Description : An edge on this signal shifts the phase of the output by 1
// cycle of the input clock
// This can be done at any time
-#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS _U(0x00100000)
-#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB _U(20)
-#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_LSB _U(20)
+#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS _u(0x00100000)
+#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB _u(20)
+#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_LSB _u(20)
#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT0_CTRL_PHASE
// Description : This delays the enable signal by up to 3 cycles of the input
// clock
// This must be set before the clock is enabled to have any effect
-#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_BITS _U(0x00030000)
-#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_MSB _U(17)
-#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_LSB _U(16)
+#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_BITS _u(0x00030000)
+#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_MSB _u(17)
+#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_LSB _u(16)
#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT0_CTRL_DC50
// Description : Enables duty cycle correction for odd divisors
-#define CLOCKS_CLK_GPOUT0_CTRL_DC50_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT0_CTRL_DC50_BITS _U(0x00001000)
-#define CLOCKS_CLK_GPOUT0_CTRL_DC50_MSB _U(12)
-#define CLOCKS_CLK_GPOUT0_CTRL_DC50_LSB _U(12)
+#define CLOCKS_CLK_GPOUT0_CTRL_DC50_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_DC50_BITS _u(0x00001000)
+#define CLOCKS_CLK_GPOUT0_CTRL_DC50_MSB _u(12)
+#define CLOCKS_CLK_GPOUT0_CTRL_DC50_LSB _u(12)
#define CLOCKS_CLK_GPOUT0_CTRL_DC50_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT0_CTRL_ENABLE
// Description : Starts and stops the clock generator cleanly
-#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS _U(0x00000800)
-#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_MSB _U(11)
-#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_LSB _U(11)
+#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS _u(0x00000800)
+#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_MSB _u(11)
+#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_LSB _u(11)
#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT0_CTRL_KILL
// Description : Asynchronously kills the clock generator
-#define CLOCKS_CLK_GPOUT0_CTRL_KILL_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT0_CTRL_KILL_BITS _U(0x00000400)
-#define CLOCKS_CLK_GPOUT0_CTRL_KILL_MSB _U(10)
-#define CLOCKS_CLK_GPOUT0_CTRL_KILL_LSB _U(10)
+#define CLOCKS_CLK_GPOUT0_CTRL_KILL_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_KILL_BITS _u(0x00000400)
+#define CLOCKS_CLK_GPOUT0_CTRL_KILL_MSB _u(10)
+#define CLOCKS_CLK_GPOUT0_CTRL_KILL_LSB _u(10)
#define CLOCKS_CLK_GPOUT0_CTRL_KILL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT0_CTRL_AUXSRC
@@ -75,43 +75,43 @@
// 0x8 -> clk_adc
// 0x9 -> clk_rtc
// 0xa -> clk_ref
-#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS _U(0x000001e0)
-#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB _U(8)
-#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB _U(5)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS _u(0x000001e0)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB _u(8)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB _u(5)
#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ACCESS "RW"
-#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _U(0x0)
-#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _U(0x1)
-#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _U(0x2)
-#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _U(0x3)
-#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _U(0x4)
-#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _U(0x5)
-#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS _U(0x6)
-#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB _U(0x7)
-#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC _U(0x8)
-#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_RTC _U(0x9)
-#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF _U(0xa)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa)
// =============================================================================
// Register : CLOCKS_CLK_GPOUT0_DIV
// Description : Clock divisor, can be changed on-the-fly
-#define CLOCKS_CLK_GPOUT0_DIV_OFFSET _U(0x00000004)
-#define CLOCKS_CLK_GPOUT0_DIV_BITS _U(0xffffffff)
-#define CLOCKS_CLK_GPOUT0_DIV_RESET _U(0x00000100)
+#define CLOCKS_CLK_GPOUT0_DIV_OFFSET _u(0x00000004)
+#define CLOCKS_CLK_GPOUT0_DIV_BITS _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT0_DIV_RESET _u(0x00000100)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT0_DIV_INT
// Description : Integer component of the divisor, 0 -> divide by 2^16
-#define CLOCKS_CLK_GPOUT0_DIV_INT_RESET _U(0x000001)
-#define CLOCKS_CLK_GPOUT0_DIV_INT_BITS _U(0xffffff00)
-#define CLOCKS_CLK_GPOUT0_DIV_INT_MSB _U(31)
-#define CLOCKS_CLK_GPOUT0_DIV_INT_LSB _U(8)
+#define CLOCKS_CLK_GPOUT0_DIV_INT_RESET _u(0x000001)
+#define CLOCKS_CLK_GPOUT0_DIV_INT_BITS _u(0xffffff00)
+#define CLOCKS_CLK_GPOUT0_DIV_INT_MSB _u(31)
+#define CLOCKS_CLK_GPOUT0_DIV_INT_LSB _u(8)
#define CLOCKS_CLK_GPOUT0_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT0_DIV_FRAC
// Description : Fractional component of the divisor
-#define CLOCKS_CLK_GPOUT0_DIV_FRAC_RESET _U(0x00)
-#define CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS _U(0x000000ff)
-#define CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB _U(7)
-#define CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB _U(0)
+#define CLOCKS_CLK_GPOUT0_DIV_FRAC_RESET _u(0x00)
+#define CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS _u(0x000000ff)
+#define CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB _u(7)
+#define CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB _u(0)
#define CLOCKS_CLK_GPOUT0_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_CLK_GPOUT0_SELECTED
@@ -120,61 +120,61 @@
// This slice does not have a glitchless mux (only the AUX_SRC
// field is present, not SRC) so this register is hardwired to
// 0x1.
-#define CLOCKS_CLK_GPOUT0_SELECTED_OFFSET _U(0x00000008)
-#define CLOCKS_CLK_GPOUT0_SELECTED_BITS _U(0xffffffff)
-#define CLOCKS_CLK_GPOUT0_SELECTED_RESET _U(0x00000001)
-#define CLOCKS_CLK_GPOUT0_SELECTED_MSB _U(31)
-#define CLOCKS_CLK_GPOUT0_SELECTED_LSB _U(0)
+#define CLOCKS_CLK_GPOUT0_SELECTED_OFFSET _u(0x00000008)
+#define CLOCKS_CLK_GPOUT0_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT0_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_GPOUT0_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_GPOUT0_SELECTED_LSB _u(0)
#define CLOCKS_CLK_GPOUT0_SELECTED_ACCESS "RO"
// =============================================================================
// Register : CLOCKS_CLK_GPOUT1_CTRL
// Description : Clock control, can be changed on-the-fly (except for auxsrc)
-#define CLOCKS_CLK_GPOUT1_CTRL_OFFSET _U(0x0000000c)
-#define CLOCKS_CLK_GPOUT1_CTRL_BITS _U(0x00131de0)
-#define CLOCKS_CLK_GPOUT1_CTRL_RESET _U(0x00000000)
+#define CLOCKS_CLK_GPOUT1_CTRL_OFFSET _u(0x0000000c)
+#define CLOCKS_CLK_GPOUT1_CTRL_BITS _u(0x00131de0)
+#define CLOCKS_CLK_GPOUT1_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT1_CTRL_NUDGE
// Description : An edge on this signal shifts the phase of the output by 1
// cycle of the input clock
// This can be done at any time
-#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_BITS _U(0x00100000)
-#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_MSB _U(20)
-#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_LSB _U(20)
+#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_BITS _u(0x00100000)
+#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_MSB _u(20)
+#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_LSB _u(20)
#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT1_CTRL_PHASE
// Description : This delays the enable signal by up to 3 cycles of the input
// clock
// This must be set before the clock is enabled to have any effect
-#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_BITS _U(0x00030000)
-#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_MSB _U(17)
-#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_LSB _U(16)
+#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_BITS _u(0x00030000)
+#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_MSB _u(17)
+#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_LSB _u(16)
#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT1_CTRL_DC50
// Description : Enables duty cycle correction for odd divisors
-#define CLOCKS_CLK_GPOUT1_CTRL_DC50_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT1_CTRL_DC50_BITS _U(0x00001000)
-#define CLOCKS_CLK_GPOUT1_CTRL_DC50_MSB _U(12)
-#define CLOCKS_CLK_GPOUT1_CTRL_DC50_LSB _U(12)
+#define CLOCKS_CLK_GPOUT1_CTRL_DC50_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_DC50_BITS _u(0x00001000)
+#define CLOCKS_CLK_GPOUT1_CTRL_DC50_MSB _u(12)
+#define CLOCKS_CLK_GPOUT1_CTRL_DC50_LSB _u(12)
#define CLOCKS_CLK_GPOUT1_CTRL_DC50_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT1_CTRL_ENABLE
// Description : Starts and stops the clock generator cleanly
-#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_BITS _U(0x00000800)
-#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_MSB _U(11)
-#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_LSB _U(11)
+#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_BITS _u(0x00000800)
+#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_MSB _u(11)
+#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_LSB _u(11)
#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT1_CTRL_KILL
// Description : Asynchronously kills the clock generator
-#define CLOCKS_CLK_GPOUT1_CTRL_KILL_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT1_CTRL_KILL_BITS _U(0x00000400)
-#define CLOCKS_CLK_GPOUT1_CTRL_KILL_MSB _U(10)
-#define CLOCKS_CLK_GPOUT1_CTRL_KILL_LSB _U(10)
+#define CLOCKS_CLK_GPOUT1_CTRL_KILL_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_KILL_BITS _u(0x00000400)
+#define CLOCKS_CLK_GPOUT1_CTRL_KILL_MSB _u(10)
+#define CLOCKS_CLK_GPOUT1_CTRL_KILL_LSB _u(10)
#define CLOCKS_CLK_GPOUT1_CTRL_KILL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT1_CTRL_AUXSRC
@@ -190,43 +190,43 @@
// 0x8 -> clk_adc
// 0x9 -> clk_rtc
// 0xa -> clk_ref
-#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS _U(0x000001e0)
-#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB _U(8)
-#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB _U(5)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS _u(0x000001e0)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB _u(8)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB _u(5)
#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ACCESS "RW"
-#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _U(0x0)
-#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _U(0x1)
-#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _U(0x2)
-#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _U(0x3)
-#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _U(0x4)
-#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _U(0x5)
-#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS _U(0x6)
-#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB _U(0x7)
-#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC _U(0x8)
-#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_RTC _U(0x9)
-#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF _U(0xa)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa)
// =============================================================================
// Register : CLOCKS_CLK_GPOUT1_DIV
// Description : Clock divisor, can be changed on-the-fly
-#define CLOCKS_CLK_GPOUT1_DIV_OFFSET _U(0x00000010)
-#define CLOCKS_CLK_GPOUT1_DIV_BITS _U(0xffffffff)
-#define CLOCKS_CLK_GPOUT1_DIV_RESET _U(0x00000100)
+#define CLOCKS_CLK_GPOUT1_DIV_OFFSET _u(0x00000010)
+#define CLOCKS_CLK_GPOUT1_DIV_BITS _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT1_DIV_RESET _u(0x00000100)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT1_DIV_INT
// Description : Integer component of the divisor, 0 -> divide by 2^16
-#define CLOCKS_CLK_GPOUT1_DIV_INT_RESET _U(0x000001)
-#define CLOCKS_CLK_GPOUT1_DIV_INT_BITS _U(0xffffff00)
-#define CLOCKS_CLK_GPOUT1_DIV_INT_MSB _U(31)
-#define CLOCKS_CLK_GPOUT1_DIV_INT_LSB _U(8)
+#define CLOCKS_CLK_GPOUT1_DIV_INT_RESET _u(0x000001)
+#define CLOCKS_CLK_GPOUT1_DIV_INT_BITS _u(0xffffff00)
+#define CLOCKS_CLK_GPOUT1_DIV_INT_MSB _u(31)
+#define CLOCKS_CLK_GPOUT1_DIV_INT_LSB _u(8)
#define CLOCKS_CLK_GPOUT1_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT1_DIV_FRAC
// Description : Fractional component of the divisor
-#define CLOCKS_CLK_GPOUT1_DIV_FRAC_RESET _U(0x00)
-#define CLOCKS_CLK_GPOUT1_DIV_FRAC_BITS _U(0x000000ff)
-#define CLOCKS_CLK_GPOUT1_DIV_FRAC_MSB _U(7)
-#define CLOCKS_CLK_GPOUT1_DIV_FRAC_LSB _U(0)
+#define CLOCKS_CLK_GPOUT1_DIV_FRAC_RESET _u(0x00)
+#define CLOCKS_CLK_GPOUT1_DIV_FRAC_BITS _u(0x000000ff)
+#define CLOCKS_CLK_GPOUT1_DIV_FRAC_MSB _u(7)
+#define CLOCKS_CLK_GPOUT1_DIV_FRAC_LSB _u(0)
#define CLOCKS_CLK_GPOUT1_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_CLK_GPOUT1_SELECTED
@@ -235,61 +235,61 @@
// This slice does not have a glitchless mux (only the AUX_SRC
// field is present, not SRC) so this register is hardwired to
// 0x1.
-#define CLOCKS_CLK_GPOUT1_SELECTED_OFFSET _U(0x00000014)
-#define CLOCKS_CLK_GPOUT1_SELECTED_BITS _U(0xffffffff)
-#define CLOCKS_CLK_GPOUT1_SELECTED_RESET _U(0x00000001)
-#define CLOCKS_CLK_GPOUT1_SELECTED_MSB _U(31)
-#define CLOCKS_CLK_GPOUT1_SELECTED_LSB _U(0)
+#define CLOCKS_CLK_GPOUT1_SELECTED_OFFSET _u(0x00000014)
+#define CLOCKS_CLK_GPOUT1_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT1_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_GPOUT1_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_GPOUT1_SELECTED_LSB _u(0)
#define CLOCKS_CLK_GPOUT1_SELECTED_ACCESS "RO"
// =============================================================================
// Register : CLOCKS_CLK_GPOUT2_CTRL
// Description : Clock control, can be changed on-the-fly (except for auxsrc)
-#define CLOCKS_CLK_GPOUT2_CTRL_OFFSET _U(0x00000018)
-#define CLOCKS_CLK_GPOUT2_CTRL_BITS _U(0x00131de0)
-#define CLOCKS_CLK_GPOUT2_CTRL_RESET _U(0x00000000)
+#define CLOCKS_CLK_GPOUT2_CTRL_OFFSET _u(0x00000018)
+#define CLOCKS_CLK_GPOUT2_CTRL_BITS _u(0x00131de0)
+#define CLOCKS_CLK_GPOUT2_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT2_CTRL_NUDGE
// Description : An edge on this signal shifts the phase of the output by 1
// cycle of the input clock
// This can be done at any time
-#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_BITS _U(0x00100000)
-#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_MSB _U(20)
-#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_LSB _U(20)
+#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_BITS _u(0x00100000)
+#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_MSB _u(20)
+#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_LSB _u(20)
#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT2_CTRL_PHASE
// Description : This delays the enable signal by up to 3 cycles of the input
// clock
// This must be set before the clock is enabled to have any effect
-#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_BITS _U(0x00030000)
-#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_MSB _U(17)
-#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_LSB _U(16)
+#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_BITS _u(0x00030000)
+#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_MSB _u(17)
+#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_LSB _u(16)
#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT2_CTRL_DC50
// Description : Enables duty cycle correction for odd divisors
-#define CLOCKS_CLK_GPOUT2_CTRL_DC50_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT2_CTRL_DC50_BITS _U(0x00001000)
-#define CLOCKS_CLK_GPOUT2_CTRL_DC50_MSB _U(12)
-#define CLOCKS_CLK_GPOUT2_CTRL_DC50_LSB _U(12)
+#define CLOCKS_CLK_GPOUT2_CTRL_DC50_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_DC50_BITS _u(0x00001000)
+#define CLOCKS_CLK_GPOUT2_CTRL_DC50_MSB _u(12)
+#define CLOCKS_CLK_GPOUT2_CTRL_DC50_LSB _u(12)
#define CLOCKS_CLK_GPOUT2_CTRL_DC50_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT2_CTRL_ENABLE
// Description : Starts and stops the clock generator cleanly
-#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_BITS _U(0x00000800)
-#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_MSB _U(11)
-#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_LSB _U(11)
+#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_BITS _u(0x00000800)
+#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_MSB _u(11)
+#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_LSB _u(11)
#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT2_CTRL_KILL
// Description : Asynchronously kills the clock generator
-#define CLOCKS_CLK_GPOUT2_CTRL_KILL_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT2_CTRL_KILL_BITS _U(0x00000400)
-#define CLOCKS_CLK_GPOUT2_CTRL_KILL_MSB _U(10)
-#define CLOCKS_CLK_GPOUT2_CTRL_KILL_LSB _U(10)
+#define CLOCKS_CLK_GPOUT2_CTRL_KILL_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_KILL_BITS _u(0x00000400)
+#define CLOCKS_CLK_GPOUT2_CTRL_KILL_MSB _u(10)
+#define CLOCKS_CLK_GPOUT2_CTRL_KILL_LSB _u(10)
#define CLOCKS_CLK_GPOUT2_CTRL_KILL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT2_CTRL_AUXSRC
@@ -305,43 +305,43 @@
// 0x8 -> clk_adc
// 0x9 -> clk_rtc
// 0xa -> clk_ref
-#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS _U(0x000001e0)
-#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB _U(8)
-#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB _U(5)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS _u(0x000001e0)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB _u(8)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB _u(5)
#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ACCESS "RW"
-#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _U(0x0)
-#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _U(0x1)
-#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _U(0x2)
-#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _U(0x3)
-#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _U(0x4)
-#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _U(0x5)
-#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS _U(0x6)
-#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB _U(0x7)
-#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC _U(0x8)
-#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_RTC _U(0x9)
-#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF _U(0xa)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa)
// =============================================================================
// Register : CLOCKS_CLK_GPOUT2_DIV
// Description : Clock divisor, can be changed on-the-fly
-#define CLOCKS_CLK_GPOUT2_DIV_OFFSET _U(0x0000001c)
-#define CLOCKS_CLK_GPOUT2_DIV_BITS _U(0xffffffff)
-#define CLOCKS_CLK_GPOUT2_DIV_RESET _U(0x00000100)
+#define CLOCKS_CLK_GPOUT2_DIV_OFFSET _u(0x0000001c)
+#define CLOCKS_CLK_GPOUT2_DIV_BITS _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT2_DIV_RESET _u(0x00000100)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT2_DIV_INT
// Description : Integer component of the divisor, 0 -> divide by 2^16
-#define CLOCKS_CLK_GPOUT2_DIV_INT_RESET _U(0x000001)
-#define CLOCKS_CLK_GPOUT2_DIV_INT_BITS _U(0xffffff00)
-#define CLOCKS_CLK_GPOUT2_DIV_INT_MSB _U(31)
-#define CLOCKS_CLK_GPOUT2_DIV_INT_LSB _U(8)
+#define CLOCKS_CLK_GPOUT2_DIV_INT_RESET _u(0x000001)
+#define CLOCKS_CLK_GPOUT2_DIV_INT_BITS _u(0xffffff00)
+#define CLOCKS_CLK_GPOUT2_DIV_INT_MSB _u(31)
+#define CLOCKS_CLK_GPOUT2_DIV_INT_LSB _u(8)
#define CLOCKS_CLK_GPOUT2_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT2_DIV_FRAC
// Description : Fractional component of the divisor
-#define CLOCKS_CLK_GPOUT2_DIV_FRAC_RESET _U(0x00)
-#define CLOCKS_CLK_GPOUT2_DIV_FRAC_BITS _U(0x000000ff)
-#define CLOCKS_CLK_GPOUT2_DIV_FRAC_MSB _U(7)
-#define CLOCKS_CLK_GPOUT2_DIV_FRAC_LSB _U(0)
+#define CLOCKS_CLK_GPOUT2_DIV_FRAC_RESET _u(0x00)
+#define CLOCKS_CLK_GPOUT2_DIV_FRAC_BITS _u(0x000000ff)
+#define CLOCKS_CLK_GPOUT2_DIV_FRAC_MSB _u(7)
+#define CLOCKS_CLK_GPOUT2_DIV_FRAC_LSB _u(0)
#define CLOCKS_CLK_GPOUT2_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_CLK_GPOUT2_SELECTED
@@ -350,61 +350,61 @@
// This slice does not have a glitchless mux (only the AUX_SRC
// field is present, not SRC) so this register is hardwired to
// 0x1.
-#define CLOCKS_CLK_GPOUT2_SELECTED_OFFSET _U(0x00000020)
-#define CLOCKS_CLK_GPOUT2_SELECTED_BITS _U(0xffffffff)
-#define CLOCKS_CLK_GPOUT2_SELECTED_RESET _U(0x00000001)
-#define CLOCKS_CLK_GPOUT2_SELECTED_MSB _U(31)
-#define CLOCKS_CLK_GPOUT2_SELECTED_LSB _U(0)
+#define CLOCKS_CLK_GPOUT2_SELECTED_OFFSET _u(0x00000020)
+#define CLOCKS_CLK_GPOUT2_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT2_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_GPOUT2_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_GPOUT2_SELECTED_LSB _u(0)
#define CLOCKS_CLK_GPOUT2_SELECTED_ACCESS "RO"
// =============================================================================
// Register : CLOCKS_CLK_GPOUT3_CTRL
// Description : Clock control, can be changed on-the-fly (except for auxsrc)
-#define CLOCKS_CLK_GPOUT3_CTRL_OFFSET _U(0x00000024)
-#define CLOCKS_CLK_GPOUT3_CTRL_BITS _U(0x00131de0)
-#define CLOCKS_CLK_GPOUT3_CTRL_RESET _U(0x00000000)
+#define CLOCKS_CLK_GPOUT3_CTRL_OFFSET _u(0x00000024)
+#define CLOCKS_CLK_GPOUT3_CTRL_BITS _u(0x00131de0)
+#define CLOCKS_CLK_GPOUT3_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT3_CTRL_NUDGE
// Description : An edge on this signal shifts the phase of the output by 1
// cycle of the input clock
// This can be done at any time
-#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_BITS _U(0x00100000)
-#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_MSB _U(20)
-#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_LSB _U(20)
+#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_BITS _u(0x00100000)
+#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_MSB _u(20)
+#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_LSB _u(20)
#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT3_CTRL_PHASE
// Description : This delays the enable signal by up to 3 cycles of the input
// clock
// This must be set before the clock is enabled to have any effect
-#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_BITS _U(0x00030000)
-#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_MSB _U(17)
-#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_LSB _U(16)
+#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_BITS _u(0x00030000)
+#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_MSB _u(17)
+#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_LSB _u(16)
#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT3_CTRL_DC50
// Description : Enables duty cycle correction for odd divisors
-#define CLOCKS_CLK_GPOUT3_CTRL_DC50_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT3_CTRL_DC50_BITS _U(0x00001000)
-#define CLOCKS_CLK_GPOUT3_CTRL_DC50_MSB _U(12)
-#define CLOCKS_CLK_GPOUT3_CTRL_DC50_LSB _U(12)
+#define CLOCKS_CLK_GPOUT3_CTRL_DC50_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_DC50_BITS _u(0x00001000)
+#define CLOCKS_CLK_GPOUT3_CTRL_DC50_MSB _u(12)
+#define CLOCKS_CLK_GPOUT3_CTRL_DC50_LSB _u(12)
#define CLOCKS_CLK_GPOUT3_CTRL_DC50_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT3_CTRL_ENABLE
// Description : Starts and stops the clock generator cleanly
-#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_BITS _U(0x00000800)
-#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_MSB _U(11)
-#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_LSB _U(11)
+#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_BITS _u(0x00000800)
+#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_MSB _u(11)
+#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_LSB _u(11)
#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT3_CTRL_KILL
// Description : Asynchronously kills the clock generator
-#define CLOCKS_CLK_GPOUT3_CTRL_KILL_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT3_CTRL_KILL_BITS _U(0x00000400)
-#define CLOCKS_CLK_GPOUT3_CTRL_KILL_MSB _U(10)
-#define CLOCKS_CLK_GPOUT3_CTRL_KILL_LSB _U(10)
+#define CLOCKS_CLK_GPOUT3_CTRL_KILL_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_KILL_BITS _u(0x00000400)
+#define CLOCKS_CLK_GPOUT3_CTRL_KILL_MSB _u(10)
+#define CLOCKS_CLK_GPOUT3_CTRL_KILL_LSB _u(10)
#define CLOCKS_CLK_GPOUT3_CTRL_KILL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT3_CTRL_AUXSRC
@@ -420,43 +420,43 @@
// 0x8 -> clk_adc
// 0x9 -> clk_rtc
// 0xa -> clk_ref
-#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET _U(0x0)
-#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS _U(0x000001e0)
-#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB _U(8)
-#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB _U(5)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS _u(0x000001e0)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB _u(8)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB _u(5)
#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ACCESS "RW"
-#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _U(0x0)
-#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _U(0x1)
-#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _U(0x2)
-#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _U(0x3)
-#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _U(0x4)
-#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _U(0x5)
-#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS _U(0x6)
-#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB _U(0x7)
-#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC _U(0x8)
-#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_RTC _U(0x9)
-#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF _U(0xa)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa)
// =============================================================================
// Register : CLOCKS_CLK_GPOUT3_DIV
// Description : Clock divisor, can be changed on-the-fly
-#define CLOCKS_CLK_GPOUT3_DIV_OFFSET _U(0x00000028)
-#define CLOCKS_CLK_GPOUT3_DIV_BITS _U(0xffffffff)
-#define CLOCKS_CLK_GPOUT3_DIV_RESET _U(0x00000100)
+#define CLOCKS_CLK_GPOUT3_DIV_OFFSET _u(0x00000028)
+#define CLOCKS_CLK_GPOUT3_DIV_BITS _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT3_DIV_RESET _u(0x00000100)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT3_DIV_INT
// Description : Integer component of the divisor, 0 -> divide by 2^16
-#define CLOCKS_CLK_GPOUT3_DIV_INT_RESET _U(0x000001)
-#define CLOCKS_CLK_GPOUT3_DIV_INT_BITS _U(0xffffff00)
-#define CLOCKS_CLK_GPOUT3_DIV_INT_MSB _U(31)
-#define CLOCKS_CLK_GPOUT3_DIV_INT_LSB _U(8)
+#define CLOCKS_CLK_GPOUT3_DIV_INT_RESET _u(0x000001)
+#define CLOCKS_CLK_GPOUT3_DIV_INT_BITS _u(0xffffff00)
+#define CLOCKS_CLK_GPOUT3_DIV_INT_MSB _u(31)
+#define CLOCKS_CLK_GPOUT3_DIV_INT_LSB _u(8)
#define CLOCKS_CLK_GPOUT3_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_GPOUT3_DIV_FRAC
// Description : Fractional component of the divisor
-#define CLOCKS_CLK_GPOUT3_DIV_FRAC_RESET _U(0x00)
-#define CLOCKS_CLK_GPOUT3_DIV_FRAC_BITS _U(0x000000ff)
-#define CLOCKS_CLK_GPOUT3_DIV_FRAC_MSB _U(7)
-#define CLOCKS_CLK_GPOUT3_DIV_FRAC_LSB _U(0)
+#define CLOCKS_CLK_GPOUT3_DIV_FRAC_RESET _u(0x00)
+#define CLOCKS_CLK_GPOUT3_DIV_FRAC_BITS _u(0x000000ff)
+#define CLOCKS_CLK_GPOUT3_DIV_FRAC_MSB _u(7)
+#define CLOCKS_CLK_GPOUT3_DIV_FRAC_LSB _u(0)
#define CLOCKS_CLK_GPOUT3_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_CLK_GPOUT3_SELECTED
@@ -465,32 +465,32 @@
// This slice does not have a glitchless mux (only the AUX_SRC
// field is present, not SRC) so this register is hardwired to
// 0x1.
-#define CLOCKS_CLK_GPOUT3_SELECTED_OFFSET _U(0x0000002c)
-#define CLOCKS_CLK_GPOUT3_SELECTED_BITS _U(0xffffffff)
-#define CLOCKS_CLK_GPOUT3_SELECTED_RESET _U(0x00000001)
-#define CLOCKS_CLK_GPOUT3_SELECTED_MSB _U(31)
-#define CLOCKS_CLK_GPOUT3_SELECTED_LSB _U(0)
+#define CLOCKS_CLK_GPOUT3_SELECTED_OFFSET _u(0x0000002c)
+#define CLOCKS_CLK_GPOUT3_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT3_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_GPOUT3_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_GPOUT3_SELECTED_LSB _u(0)
#define CLOCKS_CLK_GPOUT3_SELECTED_ACCESS "RO"
// =============================================================================
// Register : CLOCKS_CLK_REF_CTRL
// Description : Clock control, can be changed on-the-fly (except for auxsrc)
-#define CLOCKS_CLK_REF_CTRL_OFFSET _U(0x00000030)
-#define CLOCKS_CLK_REF_CTRL_BITS _U(0x00000063)
-#define CLOCKS_CLK_REF_CTRL_RESET _U(0x00000000)
+#define CLOCKS_CLK_REF_CTRL_OFFSET _u(0x00000030)
+#define CLOCKS_CLK_REF_CTRL_BITS _u(0x00000063)
+#define CLOCKS_CLK_REF_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_REF_CTRL_AUXSRC
// Description : Selects the auxiliary clock source, will glitch when switching
// 0x0 -> clksrc_pll_usb
// 0x1 -> clksrc_gpin0
// 0x2 -> clksrc_gpin1
-#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET _U(0x0)
-#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS _U(0x00000060)
-#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB _U(6)
-#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB _U(5)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS _u(0x00000060)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB _u(6)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB _u(5)
#define CLOCKS_CLK_REF_CTRL_AUXSRC_ACCESS "RW"
-#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _U(0x0)
-#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _U(0x1)
-#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _U(0x2)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_REF_CTRL_SRC
// Description : Selects the clock source glitchlessly, can be changed
@@ -499,26 +499,26 @@
// 0x1 -> clksrc_clk_ref_aux
// 0x2 -> xosc_clksrc
#define CLOCKS_CLK_REF_CTRL_SRC_RESET "-"
-#define CLOCKS_CLK_REF_CTRL_SRC_BITS _U(0x00000003)
-#define CLOCKS_CLK_REF_CTRL_SRC_MSB _U(1)
-#define CLOCKS_CLK_REF_CTRL_SRC_LSB _U(0)
+#define CLOCKS_CLK_REF_CTRL_SRC_BITS _u(0x00000003)
+#define CLOCKS_CLK_REF_CTRL_SRC_MSB _u(1)
+#define CLOCKS_CLK_REF_CTRL_SRC_LSB _u(0)
#define CLOCKS_CLK_REF_CTRL_SRC_ACCESS "RW"
-#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH _U(0x0)
-#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX _U(0x1)
-#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC _U(0x2)
+#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH _u(0x0)
+#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX _u(0x1)
+#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC _u(0x2)
// =============================================================================
// Register : CLOCKS_CLK_REF_DIV
// Description : Clock divisor, can be changed on-the-fly
-#define CLOCKS_CLK_REF_DIV_OFFSET _U(0x00000034)
-#define CLOCKS_CLK_REF_DIV_BITS _U(0x00000300)
-#define CLOCKS_CLK_REF_DIV_RESET _U(0x00000100)
+#define CLOCKS_CLK_REF_DIV_OFFSET _u(0x00000034)
+#define CLOCKS_CLK_REF_DIV_BITS _u(0x00000300)
+#define CLOCKS_CLK_REF_DIV_RESET _u(0x00000100)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_REF_DIV_INT
// Description : Integer component of the divisor, 0 -> divide by 2^16
-#define CLOCKS_CLK_REF_DIV_INT_RESET _U(0x1)
-#define CLOCKS_CLK_REF_DIV_INT_BITS _U(0x00000300)
-#define CLOCKS_CLK_REF_DIV_INT_MSB _U(9)
-#define CLOCKS_CLK_REF_DIV_INT_LSB _U(8)
+#define CLOCKS_CLK_REF_DIV_INT_RESET _u(0x1)
+#define CLOCKS_CLK_REF_DIV_INT_BITS _u(0x00000300)
+#define CLOCKS_CLK_REF_DIV_INT_MSB _u(9)
+#define CLOCKS_CLK_REF_DIV_INT_LSB _u(8)
#define CLOCKS_CLK_REF_DIV_INT_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_CLK_REF_SELECTED
@@ -532,18 +532,18 @@
// indicating that clock is currently present at the output of the
// glitchless mux. Whilst switching is in progress, this register
// may briefly show all-0s.
-#define CLOCKS_CLK_REF_SELECTED_OFFSET _U(0x00000038)
-#define CLOCKS_CLK_REF_SELECTED_BITS _U(0xffffffff)
-#define CLOCKS_CLK_REF_SELECTED_RESET _U(0x00000001)
-#define CLOCKS_CLK_REF_SELECTED_MSB _U(31)
-#define CLOCKS_CLK_REF_SELECTED_LSB _U(0)
+#define CLOCKS_CLK_REF_SELECTED_OFFSET _u(0x00000038)
+#define CLOCKS_CLK_REF_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_REF_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_REF_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_REF_SELECTED_LSB _u(0)
#define CLOCKS_CLK_REF_SELECTED_ACCESS "RO"
// =============================================================================
// Register : CLOCKS_CLK_SYS_CTRL
// Description : Clock control, can be changed on-the-fly (except for auxsrc)
-#define CLOCKS_CLK_SYS_CTRL_OFFSET _U(0x0000003c)
-#define CLOCKS_CLK_SYS_CTRL_BITS _U(0x000000e1)
-#define CLOCKS_CLK_SYS_CTRL_RESET _U(0x00000000)
+#define CLOCKS_CLK_SYS_CTRL_OFFSET _u(0x0000003c)
+#define CLOCKS_CLK_SYS_CTRL_BITS _u(0x000000e1)
+#define CLOCKS_CLK_SYS_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_SYS_CTRL_AUXSRC
// Description : Selects the auxiliary clock source, will glitch when switching
@@ -553,51 +553,51 @@
// 0x3 -> xosc_clksrc
// 0x4 -> clksrc_gpin0
// 0x5 -> clksrc_gpin1
-#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _U(0x0)
-#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS _U(0x000000e0)
-#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB _U(7)
-#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB _U(5)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS _u(0x000000e0)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB _u(7)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB _u(5)
#define CLOCKS_CLK_SYS_CTRL_AUXSRC_ACCESS "RW"
-#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _U(0x0)
-#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _U(0x1)
-#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _U(0x2)
-#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _U(0x3)
-#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _U(0x4)
-#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _U(0x5)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x1)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x2)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_SYS_CTRL_SRC
// Description : Selects the clock source glitchlessly, can be changed
// on-the-fly
// 0x0 -> clk_ref
// 0x1 -> clksrc_clk_sys_aux
-#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _U(0x0)
-#define CLOCKS_CLK_SYS_CTRL_SRC_BITS _U(0x00000001)
-#define CLOCKS_CLK_SYS_CTRL_SRC_MSB _U(0)
-#define CLOCKS_CLK_SYS_CTRL_SRC_LSB _U(0)
+#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _u(0x0)
+#define CLOCKS_CLK_SYS_CTRL_SRC_BITS _u(0x00000001)
+#define CLOCKS_CLK_SYS_CTRL_SRC_MSB _u(0)
+#define CLOCKS_CLK_SYS_CTRL_SRC_LSB _u(0)
#define CLOCKS_CLK_SYS_CTRL_SRC_ACCESS "RW"
-#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF _U(0x0)
-#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX _U(0x1)
+#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF _u(0x0)
+#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX _u(0x1)
// =============================================================================
// Register : CLOCKS_CLK_SYS_DIV
// Description : Clock divisor, can be changed on-the-fly
-#define CLOCKS_CLK_SYS_DIV_OFFSET _U(0x00000040)
-#define CLOCKS_CLK_SYS_DIV_BITS _U(0xffffffff)
-#define CLOCKS_CLK_SYS_DIV_RESET _U(0x00000100)
+#define CLOCKS_CLK_SYS_DIV_OFFSET _u(0x00000040)
+#define CLOCKS_CLK_SYS_DIV_BITS _u(0xffffffff)
+#define CLOCKS_CLK_SYS_DIV_RESET _u(0x00000100)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_SYS_DIV_INT
// Description : Integer component of the divisor, 0 -> divide by 2^16
-#define CLOCKS_CLK_SYS_DIV_INT_RESET _U(0x000001)
-#define CLOCKS_CLK_SYS_DIV_INT_BITS _U(0xffffff00)
-#define CLOCKS_CLK_SYS_DIV_INT_MSB _U(31)
-#define CLOCKS_CLK_SYS_DIV_INT_LSB _U(8)
+#define CLOCKS_CLK_SYS_DIV_INT_RESET _u(0x000001)
+#define CLOCKS_CLK_SYS_DIV_INT_BITS _u(0xffffff00)
+#define CLOCKS_CLK_SYS_DIV_INT_MSB _u(31)
+#define CLOCKS_CLK_SYS_DIV_INT_LSB _u(8)
#define CLOCKS_CLK_SYS_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_SYS_DIV_FRAC
// Description : Fractional component of the divisor
-#define CLOCKS_CLK_SYS_DIV_FRAC_RESET _U(0x00)
-#define CLOCKS_CLK_SYS_DIV_FRAC_BITS _U(0x000000ff)
-#define CLOCKS_CLK_SYS_DIV_FRAC_MSB _U(7)
-#define CLOCKS_CLK_SYS_DIV_FRAC_LSB _U(0)
+#define CLOCKS_CLK_SYS_DIV_FRAC_RESET _u(0x00)
+#define CLOCKS_CLK_SYS_DIV_FRAC_BITS _u(0x000000ff)
+#define CLOCKS_CLK_SYS_DIV_FRAC_MSB _u(7)
+#define CLOCKS_CLK_SYS_DIV_FRAC_LSB _u(0)
#define CLOCKS_CLK_SYS_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_CLK_SYS_SELECTED
@@ -611,33 +611,33 @@
// indicating that clock is currently present at the output of the
// glitchless mux. Whilst switching is in progress, this register
// may briefly show all-0s.
-#define CLOCKS_CLK_SYS_SELECTED_OFFSET _U(0x00000044)
-#define CLOCKS_CLK_SYS_SELECTED_BITS _U(0xffffffff)
-#define CLOCKS_CLK_SYS_SELECTED_RESET _U(0x00000001)
-#define CLOCKS_CLK_SYS_SELECTED_MSB _U(31)
-#define CLOCKS_CLK_SYS_SELECTED_LSB _U(0)
+#define CLOCKS_CLK_SYS_SELECTED_OFFSET _u(0x00000044)
+#define CLOCKS_CLK_SYS_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_SYS_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_SYS_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_SYS_SELECTED_LSB _u(0)
#define CLOCKS_CLK_SYS_SELECTED_ACCESS "RO"
// =============================================================================
// Register : CLOCKS_CLK_PERI_CTRL
// Description : Clock control, can be changed on-the-fly (except for auxsrc)
-#define CLOCKS_CLK_PERI_CTRL_OFFSET _U(0x00000048)
-#define CLOCKS_CLK_PERI_CTRL_BITS _U(0x00000ce0)
-#define CLOCKS_CLK_PERI_CTRL_RESET _U(0x00000000)
+#define CLOCKS_CLK_PERI_CTRL_OFFSET _u(0x00000048)
+#define CLOCKS_CLK_PERI_CTRL_BITS _u(0x00000ce0)
+#define CLOCKS_CLK_PERI_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_PERI_CTRL_ENABLE
// Description : Starts and stops the clock generator cleanly
-#define CLOCKS_CLK_PERI_CTRL_ENABLE_RESET _U(0x0)
-#define CLOCKS_CLK_PERI_CTRL_ENABLE_BITS _U(0x00000800)
-#define CLOCKS_CLK_PERI_CTRL_ENABLE_MSB _U(11)
-#define CLOCKS_CLK_PERI_CTRL_ENABLE_LSB _U(11)
+#define CLOCKS_CLK_PERI_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_PERI_CTRL_ENABLE_BITS _u(0x00000800)
+#define CLOCKS_CLK_PERI_CTRL_ENABLE_MSB _u(11)
+#define CLOCKS_CLK_PERI_CTRL_ENABLE_LSB _u(11)
#define CLOCKS_CLK_PERI_CTRL_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_PERI_CTRL_KILL
// Description : Asynchronously kills the clock generator
-#define CLOCKS_CLK_PERI_CTRL_KILL_RESET _U(0x0)
-#define CLOCKS_CLK_PERI_CTRL_KILL_BITS _U(0x00000400)
-#define CLOCKS_CLK_PERI_CTRL_KILL_MSB _U(10)
-#define CLOCKS_CLK_PERI_CTRL_KILL_LSB _U(10)
+#define CLOCKS_CLK_PERI_CTRL_KILL_RESET _u(0x0)
+#define CLOCKS_CLK_PERI_CTRL_KILL_BITS _u(0x00000400)
+#define CLOCKS_CLK_PERI_CTRL_KILL_MSB _u(10)
+#define CLOCKS_CLK_PERI_CTRL_KILL_LSB _u(10)
#define CLOCKS_CLK_PERI_CTRL_KILL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_PERI_CTRL_AUXSRC
@@ -649,18 +649,18 @@
// 0x4 -> xosc_clksrc
// 0x5 -> clksrc_gpin0
// 0x6 -> clksrc_gpin1
-#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET _U(0x0)
-#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS _U(0x000000e0)
-#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB _U(7)
-#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB _U(5)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS _u(0x000000e0)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB _u(7)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB _u(5)
#define CLOCKS_CLK_PERI_CTRL_AUXSRC_ACCESS "RW"
-#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS _U(0x0)
-#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _U(0x1)
-#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _U(0x2)
-#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _U(0x3)
-#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _U(0x4)
-#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _U(0x5)
-#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _U(0x6)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x0)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x2)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x3)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x4)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x5)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x6)
// =============================================================================
// Register : CLOCKS_CLK_PERI_SELECTED
// Description : Indicates which SRC is currently selected by the glitchless mux
@@ -668,53 +668,53 @@
// This slice does not have a glitchless mux (only the AUX_SRC
// field is present, not SRC) so this register is hardwired to
// 0x1.
-#define CLOCKS_CLK_PERI_SELECTED_OFFSET _U(0x00000050)
-#define CLOCKS_CLK_PERI_SELECTED_BITS _U(0xffffffff)
-#define CLOCKS_CLK_PERI_SELECTED_RESET _U(0x00000001)
-#define CLOCKS_CLK_PERI_SELECTED_MSB _U(31)
-#define CLOCKS_CLK_PERI_SELECTED_LSB _U(0)
+#define CLOCKS_CLK_PERI_SELECTED_OFFSET _u(0x00000050)
+#define CLOCKS_CLK_PERI_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_PERI_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_PERI_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_PERI_SELECTED_LSB _u(0)
#define CLOCKS_CLK_PERI_SELECTED_ACCESS "RO"
// =============================================================================
// Register : CLOCKS_CLK_USB_CTRL
// Description : Clock control, can be changed on-the-fly (except for auxsrc)
-#define CLOCKS_CLK_USB_CTRL_OFFSET _U(0x00000054)
-#define CLOCKS_CLK_USB_CTRL_BITS _U(0x00130ce0)
-#define CLOCKS_CLK_USB_CTRL_RESET _U(0x00000000)
+#define CLOCKS_CLK_USB_CTRL_OFFSET _u(0x00000054)
+#define CLOCKS_CLK_USB_CTRL_BITS _u(0x00130ce0)
+#define CLOCKS_CLK_USB_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_USB_CTRL_NUDGE
// Description : An edge on this signal shifts the phase of the output by 1
// cycle of the input clock
// This can be done at any time
-#define CLOCKS_CLK_USB_CTRL_NUDGE_RESET _U(0x0)
-#define CLOCKS_CLK_USB_CTRL_NUDGE_BITS _U(0x00100000)
-#define CLOCKS_CLK_USB_CTRL_NUDGE_MSB _U(20)
-#define CLOCKS_CLK_USB_CTRL_NUDGE_LSB _U(20)
+#define CLOCKS_CLK_USB_CTRL_NUDGE_RESET _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_NUDGE_BITS _u(0x00100000)
+#define CLOCKS_CLK_USB_CTRL_NUDGE_MSB _u(20)
+#define CLOCKS_CLK_USB_CTRL_NUDGE_LSB _u(20)
#define CLOCKS_CLK_USB_CTRL_NUDGE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_USB_CTRL_PHASE
// Description : This delays the enable signal by up to 3 cycles of the input
// clock
// This must be set before the clock is enabled to have any effect
-#define CLOCKS_CLK_USB_CTRL_PHASE_RESET _U(0x0)
-#define CLOCKS_CLK_USB_CTRL_PHASE_BITS _U(0x00030000)
-#define CLOCKS_CLK_USB_CTRL_PHASE_MSB _U(17)
-#define CLOCKS_CLK_USB_CTRL_PHASE_LSB _U(16)
+#define CLOCKS_CLK_USB_CTRL_PHASE_RESET _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_PHASE_BITS _u(0x00030000)
+#define CLOCKS_CLK_USB_CTRL_PHASE_MSB _u(17)
+#define CLOCKS_CLK_USB_CTRL_PHASE_LSB _u(16)
#define CLOCKS_CLK_USB_CTRL_PHASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_USB_CTRL_ENABLE
// Description : Starts and stops the clock generator cleanly
-#define CLOCKS_CLK_USB_CTRL_ENABLE_RESET _U(0x0)
-#define CLOCKS_CLK_USB_CTRL_ENABLE_BITS _U(0x00000800)
-#define CLOCKS_CLK_USB_CTRL_ENABLE_MSB _U(11)
-#define CLOCKS_CLK_USB_CTRL_ENABLE_LSB _U(11)
+#define CLOCKS_CLK_USB_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_ENABLE_BITS _u(0x00000800)
+#define CLOCKS_CLK_USB_CTRL_ENABLE_MSB _u(11)
+#define CLOCKS_CLK_USB_CTRL_ENABLE_LSB _u(11)
#define CLOCKS_CLK_USB_CTRL_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_USB_CTRL_KILL
// Description : Asynchronously kills the clock generator
-#define CLOCKS_CLK_USB_CTRL_KILL_RESET _U(0x0)
-#define CLOCKS_CLK_USB_CTRL_KILL_BITS _U(0x00000400)
-#define CLOCKS_CLK_USB_CTRL_KILL_MSB _U(10)
-#define CLOCKS_CLK_USB_CTRL_KILL_LSB _U(10)
+#define CLOCKS_CLK_USB_CTRL_KILL_RESET _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_KILL_BITS _u(0x00000400)
+#define CLOCKS_CLK_USB_CTRL_KILL_MSB _u(10)
+#define CLOCKS_CLK_USB_CTRL_KILL_LSB _u(10)
#define CLOCKS_CLK_USB_CTRL_KILL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_USB_CTRL_AUXSRC
@@ -725,30 +725,30 @@
// 0x3 -> xosc_clksrc
// 0x4 -> clksrc_gpin0
// 0x5 -> clksrc_gpin1
-#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET _U(0x0)
-#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS _U(0x000000e0)
-#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB _U(7)
-#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB _U(5)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS _u(0x000000e0)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB _u(7)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB _u(5)
#define CLOCKS_CLK_USB_CTRL_AUXSRC_ACCESS "RW"
-#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _U(0x0)
-#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _U(0x1)
-#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _U(0x2)
-#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _U(0x3)
-#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _U(0x4)
-#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _U(0x5)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5)
// =============================================================================
// Register : CLOCKS_CLK_USB_DIV
// Description : Clock divisor, can be changed on-the-fly
-#define CLOCKS_CLK_USB_DIV_OFFSET _U(0x00000058)
-#define CLOCKS_CLK_USB_DIV_BITS _U(0x00000300)
-#define CLOCKS_CLK_USB_DIV_RESET _U(0x00000100)
+#define CLOCKS_CLK_USB_DIV_OFFSET _u(0x00000058)
+#define CLOCKS_CLK_USB_DIV_BITS _u(0x00000300)
+#define CLOCKS_CLK_USB_DIV_RESET _u(0x00000100)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_USB_DIV_INT
// Description : Integer component of the divisor, 0 -> divide by 2^16
-#define CLOCKS_CLK_USB_DIV_INT_RESET _U(0x1)
-#define CLOCKS_CLK_USB_DIV_INT_BITS _U(0x00000300)
-#define CLOCKS_CLK_USB_DIV_INT_MSB _U(9)
-#define CLOCKS_CLK_USB_DIV_INT_LSB _U(8)
+#define CLOCKS_CLK_USB_DIV_INT_RESET _u(0x1)
+#define CLOCKS_CLK_USB_DIV_INT_BITS _u(0x00000300)
+#define CLOCKS_CLK_USB_DIV_INT_MSB _u(9)
+#define CLOCKS_CLK_USB_DIV_INT_LSB _u(8)
#define CLOCKS_CLK_USB_DIV_INT_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_CLK_USB_SELECTED
@@ -757,53 +757,53 @@
// This slice does not have a glitchless mux (only the AUX_SRC
// field is present, not SRC) so this register is hardwired to
// 0x1.
-#define CLOCKS_CLK_USB_SELECTED_OFFSET _U(0x0000005c)
-#define CLOCKS_CLK_USB_SELECTED_BITS _U(0xffffffff)
-#define CLOCKS_CLK_USB_SELECTED_RESET _U(0x00000001)
-#define CLOCKS_CLK_USB_SELECTED_MSB _U(31)
-#define CLOCKS_CLK_USB_SELECTED_LSB _U(0)
+#define CLOCKS_CLK_USB_SELECTED_OFFSET _u(0x0000005c)
+#define CLOCKS_CLK_USB_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_USB_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_USB_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_USB_SELECTED_LSB _u(0)
#define CLOCKS_CLK_USB_SELECTED_ACCESS "RO"
// =============================================================================
// Register : CLOCKS_CLK_ADC_CTRL
// Description : Clock control, can be changed on-the-fly (except for auxsrc)
-#define CLOCKS_CLK_ADC_CTRL_OFFSET _U(0x00000060)
-#define CLOCKS_CLK_ADC_CTRL_BITS _U(0x00130ce0)
-#define CLOCKS_CLK_ADC_CTRL_RESET _U(0x00000000)
+#define CLOCKS_CLK_ADC_CTRL_OFFSET _u(0x00000060)
+#define CLOCKS_CLK_ADC_CTRL_BITS _u(0x00130ce0)
+#define CLOCKS_CLK_ADC_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_ADC_CTRL_NUDGE
// Description : An edge on this signal shifts the phase of the output by 1
// cycle of the input clock
// This can be done at any time
-#define CLOCKS_CLK_ADC_CTRL_NUDGE_RESET _U(0x0)
-#define CLOCKS_CLK_ADC_CTRL_NUDGE_BITS _U(0x00100000)
-#define CLOCKS_CLK_ADC_CTRL_NUDGE_MSB _U(20)
-#define CLOCKS_CLK_ADC_CTRL_NUDGE_LSB _U(20)
+#define CLOCKS_CLK_ADC_CTRL_NUDGE_RESET _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_NUDGE_BITS _u(0x00100000)
+#define CLOCKS_CLK_ADC_CTRL_NUDGE_MSB _u(20)
+#define CLOCKS_CLK_ADC_CTRL_NUDGE_LSB _u(20)
#define CLOCKS_CLK_ADC_CTRL_NUDGE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_ADC_CTRL_PHASE
// Description : This delays the enable signal by up to 3 cycles of the input
// clock
// This must be set before the clock is enabled to have any effect
-#define CLOCKS_CLK_ADC_CTRL_PHASE_RESET _U(0x0)
-#define CLOCKS_CLK_ADC_CTRL_PHASE_BITS _U(0x00030000)
-#define CLOCKS_CLK_ADC_CTRL_PHASE_MSB _U(17)
-#define CLOCKS_CLK_ADC_CTRL_PHASE_LSB _U(16)
+#define CLOCKS_CLK_ADC_CTRL_PHASE_RESET _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_PHASE_BITS _u(0x00030000)
+#define CLOCKS_CLK_ADC_CTRL_PHASE_MSB _u(17)
+#define CLOCKS_CLK_ADC_CTRL_PHASE_LSB _u(16)
#define CLOCKS_CLK_ADC_CTRL_PHASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_ADC_CTRL_ENABLE
// Description : Starts and stops the clock generator cleanly
-#define CLOCKS_CLK_ADC_CTRL_ENABLE_RESET _U(0x0)
-#define CLOCKS_CLK_ADC_CTRL_ENABLE_BITS _U(0x00000800)
-#define CLOCKS_CLK_ADC_CTRL_ENABLE_MSB _U(11)
-#define CLOCKS_CLK_ADC_CTRL_ENABLE_LSB _U(11)
+#define CLOCKS_CLK_ADC_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_ENABLE_BITS _u(0x00000800)
+#define CLOCKS_CLK_ADC_CTRL_ENABLE_MSB _u(11)
+#define CLOCKS_CLK_ADC_CTRL_ENABLE_LSB _u(11)
#define CLOCKS_CLK_ADC_CTRL_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_ADC_CTRL_KILL
// Description : Asynchronously kills the clock generator
-#define CLOCKS_CLK_ADC_CTRL_KILL_RESET _U(0x0)
-#define CLOCKS_CLK_ADC_CTRL_KILL_BITS _U(0x00000400)
-#define CLOCKS_CLK_ADC_CTRL_KILL_MSB _U(10)
-#define CLOCKS_CLK_ADC_CTRL_KILL_LSB _U(10)
+#define CLOCKS_CLK_ADC_CTRL_KILL_RESET _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_KILL_BITS _u(0x00000400)
+#define CLOCKS_CLK_ADC_CTRL_KILL_MSB _u(10)
+#define CLOCKS_CLK_ADC_CTRL_KILL_LSB _u(10)
#define CLOCKS_CLK_ADC_CTRL_KILL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_ADC_CTRL_AUXSRC
@@ -814,30 +814,30 @@
// 0x3 -> xosc_clksrc
// 0x4 -> clksrc_gpin0
// 0x5 -> clksrc_gpin1
-#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET _U(0x0)
-#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS _U(0x000000e0)
-#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB _U(7)
-#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB _U(5)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS _u(0x000000e0)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB _u(7)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB _u(5)
#define CLOCKS_CLK_ADC_CTRL_AUXSRC_ACCESS "RW"
-#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _U(0x0)
-#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _U(0x1)
-#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _U(0x2)
-#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _U(0x3)
-#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _U(0x4)
-#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _U(0x5)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5)
// =============================================================================
// Register : CLOCKS_CLK_ADC_DIV
// Description : Clock divisor, can be changed on-the-fly
-#define CLOCKS_CLK_ADC_DIV_OFFSET _U(0x00000064)
-#define CLOCKS_CLK_ADC_DIV_BITS _U(0x00000300)
-#define CLOCKS_CLK_ADC_DIV_RESET _U(0x00000100)
+#define CLOCKS_CLK_ADC_DIV_OFFSET _u(0x00000064)
+#define CLOCKS_CLK_ADC_DIV_BITS _u(0x00000300)
+#define CLOCKS_CLK_ADC_DIV_RESET _u(0x00000100)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_ADC_DIV_INT
// Description : Integer component of the divisor, 0 -> divide by 2^16
-#define CLOCKS_CLK_ADC_DIV_INT_RESET _U(0x1)
-#define CLOCKS_CLK_ADC_DIV_INT_BITS _U(0x00000300)
-#define CLOCKS_CLK_ADC_DIV_INT_MSB _U(9)
-#define CLOCKS_CLK_ADC_DIV_INT_LSB _U(8)
+#define CLOCKS_CLK_ADC_DIV_INT_RESET _u(0x1)
+#define CLOCKS_CLK_ADC_DIV_INT_BITS _u(0x00000300)
+#define CLOCKS_CLK_ADC_DIV_INT_MSB _u(9)
+#define CLOCKS_CLK_ADC_DIV_INT_LSB _u(8)
#define CLOCKS_CLK_ADC_DIV_INT_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_CLK_ADC_SELECTED
@@ -846,53 +846,53 @@
// This slice does not have a glitchless mux (only the AUX_SRC
// field is present, not SRC) so this register is hardwired to
// 0x1.
-#define CLOCKS_CLK_ADC_SELECTED_OFFSET _U(0x00000068)
-#define CLOCKS_CLK_ADC_SELECTED_BITS _U(0xffffffff)
-#define CLOCKS_CLK_ADC_SELECTED_RESET _U(0x00000001)
-#define CLOCKS_CLK_ADC_SELECTED_MSB _U(31)
-#define CLOCKS_CLK_ADC_SELECTED_LSB _U(0)
+#define CLOCKS_CLK_ADC_SELECTED_OFFSET _u(0x00000068)
+#define CLOCKS_CLK_ADC_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_ADC_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_ADC_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_ADC_SELECTED_LSB _u(0)
#define CLOCKS_CLK_ADC_SELECTED_ACCESS "RO"
// =============================================================================
// Register : CLOCKS_CLK_RTC_CTRL
// Description : Clock control, can be changed on-the-fly (except for auxsrc)
-#define CLOCKS_CLK_RTC_CTRL_OFFSET _U(0x0000006c)
-#define CLOCKS_CLK_RTC_CTRL_BITS _U(0x00130ce0)
-#define CLOCKS_CLK_RTC_CTRL_RESET _U(0x00000000)
+#define CLOCKS_CLK_RTC_CTRL_OFFSET _u(0x0000006c)
+#define CLOCKS_CLK_RTC_CTRL_BITS _u(0x00130ce0)
+#define CLOCKS_CLK_RTC_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_RTC_CTRL_NUDGE
// Description : An edge on this signal shifts the phase of the output by 1
// cycle of the input clock
// This can be done at any time
-#define CLOCKS_CLK_RTC_CTRL_NUDGE_RESET _U(0x0)
-#define CLOCKS_CLK_RTC_CTRL_NUDGE_BITS _U(0x00100000)
-#define CLOCKS_CLK_RTC_CTRL_NUDGE_MSB _U(20)
-#define CLOCKS_CLK_RTC_CTRL_NUDGE_LSB _U(20)
+#define CLOCKS_CLK_RTC_CTRL_NUDGE_RESET _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_NUDGE_BITS _u(0x00100000)
+#define CLOCKS_CLK_RTC_CTRL_NUDGE_MSB _u(20)
+#define CLOCKS_CLK_RTC_CTRL_NUDGE_LSB _u(20)
#define CLOCKS_CLK_RTC_CTRL_NUDGE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_RTC_CTRL_PHASE
// Description : This delays the enable signal by up to 3 cycles of the input
// clock
// This must be set before the clock is enabled to have any effect
-#define CLOCKS_CLK_RTC_CTRL_PHASE_RESET _U(0x0)
-#define CLOCKS_CLK_RTC_CTRL_PHASE_BITS _U(0x00030000)
-#define CLOCKS_CLK_RTC_CTRL_PHASE_MSB _U(17)
-#define CLOCKS_CLK_RTC_CTRL_PHASE_LSB _U(16)
+#define CLOCKS_CLK_RTC_CTRL_PHASE_RESET _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_PHASE_BITS _u(0x00030000)
+#define CLOCKS_CLK_RTC_CTRL_PHASE_MSB _u(17)
+#define CLOCKS_CLK_RTC_CTRL_PHASE_LSB _u(16)
#define CLOCKS_CLK_RTC_CTRL_PHASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_RTC_CTRL_ENABLE
// Description : Starts and stops the clock generator cleanly
-#define CLOCKS_CLK_RTC_CTRL_ENABLE_RESET _U(0x0)
-#define CLOCKS_CLK_RTC_CTRL_ENABLE_BITS _U(0x00000800)
-#define CLOCKS_CLK_RTC_CTRL_ENABLE_MSB _U(11)
-#define CLOCKS_CLK_RTC_CTRL_ENABLE_LSB _U(11)
+#define CLOCKS_CLK_RTC_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_ENABLE_BITS _u(0x00000800)
+#define CLOCKS_CLK_RTC_CTRL_ENABLE_MSB _u(11)
+#define CLOCKS_CLK_RTC_CTRL_ENABLE_LSB _u(11)
#define CLOCKS_CLK_RTC_CTRL_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_RTC_CTRL_KILL
// Description : Asynchronously kills the clock generator
-#define CLOCKS_CLK_RTC_CTRL_KILL_RESET _U(0x0)
-#define CLOCKS_CLK_RTC_CTRL_KILL_BITS _U(0x00000400)
-#define CLOCKS_CLK_RTC_CTRL_KILL_MSB _U(10)
-#define CLOCKS_CLK_RTC_CTRL_KILL_LSB _U(10)
+#define CLOCKS_CLK_RTC_CTRL_KILL_RESET _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_KILL_BITS _u(0x00000400)
+#define CLOCKS_CLK_RTC_CTRL_KILL_MSB _u(10)
+#define CLOCKS_CLK_RTC_CTRL_KILL_LSB _u(10)
#define CLOCKS_CLK_RTC_CTRL_KILL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_RTC_CTRL_AUXSRC
@@ -903,38 +903,38 @@
// 0x3 -> xosc_clksrc
// 0x4 -> clksrc_gpin0
// 0x5 -> clksrc_gpin1
-#define CLOCKS_CLK_RTC_CTRL_AUXSRC_RESET _U(0x0)
-#define CLOCKS_CLK_RTC_CTRL_AUXSRC_BITS _U(0x000000e0)
-#define CLOCKS_CLK_RTC_CTRL_AUXSRC_MSB _U(7)
-#define CLOCKS_CLK_RTC_CTRL_AUXSRC_LSB _U(5)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_BITS _u(0x000000e0)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_MSB _u(7)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_LSB _u(5)
#define CLOCKS_CLK_RTC_CTRL_AUXSRC_ACCESS "RW"
-#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _U(0x0)
-#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _U(0x1)
-#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _U(0x2)
-#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _U(0x3)
-#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _U(0x4)
-#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _U(0x5)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5)
// =============================================================================
// Register : CLOCKS_CLK_RTC_DIV
// Description : Clock divisor, can be changed on-the-fly
-#define CLOCKS_CLK_RTC_DIV_OFFSET _U(0x00000070)
-#define CLOCKS_CLK_RTC_DIV_BITS _U(0xffffffff)
-#define CLOCKS_CLK_RTC_DIV_RESET _U(0x00000100)
+#define CLOCKS_CLK_RTC_DIV_OFFSET _u(0x00000070)
+#define CLOCKS_CLK_RTC_DIV_BITS _u(0xffffffff)
+#define CLOCKS_CLK_RTC_DIV_RESET _u(0x00000100)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_RTC_DIV_INT
// Description : Integer component of the divisor, 0 -> divide by 2^16
-#define CLOCKS_CLK_RTC_DIV_INT_RESET _U(0x000001)
-#define CLOCKS_CLK_RTC_DIV_INT_BITS _U(0xffffff00)
-#define CLOCKS_CLK_RTC_DIV_INT_MSB _U(31)
-#define CLOCKS_CLK_RTC_DIV_INT_LSB _U(8)
+#define CLOCKS_CLK_RTC_DIV_INT_RESET _u(0x000001)
+#define CLOCKS_CLK_RTC_DIV_INT_BITS _u(0xffffff00)
+#define CLOCKS_CLK_RTC_DIV_INT_MSB _u(31)
+#define CLOCKS_CLK_RTC_DIV_INT_LSB _u(8)
#define CLOCKS_CLK_RTC_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_RTC_DIV_FRAC
// Description : Fractional component of the divisor
-#define CLOCKS_CLK_RTC_DIV_FRAC_RESET _U(0x00)
-#define CLOCKS_CLK_RTC_DIV_FRAC_BITS _U(0x000000ff)
-#define CLOCKS_CLK_RTC_DIV_FRAC_MSB _U(7)
-#define CLOCKS_CLK_RTC_DIV_FRAC_LSB _U(0)
+#define CLOCKS_CLK_RTC_DIV_FRAC_RESET _u(0x00)
+#define CLOCKS_CLK_RTC_DIV_FRAC_BITS _u(0x000000ff)
+#define CLOCKS_CLK_RTC_DIV_FRAC_MSB _u(7)
+#define CLOCKS_CLK_RTC_DIV_FRAC_LSB _u(0)
#define CLOCKS_CLK_RTC_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_CLK_RTC_SELECTED
@@ -943,117 +943,117 @@
// This slice does not have a glitchless mux (only the AUX_SRC
// field is present, not SRC) so this register is hardwired to
// 0x1.
-#define CLOCKS_CLK_RTC_SELECTED_OFFSET _U(0x00000074)
-#define CLOCKS_CLK_RTC_SELECTED_BITS _U(0xffffffff)
-#define CLOCKS_CLK_RTC_SELECTED_RESET _U(0x00000001)
-#define CLOCKS_CLK_RTC_SELECTED_MSB _U(31)
-#define CLOCKS_CLK_RTC_SELECTED_LSB _U(0)
+#define CLOCKS_CLK_RTC_SELECTED_OFFSET _u(0x00000074)
+#define CLOCKS_CLK_RTC_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_RTC_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_RTC_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_RTC_SELECTED_LSB _u(0)
#define CLOCKS_CLK_RTC_SELECTED_ACCESS "RO"
// =============================================================================
// Register : CLOCKS_CLK_SYS_RESUS_CTRL
// Description : None
-#define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET _U(0x00000078)
-#define CLOCKS_CLK_SYS_RESUS_CTRL_BITS _U(0x000111ff)
-#define CLOCKS_CLK_SYS_RESUS_CTRL_RESET _U(0x000000ff)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET _u(0x00000078)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_BITS _u(0x000111ff)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_RESET _u(0x000000ff)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR
// Description : For clearing the resus after the fault that triggered it has
// been corrected
-#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_RESET _U(0x0)
-#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS _U(0x00010000)
-#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_MSB _U(16)
-#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_LSB _U(16)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_RESET _u(0x0)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS _u(0x00010000)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_MSB _u(16)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_LSB _u(16)
#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_SYS_RESUS_CTRL_FRCE
// Description : Force a resus, for test purposes only
-#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_RESET _U(0x0)
-#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_BITS _U(0x00001000)
-#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_MSB _U(12)
-#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_LSB _U(12)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_RESET _u(0x0)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_BITS _u(0x00001000)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_MSB _u(12)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_LSB _u(12)
#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE
// Description : Enable resus
-#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_RESET _U(0x0)
-#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS _U(0x00000100)
-#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_MSB _U(8)
-#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_LSB _U(8)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS _u(0x00000100)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_MSB _u(8)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_LSB _u(8)
#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT
// Description : This is expressed as a number of clk_ref cycles
// and must be >= 2x clk_ref_freq/min_clk_tst_freq
-#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_RESET _U(0xff)
-#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_BITS _U(0x000000ff)
-#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MSB _U(7)
-#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_LSB _U(0)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_RESET _u(0xff)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_BITS _u(0x000000ff)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MSB _u(7)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_LSB _u(0)
#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_CLK_SYS_RESUS_STATUS
// Description : None
-#define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET _U(0x0000007c)
-#define CLOCKS_CLK_SYS_RESUS_STATUS_BITS _U(0x00000001)
-#define CLOCKS_CLK_SYS_RESUS_STATUS_RESET _U(0x00000000)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET _u(0x0000007c)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_BITS _u(0x00000001)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED
// Description : Clock has been resuscitated, correct the error then send
// ctrl_clear=1
-#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_RESET _U(0x0)
-#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS _U(0x00000001)
-#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_MSB _U(0)
-#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_LSB _U(0)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_RESET _u(0x0)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS _u(0x00000001)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_MSB _u(0)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_LSB _u(0)
#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_ACCESS "RO"
// =============================================================================
// Register : CLOCKS_FC0_REF_KHZ
// Description : Reference clock frequency in kHz
-#define CLOCKS_FC0_REF_KHZ_OFFSET _U(0x00000080)
-#define CLOCKS_FC0_REF_KHZ_BITS _U(0x000fffff)
-#define CLOCKS_FC0_REF_KHZ_RESET _U(0x00000000)
-#define CLOCKS_FC0_REF_KHZ_MSB _U(19)
-#define CLOCKS_FC0_REF_KHZ_LSB _U(0)
+#define CLOCKS_FC0_REF_KHZ_OFFSET _u(0x00000080)
+#define CLOCKS_FC0_REF_KHZ_BITS _u(0x000fffff)
+#define CLOCKS_FC0_REF_KHZ_RESET _u(0x00000000)
+#define CLOCKS_FC0_REF_KHZ_MSB _u(19)
+#define CLOCKS_FC0_REF_KHZ_LSB _u(0)
#define CLOCKS_FC0_REF_KHZ_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_FC0_MIN_KHZ
// Description : Minimum pass frequency in kHz. This is optional. Set to 0 if
// you are not using the pass/fail flags
-#define CLOCKS_FC0_MIN_KHZ_OFFSET _U(0x00000084)
-#define CLOCKS_FC0_MIN_KHZ_BITS _U(0x01ffffff)
-#define CLOCKS_FC0_MIN_KHZ_RESET _U(0x00000000)
-#define CLOCKS_FC0_MIN_KHZ_MSB _U(24)
-#define CLOCKS_FC0_MIN_KHZ_LSB _U(0)
+#define CLOCKS_FC0_MIN_KHZ_OFFSET _u(0x00000084)
+#define CLOCKS_FC0_MIN_KHZ_BITS _u(0x01ffffff)
+#define CLOCKS_FC0_MIN_KHZ_RESET _u(0x00000000)
+#define CLOCKS_FC0_MIN_KHZ_MSB _u(24)
+#define CLOCKS_FC0_MIN_KHZ_LSB _u(0)
#define CLOCKS_FC0_MIN_KHZ_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_FC0_MAX_KHZ
// Description : Maximum pass frequency in kHz. This is optional. Set to
// 0x1ffffff if you are not using the pass/fail flags
-#define CLOCKS_FC0_MAX_KHZ_OFFSET _U(0x00000088)
-#define CLOCKS_FC0_MAX_KHZ_BITS _U(0x01ffffff)
-#define CLOCKS_FC0_MAX_KHZ_RESET _U(0x01ffffff)
-#define CLOCKS_FC0_MAX_KHZ_MSB _U(24)
-#define CLOCKS_FC0_MAX_KHZ_LSB _U(0)
+#define CLOCKS_FC0_MAX_KHZ_OFFSET _u(0x00000088)
+#define CLOCKS_FC0_MAX_KHZ_BITS _u(0x01ffffff)
+#define CLOCKS_FC0_MAX_KHZ_RESET _u(0x01ffffff)
+#define CLOCKS_FC0_MAX_KHZ_MSB _u(24)
+#define CLOCKS_FC0_MAX_KHZ_LSB _u(0)
#define CLOCKS_FC0_MAX_KHZ_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_FC0_DELAY
// Description : Delays the start of frequency counting to allow the mux to
// settle
// Delay is measured in multiples of the reference clock period
-#define CLOCKS_FC0_DELAY_OFFSET _U(0x0000008c)
-#define CLOCKS_FC0_DELAY_BITS _U(0x00000007)
-#define CLOCKS_FC0_DELAY_RESET _U(0x00000001)
-#define CLOCKS_FC0_DELAY_MSB _U(2)
-#define CLOCKS_FC0_DELAY_LSB _U(0)
+#define CLOCKS_FC0_DELAY_OFFSET _u(0x0000008c)
+#define CLOCKS_FC0_DELAY_BITS _u(0x00000007)
+#define CLOCKS_FC0_DELAY_RESET _u(0x00000001)
+#define CLOCKS_FC0_DELAY_MSB _u(2)
+#define CLOCKS_FC0_DELAY_LSB _u(0)
#define CLOCKS_FC0_DELAY_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_FC0_INTERVAL
// Description : The test interval is 0.98us * 2**interval, but let's call it
// 1us * 2**interval
// The default gives a test interval of 250us
-#define CLOCKS_FC0_INTERVAL_OFFSET _U(0x00000090)
-#define CLOCKS_FC0_INTERVAL_BITS _U(0x0000000f)
-#define CLOCKS_FC0_INTERVAL_RESET _U(0x00000008)
-#define CLOCKS_FC0_INTERVAL_MSB _U(3)
-#define CLOCKS_FC0_INTERVAL_LSB _U(0)
+#define CLOCKS_FC0_INTERVAL_OFFSET _u(0x00000090)
+#define CLOCKS_FC0_INTERVAL_BITS _u(0x0000000f)
+#define CLOCKS_FC0_INTERVAL_RESET _u(0x00000008)
+#define CLOCKS_FC0_INTERVAL_MSB _u(3)
+#define CLOCKS_FC0_INTERVAL_LSB _u(0)
#define CLOCKS_FC0_INTERVAL_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_FC0_SRC
@@ -1073,1337 +1073,1337 @@
// 0x0b -> clk_usb
// 0x0c -> clk_adc
// 0x0d -> clk_rtc
-#define CLOCKS_FC0_SRC_OFFSET _U(0x00000094)
-#define CLOCKS_FC0_SRC_BITS _U(0x000000ff)
-#define CLOCKS_FC0_SRC_RESET _U(0x00000000)
-#define CLOCKS_FC0_SRC_MSB _U(7)
-#define CLOCKS_FC0_SRC_LSB _U(0)
+#define CLOCKS_FC0_SRC_OFFSET _u(0x00000094)
+#define CLOCKS_FC0_SRC_BITS _u(0x000000ff)
+#define CLOCKS_FC0_SRC_RESET _u(0x00000000)
+#define CLOCKS_FC0_SRC_MSB _u(7)
+#define CLOCKS_FC0_SRC_LSB _u(0)
#define CLOCKS_FC0_SRC_ACCESS "RW"
-#define CLOCKS_FC0_SRC_VALUE_NULL _U(0x00)
-#define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY _U(0x01)
-#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY _U(0x02)
-#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC _U(0x03)
-#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH _U(0x04)
-#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC _U(0x05)
-#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 _U(0x06)
-#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 _U(0x07)
-#define CLOCKS_FC0_SRC_VALUE_CLK_REF _U(0x08)
-#define CLOCKS_FC0_SRC_VALUE_CLK_SYS _U(0x09)
-#define CLOCKS_FC0_SRC_VALUE_CLK_PERI _U(0x0a)
-#define CLOCKS_FC0_SRC_VALUE_CLK_USB _U(0x0b)
-#define CLOCKS_FC0_SRC_VALUE_CLK_ADC _U(0x0c)
-#define CLOCKS_FC0_SRC_VALUE_CLK_RTC _U(0x0d)
+#define CLOCKS_FC0_SRC_VALUE_NULL _u(0x00)
+#define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY _u(0x01)
+#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY _u(0x02)
+#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC _u(0x03)
+#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH _u(0x04)
+#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC _u(0x05)
+#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 _u(0x06)
+#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 _u(0x07)
+#define CLOCKS_FC0_SRC_VALUE_CLK_REF _u(0x08)
+#define CLOCKS_FC0_SRC_VALUE_CLK_SYS _u(0x09)
+#define CLOCKS_FC0_SRC_VALUE_CLK_PERI _u(0x0a)
+#define CLOCKS_FC0_SRC_VALUE_CLK_USB _u(0x0b)
+#define CLOCKS_FC0_SRC_VALUE_CLK_ADC _u(0x0c)
+#define CLOCKS_FC0_SRC_VALUE_CLK_RTC _u(0x0d)
// =============================================================================
// Register : CLOCKS_FC0_STATUS
// Description : Frequency counter status
-#define CLOCKS_FC0_STATUS_OFFSET _U(0x00000098)
-#define CLOCKS_FC0_STATUS_BITS _U(0x11111111)
-#define CLOCKS_FC0_STATUS_RESET _U(0x00000000)
+#define CLOCKS_FC0_STATUS_OFFSET _u(0x00000098)
+#define CLOCKS_FC0_STATUS_BITS _u(0x11111111)
+#define CLOCKS_FC0_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_FC0_STATUS_DIED
// Description : Test clock stopped during test
-#define CLOCKS_FC0_STATUS_DIED_RESET _U(0x0)
-#define CLOCKS_FC0_STATUS_DIED_BITS _U(0x10000000)
-#define CLOCKS_FC0_STATUS_DIED_MSB _U(28)
-#define CLOCKS_FC0_STATUS_DIED_LSB _U(28)
+#define CLOCKS_FC0_STATUS_DIED_RESET _u(0x0)
+#define CLOCKS_FC0_STATUS_DIED_BITS _u(0x10000000)
+#define CLOCKS_FC0_STATUS_DIED_MSB _u(28)
+#define CLOCKS_FC0_STATUS_DIED_LSB _u(28)
#define CLOCKS_FC0_STATUS_DIED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_FC0_STATUS_FAST
// Description : Test clock faster than expected, only valid when status_done=1
-#define CLOCKS_FC0_STATUS_FAST_RESET _U(0x0)
-#define CLOCKS_FC0_STATUS_FAST_BITS _U(0x01000000)
-#define CLOCKS_FC0_STATUS_FAST_MSB _U(24)
-#define CLOCKS_FC0_STATUS_FAST_LSB _U(24)
+#define CLOCKS_FC0_STATUS_FAST_RESET _u(0x0)
+#define CLOCKS_FC0_STATUS_FAST_BITS _u(0x01000000)
+#define CLOCKS_FC0_STATUS_FAST_MSB _u(24)
+#define CLOCKS_FC0_STATUS_FAST_LSB _u(24)
#define CLOCKS_FC0_STATUS_FAST_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_FC0_STATUS_SLOW
// Description : Test clock slower than expected, only valid when status_done=1
-#define CLOCKS_FC0_STATUS_SLOW_RESET _U(0x0)
-#define CLOCKS_FC0_STATUS_SLOW_BITS _U(0x00100000)
-#define CLOCKS_FC0_STATUS_SLOW_MSB _U(20)
-#define CLOCKS_FC0_STATUS_SLOW_LSB _U(20)
+#define CLOCKS_FC0_STATUS_SLOW_RESET _u(0x0)
+#define CLOCKS_FC0_STATUS_SLOW_BITS _u(0x00100000)
+#define CLOCKS_FC0_STATUS_SLOW_MSB _u(20)
+#define CLOCKS_FC0_STATUS_SLOW_LSB _u(20)
#define CLOCKS_FC0_STATUS_SLOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_FC0_STATUS_FAIL
// Description : Test failed
-#define CLOCKS_FC0_STATUS_FAIL_RESET _U(0x0)
-#define CLOCKS_FC0_STATUS_FAIL_BITS _U(0x00010000)
-#define CLOCKS_FC0_STATUS_FAIL_MSB _U(16)
-#define CLOCKS_FC0_STATUS_FAIL_LSB _U(16)
+#define CLOCKS_FC0_STATUS_FAIL_RESET _u(0x0)
+#define CLOCKS_FC0_STATUS_FAIL_BITS _u(0x00010000)
+#define CLOCKS_FC0_STATUS_FAIL_MSB _u(16)
+#define CLOCKS_FC0_STATUS_FAIL_LSB _u(16)
#define CLOCKS_FC0_STATUS_FAIL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_FC0_STATUS_WAITING
// Description : Waiting for test clock to start
-#define CLOCKS_FC0_STATUS_WAITING_RESET _U(0x0)
-#define CLOCKS_FC0_STATUS_WAITING_BITS _U(0x00001000)
-#define CLOCKS_FC0_STATUS_WAITING_MSB _U(12)
-#define CLOCKS_FC0_STATUS_WAITING_LSB _U(12)
+#define CLOCKS_FC0_STATUS_WAITING_RESET _u(0x0)
+#define CLOCKS_FC0_STATUS_WAITING_BITS _u(0x00001000)
+#define CLOCKS_FC0_STATUS_WAITING_MSB _u(12)
+#define CLOCKS_FC0_STATUS_WAITING_LSB _u(12)
#define CLOCKS_FC0_STATUS_WAITING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_FC0_STATUS_RUNNING
// Description : Test running
-#define CLOCKS_FC0_STATUS_RUNNING_RESET _U(0x0)
-#define CLOCKS_FC0_STATUS_RUNNING_BITS _U(0x00000100)
-#define CLOCKS_FC0_STATUS_RUNNING_MSB _U(8)
-#define CLOCKS_FC0_STATUS_RUNNING_LSB _U(8)
+#define CLOCKS_FC0_STATUS_RUNNING_RESET _u(0x0)
+#define CLOCKS_FC0_STATUS_RUNNING_BITS _u(0x00000100)
+#define CLOCKS_FC0_STATUS_RUNNING_MSB _u(8)
+#define CLOCKS_FC0_STATUS_RUNNING_LSB _u(8)
#define CLOCKS_FC0_STATUS_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_FC0_STATUS_DONE
// Description : Test complete
-#define CLOCKS_FC0_STATUS_DONE_RESET _U(0x0)
-#define CLOCKS_FC0_STATUS_DONE_BITS _U(0x00000010)
-#define CLOCKS_FC0_STATUS_DONE_MSB _U(4)
-#define CLOCKS_FC0_STATUS_DONE_LSB _U(4)
+#define CLOCKS_FC0_STATUS_DONE_RESET _u(0x0)
+#define CLOCKS_FC0_STATUS_DONE_BITS _u(0x00000010)
+#define CLOCKS_FC0_STATUS_DONE_MSB _u(4)
+#define CLOCKS_FC0_STATUS_DONE_LSB _u(4)
#define CLOCKS_FC0_STATUS_DONE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_FC0_STATUS_PASS
// Description : Test passed
-#define CLOCKS_FC0_STATUS_PASS_RESET _U(0x0)
-#define CLOCKS_FC0_STATUS_PASS_BITS _U(0x00000001)
-#define CLOCKS_FC0_STATUS_PASS_MSB _U(0)
-#define CLOCKS_FC0_STATUS_PASS_LSB _U(0)
+#define CLOCKS_FC0_STATUS_PASS_RESET _u(0x0)
+#define CLOCKS_FC0_STATUS_PASS_BITS _u(0x00000001)
+#define CLOCKS_FC0_STATUS_PASS_MSB _u(0)
+#define CLOCKS_FC0_STATUS_PASS_LSB _u(0)
#define CLOCKS_FC0_STATUS_PASS_ACCESS "RO"
// =============================================================================
// Register : CLOCKS_FC0_RESULT
// Description : Result of frequency measurement, only valid when status_done=1
-#define CLOCKS_FC0_RESULT_OFFSET _U(0x0000009c)
-#define CLOCKS_FC0_RESULT_BITS _U(0x3fffffff)
-#define CLOCKS_FC0_RESULT_RESET _U(0x00000000)
+#define CLOCKS_FC0_RESULT_OFFSET _u(0x0000009c)
+#define CLOCKS_FC0_RESULT_BITS _u(0x3fffffff)
+#define CLOCKS_FC0_RESULT_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_FC0_RESULT_KHZ
// Description : None
-#define CLOCKS_FC0_RESULT_KHZ_RESET _U(0x0000000)
-#define CLOCKS_FC0_RESULT_KHZ_BITS _U(0x3fffffe0)
-#define CLOCKS_FC0_RESULT_KHZ_MSB _U(29)
-#define CLOCKS_FC0_RESULT_KHZ_LSB _U(5)
+#define CLOCKS_FC0_RESULT_KHZ_RESET _u(0x0000000)
+#define CLOCKS_FC0_RESULT_KHZ_BITS _u(0x3fffffe0)
+#define CLOCKS_FC0_RESULT_KHZ_MSB _u(29)
+#define CLOCKS_FC0_RESULT_KHZ_LSB _u(5)
#define CLOCKS_FC0_RESULT_KHZ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_FC0_RESULT_FRAC
// Description : None
-#define CLOCKS_FC0_RESULT_FRAC_RESET _U(0x00)
-#define CLOCKS_FC0_RESULT_FRAC_BITS _U(0x0000001f)
-#define CLOCKS_FC0_RESULT_FRAC_MSB _U(4)
-#define CLOCKS_FC0_RESULT_FRAC_LSB _U(0)
+#define CLOCKS_FC0_RESULT_FRAC_RESET _u(0x00)
+#define CLOCKS_FC0_RESULT_FRAC_BITS _u(0x0000001f)
+#define CLOCKS_FC0_RESULT_FRAC_MSB _u(4)
+#define CLOCKS_FC0_RESULT_FRAC_LSB _u(0)
#define CLOCKS_FC0_RESULT_FRAC_ACCESS "RO"
// =============================================================================
// Register : CLOCKS_WAKE_EN0
// Description : enable clock in wake mode
-#define CLOCKS_WAKE_EN0_OFFSET _U(0x000000a0)
-#define CLOCKS_WAKE_EN0_BITS _U(0xffffffff)
-#define CLOCKS_WAKE_EN0_RESET _U(0xffffffff)
+#define CLOCKS_WAKE_EN0_OFFSET _u(0x000000a0)
+#define CLOCKS_WAKE_EN0_BITS _u(0xffffffff)
+#define CLOCKS_WAKE_EN0_RESET _u(0xffffffff)
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM3
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_BITS _U(0x80000000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_MSB _U(31)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_LSB _U(31)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_BITS _u(0x80000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_MSB _u(31)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_LSB _u(31)
#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM2
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_BITS _U(0x40000000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_MSB _U(30)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_LSB _U(30)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_BITS _u(0x40000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_MSB _u(30)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_LSB _u(30)
#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM1
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_BITS _U(0x20000000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_MSB _U(29)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_LSB _U(29)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_BITS _u(0x20000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_MSB _u(29)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_LSB _u(29)
#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM0
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_BITS _U(0x10000000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_MSB _U(28)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_LSB _U(28)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_BITS _u(0x10000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_MSB _u(28)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_LSB _u(28)
#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI1
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS _U(0x08000000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_MSB _U(27)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_LSB _U(27)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS _u(0x08000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_MSB _u(27)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_LSB _u(27)
#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI1
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS _U(0x04000000)
-#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_MSB _U(26)
-#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_LSB _U(26)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS _u(0x04000000)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_MSB _u(26)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_LSB _u(26)
#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI0
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS _U(0x02000000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_MSB _U(25)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_LSB _U(25)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS _u(0x02000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_MSB _u(25)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_LSB _u(25)
#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI0
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS _U(0x01000000)
-#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_MSB _U(24)
-#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_LSB _U(24)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS _u(0x01000000)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_MSB _u(24)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_LSB _u(24)
#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_SIO
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS _U(0x00800000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB _U(23)
-#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_LSB _U(23)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS _u(0x00800000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB _u(23)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_LSB _u(23)
#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_RTC
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_BITS _U(0x00400000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_MSB _U(22)
-#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_LSB _U(22)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_BITS _u(0x00400000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_MSB _u(22)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_LSB _u(22)
#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_RTC_RTC
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_BITS _U(0x00200000)
-#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_MSB _U(21)
-#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_LSB _U(21)
+#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_BITS _u(0x00200000)
+#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_MSB _u(21)
+#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_LSB _u(21)
#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_ROSC
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS _U(0x00100000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB _U(20)
-#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_LSB _U(20)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS _u(0x00100000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB _u(20)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_LSB _u(20)
#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_ROM
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS _U(0x00080000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB _U(19)
-#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_LSB _U(19)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS _u(0x00080000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB _u(19)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_LSB _u(19)
#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_RESETS
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS _U(0x00040000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB _U(18)
-#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_LSB _U(18)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS _u(0x00040000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB _u(18)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_LSB _u(18)
#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_PWM
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS _U(0x00020000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB _U(17)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_LSB _U(17)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS _u(0x00020000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB _u(17)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_LSB _u(17)
#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_PSM
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS _U(0x00010000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB _U(16)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_LSB _U(16)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS _u(0x00010000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB _u(16)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_LSB _u(16)
#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS _U(0x00008000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB _U(15)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_LSB _U(15)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS _u(0x00008000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB _u(15)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_LSB _u(15)
#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS _U(0x00004000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB _U(14)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_LSB _U(14)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00004000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB _u(14)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_LSB _u(14)
#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO1
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS _U(0x00002000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB _U(13)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_LSB _U(13)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS _u(0x00002000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB _u(13)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_LSB _u(13)
#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO0
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS _U(0x00001000)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB _U(12)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_LSB _U(12)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS _u(0x00001000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB _u(12)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_LSB _u(12)
#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_PADS
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS _U(0x00000800)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB _U(11)
-#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_LSB _U(11)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS _u(0x00000800)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB _u(11)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_LSB _u(11)
#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _U(0x00000400)
-#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _U(10)
-#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _U(10)
+#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400)
+#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10)
+#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _u(10)
#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_JTAG
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS _U(0x00000200)
-#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB _U(9)
-#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_LSB _U(9)
+#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS _u(0x00000200)
+#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB _u(9)
+#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_LSB _u(9)
#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_IO
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS _U(0x00000100)
-#define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB _U(8)
-#define CLOCKS_WAKE_EN0_CLK_SYS_IO_LSB _U(8)
+#define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS _u(0x00000100)
+#define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB _u(8)
+#define CLOCKS_WAKE_EN0_CLK_SYS_IO_LSB _u(8)
#define CLOCKS_WAKE_EN0_CLK_SYS_IO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C1
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS _U(0x00000080)
-#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB _U(7)
-#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_LSB _U(7)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS _u(0x00000080)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB _u(7)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_LSB _u(7)
#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C0
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS _U(0x00000040)
-#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB _U(6)
-#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_LSB _U(6)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS _u(0x00000040)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB _u(6)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_LSB _u(6)
#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_DMA
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS _U(0x00000020)
-#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB _U(5)
-#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_LSB _U(5)
+#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS _u(0x00000020)
+#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB _u(5)
+#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_LSB _u(5)
#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS _U(0x00000010)
-#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB _U(4)
-#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_LSB _U(4)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB _u(4)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_LSB _u(4)
#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS _U(0x00000008)
-#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB _U(3)
-#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_LSB _U(3)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000008)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB _u(3)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_LSB _u(3)
#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_ADC
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS _U(0x00000004)
-#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB _U(2)
-#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_LSB _U(2)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS _u(0x00000004)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB _u(2)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_LSB _u(2)
#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_ADC_ADC
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_BITS _U(0x00000002)
-#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_MSB _U(1)
-#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_LSB _U(1)
+#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_BITS _u(0x00000002)
+#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_MSB _u(1)
+#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_LSB _u(1)
#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS
// Description : None
-#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET _U(0x1)
-#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS _U(0x00000001)
-#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB _U(0)
-#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_LSB _U(0)
+#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001)
+#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB _u(0)
+#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_LSB _u(0)
#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_WAKE_EN1
// Description : enable clock in wake mode
-#define CLOCKS_WAKE_EN1_OFFSET _U(0x000000a4)
-#define CLOCKS_WAKE_EN1_BITS _U(0x00007fff)
-#define CLOCKS_WAKE_EN1_RESET _U(0x00007fff)
+#define CLOCKS_WAKE_EN1_OFFSET _u(0x000000a4)
+#define CLOCKS_WAKE_EN1_BITS _u(0x00007fff)
+#define CLOCKS_WAKE_EN1_RESET _u(0x00007fff)
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN1_CLK_SYS_XOSC
// Description : None
-#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET _U(0x1)
-#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS _U(0x00004000)
-#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB _U(14)
-#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_LSB _U(14)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS _u(0x00004000)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB _u(14)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_LSB _u(14)
#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN1_CLK_SYS_XIP
// Description : None
-#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET _U(0x1)
-#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS _U(0x00002000)
-#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB _U(13)
-#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_LSB _U(13)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS _u(0x00002000)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB _u(13)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_LSB _u(13)
#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG
// Description : None
-#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET _U(0x1)
-#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS _U(0x00001000)
-#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB _U(12)
-#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_LSB _U(12)
+#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS _u(0x00001000)
+#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB _u(12)
+#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_LSB _u(12)
#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN1_CLK_USB_USBCTRL
// Description : None
-#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_RESET _U(0x1)
-#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_BITS _U(0x00000800)
-#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_MSB _U(11)
-#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_LSB _U(11)
+#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_BITS _u(0x00000800)
+#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_MSB _u(11)
+#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_LSB _u(11)
#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL
// Description : None
-#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET _U(0x1)
-#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS _U(0x00000400)
-#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB _U(10)
-#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_LSB _U(10)
+#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS _u(0x00000400)
+#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB _u(10)
+#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_LSB _u(10)
#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN1_CLK_SYS_UART1
// Description : None
-#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET _U(0x1)
-#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS _U(0x00000200)
-#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB _U(9)
-#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_LSB _U(9)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS _u(0x00000200)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB _u(9)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_LSB _u(9)
#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN1_CLK_PERI_UART1
// Description : None
-#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET _U(0x1)
-#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS _U(0x00000100)
-#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB _U(8)
-#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_LSB _U(8)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS _u(0x00000100)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB _u(8)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_LSB _u(8)
#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN1_CLK_SYS_UART0
// Description : None
-#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET _U(0x1)
-#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS _U(0x00000080)
-#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB _U(7)
-#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_LSB _U(7)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS _u(0x00000080)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB _u(7)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_LSB _u(7)
#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN1_CLK_PERI_UART0
// Description : None
-#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET _U(0x1)
-#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS _U(0x00000040)
-#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB _U(6)
-#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_LSB _U(6)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS _u(0x00000040)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB _u(6)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_LSB _u(6)
#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN1_CLK_SYS_TIMER
// Description : None
-#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_RESET _U(0x1)
-#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_BITS _U(0x00000020)
-#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_MSB _U(5)
-#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_LSB _U(5)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_BITS _u(0x00000020)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_MSB _u(5)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_LSB _u(5)
#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN1_CLK_SYS_TBMAN
// Description : None
-#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET _U(0x1)
-#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS _U(0x00000010)
-#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB _U(4)
-#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_LSB _U(4)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS _u(0x00000010)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB _u(4)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_LSB _u(4)
#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO
// Description : None
-#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET _U(0x1)
-#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS _U(0x00000008)
-#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB _U(3)
-#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_LSB _U(3)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS _u(0x00000008)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB _u(3)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_LSB _u(3)
#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG
// Description : None
-#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET _U(0x1)
-#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS _U(0x00000004)
-#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB _U(2)
-#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_LSB _U(2)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS _u(0x00000004)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB _u(2)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_LSB _u(2)
#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM5
// Description : None
-#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET _U(0x1)
-#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS _U(0x00000002)
-#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB _U(1)
-#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_LSB _U(1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS _u(0x00000002)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB _u(1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_LSB _u(1)
#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM4
// Description : None
-#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET _U(0x1)
-#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS _U(0x00000001)
-#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB _U(0)
-#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_LSB _U(0)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS _u(0x00000001)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB _u(0)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_LSB _u(0)
#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_SLEEP_EN0
// Description : enable clock in sleep mode
-#define CLOCKS_SLEEP_EN0_OFFSET _U(0x000000a8)
-#define CLOCKS_SLEEP_EN0_BITS _U(0xffffffff)
-#define CLOCKS_SLEEP_EN0_RESET _U(0xffffffff)
+#define CLOCKS_SLEEP_EN0_OFFSET _u(0x000000a8)
+#define CLOCKS_SLEEP_EN0_BITS _u(0xffffffff)
+#define CLOCKS_SLEEP_EN0_RESET _u(0xffffffff)
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_BITS _U(0x80000000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_MSB _U(31)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_LSB _U(31)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_BITS _u(0x80000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_MSB _u(31)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_LSB _u(31)
#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_BITS _U(0x40000000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_MSB _U(30)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_LSB _U(30)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_BITS _u(0x40000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_MSB _u(30)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_LSB _u(30)
#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_BITS _U(0x20000000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_MSB _U(29)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_LSB _U(29)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_BITS _u(0x20000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_MSB _u(29)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_LSB _u(29)
#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_BITS _U(0x10000000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_MSB _U(28)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_LSB _U(28)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_BITS _u(0x10000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_MSB _u(28)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_LSB _u(28)
#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI1
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS _U(0x08000000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_MSB _U(27)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_LSB _U(27)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS _u(0x08000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_MSB _u(27)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_LSB _u(27)
#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI1
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS _U(0x04000000)
-#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_MSB _U(26)
-#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_LSB _U(26)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS _u(0x04000000)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_MSB _u(26)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_LSB _u(26)
#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI0
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS _U(0x02000000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_MSB _U(25)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_LSB _U(25)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS _u(0x02000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_MSB _u(25)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_LSB _u(25)
#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI0
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS _U(0x01000000)
-#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_MSB _U(24)
-#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_LSB _U(24)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS _u(0x01000000)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_MSB _u(24)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_LSB _u(24)
#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SIO
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS _U(0x00800000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB _U(23)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_LSB _U(23)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS _u(0x00800000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB _u(23)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_LSB _u(23)
#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_RTC
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_BITS _U(0x00400000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_MSB _U(22)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_LSB _U(22)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_BITS _u(0x00400000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_MSB _u(22)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_LSB _u(22)
#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_RTC_RTC
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_BITS _U(0x00200000)
-#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_MSB _U(21)
-#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_LSB _U(21)
+#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_BITS _u(0x00200000)
+#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_MSB _u(21)
+#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_LSB _u(21)
#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROSC
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS _U(0x00100000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB _U(20)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_LSB _U(20)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS _u(0x00100000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB _u(20)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_LSB _u(20)
#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROM
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS _U(0x00080000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB _U(19)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_LSB _U(19)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS _u(0x00080000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB _u(19)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_LSB _u(19)
#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_RESETS
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS _U(0x00040000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB _U(18)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_LSB _U(18)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS _u(0x00040000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB _u(18)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_LSB _u(18)
#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PWM
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS _U(0x00020000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB _U(17)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_LSB _U(17)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS _u(0x00020000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB _u(17)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_LSB _u(17)
#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PSM
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS _U(0x00010000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB _U(16)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_LSB _U(16)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS _u(0x00010000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB _u(16)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_LSB _u(16)
#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS _U(0x00008000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB _U(15)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_LSB _U(15)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS _u(0x00008000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB _u(15)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_LSB _u(15)
#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS _U(0x00004000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB _U(14)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_LSB _U(14)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00004000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB _u(14)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_LSB _u(14)
#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO1
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS _U(0x00002000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB _U(13)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_LSB _U(13)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS _u(0x00002000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB _u(13)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_LSB _u(13)
#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO0
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS _U(0x00001000)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB _U(12)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_LSB _U(12)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS _u(0x00001000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB _u(12)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_LSB _u(12)
#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PADS
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS _U(0x00000800)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB _U(11)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_LSB _U(11)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS _u(0x00000800)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB _u(11)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_LSB _u(11)
#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _U(0x00000400)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _U(10)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _U(10)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _u(10)
#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_JTAG
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS _U(0x00000200)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB _U(9)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_LSB _U(9)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS _u(0x00000200)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB _u(9)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_LSB _u(9)
#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_IO
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS _U(0x00000100)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB _U(8)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_LSB _U(8)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS _u(0x00000100)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB _u(8)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_LSB _u(8)
#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C1
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS _U(0x00000080)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB _U(7)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_LSB _U(7)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS _u(0x00000080)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB _u(7)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_LSB _u(7)
#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C0
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS _U(0x00000040)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB _U(6)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_LSB _U(6)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS _u(0x00000040)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB _u(6)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_LSB _u(6)
#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_DMA
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS _U(0x00000020)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB _U(5)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_LSB _U(5)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS _u(0x00000020)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB _u(5)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_LSB _u(5)
#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS _U(0x00000010)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB _U(4)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_LSB _U(4)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB _u(4)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_LSB _u(4)
#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS _U(0x00000008)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB _U(3)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_LSB _U(3)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000008)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB _u(3)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_LSB _u(3)
#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ADC
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS _U(0x00000004)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB _U(2)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_LSB _U(2)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS _u(0x00000004)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB _u(2)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_LSB _u(2)
#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_ADC_ADC
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_BITS _U(0x00000002)
-#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_MSB _U(1)
-#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_LSB _U(1)
+#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_BITS _u(0x00000002)
+#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_MSB _u(1)
+#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_LSB _u(1)
#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS
// Description : None
-#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS _U(0x00000001)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB _U(0)
-#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_LSB _U(0)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB _u(0)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_LSB _u(0)
#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_SLEEP_EN1
// Description : enable clock in sleep mode
-#define CLOCKS_SLEEP_EN1_OFFSET _U(0x000000ac)
-#define CLOCKS_SLEEP_EN1_BITS _U(0x00007fff)
-#define CLOCKS_SLEEP_EN1_RESET _U(0x00007fff)
+#define CLOCKS_SLEEP_EN1_OFFSET _u(0x000000ac)
+#define CLOCKS_SLEEP_EN1_BITS _u(0x00007fff)
+#define CLOCKS_SLEEP_EN1_RESET _u(0x00007fff)
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN1_CLK_SYS_XOSC
// Description : None
-#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS _U(0x00004000)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB _U(14)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_LSB _U(14)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS _u(0x00004000)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB _u(14)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_LSB _u(14)
#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN1_CLK_SYS_XIP
// Description : None
-#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS _U(0x00002000)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB _U(13)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_LSB _U(13)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS _u(0x00002000)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB _u(13)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_LSB _u(13)
#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG
// Description : None
-#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS _U(0x00001000)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB _U(12)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_LSB _U(12)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS _u(0x00001000)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB _u(12)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_LSB _u(12)
#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL
// Description : None
-#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_BITS _U(0x00000800)
-#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_MSB _U(11)
-#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_LSB _U(11)
+#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_BITS _u(0x00000800)
+#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_MSB _u(11)
+#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_LSB _u(11)
#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL
// Description : None
-#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS _U(0x00000400)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB _U(10)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_LSB _U(10)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS _u(0x00000400)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB _u(10)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_LSB _u(10)
#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART1
// Description : None
-#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS _U(0x00000200)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB _U(9)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_LSB _U(9)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS _u(0x00000200)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB _u(9)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_LSB _u(9)
#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART1
// Description : None
-#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS _U(0x00000100)
-#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB _U(8)
-#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_LSB _U(8)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS _u(0x00000100)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB _u(8)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_LSB _u(8)
#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART0
// Description : None
-#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS _U(0x00000080)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB _U(7)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_LSB _U(7)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS _u(0x00000080)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB _u(7)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_LSB _u(7)
#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART0
// Description : None
-#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS _U(0x00000040)
-#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB _U(6)
-#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_LSB _U(6)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS _u(0x00000040)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB _u(6)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_LSB _u(6)
#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER
// Description : None
-#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_BITS _U(0x00000020)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_MSB _U(5)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_LSB _U(5)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_BITS _u(0x00000020)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_MSB _u(5)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_LSB _u(5)
#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN
// Description : None
-#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS _U(0x00000010)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB _U(4)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_LSB _U(4)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS _u(0x00000010)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB _u(4)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_LSB _u(4)
#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO
// Description : None
-#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS _U(0x00000008)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB _U(3)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_LSB _U(3)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS _u(0x00000008)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB _u(3)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_LSB _u(3)
#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG
// Description : None
-#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS _U(0x00000004)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB _U(2)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_LSB _U(2)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS _u(0x00000004)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB _u(2)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_LSB _u(2)
#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5
// Description : None
-#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS _U(0x00000002)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB _U(1)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_LSB _U(1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS _u(0x00000002)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB _u(1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_LSB _u(1)
#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4
// Description : None
-#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET _U(0x1)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS _U(0x00000001)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB _U(0)
-#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_LSB _U(0)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS _u(0x00000001)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB _u(0)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_LSB _u(0)
#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_ENABLED0
// Description : indicates the state of the clock enable
-#define CLOCKS_ENABLED0_OFFSET _U(0x000000b0)
-#define CLOCKS_ENABLED0_BITS _U(0xffffffff)
-#define CLOCKS_ENABLED0_RESET _U(0x00000000)
+#define CLOCKS_ENABLED0_OFFSET _u(0x000000b0)
+#define CLOCKS_ENABLED0_BITS _u(0xffffffff)
+#define CLOCKS_ENABLED0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM3
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_BITS _U(0x80000000)
-#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_MSB _U(31)
-#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_LSB _U(31)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_BITS _u(0x80000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_MSB _u(31)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_LSB _u(31)
#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM2
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_BITS _U(0x40000000)
-#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_MSB _U(30)
-#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_LSB _U(30)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_BITS _u(0x40000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_MSB _u(30)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_LSB _u(30)
#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM1
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_BITS _U(0x20000000)
-#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_MSB _U(29)
-#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_LSB _U(29)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_BITS _u(0x20000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_MSB _u(29)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_LSB _u(29)
#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM0
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_BITS _U(0x10000000)
-#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_MSB _U(28)
-#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_LSB _U(28)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_BITS _u(0x10000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_MSB _u(28)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_LSB _u(28)
#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_SPI1
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_SPI1_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_SPI1_BITS _U(0x08000000)
-#define CLOCKS_ENABLED0_CLK_SYS_SPI1_MSB _U(27)
-#define CLOCKS_ENABLED0_CLK_SYS_SPI1_LSB _U(27)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI1_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI1_BITS _u(0x08000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI1_MSB _u(27)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI1_LSB _u(27)
#define CLOCKS_ENABLED0_CLK_SYS_SPI1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_PERI_SPI1
// Description : None
-#define CLOCKS_ENABLED0_CLK_PERI_SPI1_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_PERI_SPI1_BITS _U(0x04000000)
-#define CLOCKS_ENABLED0_CLK_PERI_SPI1_MSB _U(26)
-#define CLOCKS_ENABLED0_CLK_PERI_SPI1_LSB _U(26)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI1_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI1_BITS _u(0x04000000)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI1_MSB _u(26)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI1_LSB _u(26)
#define CLOCKS_ENABLED0_CLK_PERI_SPI1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_SPI0
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_SPI0_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_SPI0_BITS _U(0x02000000)
-#define CLOCKS_ENABLED0_CLK_SYS_SPI0_MSB _U(25)
-#define CLOCKS_ENABLED0_CLK_SYS_SPI0_LSB _U(25)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI0_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI0_BITS _u(0x02000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI0_MSB _u(25)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI0_LSB _u(25)
#define CLOCKS_ENABLED0_CLK_SYS_SPI0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_PERI_SPI0
// Description : None
-#define CLOCKS_ENABLED0_CLK_PERI_SPI0_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_PERI_SPI0_BITS _U(0x01000000)
-#define CLOCKS_ENABLED0_CLK_PERI_SPI0_MSB _U(24)
-#define CLOCKS_ENABLED0_CLK_PERI_SPI0_LSB _U(24)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI0_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI0_BITS _u(0x01000000)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI0_MSB _u(24)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI0_LSB _u(24)
#define CLOCKS_ENABLED0_CLK_PERI_SPI0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_SIO
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS _U(0x00800000)
-#define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB _U(23)
-#define CLOCKS_ENABLED0_CLK_SYS_SIO_LSB _U(23)
+#define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS _u(0x00800000)
+#define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB _u(23)
+#define CLOCKS_ENABLED0_CLK_SYS_SIO_LSB _u(23)
#define CLOCKS_ENABLED0_CLK_SYS_SIO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_RTC
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_RTC_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_RTC_BITS _U(0x00400000)
-#define CLOCKS_ENABLED0_CLK_SYS_RTC_MSB _U(22)
-#define CLOCKS_ENABLED0_CLK_SYS_RTC_LSB _U(22)
+#define CLOCKS_ENABLED0_CLK_SYS_RTC_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_RTC_BITS _u(0x00400000)
+#define CLOCKS_ENABLED0_CLK_SYS_RTC_MSB _u(22)
+#define CLOCKS_ENABLED0_CLK_SYS_RTC_LSB _u(22)
#define CLOCKS_ENABLED0_CLK_SYS_RTC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_RTC_RTC
// Description : None
-#define CLOCKS_ENABLED0_CLK_RTC_RTC_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_RTC_RTC_BITS _U(0x00200000)
-#define CLOCKS_ENABLED0_CLK_RTC_RTC_MSB _U(21)
-#define CLOCKS_ENABLED0_CLK_RTC_RTC_LSB _U(21)
+#define CLOCKS_ENABLED0_CLK_RTC_RTC_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_RTC_RTC_BITS _u(0x00200000)
+#define CLOCKS_ENABLED0_CLK_RTC_RTC_MSB _u(21)
+#define CLOCKS_ENABLED0_CLK_RTC_RTC_LSB _u(21)
#define CLOCKS_ENABLED0_CLK_RTC_RTC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_ROSC
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS _U(0x00100000)
-#define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB _U(20)
-#define CLOCKS_ENABLED0_CLK_SYS_ROSC_LSB _U(20)
+#define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS _u(0x00100000)
+#define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB _u(20)
+#define CLOCKS_ENABLED0_CLK_SYS_ROSC_LSB _u(20)
#define CLOCKS_ENABLED0_CLK_SYS_ROSC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_ROM
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS _U(0x00080000)
-#define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB _U(19)
-#define CLOCKS_ENABLED0_CLK_SYS_ROM_LSB _U(19)
+#define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS _u(0x00080000)
+#define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB _u(19)
+#define CLOCKS_ENABLED0_CLK_SYS_ROM_LSB _u(19)
#define CLOCKS_ENABLED0_CLK_SYS_ROM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_RESETS
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS _U(0x00040000)
-#define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB _U(18)
-#define CLOCKS_ENABLED0_CLK_SYS_RESETS_LSB _U(18)
+#define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS _u(0x00040000)
+#define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB _u(18)
+#define CLOCKS_ENABLED0_CLK_SYS_RESETS_LSB _u(18)
#define CLOCKS_ENABLED0_CLK_SYS_RESETS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_PWM
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS _U(0x00020000)
-#define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB _U(17)
-#define CLOCKS_ENABLED0_CLK_SYS_PWM_LSB _U(17)
+#define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS _u(0x00020000)
+#define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB _u(17)
+#define CLOCKS_ENABLED0_CLK_SYS_PWM_LSB _u(17)
#define CLOCKS_ENABLED0_CLK_SYS_PWM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_PSM
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS _U(0x00010000)
-#define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB _U(16)
-#define CLOCKS_ENABLED0_CLK_SYS_PSM_LSB _U(16)
+#define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS _u(0x00010000)
+#define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB _u(16)
+#define CLOCKS_ENABLED0_CLK_SYS_PSM_LSB _u(16)
#define CLOCKS_ENABLED0_CLK_SYS_PSM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_PLL_USB
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS _U(0x00008000)
-#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB _U(15)
-#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_LSB _U(15)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS _u(0x00008000)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB _u(15)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_LSB _u(15)
#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_PLL_SYS
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS _U(0x00004000)
-#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB _U(14)
-#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_LSB _U(14)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS _u(0x00004000)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB _u(14)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_LSB _u(14)
#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_PIO1
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS _U(0x00002000)
-#define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB _U(13)
-#define CLOCKS_ENABLED0_CLK_SYS_PIO1_LSB _U(13)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS _u(0x00002000)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB _u(13)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO1_LSB _u(13)
#define CLOCKS_ENABLED0_CLK_SYS_PIO1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_PIO0
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS _U(0x00001000)
-#define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB _U(12)
-#define CLOCKS_ENABLED0_CLK_SYS_PIO0_LSB _U(12)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS _u(0x00001000)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB _u(12)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO0_LSB _u(12)
#define CLOCKS_ENABLED0_CLK_SYS_PIO0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_PADS
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS _U(0x00000800)
-#define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB _U(11)
-#define CLOCKS_ENABLED0_CLK_SYS_PADS_LSB _U(11)
+#define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS _u(0x00000800)
+#define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB _u(11)
+#define CLOCKS_ENABLED0_CLK_SYS_PADS_LSB _u(11)
#define CLOCKS_ENABLED0_CLK_SYS_PADS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _U(0x00000400)
-#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _U(10)
-#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _U(10)
+#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400)
+#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10)
+#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _u(10)
#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_JTAG
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS _U(0x00000200)
-#define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB _U(9)
-#define CLOCKS_ENABLED0_CLK_SYS_JTAG_LSB _U(9)
+#define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS _u(0x00000200)
+#define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB _u(9)
+#define CLOCKS_ENABLED0_CLK_SYS_JTAG_LSB _u(9)
#define CLOCKS_ENABLED0_CLK_SYS_JTAG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_IO
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_IO_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_IO_BITS _U(0x00000100)
-#define CLOCKS_ENABLED0_CLK_SYS_IO_MSB _U(8)
-#define CLOCKS_ENABLED0_CLK_SYS_IO_LSB _U(8)
+#define CLOCKS_ENABLED0_CLK_SYS_IO_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_IO_BITS _u(0x00000100)
+#define CLOCKS_ENABLED0_CLK_SYS_IO_MSB _u(8)
+#define CLOCKS_ENABLED0_CLK_SYS_IO_LSB _u(8)
#define CLOCKS_ENABLED0_CLK_SYS_IO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_I2C1
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS _U(0x00000080)
-#define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB _U(7)
-#define CLOCKS_ENABLED0_CLK_SYS_I2C1_LSB _U(7)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS _u(0x00000080)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB _u(7)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C1_LSB _u(7)
#define CLOCKS_ENABLED0_CLK_SYS_I2C1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_I2C0
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS _U(0x00000040)
-#define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB _U(6)
-#define CLOCKS_ENABLED0_CLK_SYS_I2C0_LSB _U(6)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS _u(0x00000040)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB _u(6)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C0_LSB _u(6)
#define CLOCKS_ENABLED0_CLK_SYS_I2C0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_DMA
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS _U(0x00000020)
-#define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB _U(5)
-#define CLOCKS_ENABLED0_CLK_SYS_DMA_LSB _U(5)
+#define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS _u(0x00000020)
+#define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB _u(5)
+#define CLOCKS_ENABLED0_CLK_SYS_DMA_LSB _u(5)
#define CLOCKS_ENABLED0_CLK_SYS_DMA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS _U(0x00000010)
-#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB _U(4)
-#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_LSB _U(4)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB _u(4)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_LSB _u(4)
#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_BUSCTRL
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS _U(0x00000008)
-#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB _U(3)
-#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_LSB _U(3)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS _u(0x00000008)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB _u(3)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_LSB _u(3)
#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_ADC
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS _U(0x00000004)
-#define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB _U(2)
-#define CLOCKS_ENABLED0_CLK_SYS_ADC_LSB _U(2)
+#define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS _u(0x00000004)
+#define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB _u(2)
+#define CLOCKS_ENABLED0_CLK_SYS_ADC_LSB _u(2)
#define CLOCKS_ENABLED0_CLK_SYS_ADC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_ADC_ADC
// Description : None
-#define CLOCKS_ENABLED0_CLK_ADC_ADC_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_ADC_ADC_BITS _U(0x00000002)
-#define CLOCKS_ENABLED0_CLK_ADC_ADC_MSB _U(1)
-#define CLOCKS_ENABLED0_CLK_ADC_ADC_LSB _U(1)
+#define CLOCKS_ENABLED0_CLK_ADC_ADC_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_ADC_ADC_BITS _u(0x00000002)
+#define CLOCKS_ENABLED0_CLK_ADC_ADC_MSB _u(1)
+#define CLOCKS_ENABLED0_CLK_ADC_ADC_LSB _u(1)
#define CLOCKS_ENABLED0_CLK_ADC_ADC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED0_CLK_SYS_CLOCKS
// Description : None
-#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET _U(0x0)
-#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS _U(0x00000001)
-#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB _U(0)
-#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_LSB _U(0)
+#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS _u(0x00000001)
+#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB _u(0)
+#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_LSB _u(0)
#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_ACCESS "RO"
// =============================================================================
// Register : CLOCKS_ENABLED1
// Description : indicates the state of the clock enable
-#define CLOCKS_ENABLED1_OFFSET _U(0x000000b4)
-#define CLOCKS_ENABLED1_BITS _U(0x00007fff)
-#define CLOCKS_ENABLED1_RESET _U(0x00000000)
+#define CLOCKS_ENABLED1_OFFSET _u(0x000000b4)
+#define CLOCKS_ENABLED1_BITS _u(0x00007fff)
+#define CLOCKS_ENABLED1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED1_CLK_SYS_XOSC
// Description : None
-#define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET _U(0x0)
-#define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS _U(0x00004000)
-#define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB _U(14)
-#define CLOCKS_ENABLED1_CLK_SYS_XOSC_LSB _U(14)
+#define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS _u(0x00004000)
+#define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB _u(14)
+#define CLOCKS_ENABLED1_CLK_SYS_XOSC_LSB _u(14)
#define CLOCKS_ENABLED1_CLK_SYS_XOSC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED1_CLK_SYS_XIP
// Description : None
-#define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET _U(0x0)
-#define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS _U(0x00002000)
-#define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB _U(13)
-#define CLOCKS_ENABLED1_CLK_SYS_XIP_LSB _U(13)
+#define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS _u(0x00002000)
+#define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB _u(13)
+#define CLOCKS_ENABLED1_CLK_SYS_XIP_LSB _u(13)
#define CLOCKS_ENABLED1_CLK_SYS_XIP_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED1_CLK_SYS_WATCHDOG
// Description : None
-#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET _U(0x0)
-#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS _U(0x00001000)
-#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB _U(12)
-#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_LSB _U(12)
+#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS _u(0x00001000)
+#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB _u(12)
+#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_LSB _u(12)
#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED1_CLK_USB_USBCTRL
// Description : None
-#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_RESET _U(0x0)
-#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_BITS _U(0x00000800)
-#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_MSB _U(11)
-#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_LSB _U(11)
+#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_BITS _u(0x00000800)
+#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_MSB _u(11)
+#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_LSB _u(11)
#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED1_CLK_SYS_USBCTRL
// Description : None
-#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET _U(0x0)
-#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS _U(0x00000400)
-#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB _U(10)
-#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_LSB _U(10)
+#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS _u(0x00000400)
+#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB _u(10)
+#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_LSB _u(10)
#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED1_CLK_SYS_UART1
// Description : None
-#define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET _U(0x0)
-#define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS _U(0x00000200)
-#define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB _U(9)
-#define CLOCKS_ENABLED1_CLK_SYS_UART1_LSB _U(9)
+#define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS _u(0x00000200)
+#define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB _u(9)
+#define CLOCKS_ENABLED1_CLK_SYS_UART1_LSB _u(9)
#define CLOCKS_ENABLED1_CLK_SYS_UART1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED1_CLK_PERI_UART1
// Description : None
-#define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET _U(0x0)
-#define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS _U(0x00000100)
-#define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB _U(8)
-#define CLOCKS_ENABLED1_CLK_PERI_UART1_LSB _U(8)
+#define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS _u(0x00000100)
+#define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB _u(8)
+#define CLOCKS_ENABLED1_CLK_PERI_UART1_LSB _u(8)
#define CLOCKS_ENABLED1_CLK_PERI_UART1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED1_CLK_SYS_UART0
// Description : None
-#define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET _U(0x0)
-#define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS _U(0x00000080)
-#define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB _U(7)
-#define CLOCKS_ENABLED1_CLK_SYS_UART0_LSB _U(7)
+#define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS _u(0x00000080)
+#define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB _u(7)
+#define CLOCKS_ENABLED1_CLK_SYS_UART0_LSB _u(7)
#define CLOCKS_ENABLED1_CLK_SYS_UART0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED1_CLK_PERI_UART0
// Description : None
-#define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET _U(0x0)
-#define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS _U(0x00000040)
-#define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB _U(6)
-#define CLOCKS_ENABLED1_CLK_PERI_UART0_LSB _U(6)
+#define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS _u(0x00000040)
+#define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB _u(6)
+#define CLOCKS_ENABLED1_CLK_PERI_UART0_LSB _u(6)
#define CLOCKS_ENABLED1_CLK_PERI_UART0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED1_CLK_SYS_TIMER
// Description : None
-#define CLOCKS_ENABLED1_CLK_SYS_TIMER_RESET _U(0x0)
-#define CLOCKS_ENABLED1_CLK_SYS_TIMER_BITS _U(0x00000020)
-#define CLOCKS_ENABLED1_CLK_SYS_TIMER_MSB _U(5)
-#define CLOCKS_ENABLED1_CLK_SYS_TIMER_LSB _U(5)
+#define CLOCKS_ENABLED1_CLK_SYS_TIMER_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_TIMER_BITS _u(0x00000020)
+#define CLOCKS_ENABLED1_CLK_SYS_TIMER_MSB _u(5)
+#define CLOCKS_ENABLED1_CLK_SYS_TIMER_LSB _u(5)
#define CLOCKS_ENABLED1_CLK_SYS_TIMER_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED1_CLK_SYS_TBMAN
// Description : None
-#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET _U(0x0)
-#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS _U(0x00000010)
-#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB _U(4)
-#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_LSB _U(4)
+#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS _u(0x00000010)
+#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB _u(4)
+#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_LSB _u(4)
#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED1_CLK_SYS_SYSINFO
// Description : None
-#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET _U(0x0)
-#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS _U(0x00000008)
-#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB _U(3)
-#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_LSB _U(3)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS _u(0x00000008)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB _u(3)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_LSB _u(3)
#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED1_CLK_SYS_SYSCFG
// Description : None
-#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET _U(0x0)
-#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS _U(0x00000004)
-#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB _U(2)
-#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_LSB _U(2)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS _u(0x00000004)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB _u(2)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_LSB _u(2)
#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM5
// Description : None
-#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET _U(0x0)
-#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS _U(0x00000002)
-#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB _U(1)
-#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_LSB _U(1)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS _u(0x00000002)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB _u(1)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_LSB _u(1)
#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM4
// Description : None
-#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET _U(0x0)
-#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS _U(0x00000001)
-#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB _U(0)
-#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_LSB _U(0)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS _u(0x00000001)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB _u(0)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_LSB _u(0)
#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_ACCESS "RO"
// =============================================================================
// Register : CLOCKS_INTR
// Description : Raw Interrupts
-#define CLOCKS_INTR_OFFSET _U(0x000000b8)
-#define CLOCKS_INTR_BITS _U(0x00000001)
-#define CLOCKS_INTR_RESET _U(0x00000000)
+#define CLOCKS_INTR_OFFSET _u(0x000000b8)
+#define CLOCKS_INTR_BITS _u(0x00000001)
+#define CLOCKS_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_INTR_CLK_SYS_RESUS
// Description : None
-#define CLOCKS_INTR_CLK_SYS_RESUS_RESET _U(0x0)
-#define CLOCKS_INTR_CLK_SYS_RESUS_BITS _U(0x00000001)
-#define CLOCKS_INTR_CLK_SYS_RESUS_MSB _U(0)
-#define CLOCKS_INTR_CLK_SYS_RESUS_LSB _U(0)
+#define CLOCKS_INTR_CLK_SYS_RESUS_RESET _u(0x0)
+#define CLOCKS_INTR_CLK_SYS_RESUS_BITS _u(0x00000001)
+#define CLOCKS_INTR_CLK_SYS_RESUS_MSB _u(0)
+#define CLOCKS_INTR_CLK_SYS_RESUS_LSB _u(0)
#define CLOCKS_INTR_CLK_SYS_RESUS_ACCESS "RO"
// =============================================================================
// Register : CLOCKS_INTE
// Description : Interrupt Enable
-#define CLOCKS_INTE_OFFSET _U(0x000000bc)
-#define CLOCKS_INTE_BITS _U(0x00000001)
-#define CLOCKS_INTE_RESET _U(0x00000000)
+#define CLOCKS_INTE_OFFSET _u(0x000000bc)
+#define CLOCKS_INTE_BITS _u(0x00000001)
+#define CLOCKS_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_INTE_CLK_SYS_RESUS
// Description : None
-#define CLOCKS_INTE_CLK_SYS_RESUS_RESET _U(0x0)
-#define CLOCKS_INTE_CLK_SYS_RESUS_BITS _U(0x00000001)
-#define CLOCKS_INTE_CLK_SYS_RESUS_MSB _U(0)
-#define CLOCKS_INTE_CLK_SYS_RESUS_LSB _U(0)
+#define CLOCKS_INTE_CLK_SYS_RESUS_RESET _u(0x0)
+#define CLOCKS_INTE_CLK_SYS_RESUS_BITS _u(0x00000001)
+#define CLOCKS_INTE_CLK_SYS_RESUS_MSB _u(0)
+#define CLOCKS_INTE_CLK_SYS_RESUS_LSB _u(0)
#define CLOCKS_INTE_CLK_SYS_RESUS_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_INTF
// Description : Interrupt Force
-#define CLOCKS_INTF_OFFSET _U(0x000000c0)
-#define CLOCKS_INTF_BITS _U(0x00000001)
-#define CLOCKS_INTF_RESET _U(0x00000000)
+#define CLOCKS_INTF_OFFSET _u(0x000000c0)
+#define CLOCKS_INTF_BITS _u(0x00000001)
+#define CLOCKS_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_INTF_CLK_SYS_RESUS
// Description : None
-#define CLOCKS_INTF_CLK_SYS_RESUS_RESET _U(0x0)
-#define CLOCKS_INTF_CLK_SYS_RESUS_BITS _U(0x00000001)
-#define CLOCKS_INTF_CLK_SYS_RESUS_MSB _U(0)
-#define CLOCKS_INTF_CLK_SYS_RESUS_LSB _U(0)
+#define CLOCKS_INTF_CLK_SYS_RESUS_RESET _u(0x0)
+#define CLOCKS_INTF_CLK_SYS_RESUS_BITS _u(0x00000001)
+#define CLOCKS_INTF_CLK_SYS_RESUS_MSB _u(0)
+#define CLOCKS_INTF_CLK_SYS_RESUS_LSB _u(0)
#define CLOCKS_INTF_CLK_SYS_RESUS_ACCESS "RW"
// =============================================================================
// Register : CLOCKS_INTS
// Description : Interrupt status after masking & forcing
-#define CLOCKS_INTS_OFFSET _U(0x000000c4)
-#define CLOCKS_INTS_BITS _U(0x00000001)
-#define CLOCKS_INTS_RESET _U(0x00000000)
+#define CLOCKS_INTS_OFFSET _u(0x000000c4)
+#define CLOCKS_INTS_BITS _u(0x00000001)
+#define CLOCKS_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CLOCKS_INTS_CLK_SYS_RESUS
// Description : None
-#define CLOCKS_INTS_CLK_SYS_RESUS_RESET _U(0x0)
-#define CLOCKS_INTS_CLK_SYS_RESUS_BITS _U(0x00000001)
-#define CLOCKS_INTS_CLK_SYS_RESUS_MSB _U(0)
-#define CLOCKS_INTS_CLK_SYS_RESUS_LSB _U(0)
+#define CLOCKS_INTS_CLK_SYS_RESUS_RESET _u(0x0)
+#define CLOCKS_INTS_CLK_SYS_RESUS_BITS _u(0x00000001)
+#define CLOCKS_INTS_CLK_SYS_RESUS_MSB _u(0)
+#define CLOCKS_INTS_CLK_SYS_RESUS_LSB _u(0)
#define CLOCKS_INTS_CLK_SYS_RESUS_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_CLOCKS_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/dma.h b/src/rp2040/hardware_regs/include/hardware/regs/dma.h
index 2c3bae1..49938ba 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/dma.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/dma.h
@@ -17,11 +17,11 @@
// This register updates automatically each time a read completes.
// The current value is the next address to be read by this
// channel.
-#define DMA_CH0_READ_ADDR_OFFSET _U(0x00000000)
-#define DMA_CH0_READ_ADDR_BITS _U(0xffffffff)
-#define DMA_CH0_READ_ADDR_RESET _U(0x00000000)
-#define DMA_CH0_READ_ADDR_MSB _U(31)
-#define DMA_CH0_READ_ADDR_LSB _U(0)
+#define DMA_CH0_READ_ADDR_OFFSET _u(0x00000000)
+#define DMA_CH0_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH0_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH0_READ_ADDR_MSB _u(31)
+#define DMA_CH0_READ_ADDR_LSB _u(0)
#define DMA_CH0_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH0_WRITE_ADDR
@@ -29,11 +29,11 @@
// This register updates automatically each time a write
// completes. The current value is the next address to be written
// by this channel.
-#define DMA_CH0_WRITE_ADDR_OFFSET _U(0x00000004)
-#define DMA_CH0_WRITE_ADDR_BITS _U(0xffffffff)
-#define DMA_CH0_WRITE_ADDR_RESET _U(0x00000000)
-#define DMA_CH0_WRITE_ADDR_MSB _U(31)
-#define DMA_CH0_WRITE_ADDR_LSB _U(0)
+#define DMA_CH0_WRITE_ADDR_OFFSET _u(0x00000004)
+#define DMA_CH0_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH0_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH0_WRITE_ADDR_MSB _u(31)
+#define DMA_CH0_WRITE_ADDR_LSB _u(0)
#define DMA_CH0_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH0_TRANS_COUNT
@@ -57,27 +57,27 @@
// is used as a trigger, the written value is used immediately as
// the length of the new transfer sequence, as well as being
// written to RELOAD.
-#define DMA_CH0_TRANS_COUNT_OFFSET _U(0x00000008)
-#define DMA_CH0_TRANS_COUNT_BITS _U(0xffffffff)
-#define DMA_CH0_TRANS_COUNT_RESET _U(0x00000000)
-#define DMA_CH0_TRANS_COUNT_MSB _U(31)
-#define DMA_CH0_TRANS_COUNT_LSB _U(0)
+#define DMA_CH0_TRANS_COUNT_OFFSET _u(0x00000008)
+#define DMA_CH0_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH0_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH0_TRANS_COUNT_MSB _u(31)
+#define DMA_CH0_TRANS_COUNT_LSB _u(0)
#define DMA_CH0_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH0_CTRL_TRIG
// Description : DMA Channel 0 Control and Status
-#define DMA_CH0_CTRL_TRIG_OFFSET _U(0x0000000c)
-#define DMA_CH0_CTRL_TRIG_BITS _U(0xe1ffffff)
-#define DMA_CH0_CTRL_TRIG_RESET _U(0x00000000)
+#define DMA_CH0_CTRL_TRIG_OFFSET _u(0x0000000c)
+#define DMA_CH0_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH0_CTRL_TRIG_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : DMA_CH0_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
// halts when it encounters any bus error, and always raises its
// channel IRQ flag.
-#define DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET _U(0x0)
-#define DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS _U(0x80000000)
-#define DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB _U(31)
-#define DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB _U(31)
+#define DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB _u(31)
#define DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH0_CTRL_TRIG_READ_ERROR
@@ -86,10 +86,10 @@
// READ_ADDR shows the approximate address where the bus error was
// encountered (will not to be earlier, or more than 3 transfers
// later)
-#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET _U(0x0)
-#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS _U(0x40000000)
-#define DMA_CH0_CTRL_TRIG_READ_ERROR_MSB _U(30)
-#define DMA_CH0_CTRL_TRIG_READ_ERROR_LSB _U(30)
+#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH0_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH0_CTRL_TRIG_READ_ERROR_LSB _u(30)
#define DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH0_CTRL_TRIG_WRITE_ERROR
@@ -98,10 +98,10 @@
// WRITE_ADDR shows the approximate address where the bus error
// was encountered (will not to be earlier, or more than 5
// transfers later)
-#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET _U(0x0)
-#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS _U(0x20000000)
-#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB _U(29)
-#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB _U(29)
+#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH0_CTRL_TRIG_BUSY
@@ -112,10 +112,10 @@
//
// To terminate a sequence early (and clear the BUSY flag), see
// CHAN_ABORT.
-#define DMA_CH0_CTRL_TRIG_BUSY_RESET _U(0x0)
-#define DMA_CH0_CTRL_TRIG_BUSY_BITS _U(0x01000000)
-#define DMA_CH0_CTRL_TRIG_BUSY_MSB _U(24)
-#define DMA_CH0_CTRL_TRIG_BUSY_LSB _U(24)
+#define DMA_CH0_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH0_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH0_CTRL_TRIG_BUSY_LSB _u(24)
#define DMA_CH0_CTRL_TRIG_BUSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH0_CTRL_TRIG_SNIFF_EN
@@ -126,10 +126,10 @@
//
// This allows checksum to be enabled or disabled on a
// per-control- block basis.
-#define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET _U(0x0)
-#define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS _U(0x00800000)
-#define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB _U(23)
-#define DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB _U(23)
+#define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB _u(23)
#define DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH0_CTRL_TRIG_BSWAP
@@ -137,10 +137,10 @@
// For byte data, this has no effect. For halfword data, the two
// bytes of each halfword are swapped. For word data, the four
// bytes of each word are swapped to reverse order.
-#define DMA_CH0_CTRL_TRIG_BSWAP_RESET _U(0x0)
-#define DMA_CH0_CTRL_TRIG_BSWAP_BITS _U(0x00400000)
-#define DMA_CH0_CTRL_TRIG_BSWAP_MSB _U(22)
-#define DMA_CH0_CTRL_TRIG_BSWAP_LSB _U(22)
+#define DMA_CH0_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH0_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH0_CTRL_TRIG_BSWAP_LSB _u(22)
#define DMA_CH0_CTRL_TRIG_BSWAP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH0_CTRL_TRIG_IRQ_QUIET
@@ -151,10 +151,10 @@
//
// This reduces the number of interrupts to be serviced by the CPU
// when transferring a DMA chain of many small control blocks.
-#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET _U(0x0)
-#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS _U(0x00200000)
-#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB _U(21)
-#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB _U(21)
+#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH0_CTRL_TRIG_TREQ_SEL
@@ -168,36 +168,36 @@
// 0x3d -> Select Timer 2 as TREQ (Optional)
// 0x3e -> Select Timer 3 as TREQ (Optional)
// 0x3f -> Permanent request, for unpaced transfers.
-#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _U(0x00)
-#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _U(0x001f8000)
-#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _U(20)
-#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB _U(15)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB _u(15)
#define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
-#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _U(0x3b)
-#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _U(0x3c)
-#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _U(0x3d)
-#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _U(0x3e)
-#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _U(0x3f)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
// -----------------------------------------------------------------------------
// Field : DMA_CH0_CTRL_TRIG_CHAIN_TO
// Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_.
// Reset value is equal to channel number (0).
-#define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET _U(0x0)
-#define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS _U(0x00007800)
-#define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB _U(14)
-#define DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB _U(11)
+#define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB _u(11)
#define DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH0_CTRL_TRIG_RING_SEL
// Description : Select whether RING_SIZE applies to read or write addresses.
// If 0, read addresses are wrapped on a (1 << RING_SIZE)
// boundary. If 1, write addresses are wrapped.
-#define DMA_CH0_CTRL_TRIG_RING_SEL_RESET _U(0x0)
-#define DMA_CH0_CTRL_TRIG_RING_SEL_BITS _U(0x00000400)
-#define DMA_CH0_CTRL_TRIG_RING_SEL_MSB _U(10)
-#define DMA_CH0_CTRL_TRIG_RING_SEL_LSB _U(10)
+#define DMA_CH0_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH0_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH0_CTRL_TRIG_RING_SEL_LSB _u(10)
#define DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH0_CTRL_TRIG_RING_SIZE
@@ -210,12 +210,12 @@
// apply to either read or write addresses, based on value of
// RING_SEL.
// 0x0 -> RING_NONE
-#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET _U(0x0)
-#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS _U(0x000003c0)
-#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB _U(9)
-#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB _U(6)
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB _u(6)
#define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW"
-#define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _U(0x0)
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
// -----------------------------------------------------------------------------
// Field : DMA_CH0_CTRL_TRIG_INCR_WRITE
// Description : If 1, the write address increments with each transfer. If 0,
@@ -223,10 +223,10 @@
//
// Generally this should be disabled for memory-to-peripheral
// transfers.
-#define DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET _U(0x0)
-#define DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS _U(0x00000020)
-#define DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB _U(5)
-#define DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB _U(5)
+#define DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB _u(5)
#define DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH0_CTRL_TRIG_INCR_READ
@@ -235,10 +235,10 @@
//
// Generally this should be disabled for peripheral-to-memory
// transfers.
-#define DMA_CH0_CTRL_TRIG_INCR_READ_RESET _U(0x0)
-#define DMA_CH0_CTRL_TRIG_INCR_READ_BITS _U(0x00000010)
-#define DMA_CH0_CTRL_TRIG_INCR_READ_MSB _U(4)
-#define DMA_CH0_CTRL_TRIG_INCR_READ_LSB _U(4)
+#define DMA_CH0_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH0_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH0_CTRL_TRIG_INCR_READ_LSB _u(4)
#define DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH0_CTRL_TRIG_DATA_SIZE
@@ -248,14 +248,14 @@
// 0x0 -> SIZE_BYTE
// 0x1 -> SIZE_HALFWORD
// 0x2 -> SIZE_WORD
-#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET _U(0x0)
-#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS _U(0x0000000c)
-#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB _U(3)
-#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB _U(2)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB _u(2)
#define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
-#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _U(0x0)
-#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _U(0x1)
-#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _U(0x2)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
// -----------------------------------------------------------------------------
// Field : DMA_CH0_CTRL_TRIG_HIGH_PRIORITY
// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
@@ -268,10 +268,10 @@
// channels. The DMA's bus priority is not changed. If the DMA is
// not saturated then a low priority channel will see no loss of
// throughput.
-#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET _U(0x0)
-#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS _U(0x00000002)
-#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB _U(1)
-#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB _U(1)
+#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH0_CTRL_TRIG_EN
@@ -281,124 +281,124 @@
// 0, the channel will ignore triggers, stop issuing transfers,
// and pause the current transfer sequence (i.e. BUSY will remain
// high if already high)
-#define DMA_CH0_CTRL_TRIG_EN_RESET _U(0x0)
-#define DMA_CH0_CTRL_TRIG_EN_BITS _U(0x00000001)
-#define DMA_CH0_CTRL_TRIG_EN_MSB _U(0)
-#define DMA_CH0_CTRL_TRIG_EN_LSB _U(0)
+#define DMA_CH0_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH0_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH0_CTRL_TRIG_EN_LSB _u(0)
#define DMA_CH0_CTRL_TRIG_EN_ACCESS "RW"
// =============================================================================
// Register : DMA_CH0_AL1_CTRL
// Description : Alias for channel 0 CTRL register
-#define DMA_CH0_AL1_CTRL_OFFSET _U(0x00000010)
-#define DMA_CH0_AL1_CTRL_BITS _U(0xffffffff)
+#define DMA_CH0_AL1_CTRL_OFFSET _u(0x00000010)
+#define DMA_CH0_AL1_CTRL_BITS _u(0xffffffff)
#define DMA_CH0_AL1_CTRL_RESET "-"
-#define DMA_CH0_AL1_CTRL_MSB _U(31)
-#define DMA_CH0_AL1_CTRL_LSB _U(0)
+#define DMA_CH0_AL1_CTRL_MSB _u(31)
+#define DMA_CH0_AL1_CTRL_LSB _u(0)
#define DMA_CH0_AL1_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH0_AL1_READ_ADDR
// Description : Alias for channel 0 READ_ADDR register
-#define DMA_CH0_AL1_READ_ADDR_OFFSET _U(0x00000014)
-#define DMA_CH0_AL1_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH0_AL1_READ_ADDR_OFFSET _u(0x00000014)
+#define DMA_CH0_AL1_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH0_AL1_READ_ADDR_RESET "-"
-#define DMA_CH0_AL1_READ_ADDR_MSB _U(31)
-#define DMA_CH0_AL1_READ_ADDR_LSB _U(0)
+#define DMA_CH0_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH0_AL1_READ_ADDR_LSB _u(0)
#define DMA_CH0_AL1_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH0_AL1_WRITE_ADDR
// Description : Alias for channel 0 WRITE_ADDR register
-#define DMA_CH0_AL1_WRITE_ADDR_OFFSET _U(0x00000018)
-#define DMA_CH0_AL1_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH0_AL1_WRITE_ADDR_OFFSET _u(0x00000018)
+#define DMA_CH0_AL1_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH0_AL1_WRITE_ADDR_RESET "-"
-#define DMA_CH0_AL1_WRITE_ADDR_MSB _U(31)
-#define DMA_CH0_AL1_WRITE_ADDR_LSB _U(0)
+#define DMA_CH0_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH0_AL1_WRITE_ADDR_LSB _u(0)
#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH0_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 0 TRANS_COUNT register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET _U(0x0000001c)
-#define DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS _U(0xffffffff)
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000001c)
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
#define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET "-"
-#define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB _U(31)
-#define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB _U(0)
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB _u(0)
#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH0_AL2_CTRL
// Description : Alias for channel 0 CTRL register
-#define DMA_CH0_AL2_CTRL_OFFSET _U(0x00000020)
-#define DMA_CH0_AL2_CTRL_BITS _U(0xffffffff)
+#define DMA_CH0_AL2_CTRL_OFFSET _u(0x00000020)
+#define DMA_CH0_AL2_CTRL_BITS _u(0xffffffff)
#define DMA_CH0_AL2_CTRL_RESET "-"
-#define DMA_CH0_AL2_CTRL_MSB _U(31)
-#define DMA_CH0_AL2_CTRL_LSB _U(0)
+#define DMA_CH0_AL2_CTRL_MSB _u(31)
+#define DMA_CH0_AL2_CTRL_LSB _u(0)
#define DMA_CH0_AL2_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH0_AL2_TRANS_COUNT
// Description : Alias for channel 0 TRANS_COUNT register
-#define DMA_CH0_AL2_TRANS_COUNT_OFFSET _U(0x00000024)
-#define DMA_CH0_AL2_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH0_AL2_TRANS_COUNT_OFFSET _u(0x00000024)
+#define DMA_CH0_AL2_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH0_AL2_TRANS_COUNT_RESET "-"
-#define DMA_CH0_AL2_TRANS_COUNT_MSB _U(31)
-#define DMA_CH0_AL2_TRANS_COUNT_LSB _U(0)
+#define DMA_CH0_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH0_AL2_TRANS_COUNT_LSB _u(0)
#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH0_AL2_READ_ADDR
// Description : Alias for channel 0 READ_ADDR register
-#define DMA_CH0_AL2_READ_ADDR_OFFSET _U(0x00000028)
-#define DMA_CH0_AL2_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH0_AL2_READ_ADDR_OFFSET _u(0x00000028)
+#define DMA_CH0_AL2_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH0_AL2_READ_ADDR_RESET "-"
-#define DMA_CH0_AL2_READ_ADDR_MSB _U(31)
-#define DMA_CH0_AL2_READ_ADDR_LSB _U(0)
+#define DMA_CH0_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH0_AL2_READ_ADDR_LSB _u(0)
#define DMA_CH0_AL2_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH0_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 0 WRITE_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET _U(0x0000002c)
-#define DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000002c)
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET "-"
-#define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB _U(31)
-#define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB _U(0)
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB _u(0)
#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH0_AL3_CTRL
// Description : Alias for channel 0 CTRL register
-#define DMA_CH0_AL3_CTRL_OFFSET _U(0x00000030)
-#define DMA_CH0_AL3_CTRL_BITS _U(0xffffffff)
+#define DMA_CH0_AL3_CTRL_OFFSET _u(0x00000030)
+#define DMA_CH0_AL3_CTRL_BITS _u(0xffffffff)
#define DMA_CH0_AL3_CTRL_RESET "-"
-#define DMA_CH0_AL3_CTRL_MSB _U(31)
-#define DMA_CH0_AL3_CTRL_LSB _U(0)
+#define DMA_CH0_AL3_CTRL_MSB _u(31)
+#define DMA_CH0_AL3_CTRL_LSB _u(0)
#define DMA_CH0_AL3_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH0_AL3_WRITE_ADDR
// Description : Alias for channel 0 WRITE_ADDR register
-#define DMA_CH0_AL3_WRITE_ADDR_OFFSET _U(0x00000034)
-#define DMA_CH0_AL3_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH0_AL3_WRITE_ADDR_OFFSET _u(0x00000034)
+#define DMA_CH0_AL3_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH0_AL3_WRITE_ADDR_RESET "-"
-#define DMA_CH0_AL3_WRITE_ADDR_MSB _U(31)
-#define DMA_CH0_AL3_WRITE_ADDR_LSB _U(0)
+#define DMA_CH0_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH0_AL3_WRITE_ADDR_LSB _u(0)
#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH0_AL3_TRANS_COUNT
// Description : Alias for channel 0 TRANS_COUNT register
-#define DMA_CH0_AL3_TRANS_COUNT_OFFSET _U(0x00000038)
-#define DMA_CH0_AL3_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH0_AL3_TRANS_COUNT_OFFSET _u(0x00000038)
+#define DMA_CH0_AL3_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH0_AL3_TRANS_COUNT_RESET "-"
-#define DMA_CH0_AL3_TRANS_COUNT_MSB _U(31)
-#define DMA_CH0_AL3_TRANS_COUNT_LSB _U(0)
+#define DMA_CH0_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH0_AL3_TRANS_COUNT_LSB _u(0)
#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH0_AL3_READ_ADDR_TRIG
// Description : Alias for channel 0 READ_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET _U(0x0000003c)
-#define DMA_CH0_AL3_READ_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000003c)
+#define DMA_CH0_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH0_AL3_READ_ADDR_TRIG_RESET "-"
-#define DMA_CH0_AL3_READ_ADDR_TRIG_MSB _U(31)
-#define DMA_CH0_AL3_READ_ADDR_TRIG_LSB _U(0)
+#define DMA_CH0_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH0_AL3_READ_ADDR_TRIG_LSB _u(0)
#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH1_READ_ADDR
@@ -406,11 +406,11 @@
// This register updates automatically each time a read completes.
// The current value is the next address to be read by this
// channel.
-#define DMA_CH1_READ_ADDR_OFFSET _U(0x00000040)
-#define DMA_CH1_READ_ADDR_BITS _U(0xffffffff)
-#define DMA_CH1_READ_ADDR_RESET _U(0x00000000)
-#define DMA_CH1_READ_ADDR_MSB _U(31)
-#define DMA_CH1_READ_ADDR_LSB _U(0)
+#define DMA_CH1_READ_ADDR_OFFSET _u(0x00000040)
+#define DMA_CH1_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH1_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH1_READ_ADDR_MSB _u(31)
+#define DMA_CH1_READ_ADDR_LSB _u(0)
#define DMA_CH1_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH1_WRITE_ADDR
@@ -418,11 +418,11 @@
// This register updates automatically each time a write
// completes. The current value is the next address to be written
// by this channel.
-#define DMA_CH1_WRITE_ADDR_OFFSET _U(0x00000044)
-#define DMA_CH1_WRITE_ADDR_BITS _U(0xffffffff)
-#define DMA_CH1_WRITE_ADDR_RESET _U(0x00000000)
-#define DMA_CH1_WRITE_ADDR_MSB _U(31)
-#define DMA_CH1_WRITE_ADDR_LSB _U(0)
+#define DMA_CH1_WRITE_ADDR_OFFSET _u(0x00000044)
+#define DMA_CH1_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH1_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH1_WRITE_ADDR_LSB _u(0)
#define DMA_CH1_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH1_TRANS_COUNT
@@ -446,27 +446,27 @@
// is used as a trigger, the written value is used immediately as
// the length of the new transfer sequence, as well as being
// written to RELOAD.
-#define DMA_CH1_TRANS_COUNT_OFFSET _U(0x00000048)
-#define DMA_CH1_TRANS_COUNT_BITS _U(0xffffffff)
-#define DMA_CH1_TRANS_COUNT_RESET _U(0x00000000)
-#define DMA_CH1_TRANS_COUNT_MSB _U(31)
-#define DMA_CH1_TRANS_COUNT_LSB _U(0)
+#define DMA_CH1_TRANS_COUNT_OFFSET _u(0x00000048)
+#define DMA_CH1_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH1_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH1_TRANS_COUNT_MSB _u(31)
+#define DMA_CH1_TRANS_COUNT_LSB _u(0)
#define DMA_CH1_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH1_CTRL_TRIG
// Description : DMA Channel 1 Control and Status
-#define DMA_CH1_CTRL_TRIG_OFFSET _U(0x0000004c)
-#define DMA_CH1_CTRL_TRIG_BITS _U(0xe1ffffff)
-#define DMA_CH1_CTRL_TRIG_RESET _U(0x00000800)
+#define DMA_CH1_CTRL_TRIG_OFFSET _u(0x0000004c)
+#define DMA_CH1_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH1_CTRL_TRIG_RESET _u(0x00000800)
// -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
// halts when it encounters any bus error, and always raises its
// channel IRQ flag.
-#define DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET _U(0x0)
-#define DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS _U(0x80000000)
-#define DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB _U(31)
-#define DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB _U(31)
+#define DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB _u(31)
#define DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_READ_ERROR
@@ -475,10 +475,10 @@
// READ_ADDR shows the approximate address where the bus error was
// encountered (will not to be earlier, or more than 3 transfers
// later)
-#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET _U(0x0)
-#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS _U(0x40000000)
-#define DMA_CH1_CTRL_TRIG_READ_ERROR_MSB _U(30)
-#define DMA_CH1_CTRL_TRIG_READ_ERROR_LSB _U(30)
+#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH1_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH1_CTRL_TRIG_READ_ERROR_LSB _u(30)
#define DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_WRITE_ERROR
@@ -487,10 +487,10 @@
// WRITE_ADDR shows the approximate address where the bus error
// was encountered (will not to be earlier, or more than 5
// transfers later)
-#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET _U(0x0)
-#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS _U(0x20000000)
-#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB _U(29)
-#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB _U(29)
+#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_BUSY
@@ -501,10 +501,10 @@
//
// To terminate a sequence early (and clear the BUSY flag), see
// CHAN_ABORT.
-#define DMA_CH1_CTRL_TRIG_BUSY_RESET _U(0x0)
-#define DMA_CH1_CTRL_TRIG_BUSY_BITS _U(0x01000000)
-#define DMA_CH1_CTRL_TRIG_BUSY_MSB _U(24)
-#define DMA_CH1_CTRL_TRIG_BUSY_LSB _U(24)
+#define DMA_CH1_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH1_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH1_CTRL_TRIG_BUSY_LSB _u(24)
#define DMA_CH1_CTRL_TRIG_BUSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_SNIFF_EN
@@ -515,10 +515,10 @@
//
// This allows checksum to be enabled or disabled on a
// per-control- block basis.
-#define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET _U(0x0)
-#define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS _U(0x00800000)
-#define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB _U(23)
-#define DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB _U(23)
+#define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB _u(23)
#define DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_BSWAP
@@ -526,10 +526,10 @@
// For byte data, this has no effect. For halfword data, the two
// bytes of each halfword are swapped. For word data, the four
// bytes of each word are swapped to reverse order.
-#define DMA_CH1_CTRL_TRIG_BSWAP_RESET _U(0x0)
-#define DMA_CH1_CTRL_TRIG_BSWAP_BITS _U(0x00400000)
-#define DMA_CH1_CTRL_TRIG_BSWAP_MSB _U(22)
-#define DMA_CH1_CTRL_TRIG_BSWAP_LSB _U(22)
+#define DMA_CH1_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH1_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH1_CTRL_TRIG_BSWAP_LSB _u(22)
#define DMA_CH1_CTRL_TRIG_BSWAP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_IRQ_QUIET
@@ -540,10 +540,10 @@
//
// This reduces the number of interrupts to be serviced by the CPU
// when transferring a DMA chain of many small control blocks.
-#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET _U(0x0)
-#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS _U(0x00200000)
-#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB _U(21)
-#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB _U(21)
+#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_TREQ_SEL
@@ -557,36 +557,36 @@
// 0x3d -> Select Timer 2 as TREQ (Optional)
// 0x3e -> Select Timer 3 as TREQ (Optional)
// 0x3f -> Permanent request, for unpaced transfers.
-#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _U(0x00)
-#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _U(0x001f8000)
-#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _U(20)
-#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB _U(15)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB _u(15)
#define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
-#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _U(0x3b)
-#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _U(0x3c)
-#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _U(0x3d)
-#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _U(0x3e)
-#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _U(0x3f)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
// -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_CHAIN_TO
// Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_.
// Reset value is equal to channel number (1).
-#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET _U(0x1)
-#define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS _U(0x00007800)
-#define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB _U(14)
-#define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB _U(11)
+#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET _u(0x1)
+#define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB _u(11)
#define DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_RING_SEL
// Description : Select whether RING_SIZE applies to read or write addresses.
// If 0, read addresses are wrapped on a (1 << RING_SIZE)
// boundary. If 1, write addresses are wrapped.
-#define DMA_CH1_CTRL_TRIG_RING_SEL_RESET _U(0x0)
-#define DMA_CH1_CTRL_TRIG_RING_SEL_BITS _U(0x00000400)
-#define DMA_CH1_CTRL_TRIG_RING_SEL_MSB _U(10)
-#define DMA_CH1_CTRL_TRIG_RING_SEL_LSB _U(10)
+#define DMA_CH1_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH1_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH1_CTRL_TRIG_RING_SEL_LSB _u(10)
#define DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_RING_SIZE
@@ -599,12 +599,12 @@
// apply to either read or write addresses, based on value of
// RING_SEL.
// 0x0 -> RING_NONE
-#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET _U(0x0)
-#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS _U(0x000003c0)
-#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB _U(9)
-#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB _U(6)
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB _u(6)
#define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW"
-#define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _U(0x0)
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
// -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_INCR_WRITE
// Description : If 1, the write address increments with each transfer. If 0,
@@ -612,10 +612,10 @@
//
// Generally this should be disabled for memory-to-peripheral
// transfers.
-#define DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET _U(0x0)
-#define DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS _U(0x00000020)
-#define DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB _U(5)
-#define DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB _U(5)
+#define DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB _u(5)
#define DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_INCR_READ
@@ -624,10 +624,10 @@
//
// Generally this should be disabled for peripheral-to-memory
// transfers.
-#define DMA_CH1_CTRL_TRIG_INCR_READ_RESET _U(0x0)
-#define DMA_CH1_CTRL_TRIG_INCR_READ_BITS _U(0x00000010)
-#define DMA_CH1_CTRL_TRIG_INCR_READ_MSB _U(4)
-#define DMA_CH1_CTRL_TRIG_INCR_READ_LSB _U(4)
+#define DMA_CH1_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH1_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH1_CTRL_TRIG_INCR_READ_LSB _u(4)
#define DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_DATA_SIZE
@@ -637,14 +637,14 @@
// 0x0 -> SIZE_BYTE
// 0x1 -> SIZE_HALFWORD
// 0x2 -> SIZE_WORD
-#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET _U(0x0)
-#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS _U(0x0000000c)
-#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB _U(3)
-#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB _U(2)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB _u(2)
#define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
-#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _U(0x0)
-#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _U(0x1)
-#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _U(0x2)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
// -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_HIGH_PRIORITY
// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
@@ -657,10 +657,10 @@
// channels. The DMA's bus priority is not changed. If the DMA is
// not saturated then a low priority channel will see no loss of
// throughput.
-#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET _U(0x0)
-#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS _U(0x00000002)
-#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB _U(1)
-#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB _U(1)
+#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_EN
@@ -670,124 +670,124 @@
// 0, the channel will ignore triggers, stop issuing transfers,
// and pause the current transfer sequence (i.e. BUSY will remain
// high if already high)
-#define DMA_CH1_CTRL_TRIG_EN_RESET _U(0x0)
-#define DMA_CH1_CTRL_TRIG_EN_BITS _U(0x00000001)
-#define DMA_CH1_CTRL_TRIG_EN_MSB _U(0)
-#define DMA_CH1_CTRL_TRIG_EN_LSB _U(0)
+#define DMA_CH1_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH1_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH1_CTRL_TRIG_EN_LSB _u(0)
#define DMA_CH1_CTRL_TRIG_EN_ACCESS "RW"
// =============================================================================
// Register : DMA_CH1_AL1_CTRL
// Description : Alias for channel 1 CTRL register
-#define DMA_CH1_AL1_CTRL_OFFSET _U(0x00000050)
-#define DMA_CH1_AL1_CTRL_BITS _U(0xffffffff)
+#define DMA_CH1_AL1_CTRL_OFFSET _u(0x00000050)
+#define DMA_CH1_AL1_CTRL_BITS _u(0xffffffff)
#define DMA_CH1_AL1_CTRL_RESET "-"
-#define DMA_CH1_AL1_CTRL_MSB _U(31)
-#define DMA_CH1_AL1_CTRL_LSB _U(0)
+#define DMA_CH1_AL1_CTRL_MSB _u(31)
+#define DMA_CH1_AL1_CTRL_LSB _u(0)
#define DMA_CH1_AL1_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH1_AL1_READ_ADDR
// Description : Alias for channel 1 READ_ADDR register
-#define DMA_CH1_AL1_READ_ADDR_OFFSET _U(0x00000054)
-#define DMA_CH1_AL1_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH1_AL1_READ_ADDR_OFFSET _u(0x00000054)
+#define DMA_CH1_AL1_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH1_AL1_READ_ADDR_RESET "-"
-#define DMA_CH1_AL1_READ_ADDR_MSB _U(31)
-#define DMA_CH1_AL1_READ_ADDR_LSB _U(0)
+#define DMA_CH1_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH1_AL1_READ_ADDR_LSB _u(0)
#define DMA_CH1_AL1_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH1_AL1_WRITE_ADDR
// Description : Alias for channel 1 WRITE_ADDR register
-#define DMA_CH1_AL1_WRITE_ADDR_OFFSET _U(0x00000058)
-#define DMA_CH1_AL1_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH1_AL1_WRITE_ADDR_OFFSET _u(0x00000058)
+#define DMA_CH1_AL1_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH1_AL1_WRITE_ADDR_RESET "-"
-#define DMA_CH1_AL1_WRITE_ADDR_MSB _U(31)
-#define DMA_CH1_AL1_WRITE_ADDR_LSB _U(0)
+#define DMA_CH1_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH1_AL1_WRITE_ADDR_LSB _u(0)
#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH1_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 1 TRANS_COUNT register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET _U(0x0000005c)
-#define DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS _U(0xffffffff)
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000005c)
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
#define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET "-"
-#define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB _U(31)
-#define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB _U(0)
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB _u(0)
#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH1_AL2_CTRL
// Description : Alias for channel 1 CTRL register
-#define DMA_CH1_AL2_CTRL_OFFSET _U(0x00000060)
-#define DMA_CH1_AL2_CTRL_BITS _U(0xffffffff)
+#define DMA_CH1_AL2_CTRL_OFFSET _u(0x00000060)
+#define DMA_CH1_AL2_CTRL_BITS _u(0xffffffff)
#define DMA_CH1_AL2_CTRL_RESET "-"
-#define DMA_CH1_AL2_CTRL_MSB _U(31)
-#define DMA_CH1_AL2_CTRL_LSB _U(0)
+#define DMA_CH1_AL2_CTRL_MSB _u(31)
+#define DMA_CH1_AL2_CTRL_LSB _u(0)
#define DMA_CH1_AL2_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH1_AL2_TRANS_COUNT
// Description : Alias for channel 1 TRANS_COUNT register
-#define DMA_CH1_AL2_TRANS_COUNT_OFFSET _U(0x00000064)
-#define DMA_CH1_AL2_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH1_AL2_TRANS_COUNT_OFFSET _u(0x00000064)
+#define DMA_CH1_AL2_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH1_AL2_TRANS_COUNT_RESET "-"
-#define DMA_CH1_AL2_TRANS_COUNT_MSB _U(31)
-#define DMA_CH1_AL2_TRANS_COUNT_LSB _U(0)
+#define DMA_CH1_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH1_AL2_TRANS_COUNT_LSB _u(0)
#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH1_AL2_READ_ADDR
// Description : Alias for channel 1 READ_ADDR register
-#define DMA_CH1_AL2_READ_ADDR_OFFSET _U(0x00000068)
-#define DMA_CH1_AL2_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH1_AL2_READ_ADDR_OFFSET _u(0x00000068)
+#define DMA_CH1_AL2_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH1_AL2_READ_ADDR_RESET "-"
-#define DMA_CH1_AL2_READ_ADDR_MSB _U(31)
-#define DMA_CH1_AL2_READ_ADDR_LSB _U(0)
+#define DMA_CH1_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH1_AL2_READ_ADDR_LSB _u(0)
#define DMA_CH1_AL2_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH1_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 1 WRITE_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET _U(0x0000006c)
-#define DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000006c)
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET "-"
-#define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB _U(31)
-#define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB _U(0)
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB _u(0)
#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH1_AL3_CTRL
// Description : Alias for channel 1 CTRL register
-#define DMA_CH1_AL3_CTRL_OFFSET _U(0x00000070)
-#define DMA_CH1_AL3_CTRL_BITS _U(0xffffffff)
+#define DMA_CH1_AL3_CTRL_OFFSET _u(0x00000070)
+#define DMA_CH1_AL3_CTRL_BITS _u(0xffffffff)
#define DMA_CH1_AL3_CTRL_RESET "-"
-#define DMA_CH1_AL3_CTRL_MSB _U(31)
-#define DMA_CH1_AL3_CTRL_LSB _U(0)
+#define DMA_CH1_AL3_CTRL_MSB _u(31)
+#define DMA_CH1_AL3_CTRL_LSB _u(0)
#define DMA_CH1_AL3_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH1_AL3_WRITE_ADDR
// Description : Alias for channel 1 WRITE_ADDR register
-#define DMA_CH1_AL3_WRITE_ADDR_OFFSET _U(0x00000074)
-#define DMA_CH1_AL3_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH1_AL3_WRITE_ADDR_OFFSET _u(0x00000074)
+#define DMA_CH1_AL3_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH1_AL3_WRITE_ADDR_RESET "-"
-#define DMA_CH1_AL3_WRITE_ADDR_MSB _U(31)
-#define DMA_CH1_AL3_WRITE_ADDR_LSB _U(0)
+#define DMA_CH1_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH1_AL3_WRITE_ADDR_LSB _u(0)
#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH1_AL3_TRANS_COUNT
// Description : Alias for channel 1 TRANS_COUNT register
-#define DMA_CH1_AL3_TRANS_COUNT_OFFSET _U(0x00000078)
-#define DMA_CH1_AL3_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH1_AL3_TRANS_COUNT_OFFSET _u(0x00000078)
+#define DMA_CH1_AL3_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH1_AL3_TRANS_COUNT_RESET "-"
-#define DMA_CH1_AL3_TRANS_COUNT_MSB _U(31)
-#define DMA_CH1_AL3_TRANS_COUNT_LSB _U(0)
+#define DMA_CH1_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH1_AL3_TRANS_COUNT_LSB _u(0)
#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH1_AL3_READ_ADDR_TRIG
// Description : Alias for channel 1 READ_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET _U(0x0000007c)
-#define DMA_CH1_AL3_READ_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000007c)
+#define DMA_CH1_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH1_AL3_READ_ADDR_TRIG_RESET "-"
-#define DMA_CH1_AL3_READ_ADDR_TRIG_MSB _U(31)
-#define DMA_CH1_AL3_READ_ADDR_TRIG_LSB _U(0)
+#define DMA_CH1_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH1_AL3_READ_ADDR_TRIG_LSB _u(0)
#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH2_READ_ADDR
@@ -795,11 +795,11 @@
// This register updates automatically each time a read completes.
// The current value is the next address to be read by this
// channel.
-#define DMA_CH2_READ_ADDR_OFFSET _U(0x00000080)
-#define DMA_CH2_READ_ADDR_BITS _U(0xffffffff)
-#define DMA_CH2_READ_ADDR_RESET _U(0x00000000)
-#define DMA_CH2_READ_ADDR_MSB _U(31)
-#define DMA_CH2_READ_ADDR_LSB _U(0)
+#define DMA_CH2_READ_ADDR_OFFSET _u(0x00000080)
+#define DMA_CH2_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH2_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH2_READ_ADDR_MSB _u(31)
+#define DMA_CH2_READ_ADDR_LSB _u(0)
#define DMA_CH2_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH2_WRITE_ADDR
@@ -807,11 +807,11 @@
// This register updates automatically each time a write
// completes. The current value is the next address to be written
// by this channel.
-#define DMA_CH2_WRITE_ADDR_OFFSET _U(0x00000084)
-#define DMA_CH2_WRITE_ADDR_BITS _U(0xffffffff)
-#define DMA_CH2_WRITE_ADDR_RESET _U(0x00000000)
-#define DMA_CH2_WRITE_ADDR_MSB _U(31)
-#define DMA_CH2_WRITE_ADDR_LSB _U(0)
+#define DMA_CH2_WRITE_ADDR_OFFSET _u(0x00000084)
+#define DMA_CH2_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH2_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH2_WRITE_ADDR_MSB _u(31)
+#define DMA_CH2_WRITE_ADDR_LSB _u(0)
#define DMA_CH2_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH2_TRANS_COUNT
@@ -835,27 +835,27 @@
// is used as a trigger, the written value is used immediately as
// the length of the new transfer sequence, as well as being
// written to RELOAD.
-#define DMA_CH2_TRANS_COUNT_OFFSET _U(0x00000088)
-#define DMA_CH2_TRANS_COUNT_BITS _U(0xffffffff)
-#define DMA_CH2_TRANS_COUNT_RESET _U(0x00000000)
-#define DMA_CH2_TRANS_COUNT_MSB _U(31)
-#define DMA_CH2_TRANS_COUNT_LSB _U(0)
+#define DMA_CH2_TRANS_COUNT_OFFSET _u(0x00000088)
+#define DMA_CH2_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH2_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH2_TRANS_COUNT_LSB _u(0)
#define DMA_CH2_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH2_CTRL_TRIG
// Description : DMA Channel 2 Control and Status
-#define DMA_CH2_CTRL_TRIG_OFFSET _U(0x0000008c)
-#define DMA_CH2_CTRL_TRIG_BITS _U(0xe1ffffff)
-#define DMA_CH2_CTRL_TRIG_RESET _U(0x00001000)
+#define DMA_CH2_CTRL_TRIG_OFFSET _u(0x0000008c)
+#define DMA_CH2_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH2_CTRL_TRIG_RESET _u(0x00001000)
// -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
// halts when it encounters any bus error, and always raises its
// channel IRQ flag.
-#define DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET _U(0x0)
-#define DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS _U(0x80000000)
-#define DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB _U(31)
-#define DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB _U(31)
+#define DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB _u(31)
#define DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_READ_ERROR
@@ -864,10 +864,10 @@
// READ_ADDR shows the approximate address where the bus error was
// encountered (will not to be earlier, or more than 3 transfers
// later)
-#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET _U(0x0)
-#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS _U(0x40000000)
-#define DMA_CH2_CTRL_TRIG_READ_ERROR_MSB _U(30)
-#define DMA_CH2_CTRL_TRIG_READ_ERROR_LSB _U(30)
+#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH2_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH2_CTRL_TRIG_READ_ERROR_LSB _u(30)
#define DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_WRITE_ERROR
@@ -876,10 +876,10 @@
// WRITE_ADDR shows the approximate address where the bus error
// was encountered (will not to be earlier, or more than 5
// transfers later)
-#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET _U(0x0)
-#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS _U(0x20000000)
-#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB _U(29)
-#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB _U(29)
+#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_BUSY
@@ -890,10 +890,10 @@
//
// To terminate a sequence early (and clear the BUSY flag), see
// CHAN_ABORT.
-#define DMA_CH2_CTRL_TRIG_BUSY_RESET _U(0x0)
-#define DMA_CH2_CTRL_TRIG_BUSY_BITS _U(0x01000000)
-#define DMA_CH2_CTRL_TRIG_BUSY_MSB _U(24)
-#define DMA_CH2_CTRL_TRIG_BUSY_LSB _U(24)
+#define DMA_CH2_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH2_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH2_CTRL_TRIG_BUSY_LSB _u(24)
#define DMA_CH2_CTRL_TRIG_BUSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_SNIFF_EN
@@ -904,10 +904,10 @@
//
// This allows checksum to be enabled or disabled on a
// per-control- block basis.
-#define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET _U(0x0)
-#define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS _U(0x00800000)
-#define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB _U(23)
-#define DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB _U(23)
+#define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB _u(23)
#define DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_BSWAP
@@ -915,10 +915,10 @@
// For byte data, this has no effect. For halfword data, the two
// bytes of each halfword are swapped. For word data, the four
// bytes of each word are swapped to reverse order.
-#define DMA_CH2_CTRL_TRIG_BSWAP_RESET _U(0x0)
-#define DMA_CH2_CTRL_TRIG_BSWAP_BITS _U(0x00400000)
-#define DMA_CH2_CTRL_TRIG_BSWAP_MSB _U(22)
-#define DMA_CH2_CTRL_TRIG_BSWAP_LSB _U(22)
+#define DMA_CH2_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH2_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH2_CTRL_TRIG_BSWAP_LSB _u(22)
#define DMA_CH2_CTRL_TRIG_BSWAP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_IRQ_QUIET
@@ -929,10 +929,10 @@
//
// This reduces the number of interrupts to be serviced by the CPU
// when transferring a DMA chain of many small control blocks.
-#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET _U(0x0)
-#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS _U(0x00200000)
-#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB _U(21)
-#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB _U(21)
+#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_TREQ_SEL
@@ -946,36 +946,36 @@
// 0x3d -> Select Timer 2 as TREQ (Optional)
// 0x3e -> Select Timer 3 as TREQ (Optional)
// 0x3f -> Permanent request, for unpaced transfers.
-#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _U(0x00)
-#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _U(0x001f8000)
-#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _U(20)
-#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB _U(15)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB _u(15)
#define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
-#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _U(0x3b)
-#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _U(0x3c)
-#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _U(0x3d)
-#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _U(0x3e)
-#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _U(0x3f)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
// -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_CHAIN_TO
// Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_.
// Reset value is equal to channel number (2).
-#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET _U(0x2)
-#define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS _U(0x00007800)
-#define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB _U(14)
-#define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB _U(11)
+#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET _u(0x2)
+#define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB _u(11)
#define DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_RING_SEL
// Description : Select whether RING_SIZE applies to read or write addresses.
// If 0, read addresses are wrapped on a (1 << RING_SIZE)
// boundary. If 1, write addresses are wrapped.
-#define DMA_CH2_CTRL_TRIG_RING_SEL_RESET _U(0x0)
-#define DMA_CH2_CTRL_TRIG_RING_SEL_BITS _U(0x00000400)
-#define DMA_CH2_CTRL_TRIG_RING_SEL_MSB _U(10)
-#define DMA_CH2_CTRL_TRIG_RING_SEL_LSB _U(10)
+#define DMA_CH2_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH2_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH2_CTRL_TRIG_RING_SEL_LSB _u(10)
#define DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_RING_SIZE
@@ -988,12 +988,12 @@
// apply to either read or write addresses, based on value of
// RING_SEL.
// 0x0 -> RING_NONE
-#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET _U(0x0)
-#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS _U(0x000003c0)
-#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB _U(9)
-#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB _U(6)
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB _u(6)
#define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW"
-#define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _U(0x0)
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
// -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_INCR_WRITE
// Description : If 1, the write address increments with each transfer. If 0,
@@ -1001,10 +1001,10 @@
//
// Generally this should be disabled for memory-to-peripheral
// transfers.
-#define DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET _U(0x0)
-#define DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS _U(0x00000020)
-#define DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB _U(5)
-#define DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB _U(5)
+#define DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB _u(5)
#define DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_INCR_READ
@@ -1013,10 +1013,10 @@
//
// Generally this should be disabled for peripheral-to-memory
// transfers.
-#define DMA_CH2_CTRL_TRIG_INCR_READ_RESET _U(0x0)
-#define DMA_CH2_CTRL_TRIG_INCR_READ_BITS _U(0x00000010)
-#define DMA_CH2_CTRL_TRIG_INCR_READ_MSB _U(4)
-#define DMA_CH2_CTRL_TRIG_INCR_READ_LSB _U(4)
+#define DMA_CH2_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH2_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH2_CTRL_TRIG_INCR_READ_LSB _u(4)
#define DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_DATA_SIZE
@@ -1026,14 +1026,14 @@
// 0x0 -> SIZE_BYTE
// 0x1 -> SIZE_HALFWORD
// 0x2 -> SIZE_WORD
-#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET _U(0x0)
-#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS _U(0x0000000c)
-#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB _U(3)
-#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB _U(2)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB _u(2)
#define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
-#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _U(0x0)
-#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _U(0x1)
-#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _U(0x2)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
// -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_HIGH_PRIORITY
// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
@@ -1046,10 +1046,10 @@
// channels. The DMA's bus priority is not changed. If the DMA is
// not saturated then a low priority channel will see no loss of
// throughput.
-#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET _U(0x0)
-#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS _U(0x00000002)
-#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB _U(1)
-#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB _U(1)
+#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_EN
@@ -1059,124 +1059,124 @@
// 0, the channel will ignore triggers, stop issuing transfers,
// and pause the current transfer sequence (i.e. BUSY will remain
// high if already high)
-#define DMA_CH2_CTRL_TRIG_EN_RESET _U(0x0)
-#define DMA_CH2_CTRL_TRIG_EN_BITS _U(0x00000001)
-#define DMA_CH2_CTRL_TRIG_EN_MSB _U(0)
-#define DMA_CH2_CTRL_TRIG_EN_LSB _U(0)
+#define DMA_CH2_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH2_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH2_CTRL_TRIG_EN_LSB _u(0)
#define DMA_CH2_CTRL_TRIG_EN_ACCESS "RW"
// =============================================================================
// Register : DMA_CH2_AL1_CTRL
// Description : Alias for channel 2 CTRL register
-#define DMA_CH2_AL1_CTRL_OFFSET _U(0x00000090)
-#define DMA_CH2_AL1_CTRL_BITS _U(0xffffffff)
+#define DMA_CH2_AL1_CTRL_OFFSET _u(0x00000090)
+#define DMA_CH2_AL1_CTRL_BITS _u(0xffffffff)
#define DMA_CH2_AL1_CTRL_RESET "-"
-#define DMA_CH2_AL1_CTRL_MSB _U(31)
-#define DMA_CH2_AL1_CTRL_LSB _U(0)
+#define DMA_CH2_AL1_CTRL_MSB _u(31)
+#define DMA_CH2_AL1_CTRL_LSB _u(0)
#define DMA_CH2_AL1_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH2_AL1_READ_ADDR
// Description : Alias for channel 2 READ_ADDR register
-#define DMA_CH2_AL1_READ_ADDR_OFFSET _U(0x00000094)
-#define DMA_CH2_AL1_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH2_AL1_READ_ADDR_OFFSET _u(0x00000094)
+#define DMA_CH2_AL1_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH2_AL1_READ_ADDR_RESET "-"
-#define DMA_CH2_AL1_READ_ADDR_MSB _U(31)
-#define DMA_CH2_AL1_READ_ADDR_LSB _U(0)
+#define DMA_CH2_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH2_AL1_READ_ADDR_LSB _u(0)
#define DMA_CH2_AL1_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH2_AL1_WRITE_ADDR
// Description : Alias for channel 2 WRITE_ADDR register
-#define DMA_CH2_AL1_WRITE_ADDR_OFFSET _U(0x00000098)
-#define DMA_CH2_AL1_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH2_AL1_WRITE_ADDR_OFFSET _u(0x00000098)
+#define DMA_CH2_AL1_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH2_AL1_WRITE_ADDR_RESET "-"
-#define DMA_CH2_AL1_WRITE_ADDR_MSB _U(31)
-#define DMA_CH2_AL1_WRITE_ADDR_LSB _U(0)
+#define DMA_CH2_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH2_AL1_WRITE_ADDR_LSB _u(0)
#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH2_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 2 TRANS_COUNT register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET _U(0x0000009c)
-#define DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS _U(0xffffffff)
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000009c)
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
#define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET "-"
-#define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB _U(31)
-#define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB _U(0)
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB _u(0)
#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH2_AL2_CTRL
// Description : Alias for channel 2 CTRL register
-#define DMA_CH2_AL2_CTRL_OFFSET _U(0x000000a0)
-#define DMA_CH2_AL2_CTRL_BITS _U(0xffffffff)
+#define DMA_CH2_AL2_CTRL_OFFSET _u(0x000000a0)
+#define DMA_CH2_AL2_CTRL_BITS _u(0xffffffff)
#define DMA_CH2_AL2_CTRL_RESET "-"
-#define DMA_CH2_AL2_CTRL_MSB _U(31)
-#define DMA_CH2_AL2_CTRL_LSB _U(0)
+#define DMA_CH2_AL2_CTRL_MSB _u(31)
+#define DMA_CH2_AL2_CTRL_LSB _u(0)
#define DMA_CH2_AL2_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH2_AL2_TRANS_COUNT
// Description : Alias for channel 2 TRANS_COUNT register
-#define DMA_CH2_AL2_TRANS_COUNT_OFFSET _U(0x000000a4)
-#define DMA_CH2_AL2_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH2_AL2_TRANS_COUNT_OFFSET _u(0x000000a4)
+#define DMA_CH2_AL2_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH2_AL2_TRANS_COUNT_RESET "-"
-#define DMA_CH2_AL2_TRANS_COUNT_MSB _U(31)
-#define DMA_CH2_AL2_TRANS_COUNT_LSB _U(0)
+#define DMA_CH2_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH2_AL2_TRANS_COUNT_LSB _u(0)
#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH2_AL2_READ_ADDR
// Description : Alias for channel 2 READ_ADDR register
-#define DMA_CH2_AL2_READ_ADDR_OFFSET _U(0x000000a8)
-#define DMA_CH2_AL2_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH2_AL2_READ_ADDR_OFFSET _u(0x000000a8)
+#define DMA_CH2_AL2_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH2_AL2_READ_ADDR_RESET "-"
-#define DMA_CH2_AL2_READ_ADDR_MSB _U(31)
-#define DMA_CH2_AL2_READ_ADDR_LSB _U(0)
+#define DMA_CH2_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH2_AL2_READ_ADDR_LSB _u(0)
#define DMA_CH2_AL2_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH2_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 2 WRITE_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET _U(0x000000ac)
-#define DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ac)
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET "-"
-#define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB _U(31)
-#define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB _U(0)
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB _u(0)
#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH2_AL3_CTRL
// Description : Alias for channel 2 CTRL register
-#define DMA_CH2_AL3_CTRL_OFFSET _U(0x000000b0)
-#define DMA_CH2_AL3_CTRL_BITS _U(0xffffffff)
+#define DMA_CH2_AL3_CTRL_OFFSET _u(0x000000b0)
+#define DMA_CH2_AL3_CTRL_BITS _u(0xffffffff)
#define DMA_CH2_AL3_CTRL_RESET "-"
-#define DMA_CH2_AL3_CTRL_MSB _U(31)
-#define DMA_CH2_AL3_CTRL_LSB _U(0)
+#define DMA_CH2_AL3_CTRL_MSB _u(31)
+#define DMA_CH2_AL3_CTRL_LSB _u(0)
#define DMA_CH2_AL3_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH2_AL3_WRITE_ADDR
// Description : Alias for channel 2 WRITE_ADDR register
-#define DMA_CH2_AL3_WRITE_ADDR_OFFSET _U(0x000000b4)
-#define DMA_CH2_AL3_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH2_AL3_WRITE_ADDR_OFFSET _u(0x000000b4)
+#define DMA_CH2_AL3_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH2_AL3_WRITE_ADDR_RESET "-"
-#define DMA_CH2_AL3_WRITE_ADDR_MSB _U(31)
-#define DMA_CH2_AL3_WRITE_ADDR_LSB _U(0)
+#define DMA_CH2_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH2_AL3_WRITE_ADDR_LSB _u(0)
#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH2_AL3_TRANS_COUNT
// Description : Alias for channel 2 TRANS_COUNT register
-#define DMA_CH2_AL3_TRANS_COUNT_OFFSET _U(0x000000b8)
-#define DMA_CH2_AL3_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH2_AL3_TRANS_COUNT_OFFSET _u(0x000000b8)
+#define DMA_CH2_AL3_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH2_AL3_TRANS_COUNT_RESET "-"
-#define DMA_CH2_AL3_TRANS_COUNT_MSB _U(31)
-#define DMA_CH2_AL3_TRANS_COUNT_LSB _U(0)
+#define DMA_CH2_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH2_AL3_TRANS_COUNT_LSB _u(0)
#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH2_AL3_READ_ADDR_TRIG
// Description : Alias for channel 2 READ_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET _U(0x000000bc)
-#define DMA_CH2_AL3_READ_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000bc)
+#define DMA_CH2_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH2_AL3_READ_ADDR_TRIG_RESET "-"
-#define DMA_CH2_AL3_READ_ADDR_TRIG_MSB _U(31)
-#define DMA_CH2_AL3_READ_ADDR_TRIG_LSB _U(0)
+#define DMA_CH2_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH2_AL3_READ_ADDR_TRIG_LSB _u(0)
#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH3_READ_ADDR
@@ -1184,11 +1184,11 @@
// This register updates automatically each time a read completes.
// The current value is the next address to be read by this
// channel.
-#define DMA_CH3_READ_ADDR_OFFSET _U(0x000000c0)
-#define DMA_CH3_READ_ADDR_BITS _U(0xffffffff)
-#define DMA_CH3_READ_ADDR_RESET _U(0x00000000)
-#define DMA_CH3_READ_ADDR_MSB _U(31)
-#define DMA_CH3_READ_ADDR_LSB _U(0)
+#define DMA_CH3_READ_ADDR_OFFSET _u(0x000000c0)
+#define DMA_CH3_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH3_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH3_READ_ADDR_MSB _u(31)
+#define DMA_CH3_READ_ADDR_LSB _u(0)
#define DMA_CH3_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH3_WRITE_ADDR
@@ -1196,11 +1196,11 @@
// This register updates automatically each time a write
// completes. The current value is the next address to be written
// by this channel.
-#define DMA_CH3_WRITE_ADDR_OFFSET _U(0x000000c4)
-#define DMA_CH3_WRITE_ADDR_BITS _U(0xffffffff)
-#define DMA_CH3_WRITE_ADDR_RESET _U(0x00000000)
-#define DMA_CH3_WRITE_ADDR_MSB _U(31)
-#define DMA_CH3_WRITE_ADDR_LSB _U(0)
+#define DMA_CH3_WRITE_ADDR_OFFSET _u(0x000000c4)
+#define DMA_CH3_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH3_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH3_WRITE_ADDR_LSB _u(0)
#define DMA_CH3_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH3_TRANS_COUNT
@@ -1224,27 +1224,27 @@
// is used as a trigger, the written value is used immediately as
// the length of the new transfer sequence, as well as being
// written to RELOAD.
-#define DMA_CH3_TRANS_COUNT_OFFSET _U(0x000000c8)
-#define DMA_CH3_TRANS_COUNT_BITS _U(0xffffffff)
-#define DMA_CH3_TRANS_COUNT_RESET _U(0x00000000)
-#define DMA_CH3_TRANS_COUNT_MSB _U(31)
-#define DMA_CH3_TRANS_COUNT_LSB _U(0)
+#define DMA_CH3_TRANS_COUNT_OFFSET _u(0x000000c8)
+#define DMA_CH3_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH3_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH3_TRANS_COUNT_LSB _u(0)
#define DMA_CH3_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH3_CTRL_TRIG
// Description : DMA Channel 3 Control and Status
-#define DMA_CH3_CTRL_TRIG_OFFSET _U(0x000000cc)
-#define DMA_CH3_CTRL_TRIG_BITS _U(0xe1ffffff)
-#define DMA_CH3_CTRL_TRIG_RESET _U(0x00001800)
+#define DMA_CH3_CTRL_TRIG_OFFSET _u(0x000000cc)
+#define DMA_CH3_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH3_CTRL_TRIG_RESET _u(0x00001800)
// -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
// halts when it encounters any bus error, and always raises its
// channel IRQ flag.
-#define DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET _U(0x0)
-#define DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS _U(0x80000000)
-#define DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB _U(31)
-#define DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB _U(31)
+#define DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB _u(31)
#define DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_READ_ERROR
@@ -1253,10 +1253,10 @@
// READ_ADDR shows the approximate address where the bus error was
// encountered (will not to be earlier, or more than 3 transfers
// later)
-#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET _U(0x0)
-#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS _U(0x40000000)
-#define DMA_CH3_CTRL_TRIG_READ_ERROR_MSB _U(30)
-#define DMA_CH3_CTRL_TRIG_READ_ERROR_LSB _U(30)
+#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH3_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH3_CTRL_TRIG_READ_ERROR_LSB _u(30)
#define DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_WRITE_ERROR
@@ -1265,10 +1265,10 @@
// WRITE_ADDR shows the approximate address where the bus error
// was encountered (will not to be earlier, or more than 5
// transfers later)
-#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET _U(0x0)
-#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS _U(0x20000000)
-#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB _U(29)
-#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB _U(29)
+#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_BUSY
@@ -1279,10 +1279,10 @@
//
// To terminate a sequence early (and clear the BUSY flag), see
// CHAN_ABORT.
-#define DMA_CH3_CTRL_TRIG_BUSY_RESET _U(0x0)
-#define DMA_CH3_CTRL_TRIG_BUSY_BITS _U(0x01000000)
-#define DMA_CH3_CTRL_TRIG_BUSY_MSB _U(24)
-#define DMA_CH3_CTRL_TRIG_BUSY_LSB _U(24)
+#define DMA_CH3_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH3_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH3_CTRL_TRIG_BUSY_LSB _u(24)
#define DMA_CH3_CTRL_TRIG_BUSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_SNIFF_EN
@@ -1293,10 +1293,10 @@
//
// This allows checksum to be enabled or disabled on a
// per-control- block basis.
-#define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET _U(0x0)
-#define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS _U(0x00800000)
-#define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB _U(23)
-#define DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB _U(23)
+#define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB _u(23)
#define DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_BSWAP
@@ -1304,10 +1304,10 @@
// For byte data, this has no effect. For halfword data, the two
// bytes of each halfword are swapped. For word data, the four
// bytes of each word are swapped to reverse order.
-#define DMA_CH3_CTRL_TRIG_BSWAP_RESET _U(0x0)
-#define DMA_CH3_CTRL_TRIG_BSWAP_BITS _U(0x00400000)
-#define DMA_CH3_CTRL_TRIG_BSWAP_MSB _U(22)
-#define DMA_CH3_CTRL_TRIG_BSWAP_LSB _U(22)
+#define DMA_CH3_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH3_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH3_CTRL_TRIG_BSWAP_LSB _u(22)
#define DMA_CH3_CTRL_TRIG_BSWAP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_IRQ_QUIET
@@ -1318,10 +1318,10 @@
//
// This reduces the number of interrupts to be serviced by the CPU
// when transferring a DMA chain of many small control blocks.
-#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET _U(0x0)
-#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS _U(0x00200000)
-#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB _U(21)
-#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB _U(21)
+#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_TREQ_SEL
@@ -1335,36 +1335,36 @@
// 0x3d -> Select Timer 2 as TREQ (Optional)
// 0x3e -> Select Timer 3 as TREQ (Optional)
// 0x3f -> Permanent request, for unpaced transfers.
-#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _U(0x00)
-#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _U(0x001f8000)
-#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _U(20)
-#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB _U(15)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB _u(15)
#define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
-#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _U(0x3b)
-#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _U(0x3c)
-#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _U(0x3d)
-#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _U(0x3e)
-#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _U(0x3f)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
// -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_CHAIN_TO
// Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_.
// Reset value is equal to channel number (3).
-#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET _U(0x3)
-#define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS _U(0x00007800)
-#define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB _U(14)
-#define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB _U(11)
+#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET _u(0x3)
+#define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB _u(11)
#define DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_RING_SEL
// Description : Select whether RING_SIZE applies to read or write addresses.
// If 0, read addresses are wrapped on a (1 << RING_SIZE)
// boundary. If 1, write addresses are wrapped.
-#define DMA_CH3_CTRL_TRIG_RING_SEL_RESET _U(0x0)
-#define DMA_CH3_CTRL_TRIG_RING_SEL_BITS _U(0x00000400)
-#define DMA_CH3_CTRL_TRIG_RING_SEL_MSB _U(10)
-#define DMA_CH3_CTRL_TRIG_RING_SEL_LSB _U(10)
+#define DMA_CH3_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH3_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH3_CTRL_TRIG_RING_SEL_LSB _u(10)
#define DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_RING_SIZE
@@ -1377,12 +1377,12 @@
// apply to either read or write addresses, based on value of
// RING_SEL.
// 0x0 -> RING_NONE
-#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET _U(0x0)
-#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS _U(0x000003c0)
-#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB _U(9)
-#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB _U(6)
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB _u(6)
#define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW"
-#define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _U(0x0)
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
// -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_INCR_WRITE
// Description : If 1, the write address increments with each transfer. If 0,
@@ -1390,10 +1390,10 @@
//
// Generally this should be disabled for memory-to-peripheral
// transfers.
-#define DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET _U(0x0)
-#define DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS _U(0x00000020)
-#define DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB _U(5)
-#define DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB _U(5)
+#define DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB _u(5)
#define DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_INCR_READ
@@ -1402,10 +1402,10 @@
//
// Generally this should be disabled for peripheral-to-memory
// transfers.
-#define DMA_CH3_CTRL_TRIG_INCR_READ_RESET _U(0x0)
-#define DMA_CH3_CTRL_TRIG_INCR_READ_BITS _U(0x00000010)
-#define DMA_CH3_CTRL_TRIG_INCR_READ_MSB _U(4)
-#define DMA_CH3_CTRL_TRIG_INCR_READ_LSB _U(4)
+#define DMA_CH3_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH3_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH3_CTRL_TRIG_INCR_READ_LSB _u(4)
#define DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_DATA_SIZE
@@ -1415,14 +1415,14 @@
// 0x0 -> SIZE_BYTE
// 0x1 -> SIZE_HALFWORD
// 0x2 -> SIZE_WORD
-#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET _U(0x0)
-#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS _U(0x0000000c)
-#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB _U(3)
-#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB _U(2)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB _u(2)
#define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
-#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _U(0x0)
-#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _U(0x1)
-#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _U(0x2)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
// -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_HIGH_PRIORITY
// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
@@ -1435,10 +1435,10 @@
// channels. The DMA's bus priority is not changed. If the DMA is
// not saturated then a low priority channel will see no loss of
// throughput.
-#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET _U(0x0)
-#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS _U(0x00000002)
-#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB _U(1)
-#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB _U(1)
+#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_EN
@@ -1448,124 +1448,124 @@
// 0, the channel will ignore triggers, stop issuing transfers,
// and pause the current transfer sequence (i.e. BUSY will remain
// high if already high)
-#define DMA_CH3_CTRL_TRIG_EN_RESET _U(0x0)
-#define DMA_CH3_CTRL_TRIG_EN_BITS _U(0x00000001)
-#define DMA_CH3_CTRL_TRIG_EN_MSB _U(0)
-#define DMA_CH3_CTRL_TRIG_EN_LSB _U(0)
+#define DMA_CH3_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH3_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH3_CTRL_TRIG_EN_LSB _u(0)
#define DMA_CH3_CTRL_TRIG_EN_ACCESS "RW"
// =============================================================================
// Register : DMA_CH3_AL1_CTRL
// Description : Alias for channel 3 CTRL register
-#define DMA_CH3_AL1_CTRL_OFFSET _U(0x000000d0)
-#define DMA_CH3_AL1_CTRL_BITS _U(0xffffffff)
+#define DMA_CH3_AL1_CTRL_OFFSET _u(0x000000d0)
+#define DMA_CH3_AL1_CTRL_BITS _u(0xffffffff)
#define DMA_CH3_AL1_CTRL_RESET "-"
-#define DMA_CH3_AL1_CTRL_MSB _U(31)
-#define DMA_CH3_AL1_CTRL_LSB _U(0)
+#define DMA_CH3_AL1_CTRL_MSB _u(31)
+#define DMA_CH3_AL1_CTRL_LSB _u(0)
#define DMA_CH3_AL1_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH3_AL1_READ_ADDR
// Description : Alias for channel 3 READ_ADDR register
-#define DMA_CH3_AL1_READ_ADDR_OFFSET _U(0x000000d4)
-#define DMA_CH3_AL1_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH3_AL1_READ_ADDR_OFFSET _u(0x000000d4)
+#define DMA_CH3_AL1_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH3_AL1_READ_ADDR_RESET "-"
-#define DMA_CH3_AL1_READ_ADDR_MSB _U(31)
-#define DMA_CH3_AL1_READ_ADDR_LSB _U(0)
+#define DMA_CH3_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH3_AL1_READ_ADDR_LSB _u(0)
#define DMA_CH3_AL1_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH3_AL1_WRITE_ADDR
// Description : Alias for channel 3 WRITE_ADDR register
-#define DMA_CH3_AL1_WRITE_ADDR_OFFSET _U(0x000000d8)
-#define DMA_CH3_AL1_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH3_AL1_WRITE_ADDR_OFFSET _u(0x000000d8)
+#define DMA_CH3_AL1_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH3_AL1_WRITE_ADDR_RESET "-"
-#define DMA_CH3_AL1_WRITE_ADDR_MSB _U(31)
-#define DMA_CH3_AL1_WRITE_ADDR_LSB _U(0)
+#define DMA_CH3_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH3_AL1_WRITE_ADDR_LSB _u(0)
#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH3_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 3 TRANS_COUNT register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET _U(0x000000dc)
-#define DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS _U(0xffffffff)
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000000dc)
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
#define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET "-"
-#define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB _U(31)
-#define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB _U(0)
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB _u(0)
#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH3_AL2_CTRL
// Description : Alias for channel 3 CTRL register
-#define DMA_CH3_AL2_CTRL_OFFSET _U(0x000000e0)
-#define DMA_CH3_AL2_CTRL_BITS _U(0xffffffff)
+#define DMA_CH3_AL2_CTRL_OFFSET _u(0x000000e0)
+#define DMA_CH3_AL2_CTRL_BITS _u(0xffffffff)
#define DMA_CH3_AL2_CTRL_RESET "-"
-#define DMA_CH3_AL2_CTRL_MSB _U(31)
-#define DMA_CH3_AL2_CTRL_LSB _U(0)
+#define DMA_CH3_AL2_CTRL_MSB _u(31)
+#define DMA_CH3_AL2_CTRL_LSB _u(0)
#define DMA_CH3_AL2_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH3_AL2_TRANS_COUNT
// Description : Alias for channel 3 TRANS_COUNT register
-#define DMA_CH3_AL2_TRANS_COUNT_OFFSET _U(0x000000e4)
-#define DMA_CH3_AL2_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH3_AL2_TRANS_COUNT_OFFSET _u(0x000000e4)
+#define DMA_CH3_AL2_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH3_AL2_TRANS_COUNT_RESET "-"
-#define DMA_CH3_AL2_TRANS_COUNT_MSB _U(31)
-#define DMA_CH3_AL2_TRANS_COUNT_LSB _U(0)
+#define DMA_CH3_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH3_AL2_TRANS_COUNT_LSB _u(0)
#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH3_AL2_READ_ADDR
// Description : Alias for channel 3 READ_ADDR register
-#define DMA_CH3_AL2_READ_ADDR_OFFSET _U(0x000000e8)
-#define DMA_CH3_AL2_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH3_AL2_READ_ADDR_OFFSET _u(0x000000e8)
+#define DMA_CH3_AL2_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH3_AL2_READ_ADDR_RESET "-"
-#define DMA_CH3_AL2_READ_ADDR_MSB _U(31)
-#define DMA_CH3_AL2_READ_ADDR_LSB _U(0)
+#define DMA_CH3_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH3_AL2_READ_ADDR_LSB _u(0)
#define DMA_CH3_AL2_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH3_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 3 WRITE_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET _U(0x000000ec)
-#define DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ec)
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET "-"
-#define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB _U(31)
-#define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB _U(0)
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB _u(0)
#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH3_AL3_CTRL
// Description : Alias for channel 3 CTRL register
-#define DMA_CH3_AL3_CTRL_OFFSET _U(0x000000f0)
-#define DMA_CH3_AL3_CTRL_BITS _U(0xffffffff)
+#define DMA_CH3_AL3_CTRL_OFFSET _u(0x000000f0)
+#define DMA_CH3_AL3_CTRL_BITS _u(0xffffffff)
#define DMA_CH3_AL3_CTRL_RESET "-"
-#define DMA_CH3_AL3_CTRL_MSB _U(31)
-#define DMA_CH3_AL3_CTRL_LSB _U(0)
+#define DMA_CH3_AL3_CTRL_MSB _u(31)
+#define DMA_CH3_AL3_CTRL_LSB _u(0)
#define DMA_CH3_AL3_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH3_AL3_WRITE_ADDR
// Description : Alias for channel 3 WRITE_ADDR register
-#define DMA_CH3_AL3_WRITE_ADDR_OFFSET _U(0x000000f4)
-#define DMA_CH3_AL3_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH3_AL3_WRITE_ADDR_OFFSET _u(0x000000f4)
+#define DMA_CH3_AL3_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH3_AL3_WRITE_ADDR_RESET "-"
-#define DMA_CH3_AL3_WRITE_ADDR_MSB _U(31)
-#define DMA_CH3_AL3_WRITE_ADDR_LSB _U(0)
+#define DMA_CH3_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH3_AL3_WRITE_ADDR_LSB _u(0)
#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH3_AL3_TRANS_COUNT
// Description : Alias for channel 3 TRANS_COUNT register
-#define DMA_CH3_AL3_TRANS_COUNT_OFFSET _U(0x000000f8)
-#define DMA_CH3_AL3_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH3_AL3_TRANS_COUNT_OFFSET _u(0x000000f8)
+#define DMA_CH3_AL3_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH3_AL3_TRANS_COUNT_RESET "-"
-#define DMA_CH3_AL3_TRANS_COUNT_MSB _U(31)
-#define DMA_CH3_AL3_TRANS_COUNT_LSB _U(0)
+#define DMA_CH3_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH3_AL3_TRANS_COUNT_LSB _u(0)
#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH3_AL3_READ_ADDR_TRIG
// Description : Alias for channel 3 READ_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET _U(0x000000fc)
-#define DMA_CH3_AL3_READ_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000fc)
+#define DMA_CH3_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH3_AL3_READ_ADDR_TRIG_RESET "-"
-#define DMA_CH3_AL3_READ_ADDR_TRIG_MSB _U(31)
-#define DMA_CH3_AL3_READ_ADDR_TRIG_LSB _U(0)
+#define DMA_CH3_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH3_AL3_READ_ADDR_TRIG_LSB _u(0)
#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH4_READ_ADDR
@@ -1573,11 +1573,11 @@
// This register updates automatically each time a read completes.
// The current value is the next address to be read by this
// channel.
-#define DMA_CH4_READ_ADDR_OFFSET _U(0x00000100)
-#define DMA_CH4_READ_ADDR_BITS _U(0xffffffff)
-#define DMA_CH4_READ_ADDR_RESET _U(0x00000000)
-#define DMA_CH4_READ_ADDR_MSB _U(31)
-#define DMA_CH4_READ_ADDR_LSB _U(0)
+#define DMA_CH4_READ_ADDR_OFFSET _u(0x00000100)
+#define DMA_CH4_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH4_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH4_READ_ADDR_MSB _u(31)
+#define DMA_CH4_READ_ADDR_LSB _u(0)
#define DMA_CH4_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH4_WRITE_ADDR
@@ -1585,11 +1585,11 @@
// This register updates automatically each time a write
// completes. The current value is the next address to be written
// by this channel.
-#define DMA_CH4_WRITE_ADDR_OFFSET _U(0x00000104)
-#define DMA_CH4_WRITE_ADDR_BITS _U(0xffffffff)
-#define DMA_CH4_WRITE_ADDR_RESET _U(0x00000000)
-#define DMA_CH4_WRITE_ADDR_MSB _U(31)
-#define DMA_CH4_WRITE_ADDR_LSB _U(0)
+#define DMA_CH4_WRITE_ADDR_OFFSET _u(0x00000104)
+#define DMA_CH4_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH4_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH4_WRITE_ADDR_MSB _u(31)
+#define DMA_CH4_WRITE_ADDR_LSB _u(0)
#define DMA_CH4_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH4_TRANS_COUNT
@@ -1613,27 +1613,27 @@
// is used as a trigger, the written value is used immediately as
// the length of the new transfer sequence, as well as being
// written to RELOAD.
-#define DMA_CH4_TRANS_COUNT_OFFSET _U(0x00000108)
-#define DMA_CH4_TRANS_COUNT_BITS _U(0xffffffff)
-#define DMA_CH4_TRANS_COUNT_RESET _U(0x00000000)
-#define DMA_CH4_TRANS_COUNT_MSB _U(31)
-#define DMA_CH4_TRANS_COUNT_LSB _U(0)
+#define DMA_CH4_TRANS_COUNT_OFFSET _u(0x00000108)
+#define DMA_CH4_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH4_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH4_TRANS_COUNT_MSB _u(31)
+#define DMA_CH4_TRANS_COUNT_LSB _u(0)
#define DMA_CH4_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH4_CTRL_TRIG
// Description : DMA Channel 4 Control and Status
-#define DMA_CH4_CTRL_TRIG_OFFSET _U(0x0000010c)
-#define DMA_CH4_CTRL_TRIG_BITS _U(0xe1ffffff)
-#define DMA_CH4_CTRL_TRIG_RESET _U(0x00002000)
+#define DMA_CH4_CTRL_TRIG_OFFSET _u(0x0000010c)
+#define DMA_CH4_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH4_CTRL_TRIG_RESET _u(0x00002000)
// -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
// halts when it encounters any bus error, and always raises its
// channel IRQ flag.
-#define DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET _U(0x0)
-#define DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS _U(0x80000000)
-#define DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB _U(31)
-#define DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB _U(31)
+#define DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB _u(31)
#define DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_READ_ERROR
@@ -1642,10 +1642,10 @@
// READ_ADDR shows the approximate address where the bus error was
// encountered (will not to be earlier, or more than 3 transfers
// later)
-#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET _U(0x0)
-#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS _U(0x40000000)
-#define DMA_CH4_CTRL_TRIG_READ_ERROR_MSB _U(30)
-#define DMA_CH4_CTRL_TRIG_READ_ERROR_LSB _U(30)
+#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH4_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH4_CTRL_TRIG_READ_ERROR_LSB _u(30)
#define DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_WRITE_ERROR
@@ -1654,10 +1654,10 @@
// WRITE_ADDR shows the approximate address where the bus error
// was encountered (will not to be earlier, or more than 5
// transfers later)
-#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET _U(0x0)
-#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS _U(0x20000000)
-#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB _U(29)
-#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB _U(29)
+#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_BUSY
@@ -1668,10 +1668,10 @@
//
// To terminate a sequence early (and clear the BUSY flag), see
// CHAN_ABORT.
-#define DMA_CH4_CTRL_TRIG_BUSY_RESET _U(0x0)
-#define DMA_CH4_CTRL_TRIG_BUSY_BITS _U(0x01000000)
-#define DMA_CH4_CTRL_TRIG_BUSY_MSB _U(24)
-#define DMA_CH4_CTRL_TRIG_BUSY_LSB _U(24)
+#define DMA_CH4_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH4_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH4_CTRL_TRIG_BUSY_LSB _u(24)
#define DMA_CH4_CTRL_TRIG_BUSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_SNIFF_EN
@@ -1682,10 +1682,10 @@
//
// This allows checksum to be enabled or disabled on a
// per-control- block basis.
-#define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET _U(0x0)
-#define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS _U(0x00800000)
-#define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB _U(23)
-#define DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB _U(23)
+#define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB _u(23)
#define DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_BSWAP
@@ -1693,10 +1693,10 @@
// For byte data, this has no effect. For halfword data, the two
// bytes of each halfword are swapped. For word data, the four
// bytes of each word are swapped to reverse order.
-#define DMA_CH4_CTRL_TRIG_BSWAP_RESET _U(0x0)
-#define DMA_CH4_CTRL_TRIG_BSWAP_BITS _U(0x00400000)
-#define DMA_CH4_CTRL_TRIG_BSWAP_MSB _U(22)
-#define DMA_CH4_CTRL_TRIG_BSWAP_LSB _U(22)
+#define DMA_CH4_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH4_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH4_CTRL_TRIG_BSWAP_LSB _u(22)
#define DMA_CH4_CTRL_TRIG_BSWAP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_IRQ_QUIET
@@ -1707,10 +1707,10 @@
//
// This reduces the number of interrupts to be serviced by the CPU
// when transferring a DMA chain of many small control blocks.
-#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET _U(0x0)
-#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS _U(0x00200000)
-#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB _U(21)
-#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB _U(21)
+#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_TREQ_SEL
@@ -1724,36 +1724,36 @@
// 0x3d -> Select Timer 2 as TREQ (Optional)
// 0x3e -> Select Timer 3 as TREQ (Optional)
// 0x3f -> Permanent request, for unpaced transfers.
-#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _U(0x00)
-#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _U(0x001f8000)
-#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _U(20)
-#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB _U(15)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB _u(15)
#define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
-#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _U(0x3b)
-#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _U(0x3c)
-#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _U(0x3d)
-#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _U(0x3e)
-#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _U(0x3f)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
// -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_CHAIN_TO
// Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_.
// Reset value is equal to channel number (4).
-#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET _U(0x4)
-#define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS _U(0x00007800)
-#define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB _U(14)
-#define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB _U(11)
+#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET _u(0x4)
+#define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB _u(11)
#define DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_RING_SEL
// Description : Select whether RING_SIZE applies to read or write addresses.
// If 0, read addresses are wrapped on a (1 << RING_SIZE)
// boundary. If 1, write addresses are wrapped.
-#define DMA_CH4_CTRL_TRIG_RING_SEL_RESET _U(0x0)
-#define DMA_CH4_CTRL_TRIG_RING_SEL_BITS _U(0x00000400)
-#define DMA_CH4_CTRL_TRIG_RING_SEL_MSB _U(10)
-#define DMA_CH4_CTRL_TRIG_RING_SEL_LSB _U(10)
+#define DMA_CH4_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH4_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH4_CTRL_TRIG_RING_SEL_LSB _u(10)
#define DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_RING_SIZE
@@ -1766,12 +1766,12 @@
// apply to either read or write addresses, based on value of
// RING_SEL.
// 0x0 -> RING_NONE
-#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET _U(0x0)
-#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS _U(0x000003c0)
-#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB _U(9)
-#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB _U(6)
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB _u(6)
#define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW"
-#define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _U(0x0)
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
// -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_INCR_WRITE
// Description : If 1, the write address increments with each transfer. If 0,
@@ -1779,10 +1779,10 @@
//
// Generally this should be disabled for memory-to-peripheral
// transfers.
-#define DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET _U(0x0)
-#define DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS _U(0x00000020)
-#define DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB _U(5)
-#define DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB _U(5)
+#define DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB _u(5)
#define DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_INCR_READ
@@ -1791,10 +1791,10 @@
//
// Generally this should be disabled for peripheral-to-memory
// transfers.
-#define DMA_CH4_CTRL_TRIG_INCR_READ_RESET _U(0x0)
-#define DMA_CH4_CTRL_TRIG_INCR_READ_BITS _U(0x00000010)
-#define DMA_CH4_CTRL_TRIG_INCR_READ_MSB _U(4)
-#define DMA_CH4_CTRL_TRIG_INCR_READ_LSB _U(4)
+#define DMA_CH4_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH4_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH4_CTRL_TRIG_INCR_READ_LSB _u(4)
#define DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_DATA_SIZE
@@ -1804,14 +1804,14 @@
// 0x0 -> SIZE_BYTE
// 0x1 -> SIZE_HALFWORD
// 0x2 -> SIZE_WORD
-#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET _U(0x0)
-#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS _U(0x0000000c)
-#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB _U(3)
-#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB _U(2)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB _u(2)
#define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
-#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _U(0x0)
-#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _U(0x1)
-#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _U(0x2)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
// -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_HIGH_PRIORITY
// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
@@ -1824,10 +1824,10 @@
// channels. The DMA's bus priority is not changed. If the DMA is
// not saturated then a low priority channel will see no loss of
// throughput.
-#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET _U(0x0)
-#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS _U(0x00000002)
-#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB _U(1)
-#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB _U(1)
+#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_EN
@@ -1837,124 +1837,124 @@
// 0, the channel will ignore triggers, stop issuing transfers,
// and pause the current transfer sequence (i.e. BUSY will remain
// high if already high)
-#define DMA_CH4_CTRL_TRIG_EN_RESET _U(0x0)
-#define DMA_CH4_CTRL_TRIG_EN_BITS _U(0x00000001)
-#define DMA_CH4_CTRL_TRIG_EN_MSB _U(0)
-#define DMA_CH4_CTRL_TRIG_EN_LSB _U(0)
+#define DMA_CH4_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH4_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH4_CTRL_TRIG_EN_LSB _u(0)
#define DMA_CH4_CTRL_TRIG_EN_ACCESS "RW"
// =============================================================================
// Register : DMA_CH4_AL1_CTRL
// Description : Alias for channel 4 CTRL register
-#define DMA_CH4_AL1_CTRL_OFFSET _U(0x00000110)
-#define DMA_CH4_AL1_CTRL_BITS _U(0xffffffff)
+#define DMA_CH4_AL1_CTRL_OFFSET _u(0x00000110)
+#define DMA_CH4_AL1_CTRL_BITS _u(0xffffffff)
#define DMA_CH4_AL1_CTRL_RESET "-"
-#define DMA_CH4_AL1_CTRL_MSB _U(31)
-#define DMA_CH4_AL1_CTRL_LSB _U(0)
+#define DMA_CH4_AL1_CTRL_MSB _u(31)
+#define DMA_CH4_AL1_CTRL_LSB _u(0)
#define DMA_CH4_AL1_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH4_AL1_READ_ADDR
// Description : Alias for channel 4 READ_ADDR register
-#define DMA_CH4_AL1_READ_ADDR_OFFSET _U(0x00000114)
-#define DMA_CH4_AL1_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH4_AL1_READ_ADDR_OFFSET _u(0x00000114)
+#define DMA_CH4_AL1_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH4_AL1_READ_ADDR_RESET "-"
-#define DMA_CH4_AL1_READ_ADDR_MSB _U(31)
-#define DMA_CH4_AL1_READ_ADDR_LSB _U(0)
+#define DMA_CH4_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH4_AL1_READ_ADDR_LSB _u(0)
#define DMA_CH4_AL1_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH4_AL1_WRITE_ADDR
// Description : Alias for channel 4 WRITE_ADDR register
-#define DMA_CH4_AL1_WRITE_ADDR_OFFSET _U(0x00000118)
-#define DMA_CH4_AL1_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH4_AL1_WRITE_ADDR_OFFSET _u(0x00000118)
+#define DMA_CH4_AL1_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH4_AL1_WRITE_ADDR_RESET "-"
-#define DMA_CH4_AL1_WRITE_ADDR_MSB _U(31)
-#define DMA_CH4_AL1_WRITE_ADDR_LSB _U(0)
+#define DMA_CH4_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH4_AL1_WRITE_ADDR_LSB _u(0)
#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH4_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 4 TRANS_COUNT register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET _U(0x0000011c)
-#define DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS _U(0xffffffff)
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000011c)
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
#define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET "-"
-#define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB _U(31)
-#define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB _U(0)
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB _u(0)
#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH4_AL2_CTRL
// Description : Alias for channel 4 CTRL register
-#define DMA_CH4_AL2_CTRL_OFFSET _U(0x00000120)
-#define DMA_CH4_AL2_CTRL_BITS _U(0xffffffff)
+#define DMA_CH4_AL2_CTRL_OFFSET _u(0x00000120)
+#define DMA_CH4_AL2_CTRL_BITS _u(0xffffffff)
#define DMA_CH4_AL2_CTRL_RESET "-"
-#define DMA_CH4_AL2_CTRL_MSB _U(31)
-#define DMA_CH4_AL2_CTRL_LSB _U(0)
+#define DMA_CH4_AL2_CTRL_MSB _u(31)
+#define DMA_CH4_AL2_CTRL_LSB _u(0)
#define DMA_CH4_AL2_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH4_AL2_TRANS_COUNT
// Description : Alias for channel 4 TRANS_COUNT register
-#define DMA_CH4_AL2_TRANS_COUNT_OFFSET _U(0x00000124)
-#define DMA_CH4_AL2_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH4_AL2_TRANS_COUNT_OFFSET _u(0x00000124)
+#define DMA_CH4_AL2_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH4_AL2_TRANS_COUNT_RESET "-"
-#define DMA_CH4_AL2_TRANS_COUNT_MSB _U(31)
-#define DMA_CH4_AL2_TRANS_COUNT_LSB _U(0)
+#define DMA_CH4_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH4_AL2_TRANS_COUNT_LSB _u(0)
#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH4_AL2_READ_ADDR
// Description : Alias for channel 4 READ_ADDR register
-#define DMA_CH4_AL2_READ_ADDR_OFFSET _U(0x00000128)
-#define DMA_CH4_AL2_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH4_AL2_READ_ADDR_OFFSET _u(0x00000128)
+#define DMA_CH4_AL2_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH4_AL2_READ_ADDR_RESET "-"
-#define DMA_CH4_AL2_READ_ADDR_MSB _U(31)
-#define DMA_CH4_AL2_READ_ADDR_LSB _U(0)
+#define DMA_CH4_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH4_AL2_READ_ADDR_LSB _u(0)
#define DMA_CH4_AL2_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH4_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 4 WRITE_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET _U(0x0000012c)
-#define DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000012c)
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET "-"
-#define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB _U(31)
-#define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB _U(0)
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB _u(0)
#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH4_AL3_CTRL
// Description : Alias for channel 4 CTRL register
-#define DMA_CH4_AL3_CTRL_OFFSET _U(0x00000130)
-#define DMA_CH4_AL3_CTRL_BITS _U(0xffffffff)
+#define DMA_CH4_AL3_CTRL_OFFSET _u(0x00000130)
+#define DMA_CH4_AL3_CTRL_BITS _u(0xffffffff)
#define DMA_CH4_AL3_CTRL_RESET "-"
-#define DMA_CH4_AL3_CTRL_MSB _U(31)
-#define DMA_CH4_AL3_CTRL_LSB _U(0)
+#define DMA_CH4_AL3_CTRL_MSB _u(31)
+#define DMA_CH4_AL3_CTRL_LSB _u(0)
#define DMA_CH4_AL3_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH4_AL3_WRITE_ADDR
// Description : Alias for channel 4 WRITE_ADDR register
-#define DMA_CH4_AL3_WRITE_ADDR_OFFSET _U(0x00000134)
-#define DMA_CH4_AL3_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH4_AL3_WRITE_ADDR_OFFSET _u(0x00000134)
+#define DMA_CH4_AL3_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH4_AL3_WRITE_ADDR_RESET "-"
-#define DMA_CH4_AL3_WRITE_ADDR_MSB _U(31)
-#define DMA_CH4_AL3_WRITE_ADDR_LSB _U(0)
+#define DMA_CH4_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH4_AL3_WRITE_ADDR_LSB _u(0)
#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH4_AL3_TRANS_COUNT
// Description : Alias for channel 4 TRANS_COUNT register
-#define DMA_CH4_AL3_TRANS_COUNT_OFFSET _U(0x00000138)
-#define DMA_CH4_AL3_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH4_AL3_TRANS_COUNT_OFFSET _u(0x00000138)
+#define DMA_CH4_AL3_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH4_AL3_TRANS_COUNT_RESET "-"
-#define DMA_CH4_AL3_TRANS_COUNT_MSB _U(31)
-#define DMA_CH4_AL3_TRANS_COUNT_LSB _U(0)
+#define DMA_CH4_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH4_AL3_TRANS_COUNT_LSB _u(0)
#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH4_AL3_READ_ADDR_TRIG
// Description : Alias for channel 4 READ_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET _U(0x0000013c)
-#define DMA_CH4_AL3_READ_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000013c)
+#define DMA_CH4_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH4_AL3_READ_ADDR_TRIG_RESET "-"
-#define DMA_CH4_AL3_READ_ADDR_TRIG_MSB _U(31)
-#define DMA_CH4_AL3_READ_ADDR_TRIG_LSB _U(0)
+#define DMA_CH4_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH4_AL3_READ_ADDR_TRIG_LSB _u(0)
#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH5_READ_ADDR
@@ -1962,11 +1962,11 @@
// This register updates automatically each time a read completes.
// The current value is the next address to be read by this
// channel.
-#define DMA_CH5_READ_ADDR_OFFSET _U(0x00000140)
-#define DMA_CH5_READ_ADDR_BITS _U(0xffffffff)
-#define DMA_CH5_READ_ADDR_RESET _U(0x00000000)
-#define DMA_CH5_READ_ADDR_MSB _U(31)
-#define DMA_CH5_READ_ADDR_LSB _U(0)
+#define DMA_CH5_READ_ADDR_OFFSET _u(0x00000140)
+#define DMA_CH5_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH5_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH5_READ_ADDR_MSB _u(31)
+#define DMA_CH5_READ_ADDR_LSB _u(0)
#define DMA_CH5_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH5_WRITE_ADDR
@@ -1974,11 +1974,11 @@
// This register updates automatically each time a write
// completes. The current value is the next address to be written
// by this channel.
-#define DMA_CH5_WRITE_ADDR_OFFSET _U(0x00000144)
-#define DMA_CH5_WRITE_ADDR_BITS _U(0xffffffff)
-#define DMA_CH5_WRITE_ADDR_RESET _U(0x00000000)
-#define DMA_CH5_WRITE_ADDR_MSB _U(31)
-#define DMA_CH5_WRITE_ADDR_LSB _U(0)
+#define DMA_CH5_WRITE_ADDR_OFFSET _u(0x00000144)
+#define DMA_CH5_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH5_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH5_WRITE_ADDR_MSB _u(31)
+#define DMA_CH5_WRITE_ADDR_LSB _u(0)
#define DMA_CH5_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH5_TRANS_COUNT
@@ -2002,27 +2002,27 @@
// is used as a trigger, the written value is used immediately as
// the length of the new transfer sequence, as well as being
// written to RELOAD.
-#define DMA_CH5_TRANS_COUNT_OFFSET _U(0x00000148)
-#define DMA_CH5_TRANS_COUNT_BITS _U(0xffffffff)
-#define DMA_CH5_TRANS_COUNT_RESET _U(0x00000000)
-#define DMA_CH5_TRANS_COUNT_MSB _U(31)
-#define DMA_CH5_TRANS_COUNT_LSB _U(0)
+#define DMA_CH5_TRANS_COUNT_OFFSET _u(0x00000148)
+#define DMA_CH5_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH5_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH5_TRANS_COUNT_MSB _u(31)
+#define DMA_CH5_TRANS_COUNT_LSB _u(0)
#define DMA_CH5_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH5_CTRL_TRIG
// Description : DMA Channel 5 Control and Status
-#define DMA_CH5_CTRL_TRIG_OFFSET _U(0x0000014c)
-#define DMA_CH5_CTRL_TRIG_BITS _U(0xe1ffffff)
-#define DMA_CH5_CTRL_TRIG_RESET _U(0x00002800)
+#define DMA_CH5_CTRL_TRIG_OFFSET _u(0x0000014c)
+#define DMA_CH5_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH5_CTRL_TRIG_RESET _u(0x00002800)
// -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
// halts when it encounters any bus error, and always raises its
// channel IRQ flag.
-#define DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET _U(0x0)
-#define DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS _U(0x80000000)
-#define DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB _U(31)
-#define DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB _U(31)
+#define DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB _u(31)
#define DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_READ_ERROR
@@ -2031,10 +2031,10 @@
// READ_ADDR shows the approximate address where the bus error was
// encountered (will not to be earlier, or more than 3 transfers
// later)
-#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET _U(0x0)
-#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS _U(0x40000000)
-#define DMA_CH5_CTRL_TRIG_READ_ERROR_MSB _U(30)
-#define DMA_CH5_CTRL_TRIG_READ_ERROR_LSB _U(30)
+#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH5_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH5_CTRL_TRIG_READ_ERROR_LSB _u(30)
#define DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_WRITE_ERROR
@@ -2043,10 +2043,10 @@
// WRITE_ADDR shows the approximate address where the bus error
// was encountered (will not to be earlier, or more than 5
// transfers later)
-#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET _U(0x0)
-#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS _U(0x20000000)
-#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB _U(29)
-#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB _U(29)
+#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_BUSY
@@ -2057,10 +2057,10 @@
//
// To terminate a sequence early (and clear the BUSY flag), see
// CHAN_ABORT.
-#define DMA_CH5_CTRL_TRIG_BUSY_RESET _U(0x0)
-#define DMA_CH5_CTRL_TRIG_BUSY_BITS _U(0x01000000)
-#define DMA_CH5_CTRL_TRIG_BUSY_MSB _U(24)
-#define DMA_CH5_CTRL_TRIG_BUSY_LSB _U(24)
+#define DMA_CH5_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH5_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH5_CTRL_TRIG_BUSY_LSB _u(24)
#define DMA_CH5_CTRL_TRIG_BUSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_SNIFF_EN
@@ -2071,10 +2071,10 @@
//
// This allows checksum to be enabled or disabled on a
// per-control- block basis.
-#define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET _U(0x0)
-#define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS _U(0x00800000)
-#define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB _U(23)
-#define DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB _U(23)
+#define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB _u(23)
#define DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_BSWAP
@@ -2082,10 +2082,10 @@
// For byte data, this has no effect. For halfword data, the two
// bytes of each halfword are swapped. For word data, the four
// bytes of each word are swapped to reverse order.
-#define DMA_CH5_CTRL_TRIG_BSWAP_RESET _U(0x0)
-#define DMA_CH5_CTRL_TRIG_BSWAP_BITS _U(0x00400000)
-#define DMA_CH5_CTRL_TRIG_BSWAP_MSB _U(22)
-#define DMA_CH5_CTRL_TRIG_BSWAP_LSB _U(22)
+#define DMA_CH5_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH5_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH5_CTRL_TRIG_BSWAP_LSB _u(22)
#define DMA_CH5_CTRL_TRIG_BSWAP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_IRQ_QUIET
@@ -2096,10 +2096,10 @@
//
// This reduces the number of interrupts to be serviced by the CPU
// when transferring a DMA chain of many small control blocks.
-#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET _U(0x0)
-#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS _U(0x00200000)
-#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB _U(21)
-#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB _U(21)
+#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_TREQ_SEL
@@ -2113,36 +2113,36 @@
// 0x3d -> Select Timer 2 as TREQ (Optional)
// 0x3e -> Select Timer 3 as TREQ (Optional)
// 0x3f -> Permanent request, for unpaced transfers.
-#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _U(0x00)
-#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _U(0x001f8000)
-#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _U(20)
-#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB _U(15)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB _u(15)
#define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
-#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _U(0x3b)
-#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _U(0x3c)
-#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _U(0x3d)
-#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _U(0x3e)
-#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _U(0x3f)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
// -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_CHAIN_TO
// Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_.
// Reset value is equal to channel number (5).
-#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET _U(0x5)
-#define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS _U(0x00007800)
-#define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB _U(14)
-#define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB _U(11)
+#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET _u(0x5)
+#define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB _u(11)
#define DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_RING_SEL
// Description : Select whether RING_SIZE applies to read or write addresses.
// If 0, read addresses are wrapped on a (1 << RING_SIZE)
// boundary. If 1, write addresses are wrapped.
-#define DMA_CH5_CTRL_TRIG_RING_SEL_RESET _U(0x0)
-#define DMA_CH5_CTRL_TRIG_RING_SEL_BITS _U(0x00000400)
-#define DMA_CH5_CTRL_TRIG_RING_SEL_MSB _U(10)
-#define DMA_CH5_CTRL_TRIG_RING_SEL_LSB _U(10)
+#define DMA_CH5_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH5_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH5_CTRL_TRIG_RING_SEL_LSB _u(10)
#define DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_RING_SIZE
@@ -2155,12 +2155,12 @@
// apply to either read or write addresses, based on value of
// RING_SEL.
// 0x0 -> RING_NONE
-#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET _U(0x0)
-#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS _U(0x000003c0)
-#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB _U(9)
-#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB _U(6)
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB _u(6)
#define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW"
-#define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _U(0x0)
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
// -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_INCR_WRITE
// Description : If 1, the write address increments with each transfer. If 0,
@@ -2168,10 +2168,10 @@
//
// Generally this should be disabled for memory-to-peripheral
// transfers.
-#define DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET _U(0x0)
-#define DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS _U(0x00000020)
-#define DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB _U(5)
-#define DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB _U(5)
+#define DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB _u(5)
#define DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_INCR_READ
@@ -2180,10 +2180,10 @@
//
// Generally this should be disabled for peripheral-to-memory
// transfers.
-#define DMA_CH5_CTRL_TRIG_INCR_READ_RESET _U(0x0)
-#define DMA_CH5_CTRL_TRIG_INCR_READ_BITS _U(0x00000010)
-#define DMA_CH5_CTRL_TRIG_INCR_READ_MSB _U(4)
-#define DMA_CH5_CTRL_TRIG_INCR_READ_LSB _U(4)
+#define DMA_CH5_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH5_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH5_CTRL_TRIG_INCR_READ_LSB _u(4)
#define DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_DATA_SIZE
@@ -2193,14 +2193,14 @@
// 0x0 -> SIZE_BYTE
// 0x1 -> SIZE_HALFWORD
// 0x2 -> SIZE_WORD
-#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET _U(0x0)
-#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS _U(0x0000000c)
-#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB _U(3)
-#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB _U(2)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB _u(2)
#define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
-#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _U(0x0)
-#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _U(0x1)
-#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _U(0x2)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
// -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_HIGH_PRIORITY
// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
@@ -2213,10 +2213,10 @@
// channels. The DMA's bus priority is not changed. If the DMA is
// not saturated then a low priority channel will see no loss of
// throughput.
-#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET _U(0x0)
-#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS _U(0x00000002)
-#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB _U(1)
-#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB _U(1)
+#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_EN
@@ -2226,124 +2226,124 @@
// 0, the channel will ignore triggers, stop issuing transfers,
// and pause the current transfer sequence (i.e. BUSY will remain
// high if already high)
-#define DMA_CH5_CTRL_TRIG_EN_RESET _U(0x0)
-#define DMA_CH5_CTRL_TRIG_EN_BITS _U(0x00000001)
-#define DMA_CH5_CTRL_TRIG_EN_MSB _U(0)
-#define DMA_CH5_CTRL_TRIG_EN_LSB _U(0)
+#define DMA_CH5_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH5_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH5_CTRL_TRIG_EN_LSB _u(0)
#define DMA_CH5_CTRL_TRIG_EN_ACCESS "RW"
// =============================================================================
// Register : DMA_CH5_AL1_CTRL
// Description : Alias for channel 5 CTRL register
-#define DMA_CH5_AL1_CTRL_OFFSET _U(0x00000150)
-#define DMA_CH5_AL1_CTRL_BITS _U(0xffffffff)
+#define DMA_CH5_AL1_CTRL_OFFSET _u(0x00000150)
+#define DMA_CH5_AL1_CTRL_BITS _u(0xffffffff)
#define DMA_CH5_AL1_CTRL_RESET "-"
-#define DMA_CH5_AL1_CTRL_MSB _U(31)
-#define DMA_CH5_AL1_CTRL_LSB _U(0)
+#define DMA_CH5_AL1_CTRL_MSB _u(31)
+#define DMA_CH5_AL1_CTRL_LSB _u(0)
#define DMA_CH5_AL1_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH5_AL1_READ_ADDR
// Description : Alias for channel 5 READ_ADDR register
-#define DMA_CH5_AL1_READ_ADDR_OFFSET _U(0x00000154)
-#define DMA_CH5_AL1_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH5_AL1_READ_ADDR_OFFSET _u(0x00000154)
+#define DMA_CH5_AL1_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH5_AL1_READ_ADDR_RESET "-"
-#define DMA_CH5_AL1_READ_ADDR_MSB _U(31)
-#define DMA_CH5_AL1_READ_ADDR_LSB _U(0)
+#define DMA_CH5_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH5_AL1_READ_ADDR_LSB _u(0)
#define DMA_CH5_AL1_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH5_AL1_WRITE_ADDR
// Description : Alias for channel 5 WRITE_ADDR register
-#define DMA_CH5_AL1_WRITE_ADDR_OFFSET _U(0x00000158)
-#define DMA_CH5_AL1_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH5_AL1_WRITE_ADDR_OFFSET _u(0x00000158)
+#define DMA_CH5_AL1_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH5_AL1_WRITE_ADDR_RESET "-"
-#define DMA_CH5_AL1_WRITE_ADDR_MSB _U(31)
-#define DMA_CH5_AL1_WRITE_ADDR_LSB _U(0)
+#define DMA_CH5_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH5_AL1_WRITE_ADDR_LSB _u(0)
#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH5_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 5 TRANS_COUNT register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET _U(0x0000015c)
-#define DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS _U(0xffffffff)
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000015c)
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
#define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET "-"
-#define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB _U(31)
-#define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB _U(0)
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB _u(0)
#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH5_AL2_CTRL
// Description : Alias for channel 5 CTRL register
-#define DMA_CH5_AL2_CTRL_OFFSET _U(0x00000160)
-#define DMA_CH5_AL2_CTRL_BITS _U(0xffffffff)
+#define DMA_CH5_AL2_CTRL_OFFSET _u(0x00000160)
+#define DMA_CH5_AL2_CTRL_BITS _u(0xffffffff)
#define DMA_CH5_AL2_CTRL_RESET "-"
-#define DMA_CH5_AL2_CTRL_MSB _U(31)
-#define DMA_CH5_AL2_CTRL_LSB _U(0)
+#define DMA_CH5_AL2_CTRL_MSB _u(31)
+#define DMA_CH5_AL2_CTRL_LSB _u(0)
#define DMA_CH5_AL2_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH5_AL2_TRANS_COUNT
// Description : Alias for channel 5 TRANS_COUNT register
-#define DMA_CH5_AL2_TRANS_COUNT_OFFSET _U(0x00000164)
-#define DMA_CH5_AL2_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH5_AL2_TRANS_COUNT_OFFSET _u(0x00000164)
+#define DMA_CH5_AL2_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH5_AL2_TRANS_COUNT_RESET "-"
-#define DMA_CH5_AL2_TRANS_COUNT_MSB _U(31)
-#define DMA_CH5_AL2_TRANS_COUNT_LSB _U(0)
+#define DMA_CH5_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH5_AL2_TRANS_COUNT_LSB _u(0)
#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH5_AL2_READ_ADDR
// Description : Alias for channel 5 READ_ADDR register
-#define DMA_CH5_AL2_READ_ADDR_OFFSET _U(0x00000168)
-#define DMA_CH5_AL2_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH5_AL2_READ_ADDR_OFFSET _u(0x00000168)
+#define DMA_CH5_AL2_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH5_AL2_READ_ADDR_RESET "-"
-#define DMA_CH5_AL2_READ_ADDR_MSB _U(31)
-#define DMA_CH5_AL2_READ_ADDR_LSB _U(0)
+#define DMA_CH5_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH5_AL2_READ_ADDR_LSB _u(0)
#define DMA_CH5_AL2_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH5_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 5 WRITE_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET _U(0x0000016c)
-#define DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000016c)
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET "-"
-#define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB _U(31)
-#define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB _U(0)
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB _u(0)
#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH5_AL3_CTRL
// Description : Alias for channel 5 CTRL register
-#define DMA_CH5_AL3_CTRL_OFFSET _U(0x00000170)
-#define DMA_CH5_AL3_CTRL_BITS _U(0xffffffff)
+#define DMA_CH5_AL3_CTRL_OFFSET _u(0x00000170)
+#define DMA_CH5_AL3_CTRL_BITS _u(0xffffffff)
#define DMA_CH5_AL3_CTRL_RESET "-"
-#define DMA_CH5_AL3_CTRL_MSB _U(31)
-#define DMA_CH5_AL3_CTRL_LSB _U(0)
+#define DMA_CH5_AL3_CTRL_MSB _u(31)
+#define DMA_CH5_AL3_CTRL_LSB _u(0)
#define DMA_CH5_AL3_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH5_AL3_WRITE_ADDR
// Description : Alias for channel 5 WRITE_ADDR register
-#define DMA_CH5_AL3_WRITE_ADDR_OFFSET _U(0x00000174)
-#define DMA_CH5_AL3_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH5_AL3_WRITE_ADDR_OFFSET _u(0x00000174)
+#define DMA_CH5_AL3_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH5_AL3_WRITE_ADDR_RESET "-"
-#define DMA_CH5_AL3_WRITE_ADDR_MSB _U(31)
-#define DMA_CH5_AL3_WRITE_ADDR_LSB _U(0)
+#define DMA_CH5_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH5_AL3_WRITE_ADDR_LSB _u(0)
#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH5_AL3_TRANS_COUNT
// Description : Alias for channel 5 TRANS_COUNT register
-#define DMA_CH5_AL3_TRANS_COUNT_OFFSET _U(0x00000178)
-#define DMA_CH5_AL3_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH5_AL3_TRANS_COUNT_OFFSET _u(0x00000178)
+#define DMA_CH5_AL3_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH5_AL3_TRANS_COUNT_RESET "-"
-#define DMA_CH5_AL3_TRANS_COUNT_MSB _U(31)
-#define DMA_CH5_AL3_TRANS_COUNT_LSB _U(0)
+#define DMA_CH5_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH5_AL3_TRANS_COUNT_LSB _u(0)
#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH5_AL3_READ_ADDR_TRIG
// Description : Alias for channel 5 READ_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET _U(0x0000017c)
-#define DMA_CH5_AL3_READ_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000017c)
+#define DMA_CH5_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH5_AL3_READ_ADDR_TRIG_RESET "-"
-#define DMA_CH5_AL3_READ_ADDR_TRIG_MSB _U(31)
-#define DMA_CH5_AL3_READ_ADDR_TRIG_LSB _U(0)
+#define DMA_CH5_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH5_AL3_READ_ADDR_TRIG_LSB _u(0)
#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH6_READ_ADDR
@@ -2351,11 +2351,11 @@
// This register updates automatically each time a read completes.
// The current value is the next address to be read by this
// channel.
-#define DMA_CH6_READ_ADDR_OFFSET _U(0x00000180)
-#define DMA_CH6_READ_ADDR_BITS _U(0xffffffff)
-#define DMA_CH6_READ_ADDR_RESET _U(0x00000000)
-#define DMA_CH6_READ_ADDR_MSB _U(31)
-#define DMA_CH6_READ_ADDR_LSB _U(0)
+#define DMA_CH6_READ_ADDR_OFFSET _u(0x00000180)
+#define DMA_CH6_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH6_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH6_READ_ADDR_MSB _u(31)
+#define DMA_CH6_READ_ADDR_LSB _u(0)
#define DMA_CH6_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH6_WRITE_ADDR
@@ -2363,11 +2363,11 @@
// This register updates automatically each time a write
// completes. The current value is the next address to be written
// by this channel.
-#define DMA_CH6_WRITE_ADDR_OFFSET _U(0x00000184)
-#define DMA_CH6_WRITE_ADDR_BITS _U(0xffffffff)
-#define DMA_CH6_WRITE_ADDR_RESET _U(0x00000000)
-#define DMA_CH6_WRITE_ADDR_MSB _U(31)
-#define DMA_CH6_WRITE_ADDR_LSB _U(0)
+#define DMA_CH6_WRITE_ADDR_OFFSET _u(0x00000184)
+#define DMA_CH6_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH6_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH6_WRITE_ADDR_MSB _u(31)
+#define DMA_CH6_WRITE_ADDR_LSB _u(0)
#define DMA_CH6_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH6_TRANS_COUNT
@@ -2391,27 +2391,27 @@
// is used as a trigger, the written value is used immediately as
// the length of the new transfer sequence, as well as being
// written to RELOAD.
-#define DMA_CH6_TRANS_COUNT_OFFSET _U(0x00000188)
-#define DMA_CH6_TRANS_COUNT_BITS _U(0xffffffff)
-#define DMA_CH6_TRANS_COUNT_RESET _U(0x00000000)
-#define DMA_CH6_TRANS_COUNT_MSB _U(31)
-#define DMA_CH6_TRANS_COUNT_LSB _U(0)
+#define DMA_CH6_TRANS_COUNT_OFFSET _u(0x00000188)
+#define DMA_CH6_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH6_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH6_TRANS_COUNT_MSB _u(31)
+#define DMA_CH6_TRANS_COUNT_LSB _u(0)
#define DMA_CH6_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH6_CTRL_TRIG
// Description : DMA Channel 6 Control and Status
-#define DMA_CH6_CTRL_TRIG_OFFSET _U(0x0000018c)
-#define DMA_CH6_CTRL_TRIG_BITS _U(0xe1ffffff)
-#define DMA_CH6_CTRL_TRIG_RESET _U(0x00003000)
+#define DMA_CH6_CTRL_TRIG_OFFSET _u(0x0000018c)
+#define DMA_CH6_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH6_CTRL_TRIG_RESET _u(0x00003000)
// -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
// halts when it encounters any bus error, and always raises its
// channel IRQ flag.
-#define DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET _U(0x0)
-#define DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS _U(0x80000000)
-#define DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB _U(31)
-#define DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB _U(31)
+#define DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB _u(31)
#define DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_READ_ERROR
@@ -2420,10 +2420,10 @@
// READ_ADDR shows the approximate address where the bus error was
// encountered (will not to be earlier, or more than 3 transfers
// later)
-#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET _U(0x0)
-#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS _U(0x40000000)
-#define DMA_CH6_CTRL_TRIG_READ_ERROR_MSB _U(30)
-#define DMA_CH6_CTRL_TRIG_READ_ERROR_LSB _U(30)
+#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH6_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH6_CTRL_TRIG_READ_ERROR_LSB _u(30)
#define DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_WRITE_ERROR
@@ -2432,10 +2432,10 @@
// WRITE_ADDR shows the approximate address where the bus error
// was encountered (will not to be earlier, or more than 5
// transfers later)
-#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET _U(0x0)
-#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS _U(0x20000000)
-#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB _U(29)
-#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB _U(29)
+#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_BUSY
@@ -2446,10 +2446,10 @@
//
// To terminate a sequence early (and clear the BUSY flag), see
// CHAN_ABORT.
-#define DMA_CH6_CTRL_TRIG_BUSY_RESET _U(0x0)
-#define DMA_CH6_CTRL_TRIG_BUSY_BITS _U(0x01000000)
-#define DMA_CH6_CTRL_TRIG_BUSY_MSB _U(24)
-#define DMA_CH6_CTRL_TRIG_BUSY_LSB _U(24)
+#define DMA_CH6_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH6_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH6_CTRL_TRIG_BUSY_LSB _u(24)
#define DMA_CH6_CTRL_TRIG_BUSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_SNIFF_EN
@@ -2460,10 +2460,10 @@
//
// This allows checksum to be enabled or disabled on a
// per-control- block basis.
-#define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET _U(0x0)
-#define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS _U(0x00800000)
-#define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB _U(23)
-#define DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB _U(23)
+#define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB _u(23)
#define DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_BSWAP
@@ -2471,10 +2471,10 @@
// For byte data, this has no effect. For halfword data, the two
// bytes of each halfword are swapped. For word data, the four
// bytes of each word are swapped to reverse order.
-#define DMA_CH6_CTRL_TRIG_BSWAP_RESET _U(0x0)
-#define DMA_CH6_CTRL_TRIG_BSWAP_BITS _U(0x00400000)
-#define DMA_CH6_CTRL_TRIG_BSWAP_MSB _U(22)
-#define DMA_CH6_CTRL_TRIG_BSWAP_LSB _U(22)
+#define DMA_CH6_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH6_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH6_CTRL_TRIG_BSWAP_LSB _u(22)
#define DMA_CH6_CTRL_TRIG_BSWAP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_IRQ_QUIET
@@ -2485,10 +2485,10 @@
//
// This reduces the number of interrupts to be serviced by the CPU
// when transferring a DMA chain of many small control blocks.
-#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET _U(0x0)
-#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS _U(0x00200000)
-#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB _U(21)
-#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB _U(21)
+#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_TREQ_SEL
@@ -2502,36 +2502,36 @@
// 0x3d -> Select Timer 2 as TREQ (Optional)
// 0x3e -> Select Timer 3 as TREQ (Optional)
// 0x3f -> Permanent request, for unpaced transfers.
-#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _U(0x00)
-#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _U(0x001f8000)
-#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _U(20)
-#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB _U(15)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB _u(15)
#define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
-#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _U(0x3b)
-#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _U(0x3c)
-#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _U(0x3d)
-#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _U(0x3e)
-#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _U(0x3f)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
// -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_CHAIN_TO
// Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_.
// Reset value is equal to channel number (6).
-#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET _U(0x6)
-#define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS _U(0x00007800)
-#define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB _U(14)
-#define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB _U(11)
+#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET _u(0x6)
+#define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB _u(11)
#define DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_RING_SEL
// Description : Select whether RING_SIZE applies to read or write addresses.
// If 0, read addresses are wrapped on a (1 << RING_SIZE)
// boundary. If 1, write addresses are wrapped.
-#define DMA_CH6_CTRL_TRIG_RING_SEL_RESET _U(0x0)
-#define DMA_CH6_CTRL_TRIG_RING_SEL_BITS _U(0x00000400)
-#define DMA_CH6_CTRL_TRIG_RING_SEL_MSB _U(10)
-#define DMA_CH6_CTRL_TRIG_RING_SEL_LSB _U(10)
+#define DMA_CH6_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH6_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH6_CTRL_TRIG_RING_SEL_LSB _u(10)
#define DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_RING_SIZE
@@ -2544,12 +2544,12 @@
// apply to either read or write addresses, based on value of
// RING_SEL.
// 0x0 -> RING_NONE
-#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET _U(0x0)
-#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS _U(0x000003c0)
-#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB _U(9)
-#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB _U(6)
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB _u(6)
#define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW"
-#define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _U(0x0)
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
// -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_INCR_WRITE
// Description : If 1, the write address increments with each transfer. If 0,
@@ -2557,10 +2557,10 @@
//
// Generally this should be disabled for memory-to-peripheral
// transfers.
-#define DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET _U(0x0)
-#define DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS _U(0x00000020)
-#define DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB _U(5)
-#define DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB _U(5)
+#define DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB _u(5)
#define DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_INCR_READ
@@ -2569,10 +2569,10 @@
//
// Generally this should be disabled for peripheral-to-memory
// transfers.
-#define DMA_CH6_CTRL_TRIG_INCR_READ_RESET _U(0x0)
-#define DMA_CH6_CTRL_TRIG_INCR_READ_BITS _U(0x00000010)
-#define DMA_CH6_CTRL_TRIG_INCR_READ_MSB _U(4)
-#define DMA_CH6_CTRL_TRIG_INCR_READ_LSB _U(4)
+#define DMA_CH6_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH6_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH6_CTRL_TRIG_INCR_READ_LSB _u(4)
#define DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_DATA_SIZE
@@ -2582,14 +2582,14 @@
// 0x0 -> SIZE_BYTE
// 0x1 -> SIZE_HALFWORD
// 0x2 -> SIZE_WORD
-#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET _U(0x0)
-#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS _U(0x0000000c)
-#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB _U(3)
-#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB _U(2)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB _u(2)
#define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
-#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _U(0x0)
-#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _U(0x1)
-#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _U(0x2)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
// -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_HIGH_PRIORITY
// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
@@ -2602,10 +2602,10 @@
// channels. The DMA's bus priority is not changed. If the DMA is
// not saturated then a low priority channel will see no loss of
// throughput.
-#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET _U(0x0)
-#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS _U(0x00000002)
-#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB _U(1)
-#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB _U(1)
+#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_EN
@@ -2615,124 +2615,124 @@
// 0, the channel will ignore triggers, stop issuing transfers,
// and pause the current transfer sequence (i.e. BUSY will remain
// high if already high)
-#define DMA_CH6_CTRL_TRIG_EN_RESET _U(0x0)
-#define DMA_CH6_CTRL_TRIG_EN_BITS _U(0x00000001)
-#define DMA_CH6_CTRL_TRIG_EN_MSB _U(0)
-#define DMA_CH6_CTRL_TRIG_EN_LSB _U(0)
+#define DMA_CH6_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH6_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH6_CTRL_TRIG_EN_LSB _u(0)
#define DMA_CH6_CTRL_TRIG_EN_ACCESS "RW"
// =============================================================================
// Register : DMA_CH6_AL1_CTRL
// Description : Alias for channel 6 CTRL register
-#define DMA_CH6_AL1_CTRL_OFFSET _U(0x00000190)
-#define DMA_CH6_AL1_CTRL_BITS _U(0xffffffff)
+#define DMA_CH6_AL1_CTRL_OFFSET _u(0x00000190)
+#define DMA_CH6_AL1_CTRL_BITS _u(0xffffffff)
#define DMA_CH6_AL1_CTRL_RESET "-"
-#define DMA_CH6_AL1_CTRL_MSB _U(31)
-#define DMA_CH6_AL1_CTRL_LSB _U(0)
+#define DMA_CH6_AL1_CTRL_MSB _u(31)
+#define DMA_CH6_AL1_CTRL_LSB _u(0)
#define DMA_CH6_AL1_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH6_AL1_READ_ADDR
// Description : Alias for channel 6 READ_ADDR register
-#define DMA_CH6_AL1_READ_ADDR_OFFSET _U(0x00000194)
-#define DMA_CH6_AL1_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH6_AL1_READ_ADDR_OFFSET _u(0x00000194)
+#define DMA_CH6_AL1_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH6_AL1_READ_ADDR_RESET "-"
-#define DMA_CH6_AL1_READ_ADDR_MSB _U(31)
-#define DMA_CH6_AL1_READ_ADDR_LSB _U(0)
+#define DMA_CH6_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH6_AL1_READ_ADDR_LSB _u(0)
#define DMA_CH6_AL1_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH6_AL1_WRITE_ADDR
// Description : Alias for channel 6 WRITE_ADDR register
-#define DMA_CH6_AL1_WRITE_ADDR_OFFSET _U(0x00000198)
-#define DMA_CH6_AL1_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH6_AL1_WRITE_ADDR_OFFSET _u(0x00000198)
+#define DMA_CH6_AL1_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH6_AL1_WRITE_ADDR_RESET "-"
-#define DMA_CH6_AL1_WRITE_ADDR_MSB _U(31)
-#define DMA_CH6_AL1_WRITE_ADDR_LSB _U(0)
+#define DMA_CH6_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH6_AL1_WRITE_ADDR_LSB _u(0)
#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH6_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 6 TRANS_COUNT register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET _U(0x0000019c)
-#define DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS _U(0xffffffff)
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000019c)
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
#define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET "-"
-#define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB _U(31)
-#define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB _U(0)
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB _u(0)
#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH6_AL2_CTRL
// Description : Alias for channel 6 CTRL register
-#define DMA_CH6_AL2_CTRL_OFFSET _U(0x000001a0)
-#define DMA_CH6_AL2_CTRL_BITS _U(0xffffffff)
+#define DMA_CH6_AL2_CTRL_OFFSET _u(0x000001a0)
+#define DMA_CH6_AL2_CTRL_BITS _u(0xffffffff)
#define DMA_CH6_AL2_CTRL_RESET "-"
-#define DMA_CH6_AL2_CTRL_MSB _U(31)
-#define DMA_CH6_AL2_CTRL_LSB _U(0)
+#define DMA_CH6_AL2_CTRL_MSB _u(31)
+#define DMA_CH6_AL2_CTRL_LSB _u(0)
#define DMA_CH6_AL2_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH6_AL2_TRANS_COUNT
// Description : Alias for channel 6 TRANS_COUNT register
-#define DMA_CH6_AL2_TRANS_COUNT_OFFSET _U(0x000001a4)
-#define DMA_CH6_AL2_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH6_AL2_TRANS_COUNT_OFFSET _u(0x000001a4)
+#define DMA_CH6_AL2_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH6_AL2_TRANS_COUNT_RESET "-"
-#define DMA_CH6_AL2_TRANS_COUNT_MSB _U(31)
-#define DMA_CH6_AL2_TRANS_COUNT_LSB _U(0)
+#define DMA_CH6_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH6_AL2_TRANS_COUNT_LSB _u(0)
#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH6_AL2_READ_ADDR
// Description : Alias for channel 6 READ_ADDR register
-#define DMA_CH6_AL2_READ_ADDR_OFFSET _U(0x000001a8)
-#define DMA_CH6_AL2_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH6_AL2_READ_ADDR_OFFSET _u(0x000001a8)
+#define DMA_CH6_AL2_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH6_AL2_READ_ADDR_RESET "-"
-#define DMA_CH6_AL2_READ_ADDR_MSB _U(31)
-#define DMA_CH6_AL2_READ_ADDR_LSB _U(0)
+#define DMA_CH6_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH6_AL2_READ_ADDR_LSB _u(0)
#define DMA_CH6_AL2_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH6_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 6 WRITE_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET _U(0x000001ac)
-#define DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ac)
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET "-"
-#define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB _U(31)
-#define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB _U(0)
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB _u(0)
#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH6_AL3_CTRL
// Description : Alias for channel 6 CTRL register
-#define DMA_CH6_AL3_CTRL_OFFSET _U(0x000001b0)
-#define DMA_CH6_AL3_CTRL_BITS _U(0xffffffff)
+#define DMA_CH6_AL3_CTRL_OFFSET _u(0x000001b0)
+#define DMA_CH6_AL3_CTRL_BITS _u(0xffffffff)
#define DMA_CH6_AL3_CTRL_RESET "-"
-#define DMA_CH6_AL3_CTRL_MSB _U(31)
-#define DMA_CH6_AL3_CTRL_LSB _U(0)
+#define DMA_CH6_AL3_CTRL_MSB _u(31)
+#define DMA_CH6_AL3_CTRL_LSB _u(0)
#define DMA_CH6_AL3_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH6_AL3_WRITE_ADDR
// Description : Alias for channel 6 WRITE_ADDR register
-#define DMA_CH6_AL3_WRITE_ADDR_OFFSET _U(0x000001b4)
-#define DMA_CH6_AL3_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH6_AL3_WRITE_ADDR_OFFSET _u(0x000001b4)
+#define DMA_CH6_AL3_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH6_AL3_WRITE_ADDR_RESET "-"
-#define DMA_CH6_AL3_WRITE_ADDR_MSB _U(31)
-#define DMA_CH6_AL3_WRITE_ADDR_LSB _U(0)
+#define DMA_CH6_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH6_AL3_WRITE_ADDR_LSB _u(0)
#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH6_AL3_TRANS_COUNT
// Description : Alias for channel 6 TRANS_COUNT register
-#define DMA_CH6_AL3_TRANS_COUNT_OFFSET _U(0x000001b8)
-#define DMA_CH6_AL3_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH6_AL3_TRANS_COUNT_OFFSET _u(0x000001b8)
+#define DMA_CH6_AL3_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH6_AL3_TRANS_COUNT_RESET "-"
-#define DMA_CH6_AL3_TRANS_COUNT_MSB _U(31)
-#define DMA_CH6_AL3_TRANS_COUNT_LSB _U(0)
+#define DMA_CH6_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH6_AL3_TRANS_COUNT_LSB _u(0)
#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH6_AL3_READ_ADDR_TRIG
// Description : Alias for channel 6 READ_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET _U(0x000001bc)
-#define DMA_CH6_AL3_READ_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001bc)
+#define DMA_CH6_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH6_AL3_READ_ADDR_TRIG_RESET "-"
-#define DMA_CH6_AL3_READ_ADDR_TRIG_MSB _U(31)
-#define DMA_CH6_AL3_READ_ADDR_TRIG_LSB _U(0)
+#define DMA_CH6_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH6_AL3_READ_ADDR_TRIG_LSB _u(0)
#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH7_READ_ADDR
@@ -2740,11 +2740,11 @@
// This register updates automatically each time a read completes.
// The current value is the next address to be read by this
// channel.
-#define DMA_CH7_READ_ADDR_OFFSET _U(0x000001c0)
-#define DMA_CH7_READ_ADDR_BITS _U(0xffffffff)
-#define DMA_CH7_READ_ADDR_RESET _U(0x00000000)
-#define DMA_CH7_READ_ADDR_MSB _U(31)
-#define DMA_CH7_READ_ADDR_LSB _U(0)
+#define DMA_CH7_READ_ADDR_OFFSET _u(0x000001c0)
+#define DMA_CH7_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH7_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH7_READ_ADDR_MSB _u(31)
+#define DMA_CH7_READ_ADDR_LSB _u(0)
#define DMA_CH7_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH7_WRITE_ADDR
@@ -2752,11 +2752,11 @@
// This register updates automatically each time a write
// completes. The current value is the next address to be written
// by this channel.
-#define DMA_CH7_WRITE_ADDR_OFFSET _U(0x000001c4)
-#define DMA_CH7_WRITE_ADDR_BITS _U(0xffffffff)
-#define DMA_CH7_WRITE_ADDR_RESET _U(0x00000000)
-#define DMA_CH7_WRITE_ADDR_MSB _U(31)
-#define DMA_CH7_WRITE_ADDR_LSB _U(0)
+#define DMA_CH7_WRITE_ADDR_OFFSET _u(0x000001c4)
+#define DMA_CH7_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH7_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH7_WRITE_ADDR_MSB _u(31)
+#define DMA_CH7_WRITE_ADDR_LSB _u(0)
#define DMA_CH7_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH7_TRANS_COUNT
@@ -2780,27 +2780,27 @@
// is used as a trigger, the written value is used immediately as
// the length of the new transfer sequence, as well as being
// written to RELOAD.
-#define DMA_CH7_TRANS_COUNT_OFFSET _U(0x000001c8)
-#define DMA_CH7_TRANS_COUNT_BITS _U(0xffffffff)
-#define DMA_CH7_TRANS_COUNT_RESET _U(0x00000000)
-#define DMA_CH7_TRANS_COUNT_MSB _U(31)
-#define DMA_CH7_TRANS_COUNT_LSB _U(0)
+#define DMA_CH7_TRANS_COUNT_OFFSET _u(0x000001c8)
+#define DMA_CH7_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH7_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH7_TRANS_COUNT_MSB _u(31)
+#define DMA_CH7_TRANS_COUNT_LSB _u(0)
#define DMA_CH7_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH7_CTRL_TRIG
// Description : DMA Channel 7 Control and Status
-#define DMA_CH7_CTRL_TRIG_OFFSET _U(0x000001cc)
-#define DMA_CH7_CTRL_TRIG_BITS _U(0xe1ffffff)
-#define DMA_CH7_CTRL_TRIG_RESET _U(0x00003800)
+#define DMA_CH7_CTRL_TRIG_OFFSET _u(0x000001cc)
+#define DMA_CH7_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH7_CTRL_TRIG_RESET _u(0x00003800)
// -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
// halts when it encounters any bus error, and always raises its
// channel IRQ flag.
-#define DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET _U(0x0)
-#define DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS _U(0x80000000)
-#define DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB _U(31)
-#define DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB _U(31)
+#define DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB _u(31)
#define DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_READ_ERROR
@@ -2809,10 +2809,10 @@
// READ_ADDR shows the approximate address where the bus error was
// encountered (will not to be earlier, or more than 3 transfers
// later)
-#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET _U(0x0)
-#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS _U(0x40000000)
-#define DMA_CH7_CTRL_TRIG_READ_ERROR_MSB _U(30)
-#define DMA_CH7_CTRL_TRIG_READ_ERROR_LSB _U(30)
+#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH7_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH7_CTRL_TRIG_READ_ERROR_LSB _u(30)
#define DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_WRITE_ERROR
@@ -2821,10 +2821,10 @@
// WRITE_ADDR shows the approximate address where the bus error
// was encountered (will not to be earlier, or more than 5
// transfers later)
-#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET _U(0x0)
-#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS _U(0x20000000)
-#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB _U(29)
-#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB _U(29)
+#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_BUSY
@@ -2835,10 +2835,10 @@
//
// To terminate a sequence early (and clear the BUSY flag), see
// CHAN_ABORT.
-#define DMA_CH7_CTRL_TRIG_BUSY_RESET _U(0x0)
-#define DMA_CH7_CTRL_TRIG_BUSY_BITS _U(0x01000000)
-#define DMA_CH7_CTRL_TRIG_BUSY_MSB _U(24)
-#define DMA_CH7_CTRL_TRIG_BUSY_LSB _U(24)
+#define DMA_CH7_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH7_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH7_CTRL_TRIG_BUSY_LSB _u(24)
#define DMA_CH7_CTRL_TRIG_BUSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_SNIFF_EN
@@ -2849,10 +2849,10 @@
//
// This allows checksum to be enabled or disabled on a
// per-control- block basis.
-#define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET _U(0x0)
-#define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS _U(0x00800000)
-#define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB _U(23)
-#define DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB _U(23)
+#define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB _u(23)
#define DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_BSWAP
@@ -2860,10 +2860,10 @@
// For byte data, this has no effect. For halfword data, the two
// bytes of each halfword are swapped. For word data, the four
// bytes of each word are swapped to reverse order.
-#define DMA_CH7_CTRL_TRIG_BSWAP_RESET _U(0x0)
-#define DMA_CH7_CTRL_TRIG_BSWAP_BITS _U(0x00400000)
-#define DMA_CH7_CTRL_TRIG_BSWAP_MSB _U(22)
-#define DMA_CH7_CTRL_TRIG_BSWAP_LSB _U(22)
+#define DMA_CH7_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH7_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH7_CTRL_TRIG_BSWAP_LSB _u(22)
#define DMA_CH7_CTRL_TRIG_BSWAP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_IRQ_QUIET
@@ -2874,10 +2874,10 @@
//
// This reduces the number of interrupts to be serviced by the CPU
// when transferring a DMA chain of many small control blocks.
-#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET _U(0x0)
-#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS _U(0x00200000)
-#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB _U(21)
-#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB _U(21)
+#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_TREQ_SEL
@@ -2891,36 +2891,36 @@
// 0x3d -> Select Timer 2 as TREQ (Optional)
// 0x3e -> Select Timer 3 as TREQ (Optional)
// 0x3f -> Permanent request, for unpaced transfers.
-#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _U(0x00)
-#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _U(0x001f8000)
-#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _U(20)
-#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB _U(15)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB _u(15)
#define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
-#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _U(0x3b)
-#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _U(0x3c)
-#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _U(0x3d)
-#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _U(0x3e)
-#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _U(0x3f)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
// -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_CHAIN_TO
// Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_.
// Reset value is equal to channel number (7).
-#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET _U(0x7)
-#define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS _U(0x00007800)
-#define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB _U(14)
-#define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB _U(11)
+#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET _u(0x7)
+#define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB _u(11)
#define DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_RING_SEL
// Description : Select whether RING_SIZE applies to read or write addresses.
// If 0, read addresses are wrapped on a (1 << RING_SIZE)
// boundary. If 1, write addresses are wrapped.
-#define DMA_CH7_CTRL_TRIG_RING_SEL_RESET _U(0x0)
-#define DMA_CH7_CTRL_TRIG_RING_SEL_BITS _U(0x00000400)
-#define DMA_CH7_CTRL_TRIG_RING_SEL_MSB _U(10)
-#define DMA_CH7_CTRL_TRIG_RING_SEL_LSB _U(10)
+#define DMA_CH7_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH7_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH7_CTRL_TRIG_RING_SEL_LSB _u(10)
#define DMA_CH7_CTRL_TRIG_RING_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_RING_SIZE
@@ -2933,12 +2933,12 @@
// apply to either read or write addresses, based on value of
// RING_SEL.
// 0x0 -> RING_NONE
-#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET _U(0x0)
-#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS _U(0x000003c0)
-#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB _U(9)
-#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB _U(6)
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB _u(6)
#define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW"
-#define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _U(0x0)
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
// -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_INCR_WRITE
// Description : If 1, the write address increments with each transfer. If 0,
@@ -2946,10 +2946,10 @@
//
// Generally this should be disabled for memory-to-peripheral
// transfers.
-#define DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET _U(0x0)
-#define DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS _U(0x00000020)
-#define DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB _U(5)
-#define DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB _U(5)
+#define DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB _u(5)
#define DMA_CH7_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_INCR_READ
@@ -2958,10 +2958,10 @@
//
// Generally this should be disabled for peripheral-to-memory
// transfers.
-#define DMA_CH7_CTRL_TRIG_INCR_READ_RESET _U(0x0)
-#define DMA_CH7_CTRL_TRIG_INCR_READ_BITS _U(0x00000010)
-#define DMA_CH7_CTRL_TRIG_INCR_READ_MSB _U(4)
-#define DMA_CH7_CTRL_TRIG_INCR_READ_LSB _U(4)
+#define DMA_CH7_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH7_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH7_CTRL_TRIG_INCR_READ_LSB _u(4)
#define DMA_CH7_CTRL_TRIG_INCR_READ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_DATA_SIZE
@@ -2971,14 +2971,14 @@
// 0x0 -> SIZE_BYTE
// 0x1 -> SIZE_HALFWORD
// 0x2 -> SIZE_WORD
-#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET _U(0x0)
-#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS _U(0x0000000c)
-#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB _U(3)
-#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB _U(2)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB _u(2)
#define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
-#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _U(0x0)
-#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _U(0x1)
-#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _U(0x2)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
// -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_HIGH_PRIORITY
// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
@@ -2991,10 +2991,10 @@
// channels. The DMA's bus priority is not changed. If the DMA is
// not saturated then a low priority channel will see no loss of
// throughput.
-#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET _U(0x0)
-#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS _U(0x00000002)
-#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB _U(1)
-#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB _U(1)
+#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_EN
@@ -3004,124 +3004,124 @@
// 0, the channel will ignore triggers, stop issuing transfers,
// and pause the current transfer sequence (i.e. BUSY will remain
// high if already high)
-#define DMA_CH7_CTRL_TRIG_EN_RESET _U(0x0)
-#define DMA_CH7_CTRL_TRIG_EN_BITS _U(0x00000001)
-#define DMA_CH7_CTRL_TRIG_EN_MSB _U(0)
-#define DMA_CH7_CTRL_TRIG_EN_LSB _U(0)
+#define DMA_CH7_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH7_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH7_CTRL_TRIG_EN_LSB _u(0)
#define DMA_CH7_CTRL_TRIG_EN_ACCESS "RW"
// =============================================================================
// Register : DMA_CH7_AL1_CTRL
// Description : Alias for channel 7 CTRL register
-#define DMA_CH7_AL1_CTRL_OFFSET _U(0x000001d0)
-#define DMA_CH7_AL1_CTRL_BITS _U(0xffffffff)
+#define DMA_CH7_AL1_CTRL_OFFSET _u(0x000001d0)
+#define DMA_CH7_AL1_CTRL_BITS _u(0xffffffff)
#define DMA_CH7_AL1_CTRL_RESET "-"
-#define DMA_CH7_AL1_CTRL_MSB _U(31)
-#define DMA_CH7_AL1_CTRL_LSB _U(0)
+#define DMA_CH7_AL1_CTRL_MSB _u(31)
+#define DMA_CH7_AL1_CTRL_LSB _u(0)
#define DMA_CH7_AL1_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH7_AL1_READ_ADDR
// Description : Alias for channel 7 READ_ADDR register
-#define DMA_CH7_AL1_READ_ADDR_OFFSET _U(0x000001d4)
-#define DMA_CH7_AL1_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH7_AL1_READ_ADDR_OFFSET _u(0x000001d4)
+#define DMA_CH7_AL1_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH7_AL1_READ_ADDR_RESET "-"
-#define DMA_CH7_AL1_READ_ADDR_MSB _U(31)
-#define DMA_CH7_AL1_READ_ADDR_LSB _U(0)
+#define DMA_CH7_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH7_AL1_READ_ADDR_LSB _u(0)
#define DMA_CH7_AL1_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH7_AL1_WRITE_ADDR
// Description : Alias for channel 7 WRITE_ADDR register
-#define DMA_CH7_AL1_WRITE_ADDR_OFFSET _U(0x000001d8)
-#define DMA_CH7_AL1_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH7_AL1_WRITE_ADDR_OFFSET _u(0x000001d8)
+#define DMA_CH7_AL1_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH7_AL1_WRITE_ADDR_RESET "-"
-#define DMA_CH7_AL1_WRITE_ADDR_MSB _U(31)
-#define DMA_CH7_AL1_WRITE_ADDR_LSB _U(0)
+#define DMA_CH7_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH7_AL1_WRITE_ADDR_LSB _u(0)
#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH7_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 7 TRANS_COUNT register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET _U(0x000001dc)
-#define DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS _U(0xffffffff)
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000001dc)
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
#define DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET "-"
-#define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB _U(31)
-#define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB _U(0)
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB _u(0)
#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH7_AL2_CTRL
// Description : Alias for channel 7 CTRL register
-#define DMA_CH7_AL2_CTRL_OFFSET _U(0x000001e0)
-#define DMA_CH7_AL2_CTRL_BITS _U(0xffffffff)
+#define DMA_CH7_AL2_CTRL_OFFSET _u(0x000001e0)
+#define DMA_CH7_AL2_CTRL_BITS _u(0xffffffff)
#define DMA_CH7_AL2_CTRL_RESET "-"
-#define DMA_CH7_AL2_CTRL_MSB _U(31)
-#define DMA_CH7_AL2_CTRL_LSB _U(0)
+#define DMA_CH7_AL2_CTRL_MSB _u(31)
+#define DMA_CH7_AL2_CTRL_LSB _u(0)
#define DMA_CH7_AL2_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH7_AL2_TRANS_COUNT
// Description : Alias for channel 7 TRANS_COUNT register
-#define DMA_CH7_AL2_TRANS_COUNT_OFFSET _U(0x000001e4)
-#define DMA_CH7_AL2_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH7_AL2_TRANS_COUNT_OFFSET _u(0x000001e4)
+#define DMA_CH7_AL2_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH7_AL2_TRANS_COUNT_RESET "-"
-#define DMA_CH7_AL2_TRANS_COUNT_MSB _U(31)
-#define DMA_CH7_AL2_TRANS_COUNT_LSB _U(0)
+#define DMA_CH7_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH7_AL2_TRANS_COUNT_LSB _u(0)
#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH7_AL2_READ_ADDR
// Description : Alias for channel 7 READ_ADDR register
-#define DMA_CH7_AL2_READ_ADDR_OFFSET _U(0x000001e8)
-#define DMA_CH7_AL2_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH7_AL2_READ_ADDR_OFFSET _u(0x000001e8)
+#define DMA_CH7_AL2_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH7_AL2_READ_ADDR_RESET "-"
-#define DMA_CH7_AL2_READ_ADDR_MSB _U(31)
-#define DMA_CH7_AL2_READ_ADDR_LSB _U(0)
+#define DMA_CH7_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH7_AL2_READ_ADDR_LSB _u(0)
#define DMA_CH7_AL2_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH7_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 7 WRITE_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET _U(0x000001ec)
-#define DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ec)
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET "-"
-#define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB _U(31)
-#define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB _U(0)
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB _u(0)
#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH7_AL3_CTRL
// Description : Alias for channel 7 CTRL register
-#define DMA_CH7_AL3_CTRL_OFFSET _U(0x000001f0)
-#define DMA_CH7_AL3_CTRL_BITS _U(0xffffffff)
+#define DMA_CH7_AL3_CTRL_OFFSET _u(0x000001f0)
+#define DMA_CH7_AL3_CTRL_BITS _u(0xffffffff)
#define DMA_CH7_AL3_CTRL_RESET "-"
-#define DMA_CH7_AL3_CTRL_MSB _U(31)
-#define DMA_CH7_AL3_CTRL_LSB _U(0)
+#define DMA_CH7_AL3_CTRL_MSB _u(31)
+#define DMA_CH7_AL3_CTRL_LSB _u(0)
#define DMA_CH7_AL3_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH7_AL3_WRITE_ADDR
// Description : Alias for channel 7 WRITE_ADDR register
-#define DMA_CH7_AL3_WRITE_ADDR_OFFSET _U(0x000001f4)
-#define DMA_CH7_AL3_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH7_AL3_WRITE_ADDR_OFFSET _u(0x000001f4)
+#define DMA_CH7_AL3_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH7_AL3_WRITE_ADDR_RESET "-"
-#define DMA_CH7_AL3_WRITE_ADDR_MSB _U(31)
-#define DMA_CH7_AL3_WRITE_ADDR_LSB _U(0)
+#define DMA_CH7_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH7_AL3_WRITE_ADDR_LSB _u(0)
#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH7_AL3_TRANS_COUNT
// Description : Alias for channel 7 TRANS_COUNT register
-#define DMA_CH7_AL3_TRANS_COUNT_OFFSET _U(0x000001f8)
-#define DMA_CH7_AL3_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH7_AL3_TRANS_COUNT_OFFSET _u(0x000001f8)
+#define DMA_CH7_AL3_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH7_AL3_TRANS_COUNT_RESET "-"
-#define DMA_CH7_AL3_TRANS_COUNT_MSB _U(31)
-#define DMA_CH7_AL3_TRANS_COUNT_LSB _U(0)
+#define DMA_CH7_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH7_AL3_TRANS_COUNT_LSB _u(0)
#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH7_AL3_READ_ADDR_TRIG
// Description : Alias for channel 7 READ_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET _U(0x000001fc)
-#define DMA_CH7_AL3_READ_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001fc)
+#define DMA_CH7_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH7_AL3_READ_ADDR_TRIG_RESET "-"
-#define DMA_CH7_AL3_READ_ADDR_TRIG_MSB _U(31)
-#define DMA_CH7_AL3_READ_ADDR_TRIG_LSB _U(0)
+#define DMA_CH7_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH7_AL3_READ_ADDR_TRIG_LSB _u(0)
#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH8_READ_ADDR
@@ -3129,11 +3129,11 @@
// This register updates automatically each time a read completes.
// The current value is the next address to be read by this
// channel.
-#define DMA_CH8_READ_ADDR_OFFSET _U(0x00000200)
-#define DMA_CH8_READ_ADDR_BITS _U(0xffffffff)
-#define DMA_CH8_READ_ADDR_RESET _U(0x00000000)
-#define DMA_CH8_READ_ADDR_MSB _U(31)
-#define DMA_CH8_READ_ADDR_LSB _U(0)
+#define DMA_CH8_READ_ADDR_OFFSET _u(0x00000200)
+#define DMA_CH8_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH8_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH8_READ_ADDR_MSB _u(31)
+#define DMA_CH8_READ_ADDR_LSB _u(0)
#define DMA_CH8_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH8_WRITE_ADDR
@@ -3141,11 +3141,11 @@
// This register updates automatically each time a write
// completes. The current value is the next address to be written
// by this channel.
-#define DMA_CH8_WRITE_ADDR_OFFSET _U(0x00000204)
-#define DMA_CH8_WRITE_ADDR_BITS _U(0xffffffff)
-#define DMA_CH8_WRITE_ADDR_RESET _U(0x00000000)
-#define DMA_CH8_WRITE_ADDR_MSB _U(31)
-#define DMA_CH8_WRITE_ADDR_LSB _U(0)
+#define DMA_CH8_WRITE_ADDR_OFFSET _u(0x00000204)
+#define DMA_CH8_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH8_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH8_WRITE_ADDR_MSB _u(31)
+#define DMA_CH8_WRITE_ADDR_LSB _u(0)
#define DMA_CH8_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH8_TRANS_COUNT
@@ -3169,27 +3169,27 @@
// is used as a trigger, the written value is used immediately as
// the length of the new transfer sequence, as well as being
// written to RELOAD.
-#define DMA_CH8_TRANS_COUNT_OFFSET _U(0x00000208)
-#define DMA_CH8_TRANS_COUNT_BITS _U(0xffffffff)
-#define DMA_CH8_TRANS_COUNT_RESET _U(0x00000000)
-#define DMA_CH8_TRANS_COUNT_MSB _U(31)
-#define DMA_CH8_TRANS_COUNT_LSB _U(0)
+#define DMA_CH8_TRANS_COUNT_OFFSET _u(0x00000208)
+#define DMA_CH8_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH8_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH8_TRANS_COUNT_MSB _u(31)
+#define DMA_CH8_TRANS_COUNT_LSB _u(0)
#define DMA_CH8_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH8_CTRL_TRIG
// Description : DMA Channel 8 Control and Status
-#define DMA_CH8_CTRL_TRIG_OFFSET _U(0x0000020c)
-#define DMA_CH8_CTRL_TRIG_BITS _U(0xe1ffffff)
-#define DMA_CH8_CTRL_TRIG_RESET _U(0x00004000)
+#define DMA_CH8_CTRL_TRIG_OFFSET _u(0x0000020c)
+#define DMA_CH8_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH8_CTRL_TRIG_RESET _u(0x00004000)
// -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
// halts when it encounters any bus error, and always raises its
// channel IRQ flag.
-#define DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET _U(0x0)
-#define DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS _U(0x80000000)
-#define DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB _U(31)
-#define DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB _U(31)
+#define DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB _u(31)
#define DMA_CH8_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_READ_ERROR
@@ -3198,10 +3198,10 @@
// READ_ADDR shows the approximate address where the bus error was
// encountered (will not to be earlier, or more than 3 transfers
// later)
-#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET _U(0x0)
-#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS _U(0x40000000)
-#define DMA_CH8_CTRL_TRIG_READ_ERROR_MSB _U(30)
-#define DMA_CH8_CTRL_TRIG_READ_ERROR_LSB _U(30)
+#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH8_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH8_CTRL_TRIG_READ_ERROR_LSB _u(30)
#define DMA_CH8_CTRL_TRIG_READ_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_WRITE_ERROR
@@ -3210,10 +3210,10 @@
// WRITE_ADDR shows the approximate address where the bus error
// was encountered (will not to be earlier, or more than 5
// transfers later)
-#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET _U(0x0)
-#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS _U(0x20000000)
-#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB _U(29)
-#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB _U(29)
+#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_BUSY
@@ -3224,10 +3224,10 @@
//
// To terminate a sequence early (and clear the BUSY flag), see
// CHAN_ABORT.
-#define DMA_CH8_CTRL_TRIG_BUSY_RESET _U(0x0)
-#define DMA_CH8_CTRL_TRIG_BUSY_BITS _U(0x01000000)
-#define DMA_CH8_CTRL_TRIG_BUSY_MSB _U(24)
-#define DMA_CH8_CTRL_TRIG_BUSY_LSB _U(24)
+#define DMA_CH8_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH8_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH8_CTRL_TRIG_BUSY_LSB _u(24)
#define DMA_CH8_CTRL_TRIG_BUSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_SNIFF_EN
@@ -3238,10 +3238,10 @@
//
// This allows checksum to be enabled or disabled on a
// per-control- block basis.
-#define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET _U(0x0)
-#define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS _U(0x00800000)
-#define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB _U(23)
-#define DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB _U(23)
+#define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB _u(23)
#define DMA_CH8_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_BSWAP
@@ -3249,10 +3249,10 @@
// For byte data, this has no effect. For halfword data, the two
// bytes of each halfword are swapped. For word data, the four
// bytes of each word are swapped to reverse order.
-#define DMA_CH8_CTRL_TRIG_BSWAP_RESET _U(0x0)
-#define DMA_CH8_CTRL_TRIG_BSWAP_BITS _U(0x00400000)
-#define DMA_CH8_CTRL_TRIG_BSWAP_MSB _U(22)
-#define DMA_CH8_CTRL_TRIG_BSWAP_LSB _U(22)
+#define DMA_CH8_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH8_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH8_CTRL_TRIG_BSWAP_LSB _u(22)
#define DMA_CH8_CTRL_TRIG_BSWAP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_IRQ_QUIET
@@ -3263,10 +3263,10 @@
//
// This reduces the number of interrupts to be serviced by the CPU
// when transferring a DMA chain of many small control blocks.
-#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET _U(0x0)
-#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS _U(0x00200000)
-#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB _U(21)
-#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB _U(21)
+#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_TREQ_SEL
@@ -3280,36 +3280,36 @@
// 0x3d -> Select Timer 2 as TREQ (Optional)
// 0x3e -> Select Timer 3 as TREQ (Optional)
// 0x3f -> Permanent request, for unpaced transfers.
-#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _U(0x00)
-#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _U(0x001f8000)
-#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _U(20)
-#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB _U(15)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB _u(15)
#define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
-#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _U(0x3b)
-#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _U(0x3c)
-#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _U(0x3d)
-#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _U(0x3e)
-#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _U(0x3f)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
// -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_CHAIN_TO
// Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_.
// Reset value is equal to channel number (8).
-#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET _U(0x8)
-#define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS _U(0x00007800)
-#define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB _U(14)
-#define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB _U(11)
+#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET _u(0x8)
+#define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB _u(11)
#define DMA_CH8_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_RING_SEL
// Description : Select whether RING_SIZE applies to read or write addresses.
// If 0, read addresses are wrapped on a (1 << RING_SIZE)
// boundary. If 1, write addresses are wrapped.
-#define DMA_CH8_CTRL_TRIG_RING_SEL_RESET _U(0x0)
-#define DMA_CH8_CTRL_TRIG_RING_SEL_BITS _U(0x00000400)
-#define DMA_CH8_CTRL_TRIG_RING_SEL_MSB _U(10)
-#define DMA_CH8_CTRL_TRIG_RING_SEL_LSB _U(10)
+#define DMA_CH8_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH8_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH8_CTRL_TRIG_RING_SEL_LSB _u(10)
#define DMA_CH8_CTRL_TRIG_RING_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_RING_SIZE
@@ -3322,12 +3322,12 @@
// apply to either read or write addresses, based on value of
// RING_SEL.
// 0x0 -> RING_NONE
-#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET _U(0x0)
-#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS _U(0x000003c0)
-#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB _U(9)
-#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB _U(6)
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB _u(6)
#define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW"
-#define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _U(0x0)
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
// -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_INCR_WRITE
// Description : If 1, the write address increments with each transfer. If 0,
@@ -3335,10 +3335,10 @@
//
// Generally this should be disabled for memory-to-peripheral
// transfers.
-#define DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET _U(0x0)
-#define DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS _U(0x00000020)
-#define DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB _U(5)
-#define DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB _U(5)
+#define DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB _u(5)
#define DMA_CH8_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_INCR_READ
@@ -3347,10 +3347,10 @@
//
// Generally this should be disabled for peripheral-to-memory
// transfers.
-#define DMA_CH8_CTRL_TRIG_INCR_READ_RESET _U(0x0)
-#define DMA_CH8_CTRL_TRIG_INCR_READ_BITS _U(0x00000010)
-#define DMA_CH8_CTRL_TRIG_INCR_READ_MSB _U(4)
-#define DMA_CH8_CTRL_TRIG_INCR_READ_LSB _U(4)
+#define DMA_CH8_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH8_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH8_CTRL_TRIG_INCR_READ_LSB _u(4)
#define DMA_CH8_CTRL_TRIG_INCR_READ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_DATA_SIZE
@@ -3360,14 +3360,14 @@
// 0x0 -> SIZE_BYTE
// 0x1 -> SIZE_HALFWORD
// 0x2 -> SIZE_WORD
-#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET _U(0x0)
-#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS _U(0x0000000c)
-#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB _U(3)
-#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB _U(2)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB _u(2)
#define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
-#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _U(0x0)
-#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _U(0x1)
-#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _U(0x2)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
// -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_HIGH_PRIORITY
// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
@@ -3380,10 +3380,10 @@
// channels. The DMA's bus priority is not changed. If the DMA is
// not saturated then a low priority channel will see no loss of
// throughput.
-#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET _U(0x0)
-#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS _U(0x00000002)
-#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB _U(1)
-#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB _U(1)
+#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_EN
@@ -3393,124 +3393,124 @@
// 0, the channel will ignore triggers, stop issuing transfers,
// and pause the current transfer sequence (i.e. BUSY will remain
// high if already high)
-#define DMA_CH8_CTRL_TRIG_EN_RESET _U(0x0)
-#define DMA_CH8_CTRL_TRIG_EN_BITS _U(0x00000001)
-#define DMA_CH8_CTRL_TRIG_EN_MSB _U(0)
-#define DMA_CH8_CTRL_TRIG_EN_LSB _U(0)
+#define DMA_CH8_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH8_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH8_CTRL_TRIG_EN_LSB _u(0)
#define DMA_CH8_CTRL_TRIG_EN_ACCESS "RW"
// =============================================================================
// Register : DMA_CH8_AL1_CTRL
// Description : Alias for channel 8 CTRL register
-#define DMA_CH8_AL1_CTRL_OFFSET _U(0x00000210)
-#define DMA_CH8_AL1_CTRL_BITS _U(0xffffffff)
+#define DMA_CH8_AL1_CTRL_OFFSET _u(0x00000210)
+#define DMA_CH8_AL1_CTRL_BITS _u(0xffffffff)
#define DMA_CH8_AL1_CTRL_RESET "-"
-#define DMA_CH8_AL1_CTRL_MSB _U(31)
-#define DMA_CH8_AL1_CTRL_LSB _U(0)
+#define DMA_CH8_AL1_CTRL_MSB _u(31)
+#define DMA_CH8_AL1_CTRL_LSB _u(0)
#define DMA_CH8_AL1_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH8_AL1_READ_ADDR
// Description : Alias for channel 8 READ_ADDR register
-#define DMA_CH8_AL1_READ_ADDR_OFFSET _U(0x00000214)
-#define DMA_CH8_AL1_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH8_AL1_READ_ADDR_OFFSET _u(0x00000214)
+#define DMA_CH8_AL1_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH8_AL1_READ_ADDR_RESET "-"
-#define DMA_CH8_AL1_READ_ADDR_MSB _U(31)
-#define DMA_CH8_AL1_READ_ADDR_LSB _U(0)
+#define DMA_CH8_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH8_AL1_READ_ADDR_LSB _u(0)
#define DMA_CH8_AL1_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH8_AL1_WRITE_ADDR
// Description : Alias for channel 8 WRITE_ADDR register
-#define DMA_CH8_AL1_WRITE_ADDR_OFFSET _U(0x00000218)
-#define DMA_CH8_AL1_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH8_AL1_WRITE_ADDR_OFFSET _u(0x00000218)
+#define DMA_CH8_AL1_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH8_AL1_WRITE_ADDR_RESET "-"
-#define DMA_CH8_AL1_WRITE_ADDR_MSB _U(31)
-#define DMA_CH8_AL1_WRITE_ADDR_LSB _U(0)
+#define DMA_CH8_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH8_AL1_WRITE_ADDR_LSB _u(0)
#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH8_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 8 TRANS_COUNT register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET _U(0x0000021c)
-#define DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS _U(0xffffffff)
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000021c)
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
#define DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET "-"
-#define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB _U(31)
-#define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB _U(0)
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB _u(0)
#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH8_AL2_CTRL
// Description : Alias for channel 8 CTRL register
-#define DMA_CH8_AL2_CTRL_OFFSET _U(0x00000220)
-#define DMA_CH8_AL2_CTRL_BITS _U(0xffffffff)
+#define DMA_CH8_AL2_CTRL_OFFSET _u(0x00000220)
+#define DMA_CH8_AL2_CTRL_BITS _u(0xffffffff)
#define DMA_CH8_AL2_CTRL_RESET "-"
-#define DMA_CH8_AL2_CTRL_MSB _U(31)
-#define DMA_CH8_AL2_CTRL_LSB _U(0)
+#define DMA_CH8_AL2_CTRL_MSB _u(31)
+#define DMA_CH8_AL2_CTRL_LSB _u(0)
#define DMA_CH8_AL2_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH8_AL2_TRANS_COUNT
// Description : Alias for channel 8 TRANS_COUNT register
-#define DMA_CH8_AL2_TRANS_COUNT_OFFSET _U(0x00000224)
-#define DMA_CH8_AL2_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH8_AL2_TRANS_COUNT_OFFSET _u(0x00000224)
+#define DMA_CH8_AL2_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH8_AL2_TRANS_COUNT_RESET "-"
-#define DMA_CH8_AL2_TRANS_COUNT_MSB _U(31)
-#define DMA_CH8_AL2_TRANS_COUNT_LSB _U(0)
+#define DMA_CH8_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH8_AL2_TRANS_COUNT_LSB _u(0)
#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH8_AL2_READ_ADDR
// Description : Alias for channel 8 READ_ADDR register
-#define DMA_CH8_AL2_READ_ADDR_OFFSET _U(0x00000228)
-#define DMA_CH8_AL2_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH8_AL2_READ_ADDR_OFFSET _u(0x00000228)
+#define DMA_CH8_AL2_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH8_AL2_READ_ADDR_RESET "-"
-#define DMA_CH8_AL2_READ_ADDR_MSB _U(31)
-#define DMA_CH8_AL2_READ_ADDR_LSB _U(0)
+#define DMA_CH8_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH8_AL2_READ_ADDR_LSB _u(0)
#define DMA_CH8_AL2_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH8_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 8 WRITE_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET _U(0x0000022c)
-#define DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000022c)
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET "-"
-#define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB _U(31)
-#define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB _U(0)
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB _u(0)
#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH8_AL3_CTRL
// Description : Alias for channel 8 CTRL register
-#define DMA_CH8_AL3_CTRL_OFFSET _U(0x00000230)
-#define DMA_CH8_AL3_CTRL_BITS _U(0xffffffff)
+#define DMA_CH8_AL3_CTRL_OFFSET _u(0x00000230)
+#define DMA_CH8_AL3_CTRL_BITS _u(0xffffffff)
#define DMA_CH8_AL3_CTRL_RESET "-"
-#define DMA_CH8_AL3_CTRL_MSB _U(31)
-#define DMA_CH8_AL3_CTRL_LSB _U(0)
+#define DMA_CH8_AL3_CTRL_MSB _u(31)
+#define DMA_CH8_AL3_CTRL_LSB _u(0)
#define DMA_CH8_AL3_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH8_AL3_WRITE_ADDR
// Description : Alias for channel 8 WRITE_ADDR register
-#define DMA_CH8_AL3_WRITE_ADDR_OFFSET _U(0x00000234)
-#define DMA_CH8_AL3_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH8_AL3_WRITE_ADDR_OFFSET _u(0x00000234)
+#define DMA_CH8_AL3_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH8_AL3_WRITE_ADDR_RESET "-"
-#define DMA_CH8_AL3_WRITE_ADDR_MSB _U(31)
-#define DMA_CH8_AL3_WRITE_ADDR_LSB _U(0)
+#define DMA_CH8_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH8_AL3_WRITE_ADDR_LSB _u(0)
#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH8_AL3_TRANS_COUNT
// Description : Alias for channel 8 TRANS_COUNT register
-#define DMA_CH8_AL3_TRANS_COUNT_OFFSET _U(0x00000238)
-#define DMA_CH8_AL3_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH8_AL3_TRANS_COUNT_OFFSET _u(0x00000238)
+#define DMA_CH8_AL3_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH8_AL3_TRANS_COUNT_RESET "-"
-#define DMA_CH8_AL3_TRANS_COUNT_MSB _U(31)
-#define DMA_CH8_AL3_TRANS_COUNT_LSB _U(0)
+#define DMA_CH8_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH8_AL3_TRANS_COUNT_LSB _u(0)
#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH8_AL3_READ_ADDR_TRIG
// Description : Alias for channel 8 READ_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET _U(0x0000023c)
-#define DMA_CH8_AL3_READ_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000023c)
+#define DMA_CH8_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH8_AL3_READ_ADDR_TRIG_RESET "-"
-#define DMA_CH8_AL3_READ_ADDR_TRIG_MSB _U(31)
-#define DMA_CH8_AL3_READ_ADDR_TRIG_LSB _U(0)
+#define DMA_CH8_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH8_AL3_READ_ADDR_TRIG_LSB _u(0)
#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH9_READ_ADDR
@@ -3518,11 +3518,11 @@
// This register updates automatically each time a read completes.
// The current value is the next address to be read by this
// channel.
-#define DMA_CH9_READ_ADDR_OFFSET _U(0x00000240)
-#define DMA_CH9_READ_ADDR_BITS _U(0xffffffff)
-#define DMA_CH9_READ_ADDR_RESET _U(0x00000000)
-#define DMA_CH9_READ_ADDR_MSB _U(31)
-#define DMA_CH9_READ_ADDR_LSB _U(0)
+#define DMA_CH9_READ_ADDR_OFFSET _u(0x00000240)
+#define DMA_CH9_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH9_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH9_READ_ADDR_MSB _u(31)
+#define DMA_CH9_READ_ADDR_LSB _u(0)
#define DMA_CH9_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH9_WRITE_ADDR
@@ -3530,11 +3530,11 @@
// This register updates automatically each time a write
// completes. The current value is the next address to be written
// by this channel.
-#define DMA_CH9_WRITE_ADDR_OFFSET _U(0x00000244)
-#define DMA_CH9_WRITE_ADDR_BITS _U(0xffffffff)
-#define DMA_CH9_WRITE_ADDR_RESET _U(0x00000000)
-#define DMA_CH9_WRITE_ADDR_MSB _U(31)
-#define DMA_CH9_WRITE_ADDR_LSB _U(0)
+#define DMA_CH9_WRITE_ADDR_OFFSET _u(0x00000244)
+#define DMA_CH9_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH9_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH9_WRITE_ADDR_MSB _u(31)
+#define DMA_CH9_WRITE_ADDR_LSB _u(0)
#define DMA_CH9_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH9_TRANS_COUNT
@@ -3558,27 +3558,27 @@
// is used as a trigger, the written value is used immediately as
// the length of the new transfer sequence, as well as being
// written to RELOAD.
-#define DMA_CH9_TRANS_COUNT_OFFSET _U(0x00000248)
-#define DMA_CH9_TRANS_COUNT_BITS _U(0xffffffff)
-#define DMA_CH9_TRANS_COUNT_RESET _U(0x00000000)
-#define DMA_CH9_TRANS_COUNT_MSB _U(31)
-#define DMA_CH9_TRANS_COUNT_LSB _U(0)
+#define DMA_CH9_TRANS_COUNT_OFFSET _u(0x00000248)
+#define DMA_CH9_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH9_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH9_TRANS_COUNT_MSB _u(31)
+#define DMA_CH9_TRANS_COUNT_LSB _u(0)
#define DMA_CH9_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH9_CTRL_TRIG
// Description : DMA Channel 9 Control and Status
-#define DMA_CH9_CTRL_TRIG_OFFSET _U(0x0000024c)
-#define DMA_CH9_CTRL_TRIG_BITS _U(0xe1ffffff)
-#define DMA_CH9_CTRL_TRIG_RESET _U(0x00004800)
+#define DMA_CH9_CTRL_TRIG_OFFSET _u(0x0000024c)
+#define DMA_CH9_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH9_CTRL_TRIG_RESET _u(0x00004800)
// -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
// halts when it encounters any bus error, and always raises its
// channel IRQ flag.
-#define DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET _U(0x0)
-#define DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS _U(0x80000000)
-#define DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB _U(31)
-#define DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB _U(31)
+#define DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB _u(31)
#define DMA_CH9_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_READ_ERROR
@@ -3587,10 +3587,10 @@
// READ_ADDR shows the approximate address where the bus error was
// encountered (will not to be earlier, or more than 3 transfers
// later)
-#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET _U(0x0)
-#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS _U(0x40000000)
-#define DMA_CH9_CTRL_TRIG_READ_ERROR_MSB _U(30)
-#define DMA_CH9_CTRL_TRIG_READ_ERROR_LSB _U(30)
+#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH9_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH9_CTRL_TRIG_READ_ERROR_LSB _u(30)
#define DMA_CH9_CTRL_TRIG_READ_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_WRITE_ERROR
@@ -3599,10 +3599,10 @@
// WRITE_ADDR shows the approximate address where the bus error
// was encountered (will not to be earlier, or more than 5
// transfers later)
-#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET _U(0x0)
-#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS _U(0x20000000)
-#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB _U(29)
-#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB _U(29)
+#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_BUSY
@@ -3613,10 +3613,10 @@
//
// To terminate a sequence early (and clear the BUSY flag), see
// CHAN_ABORT.
-#define DMA_CH9_CTRL_TRIG_BUSY_RESET _U(0x0)
-#define DMA_CH9_CTRL_TRIG_BUSY_BITS _U(0x01000000)
-#define DMA_CH9_CTRL_TRIG_BUSY_MSB _U(24)
-#define DMA_CH9_CTRL_TRIG_BUSY_LSB _U(24)
+#define DMA_CH9_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH9_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH9_CTRL_TRIG_BUSY_LSB _u(24)
#define DMA_CH9_CTRL_TRIG_BUSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_SNIFF_EN
@@ -3627,10 +3627,10 @@
//
// This allows checksum to be enabled or disabled on a
// per-control- block basis.
-#define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET _U(0x0)
-#define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS _U(0x00800000)
-#define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB _U(23)
-#define DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB _U(23)
+#define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB _u(23)
#define DMA_CH9_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_BSWAP
@@ -3638,10 +3638,10 @@
// For byte data, this has no effect. For halfword data, the two
// bytes of each halfword are swapped. For word data, the four
// bytes of each word are swapped to reverse order.
-#define DMA_CH9_CTRL_TRIG_BSWAP_RESET _U(0x0)
-#define DMA_CH9_CTRL_TRIG_BSWAP_BITS _U(0x00400000)
-#define DMA_CH9_CTRL_TRIG_BSWAP_MSB _U(22)
-#define DMA_CH9_CTRL_TRIG_BSWAP_LSB _U(22)
+#define DMA_CH9_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH9_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH9_CTRL_TRIG_BSWAP_LSB _u(22)
#define DMA_CH9_CTRL_TRIG_BSWAP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_IRQ_QUIET
@@ -3652,10 +3652,10 @@
//
// This reduces the number of interrupts to be serviced by the CPU
// when transferring a DMA chain of many small control blocks.
-#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET _U(0x0)
-#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS _U(0x00200000)
-#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB _U(21)
-#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB _U(21)
+#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_TREQ_SEL
@@ -3669,36 +3669,36 @@
// 0x3d -> Select Timer 2 as TREQ (Optional)
// 0x3e -> Select Timer 3 as TREQ (Optional)
// 0x3f -> Permanent request, for unpaced transfers.
-#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _U(0x00)
-#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _U(0x001f8000)
-#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _U(20)
-#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB _U(15)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB _u(15)
#define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
-#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _U(0x3b)
-#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _U(0x3c)
-#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _U(0x3d)
-#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _U(0x3e)
-#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _U(0x3f)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
// -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_CHAIN_TO
// Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_.
// Reset value is equal to channel number (9).
-#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET _U(0x9)
-#define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS _U(0x00007800)
-#define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB _U(14)
-#define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB _U(11)
+#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET _u(0x9)
+#define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB _u(11)
#define DMA_CH9_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_RING_SEL
// Description : Select whether RING_SIZE applies to read or write addresses.
// If 0, read addresses are wrapped on a (1 << RING_SIZE)
// boundary. If 1, write addresses are wrapped.
-#define DMA_CH9_CTRL_TRIG_RING_SEL_RESET _U(0x0)
-#define DMA_CH9_CTRL_TRIG_RING_SEL_BITS _U(0x00000400)
-#define DMA_CH9_CTRL_TRIG_RING_SEL_MSB _U(10)
-#define DMA_CH9_CTRL_TRIG_RING_SEL_LSB _U(10)
+#define DMA_CH9_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH9_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH9_CTRL_TRIG_RING_SEL_LSB _u(10)
#define DMA_CH9_CTRL_TRIG_RING_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_RING_SIZE
@@ -3711,12 +3711,12 @@
// apply to either read or write addresses, based on value of
// RING_SEL.
// 0x0 -> RING_NONE
-#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET _U(0x0)
-#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS _U(0x000003c0)
-#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB _U(9)
-#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB _U(6)
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB _u(6)
#define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW"
-#define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _U(0x0)
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
// -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_INCR_WRITE
// Description : If 1, the write address increments with each transfer. If 0,
@@ -3724,10 +3724,10 @@
//
// Generally this should be disabled for memory-to-peripheral
// transfers.
-#define DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET _U(0x0)
-#define DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS _U(0x00000020)
-#define DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB _U(5)
-#define DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB _U(5)
+#define DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB _u(5)
#define DMA_CH9_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_INCR_READ
@@ -3736,10 +3736,10 @@
//
// Generally this should be disabled for peripheral-to-memory
// transfers.
-#define DMA_CH9_CTRL_TRIG_INCR_READ_RESET _U(0x0)
-#define DMA_CH9_CTRL_TRIG_INCR_READ_BITS _U(0x00000010)
-#define DMA_CH9_CTRL_TRIG_INCR_READ_MSB _U(4)
-#define DMA_CH9_CTRL_TRIG_INCR_READ_LSB _U(4)
+#define DMA_CH9_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH9_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH9_CTRL_TRIG_INCR_READ_LSB _u(4)
#define DMA_CH9_CTRL_TRIG_INCR_READ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_DATA_SIZE
@@ -3749,14 +3749,14 @@
// 0x0 -> SIZE_BYTE
// 0x1 -> SIZE_HALFWORD
// 0x2 -> SIZE_WORD
-#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET _U(0x0)
-#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS _U(0x0000000c)
-#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB _U(3)
-#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB _U(2)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB _u(2)
#define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
-#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _U(0x0)
-#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _U(0x1)
-#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _U(0x2)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
// -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_HIGH_PRIORITY
// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
@@ -3769,10 +3769,10 @@
// channels. The DMA's bus priority is not changed. If the DMA is
// not saturated then a low priority channel will see no loss of
// throughput.
-#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET _U(0x0)
-#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS _U(0x00000002)
-#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB _U(1)
-#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB _U(1)
+#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_EN
@@ -3782,124 +3782,124 @@
// 0, the channel will ignore triggers, stop issuing transfers,
// and pause the current transfer sequence (i.e. BUSY will remain
// high if already high)
-#define DMA_CH9_CTRL_TRIG_EN_RESET _U(0x0)
-#define DMA_CH9_CTRL_TRIG_EN_BITS _U(0x00000001)
-#define DMA_CH9_CTRL_TRIG_EN_MSB _U(0)
-#define DMA_CH9_CTRL_TRIG_EN_LSB _U(0)
+#define DMA_CH9_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH9_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH9_CTRL_TRIG_EN_LSB _u(0)
#define DMA_CH9_CTRL_TRIG_EN_ACCESS "RW"
// =============================================================================
// Register : DMA_CH9_AL1_CTRL
// Description : Alias for channel 9 CTRL register
-#define DMA_CH9_AL1_CTRL_OFFSET _U(0x00000250)
-#define DMA_CH9_AL1_CTRL_BITS _U(0xffffffff)
+#define DMA_CH9_AL1_CTRL_OFFSET _u(0x00000250)
+#define DMA_CH9_AL1_CTRL_BITS _u(0xffffffff)
#define DMA_CH9_AL1_CTRL_RESET "-"
-#define DMA_CH9_AL1_CTRL_MSB _U(31)
-#define DMA_CH9_AL1_CTRL_LSB _U(0)
+#define DMA_CH9_AL1_CTRL_MSB _u(31)
+#define DMA_CH9_AL1_CTRL_LSB _u(0)
#define DMA_CH9_AL1_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH9_AL1_READ_ADDR
// Description : Alias for channel 9 READ_ADDR register
-#define DMA_CH9_AL1_READ_ADDR_OFFSET _U(0x00000254)
-#define DMA_CH9_AL1_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH9_AL1_READ_ADDR_OFFSET _u(0x00000254)
+#define DMA_CH9_AL1_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH9_AL1_READ_ADDR_RESET "-"
-#define DMA_CH9_AL1_READ_ADDR_MSB _U(31)
-#define DMA_CH9_AL1_READ_ADDR_LSB _U(0)
+#define DMA_CH9_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH9_AL1_READ_ADDR_LSB _u(0)
#define DMA_CH9_AL1_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH9_AL1_WRITE_ADDR
// Description : Alias for channel 9 WRITE_ADDR register
-#define DMA_CH9_AL1_WRITE_ADDR_OFFSET _U(0x00000258)
-#define DMA_CH9_AL1_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH9_AL1_WRITE_ADDR_OFFSET _u(0x00000258)
+#define DMA_CH9_AL1_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH9_AL1_WRITE_ADDR_RESET "-"
-#define DMA_CH9_AL1_WRITE_ADDR_MSB _U(31)
-#define DMA_CH9_AL1_WRITE_ADDR_LSB _U(0)
+#define DMA_CH9_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH9_AL1_WRITE_ADDR_LSB _u(0)
#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH9_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 9 TRANS_COUNT register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET _U(0x0000025c)
-#define DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS _U(0xffffffff)
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000025c)
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
#define DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET "-"
-#define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB _U(31)
-#define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB _U(0)
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB _u(0)
#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH9_AL2_CTRL
// Description : Alias for channel 9 CTRL register
-#define DMA_CH9_AL2_CTRL_OFFSET _U(0x00000260)
-#define DMA_CH9_AL2_CTRL_BITS _U(0xffffffff)
+#define DMA_CH9_AL2_CTRL_OFFSET _u(0x00000260)
+#define DMA_CH9_AL2_CTRL_BITS _u(0xffffffff)
#define DMA_CH9_AL2_CTRL_RESET "-"
-#define DMA_CH9_AL2_CTRL_MSB _U(31)
-#define DMA_CH9_AL2_CTRL_LSB _U(0)
+#define DMA_CH9_AL2_CTRL_MSB _u(31)
+#define DMA_CH9_AL2_CTRL_LSB _u(0)
#define DMA_CH9_AL2_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH9_AL2_TRANS_COUNT
// Description : Alias for channel 9 TRANS_COUNT register
-#define DMA_CH9_AL2_TRANS_COUNT_OFFSET _U(0x00000264)
-#define DMA_CH9_AL2_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH9_AL2_TRANS_COUNT_OFFSET _u(0x00000264)
+#define DMA_CH9_AL2_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH9_AL2_TRANS_COUNT_RESET "-"
-#define DMA_CH9_AL2_TRANS_COUNT_MSB _U(31)
-#define DMA_CH9_AL2_TRANS_COUNT_LSB _U(0)
+#define DMA_CH9_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH9_AL2_TRANS_COUNT_LSB _u(0)
#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH9_AL2_READ_ADDR
// Description : Alias for channel 9 READ_ADDR register
-#define DMA_CH9_AL2_READ_ADDR_OFFSET _U(0x00000268)
-#define DMA_CH9_AL2_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH9_AL2_READ_ADDR_OFFSET _u(0x00000268)
+#define DMA_CH9_AL2_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH9_AL2_READ_ADDR_RESET "-"
-#define DMA_CH9_AL2_READ_ADDR_MSB _U(31)
-#define DMA_CH9_AL2_READ_ADDR_LSB _U(0)
+#define DMA_CH9_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH9_AL2_READ_ADDR_LSB _u(0)
#define DMA_CH9_AL2_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH9_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 9 WRITE_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET _U(0x0000026c)
-#define DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000026c)
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET "-"
-#define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB _U(31)
-#define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB _U(0)
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB _u(0)
#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH9_AL3_CTRL
// Description : Alias for channel 9 CTRL register
-#define DMA_CH9_AL3_CTRL_OFFSET _U(0x00000270)
-#define DMA_CH9_AL3_CTRL_BITS _U(0xffffffff)
+#define DMA_CH9_AL3_CTRL_OFFSET _u(0x00000270)
+#define DMA_CH9_AL3_CTRL_BITS _u(0xffffffff)
#define DMA_CH9_AL3_CTRL_RESET "-"
-#define DMA_CH9_AL3_CTRL_MSB _U(31)
-#define DMA_CH9_AL3_CTRL_LSB _U(0)
+#define DMA_CH9_AL3_CTRL_MSB _u(31)
+#define DMA_CH9_AL3_CTRL_LSB _u(0)
#define DMA_CH9_AL3_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH9_AL3_WRITE_ADDR
// Description : Alias for channel 9 WRITE_ADDR register
-#define DMA_CH9_AL3_WRITE_ADDR_OFFSET _U(0x00000274)
-#define DMA_CH9_AL3_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH9_AL3_WRITE_ADDR_OFFSET _u(0x00000274)
+#define DMA_CH9_AL3_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH9_AL3_WRITE_ADDR_RESET "-"
-#define DMA_CH9_AL3_WRITE_ADDR_MSB _U(31)
-#define DMA_CH9_AL3_WRITE_ADDR_LSB _U(0)
+#define DMA_CH9_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH9_AL3_WRITE_ADDR_LSB _u(0)
#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH9_AL3_TRANS_COUNT
// Description : Alias for channel 9 TRANS_COUNT register
-#define DMA_CH9_AL3_TRANS_COUNT_OFFSET _U(0x00000278)
-#define DMA_CH9_AL3_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH9_AL3_TRANS_COUNT_OFFSET _u(0x00000278)
+#define DMA_CH9_AL3_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH9_AL3_TRANS_COUNT_RESET "-"
-#define DMA_CH9_AL3_TRANS_COUNT_MSB _U(31)
-#define DMA_CH9_AL3_TRANS_COUNT_LSB _U(0)
+#define DMA_CH9_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH9_AL3_TRANS_COUNT_LSB _u(0)
#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH9_AL3_READ_ADDR_TRIG
// Description : Alias for channel 9 READ_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET _U(0x0000027c)
-#define DMA_CH9_AL3_READ_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000027c)
+#define DMA_CH9_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH9_AL3_READ_ADDR_TRIG_RESET "-"
-#define DMA_CH9_AL3_READ_ADDR_TRIG_MSB _U(31)
-#define DMA_CH9_AL3_READ_ADDR_TRIG_LSB _U(0)
+#define DMA_CH9_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH9_AL3_READ_ADDR_TRIG_LSB _u(0)
#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH10_READ_ADDR
@@ -3907,11 +3907,11 @@
// This register updates automatically each time a read completes.
// The current value is the next address to be read by this
// channel.
-#define DMA_CH10_READ_ADDR_OFFSET _U(0x00000280)
-#define DMA_CH10_READ_ADDR_BITS _U(0xffffffff)
-#define DMA_CH10_READ_ADDR_RESET _U(0x00000000)
-#define DMA_CH10_READ_ADDR_MSB _U(31)
-#define DMA_CH10_READ_ADDR_LSB _U(0)
+#define DMA_CH10_READ_ADDR_OFFSET _u(0x00000280)
+#define DMA_CH10_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH10_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH10_READ_ADDR_MSB _u(31)
+#define DMA_CH10_READ_ADDR_LSB _u(0)
#define DMA_CH10_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH10_WRITE_ADDR
@@ -3919,11 +3919,11 @@
// This register updates automatically each time a write
// completes. The current value is the next address to be written
// by this channel.
-#define DMA_CH10_WRITE_ADDR_OFFSET _U(0x00000284)
-#define DMA_CH10_WRITE_ADDR_BITS _U(0xffffffff)
-#define DMA_CH10_WRITE_ADDR_RESET _U(0x00000000)
-#define DMA_CH10_WRITE_ADDR_MSB _U(31)
-#define DMA_CH10_WRITE_ADDR_LSB _U(0)
+#define DMA_CH10_WRITE_ADDR_OFFSET _u(0x00000284)
+#define DMA_CH10_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH10_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH10_WRITE_ADDR_MSB _u(31)
+#define DMA_CH10_WRITE_ADDR_LSB _u(0)
#define DMA_CH10_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH10_TRANS_COUNT
@@ -3947,27 +3947,27 @@
// is used as a trigger, the written value is used immediately as
// the length of the new transfer sequence, as well as being
// written to RELOAD.
-#define DMA_CH10_TRANS_COUNT_OFFSET _U(0x00000288)
-#define DMA_CH10_TRANS_COUNT_BITS _U(0xffffffff)
-#define DMA_CH10_TRANS_COUNT_RESET _U(0x00000000)
-#define DMA_CH10_TRANS_COUNT_MSB _U(31)
-#define DMA_CH10_TRANS_COUNT_LSB _U(0)
+#define DMA_CH10_TRANS_COUNT_OFFSET _u(0x00000288)
+#define DMA_CH10_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH10_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH10_TRANS_COUNT_MSB _u(31)
+#define DMA_CH10_TRANS_COUNT_LSB _u(0)
#define DMA_CH10_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH10_CTRL_TRIG
// Description : DMA Channel 10 Control and Status
-#define DMA_CH10_CTRL_TRIG_OFFSET _U(0x0000028c)
-#define DMA_CH10_CTRL_TRIG_BITS _U(0xe1ffffff)
-#define DMA_CH10_CTRL_TRIG_RESET _U(0x00005000)
+#define DMA_CH10_CTRL_TRIG_OFFSET _u(0x0000028c)
+#define DMA_CH10_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH10_CTRL_TRIG_RESET _u(0x00005000)
// -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
// halts when it encounters any bus error, and always raises its
// channel IRQ flag.
-#define DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET _U(0x0)
-#define DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS _U(0x80000000)
-#define DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB _U(31)
-#define DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB _U(31)
+#define DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB _u(31)
#define DMA_CH10_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_READ_ERROR
@@ -3976,10 +3976,10 @@
// READ_ADDR shows the approximate address where the bus error was
// encountered (will not to be earlier, or more than 3 transfers
// later)
-#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET _U(0x0)
-#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS _U(0x40000000)
-#define DMA_CH10_CTRL_TRIG_READ_ERROR_MSB _U(30)
-#define DMA_CH10_CTRL_TRIG_READ_ERROR_LSB _U(30)
+#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH10_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH10_CTRL_TRIG_READ_ERROR_LSB _u(30)
#define DMA_CH10_CTRL_TRIG_READ_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_WRITE_ERROR
@@ -3988,10 +3988,10 @@
// WRITE_ADDR shows the approximate address where the bus error
// was encountered (will not to be earlier, or more than 5
// transfers later)
-#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET _U(0x0)
-#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS _U(0x20000000)
-#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB _U(29)
-#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB _U(29)
+#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_BUSY
@@ -4002,10 +4002,10 @@
//
// To terminate a sequence early (and clear the BUSY flag), see
// CHAN_ABORT.
-#define DMA_CH10_CTRL_TRIG_BUSY_RESET _U(0x0)
-#define DMA_CH10_CTRL_TRIG_BUSY_BITS _U(0x01000000)
-#define DMA_CH10_CTRL_TRIG_BUSY_MSB _U(24)
-#define DMA_CH10_CTRL_TRIG_BUSY_LSB _U(24)
+#define DMA_CH10_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH10_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH10_CTRL_TRIG_BUSY_LSB _u(24)
#define DMA_CH10_CTRL_TRIG_BUSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_SNIFF_EN
@@ -4016,10 +4016,10 @@
//
// This allows checksum to be enabled or disabled on a
// per-control- block basis.
-#define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET _U(0x0)
-#define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS _U(0x00800000)
-#define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB _U(23)
-#define DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB _U(23)
+#define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB _u(23)
#define DMA_CH10_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_BSWAP
@@ -4027,10 +4027,10 @@
// For byte data, this has no effect. For halfword data, the two
// bytes of each halfword are swapped. For word data, the four
// bytes of each word are swapped to reverse order.
-#define DMA_CH10_CTRL_TRIG_BSWAP_RESET _U(0x0)
-#define DMA_CH10_CTRL_TRIG_BSWAP_BITS _U(0x00400000)
-#define DMA_CH10_CTRL_TRIG_BSWAP_MSB _U(22)
-#define DMA_CH10_CTRL_TRIG_BSWAP_LSB _U(22)
+#define DMA_CH10_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH10_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH10_CTRL_TRIG_BSWAP_LSB _u(22)
#define DMA_CH10_CTRL_TRIG_BSWAP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_IRQ_QUIET
@@ -4041,10 +4041,10 @@
//
// This reduces the number of interrupts to be serviced by the CPU
// when transferring a DMA chain of many small control blocks.
-#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET _U(0x0)
-#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS _U(0x00200000)
-#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB _U(21)
-#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB _U(21)
+#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_TREQ_SEL
@@ -4058,36 +4058,36 @@
// 0x3d -> Select Timer 2 as TREQ (Optional)
// 0x3e -> Select Timer 3 as TREQ (Optional)
// 0x3f -> Permanent request, for unpaced transfers.
-#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _U(0x00)
-#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _U(0x001f8000)
-#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _U(20)
-#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB _U(15)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB _u(15)
#define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
-#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _U(0x3b)
-#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _U(0x3c)
-#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _U(0x3d)
-#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _U(0x3e)
-#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _U(0x3f)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
// -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_CHAIN_TO
// Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_.
// Reset value is equal to channel number (10).
-#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET _U(0xa)
-#define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS _U(0x00007800)
-#define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB _U(14)
-#define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB _U(11)
+#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET _u(0xa)
+#define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB _u(11)
#define DMA_CH10_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_RING_SEL
// Description : Select whether RING_SIZE applies to read or write addresses.
// If 0, read addresses are wrapped on a (1 << RING_SIZE)
// boundary. If 1, write addresses are wrapped.
-#define DMA_CH10_CTRL_TRIG_RING_SEL_RESET _U(0x0)
-#define DMA_CH10_CTRL_TRIG_RING_SEL_BITS _U(0x00000400)
-#define DMA_CH10_CTRL_TRIG_RING_SEL_MSB _U(10)
-#define DMA_CH10_CTRL_TRIG_RING_SEL_LSB _U(10)
+#define DMA_CH10_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH10_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH10_CTRL_TRIG_RING_SEL_LSB _u(10)
#define DMA_CH10_CTRL_TRIG_RING_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_RING_SIZE
@@ -4100,12 +4100,12 @@
// apply to either read or write addresses, based on value of
// RING_SEL.
// 0x0 -> RING_NONE
-#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET _U(0x0)
-#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS _U(0x000003c0)
-#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB _U(9)
-#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB _U(6)
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB _u(6)
#define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW"
-#define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _U(0x0)
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
// -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_INCR_WRITE
// Description : If 1, the write address increments with each transfer. If 0,
@@ -4113,10 +4113,10 @@
//
// Generally this should be disabled for memory-to-peripheral
// transfers.
-#define DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET _U(0x0)
-#define DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS _U(0x00000020)
-#define DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB _U(5)
-#define DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB _U(5)
+#define DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB _u(5)
#define DMA_CH10_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_INCR_READ
@@ -4125,10 +4125,10 @@
//
// Generally this should be disabled for peripheral-to-memory
// transfers.
-#define DMA_CH10_CTRL_TRIG_INCR_READ_RESET _U(0x0)
-#define DMA_CH10_CTRL_TRIG_INCR_READ_BITS _U(0x00000010)
-#define DMA_CH10_CTRL_TRIG_INCR_READ_MSB _U(4)
-#define DMA_CH10_CTRL_TRIG_INCR_READ_LSB _U(4)
+#define DMA_CH10_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH10_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH10_CTRL_TRIG_INCR_READ_LSB _u(4)
#define DMA_CH10_CTRL_TRIG_INCR_READ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_DATA_SIZE
@@ -4138,14 +4138,14 @@
// 0x0 -> SIZE_BYTE
// 0x1 -> SIZE_HALFWORD
// 0x2 -> SIZE_WORD
-#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET _U(0x0)
-#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS _U(0x0000000c)
-#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB _U(3)
-#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB _U(2)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB _u(2)
#define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
-#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _U(0x0)
-#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _U(0x1)
-#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _U(0x2)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
// -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_HIGH_PRIORITY
// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
@@ -4158,10 +4158,10 @@
// channels. The DMA's bus priority is not changed. If the DMA is
// not saturated then a low priority channel will see no loss of
// throughput.
-#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET _U(0x0)
-#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS _U(0x00000002)
-#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB _U(1)
-#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB _U(1)
+#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_EN
@@ -4171,124 +4171,124 @@
// 0, the channel will ignore triggers, stop issuing transfers,
// and pause the current transfer sequence (i.e. BUSY will remain
// high if already high)
-#define DMA_CH10_CTRL_TRIG_EN_RESET _U(0x0)
-#define DMA_CH10_CTRL_TRIG_EN_BITS _U(0x00000001)
-#define DMA_CH10_CTRL_TRIG_EN_MSB _U(0)
-#define DMA_CH10_CTRL_TRIG_EN_LSB _U(0)
+#define DMA_CH10_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH10_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH10_CTRL_TRIG_EN_LSB _u(0)
#define DMA_CH10_CTRL_TRIG_EN_ACCESS "RW"
// =============================================================================
// Register : DMA_CH10_AL1_CTRL
// Description : Alias for channel 10 CTRL register
-#define DMA_CH10_AL1_CTRL_OFFSET _U(0x00000290)
-#define DMA_CH10_AL1_CTRL_BITS _U(0xffffffff)
+#define DMA_CH10_AL1_CTRL_OFFSET _u(0x00000290)
+#define DMA_CH10_AL1_CTRL_BITS _u(0xffffffff)
#define DMA_CH10_AL1_CTRL_RESET "-"
-#define DMA_CH10_AL1_CTRL_MSB _U(31)
-#define DMA_CH10_AL1_CTRL_LSB _U(0)
+#define DMA_CH10_AL1_CTRL_MSB _u(31)
+#define DMA_CH10_AL1_CTRL_LSB _u(0)
#define DMA_CH10_AL1_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH10_AL1_READ_ADDR
// Description : Alias for channel 10 READ_ADDR register
-#define DMA_CH10_AL1_READ_ADDR_OFFSET _U(0x00000294)
-#define DMA_CH10_AL1_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH10_AL1_READ_ADDR_OFFSET _u(0x00000294)
+#define DMA_CH10_AL1_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH10_AL1_READ_ADDR_RESET "-"
-#define DMA_CH10_AL1_READ_ADDR_MSB _U(31)
-#define DMA_CH10_AL1_READ_ADDR_LSB _U(0)
+#define DMA_CH10_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH10_AL1_READ_ADDR_LSB _u(0)
#define DMA_CH10_AL1_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH10_AL1_WRITE_ADDR
// Description : Alias for channel 10 WRITE_ADDR register
-#define DMA_CH10_AL1_WRITE_ADDR_OFFSET _U(0x00000298)
-#define DMA_CH10_AL1_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH10_AL1_WRITE_ADDR_OFFSET _u(0x00000298)
+#define DMA_CH10_AL1_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH10_AL1_WRITE_ADDR_RESET "-"
-#define DMA_CH10_AL1_WRITE_ADDR_MSB _U(31)
-#define DMA_CH10_AL1_WRITE_ADDR_LSB _U(0)
+#define DMA_CH10_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH10_AL1_WRITE_ADDR_LSB _u(0)
#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH10_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 10 TRANS_COUNT register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET _U(0x0000029c)
-#define DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS _U(0xffffffff)
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000029c)
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
#define DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET "-"
-#define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB _U(31)
-#define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB _U(0)
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB _u(0)
#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH10_AL2_CTRL
// Description : Alias for channel 10 CTRL register
-#define DMA_CH10_AL2_CTRL_OFFSET _U(0x000002a0)
-#define DMA_CH10_AL2_CTRL_BITS _U(0xffffffff)
+#define DMA_CH10_AL2_CTRL_OFFSET _u(0x000002a0)
+#define DMA_CH10_AL2_CTRL_BITS _u(0xffffffff)
#define DMA_CH10_AL2_CTRL_RESET "-"
-#define DMA_CH10_AL2_CTRL_MSB _U(31)
-#define DMA_CH10_AL2_CTRL_LSB _U(0)
+#define DMA_CH10_AL2_CTRL_MSB _u(31)
+#define DMA_CH10_AL2_CTRL_LSB _u(0)
#define DMA_CH10_AL2_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH10_AL2_TRANS_COUNT
// Description : Alias for channel 10 TRANS_COUNT register
-#define DMA_CH10_AL2_TRANS_COUNT_OFFSET _U(0x000002a4)
-#define DMA_CH10_AL2_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH10_AL2_TRANS_COUNT_OFFSET _u(0x000002a4)
+#define DMA_CH10_AL2_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH10_AL2_TRANS_COUNT_RESET "-"
-#define DMA_CH10_AL2_TRANS_COUNT_MSB _U(31)
-#define DMA_CH10_AL2_TRANS_COUNT_LSB _U(0)
+#define DMA_CH10_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH10_AL2_TRANS_COUNT_LSB _u(0)
#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH10_AL2_READ_ADDR
// Description : Alias for channel 10 READ_ADDR register
-#define DMA_CH10_AL2_READ_ADDR_OFFSET _U(0x000002a8)
-#define DMA_CH10_AL2_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH10_AL2_READ_ADDR_OFFSET _u(0x000002a8)
+#define DMA_CH10_AL2_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH10_AL2_READ_ADDR_RESET "-"
-#define DMA_CH10_AL2_READ_ADDR_MSB _U(31)
-#define DMA_CH10_AL2_READ_ADDR_LSB _U(0)
+#define DMA_CH10_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH10_AL2_READ_ADDR_LSB _u(0)
#define DMA_CH10_AL2_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH10_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 10 WRITE_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET _U(0x000002ac)
-#define DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ac)
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET "-"
-#define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB _U(31)
-#define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB _U(0)
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB _u(0)
#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH10_AL3_CTRL
// Description : Alias for channel 10 CTRL register
-#define DMA_CH10_AL3_CTRL_OFFSET _U(0x000002b0)
-#define DMA_CH10_AL3_CTRL_BITS _U(0xffffffff)
+#define DMA_CH10_AL3_CTRL_OFFSET _u(0x000002b0)
+#define DMA_CH10_AL3_CTRL_BITS _u(0xffffffff)
#define DMA_CH10_AL3_CTRL_RESET "-"
-#define DMA_CH10_AL3_CTRL_MSB _U(31)
-#define DMA_CH10_AL3_CTRL_LSB _U(0)
+#define DMA_CH10_AL3_CTRL_MSB _u(31)
+#define DMA_CH10_AL3_CTRL_LSB _u(0)
#define DMA_CH10_AL3_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH10_AL3_WRITE_ADDR
// Description : Alias for channel 10 WRITE_ADDR register
-#define DMA_CH10_AL3_WRITE_ADDR_OFFSET _U(0x000002b4)
-#define DMA_CH10_AL3_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH10_AL3_WRITE_ADDR_OFFSET _u(0x000002b4)
+#define DMA_CH10_AL3_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH10_AL3_WRITE_ADDR_RESET "-"
-#define DMA_CH10_AL3_WRITE_ADDR_MSB _U(31)
-#define DMA_CH10_AL3_WRITE_ADDR_LSB _U(0)
+#define DMA_CH10_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH10_AL3_WRITE_ADDR_LSB _u(0)
#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH10_AL3_TRANS_COUNT
// Description : Alias for channel 10 TRANS_COUNT register
-#define DMA_CH10_AL3_TRANS_COUNT_OFFSET _U(0x000002b8)
-#define DMA_CH10_AL3_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH10_AL3_TRANS_COUNT_OFFSET _u(0x000002b8)
+#define DMA_CH10_AL3_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH10_AL3_TRANS_COUNT_RESET "-"
-#define DMA_CH10_AL3_TRANS_COUNT_MSB _U(31)
-#define DMA_CH10_AL3_TRANS_COUNT_LSB _U(0)
+#define DMA_CH10_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH10_AL3_TRANS_COUNT_LSB _u(0)
#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH10_AL3_READ_ADDR_TRIG
// Description : Alias for channel 10 READ_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET _U(0x000002bc)
-#define DMA_CH10_AL3_READ_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002bc)
+#define DMA_CH10_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH10_AL3_READ_ADDR_TRIG_RESET "-"
-#define DMA_CH10_AL3_READ_ADDR_TRIG_MSB _U(31)
-#define DMA_CH10_AL3_READ_ADDR_TRIG_LSB _U(0)
+#define DMA_CH10_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH10_AL3_READ_ADDR_TRIG_LSB _u(0)
#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH11_READ_ADDR
@@ -4296,11 +4296,11 @@
// This register updates automatically each time a read completes.
// The current value is the next address to be read by this
// channel.
-#define DMA_CH11_READ_ADDR_OFFSET _U(0x000002c0)
-#define DMA_CH11_READ_ADDR_BITS _U(0xffffffff)
-#define DMA_CH11_READ_ADDR_RESET _U(0x00000000)
-#define DMA_CH11_READ_ADDR_MSB _U(31)
-#define DMA_CH11_READ_ADDR_LSB _U(0)
+#define DMA_CH11_READ_ADDR_OFFSET _u(0x000002c0)
+#define DMA_CH11_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH11_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH11_READ_ADDR_MSB _u(31)
+#define DMA_CH11_READ_ADDR_LSB _u(0)
#define DMA_CH11_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH11_WRITE_ADDR
@@ -4308,11 +4308,11 @@
// This register updates automatically each time a write
// completes. The current value is the next address to be written
// by this channel.
-#define DMA_CH11_WRITE_ADDR_OFFSET _U(0x000002c4)
-#define DMA_CH11_WRITE_ADDR_BITS _U(0xffffffff)
-#define DMA_CH11_WRITE_ADDR_RESET _U(0x00000000)
-#define DMA_CH11_WRITE_ADDR_MSB _U(31)
-#define DMA_CH11_WRITE_ADDR_LSB _U(0)
+#define DMA_CH11_WRITE_ADDR_OFFSET _u(0x000002c4)
+#define DMA_CH11_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH11_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH11_WRITE_ADDR_MSB _u(31)
+#define DMA_CH11_WRITE_ADDR_LSB _u(0)
#define DMA_CH11_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH11_TRANS_COUNT
@@ -4336,27 +4336,27 @@
// is used as a trigger, the written value is used immediately as
// the length of the new transfer sequence, as well as being
// written to RELOAD.
-#define DMA_CH11_TRANS_COUNT_OFFSET _U(0x000002c8)
-#define DMA_CH11_TRANS_COUNT_BITS _U(0xffffffff)
-#define DMA_CH11_TRANS_COUNT_RESET _U(0x00000000)
-#define DMA_CH11_TRANS_COUNT_MSB _U(31)
-#define DMA_CH11_TRANS_COUNT_LSB _U(0)
+#define DMA_CH11_TRANS_COUNT_OFFSET _u(0x000002c8)
+#define DMA_CH11_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH11_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH11_TRANS_COUNT_MSB _u(31)
+#define DMA_CH11_TRANS_COUNT_LSB _u(0)
#define DMA_CH11_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH11_CTRL_TRIG
// Description : DMA Channel 11 Control and Status
-#define DMA_CH11_CTRL_TRIG_OFFSET _U(0x000002cc)
-#define DMA_CH11_CTRL_TRIG_BITS _U(0xe1ffffff)
-#define DMA_CH11_CTRL_TRIG_RESET _U(0x00005800)
+#define DMA_CH11_CTRL_TRIG_OFFSET _u(0x000002cc)
+#define DMA_CH11_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH11_CTRL_TRIG_RESET _u(0x00005800)
// -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
// halts when it encounters any bus error, and always raises its
// channel IRQ flag.
-#define DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET _U(0x0)
-#define DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS _U(0x80000000)
-#define DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB _U(31)
-#define DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB _U(31)
+#define DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB _u(31)
#define DMA_CH11_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_READ_ERROR
@@ -4365,10 +4365,10 @@
// READ_ADDR shows the approximate address where the bus error was
// encountered (will not to be earlier, or more than 3 transfers
// later)
-#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET _U(0x0)
-#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS _U(0x40000000)
-#define DMA_CH11_CTRL_TRIG_READ_ERROR_MSB _U(30)
-#define DMA_CH11_CTRL_TRIG_READ_ERROR_LSB _U(30)
+#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH11_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH11_CTRL_TRIG_READ_ERROR_LSB _u(30)
#define DMA_CH11_CTRL_TRIG_READ_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_WRITE_ERROR
@@ -4377,10 +4377,10 @@
// WRITE_ADDR shows the approximate address where the bus error
// was encountered (will not to be earlier, or more than 5
// transfers later)
-#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET _U(0x0)
-#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS _U(0x20000000)
-#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB _U(29)
-#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB _U(29)
+#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_BUSY
@@ -4391,10 +4391,10 @@
//
// To terminate a sequence early (and clear the BUSY flag), see
// CHAN_ABORT.
-#define DMA_CH11_CTRL_TRIG_BUSY_RESET _U(0x0)
-#define DMA_CH11_CTRL_TRIG_BUSY_BITS _U(0x01000000)
-#define DMA_CH11_CTRL_TRIG_BUSY_MSB _U(24)
-#define DMA_CH11_CTRL_TRIG_BUSY_LSB _U(24)
+#define DMA_CH11_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH11_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH11_CTRL_TRIG_BUSY_LSB _u(24)
#define DMA_CH11_CTRL_TRIG_BUSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_SNIFF_EN
@@ -4405,10 +4405,10 @@
//
// This allows checksum to be enabled or disabled on a
// per-control- block basis.
-#define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET _U(0x0)
-#define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS _U(0x00800000)
-#define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB _U(23)
-#define DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB _U(23)
+#define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB _u(23)
#define DMA_CH11_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_BSWAP
@@ -4416,10 +4416,10 @@
// For byte data, this has no effect. For halfword data, the two
// bytes of each halfword are swapped. For word data, the four
// bytes of each word are swapped to reverse order.
-#define DMA_CH11_CTRL_TRIG_BSWAP_RESET _U(0x0)
-#define DMA_CH11_CTRL_TRIG_BSWAP_BITS _U(0x00400000)
-#define DMA_CH11_CTRL_TRIG_BSWAP_MSB _U(22)
-#define DMA_CH11_CTRL_TRIG_BSWAP_LSB _U(22)
+#define DMA_CH11_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH11_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH11_CTRL_TRIG_BSWAP_LSB _u(22)
#define DMA_CH11_CTRL_TRIG_BSWAP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_IRQ_QUIET
@@ -4430,10 +4430,10 @@
//
// This reduces the number of interrupts to be serviced by the CPU
// when transferring a DMA chain of many small control blocks.
-#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET _U(0x0)
-#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS _U(0x00200000)
-#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB _U(21)
-#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB _U(21)
+#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_TREQ_SEL
@@ -4447,36 +4447,36 @@
// 0x3d -> Select Timer 2 as TREQ (Optional)
// 0x3e -> Select Timer 3 as TREQ (Optional)
// 0x3f -> Permanent request, for unpaced transfers.
-#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _U(0x00)
-#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _U(0x001f8000)
-#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _U(20)
-#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB _U(15)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB _u(15)
#define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
-#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _U(0x3b)
-#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _U(0x3c)
-#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _U(0x3d)
-#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _U(0x3e)
-#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _U(0x3f)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
// -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_CHAIN_TO
// Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_.
// Reset value is equal to channel number (11).
-#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET _U(0xb)
-#define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS _U(0x00007800)
-#define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB _U(14)
-#define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB _U(11)
+#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET _u(0xb)
+#define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB _u(11)
#define DMA_CH11_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_RING_SEL
// Description : Select whether RING_SIZE applies to read or write addresses.
// If 0, read addresses are wrapped on a (1 << RING_SIZE)
// boundary. If 1, write addresses are wrapped.
-#define DMA_CH11_CTRL_TRIG_RING_SEL_RESET _U(0x0)
-#define DMA_CH11_CTRL_TRIG_RING_SEL_BITS _U(0x00000400)
-#define DMA_CH11_CTRL_TRIG_RING_SEL_MSB _U(10)
-#define DMA_CH11_CTRL_TRIG_RING_SEL_LSB _U(10)
+#define DMA_CH11_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH11_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH11_CTRL_TRIG_RING_SEL_LSB _u(10)
#define DMA_CH11_CTRL_TRIG_RING_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_RING_SIZE
@@ -4489,12 +4489,12 @@
// apply to either read or write addresses, based on value of
// RING_SEL.
// 0x0 -> RING_NONE
-#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET _U(0x0)
-#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS _U(0x000003c0)
-#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB _U(9)
-#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB _U(6)
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB _u(6)
#define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW"
-#define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _U(0x0)
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
// -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_INCR_WRITE
// Description : If 1, the write address increments with each transfer. If 0,
@@ -4502,10 +4502,10 @@
//
// Generally this should be disabled for memory-to-peripheral
// transfers.
-#define DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET _U(0x0)
-#define DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS _U(0x00000020)
-#define DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB _U(5)
-#define DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB _U(5)
+#define DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB _u(5)
#define DMA_CH11_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_INCR_READ
@@ -4514,10 +4514,10 @@
//
// Generally this should be disabled for peripheral-to-memory
// transfers.
-#define DMA_CH11_CTRL_TRIG_INCR_READ_RESET _U(0x0)
-#define DMA_CH11_CTRL_TRIG_INCR_READ_BITS _U(0x00000010)
-#define DMA_CH11_CTRL_TRIG_INCR_READ_MSB _U(4)
-#define DMA_CH11_CTRL_TRIG_INCR_READ_LSB _U(4)
+#define DMA_CH11_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH11_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH11_CTRL_TRIG_INCR_READ_LSB _u(4)
#define DMA_CH11_CTRL_TRIG_INCR_READ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_DATA_SIZE
@@ -4527,14 +4527,14 @@
// 0x0 -> SIZE_BYTE
// 0x1 -> SIZE_HALFWORD
// 0x2 -> SIZE_WORD
-#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET _U(0x0)
-#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS _U(0x0000000c)
-#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB _U(3)
-#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB _U(2)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB _u(2)
#define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
-#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _U(0x0)
-#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _U(0x1)
-#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _U(0x2)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
// -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_HIGH_PRIORITY
// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
@@ -4547,10 +4547,10 @@
// channels. The DMA's bus priority is not changed. If the DMA is
// not saturated then a low priority channel will see no loss of
// throughput.
-#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET _U(0x0)
-#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS _U(0x00000002)
-#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB _U(1)
-#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB _U(1)
+#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_EN
@@ -4560,124 +4560,124 @@
// 0, the channel will ignore triggers, stop issuing transfers,
// and pause the current transfer sequence (i.e. BUSY will remain
// high if already high)
-#define DMA_CH11_CTRL_TRIG_EN_RESET _U(0x0)
-#define DMA_CH11_CTRL_TRIG_EN_BITS _U(0x00000001)
-#define DMA_CH11_CTRL_TRIG_EN_MSB _U(0)
-#define DMA_CH11_CTRL_TRIG_EN_LSB _U(0)
+#define DMA_CH11_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH11_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH11_CTRL_TRIG_EN_LSB _u(0)
#define DMA_CH11_CTRL_TRIG_EN_ACCESS "RW"
// =============================================================================
// Register : DMA_CH11_AL1_CTRL
// Description : Alias for channel 11 CTRL register
-#define DMA_CH11_AL1_CTRL_OFFSET _U(0x000002d0)
-#define DMA_CH11_AL1_CTRL_BITS _U(0xffffffff)
+#define DMA_CH11_AL1_CTRL_OFFSET _u(0x000002d0)
+#define DMA_CH11_AL1_CTRL_BITS _u(0xffffffff)
#define DMA_CH11_AL1_CTRL_RESET "-"
-#define DMA_CH11_AL1_CTRL_MSB _U(31)
-#define DMA_CH11_AL1_CTRL_LSB _U(0)
+#define DMA_CH11_AL1_CTRL_MSB _u(31)
+#define DMA_CH11_AL1_CTRL_LSB _u(0)
#define DMA_CH11_AL1_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH11_AL1_READ_ADDR
// Description : Alias for channel 11 READ_ADDR register
-#define DMA_CH11_AL1_READ_ADDR_OFFSET _U(0x000002d4)
-#define DMA_CH11_AL1_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH11_AL1_READ_ADDR_OFFSET _u(0x000002d4)
+#define DMA_CH11_AL1_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH11_AL1_READ_ADDR_RESET "-"
-#define DMA_CH11_AL1_READ_ADDR_MSB _U(31)
-#define DMA_CH11_AL1_READ_ADDR_LSB _U(0)
+#define DMA_CH11_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH11_AL1_READ_ADDR_LSB _u(0)
#define DMA_CH11_AL1_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH11_AL1_WRITE_ADDR
// Description : Alias for channel 11 WRITE_ADDR register
-#define DMA_CH11_AL1_WRITE_ADDR_OFFSET _U(0x000002d8)
-#define DMA_CH11_AL1_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH11_AL1_WRITE_ADDR_OFFSET _u(0x000002d8)
+#define DMA_CH11_AL1_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH11_AL1_WRITE_ADDR_RESET "-"
-#define DMA_CH11_AL1_WRITE_ADDR_MSB _U(31)
-#define DMA_CH11_AL1_WRITE_ADDR_LSB _U(0)
+#define DMA_CH11_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH11_AL1_WRITE_ADDR_LSB _u(0)
#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH11_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 11 TRANS_COUNT register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET _U(0x000002dc)
-#define DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS _U(0xffffffff)
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000002dc)
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
#define DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET "-"
-#define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB _U(31)
-#define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB _U(0)
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB _u(0)
#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH11_AL2_CTRL
// Description : Alias for channel 11 CTRL register
-#define DMA_CH11_AL2_CTRL_OFFSET _U(0x000002e0)
-#define DMA_CH11_AL2_CTRL_BITS _U(0xffffffff)
+#define DMA_CH11_AL2_CTRL_OFFSET _u(0x000002e0)
+#define DMA_CH11_AL2_CTRL_BITS _u(0xffffffff)
#define DMA_CH11_AL2_CTRL_RESET "-"
-#define DMA_CH11_AL2_CTRL_MSB _U(31)
-#define DMA_CH11_AL2_CTRL_LSB _U(0)
+#define DMA_CH11_AL2_CTRL_MSB _u(31)
+#define DMA_CH11_AL2_CTRL_LSB _u(0)
#define DMA_CH11_AL2_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH11_AL2_TRANS_COUNT
// Description : Alias for channel 11 TRANS_COUNT register
-#define DMA_CH11_AL2_TRANS_COUNT_OFFSET _U(0x000002e4)
-#define DMA_CH11_AL2_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH11_AL2_TRANS_COUNT_OFFSET _u(0x000002e4)
+#define DMA_CH11_AL2_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH11_AL2_TRANS_COUNT_RESET "-"
-#define DMA_CH11_AL2_TRANS_COUNT_MSB _U(31)
-#define DMA_CH11_AL2_TRANS_COUNT_LSB _U(0)
+#define DMA_CH11_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH11_AL2_TRANS_COUNT_LSB _u(0)
#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH11_AL2_READ_ADDR
// Description : Alias for channel 11 READ_ADDR register
-#define DMA_CH11_AL2_READ_ADDR_OFFSET _U(0x000002e8)
-#define DMA_CH11_AL2_READ_ADDR_BITS _U(0xffffffff)
+#define DMA_CH11_AL2_READ_ADDR_OFFSET _u(0x000002e8)
+#define DMA_CH11_AL2_READ_ADDR_BITS _u(0xffffffff)
#define DMA_CH11_AL2_READ_ADDR_RESET "-"
-#define DMA_CH11_AL2_READ_ADDR_MSB _U(31)
-#define DMA_CH11_AL2_READ_ADDR_LSB _U(0)
+#define DMA_CH11_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH11_AL2_READ_ADDR_LSB _u(0)
#define DMA_CH11_AL2_READ_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH11_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 11 WRITE_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET _U(0x000002ec)
-#define DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ec)
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET "-"
-#define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB _U(31)
-#define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB _U(0)
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB _u(0)
#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_CH11_AL3_CTRL
// Description : Alias for channel 11 CTRL register
-#define DMA_CH11_AL3_CTRL_OFFSET _U(0x000002f0)
-#define DMA_CH11_AL3_CTRL_BITS _U(0xffffffff)
+#define DMA_CH11_AL3_CTRL_OFFSET _u(0x000002f0)
+#define DMA_CH11_AL3_CTRL_BITS _u(0xffffffff)
#define DMA_CH11_AL3_CTRL_RESET "-"
-#define DMA_CH11_AL3_CTRL_MSB _U(31)
-#define DMA_CH11_AL3_CTRL_LSB _U(0)
+#define DMA_CH11_AL3_CTRL_MSB _u(31)
+#define DMA_CH11_AL3_CTRL_LSB _u(0)
#define DMA_CH11_AL3_CTRL_ACCESS "RO"
// =============================================================================
// Register : DMA_CH11_AL3_WRITE_ADDR
// Description : Alias for channel 11 WRITE_ADDR register
-#define DMA_CH11_AL3_WRITE_ADDR_OFFSET _U(0x000002f4)
-#define DMA_CH11_AL3_WRITE_ADDR_BITS _U(0xffffffff)
+#define DMA_CH11_AL3_WRITE_ADDR_OFFSET _u(0x000002f4)
+#define DMA_CH11_AL3_WRITE_ADDR_BITS _u(0xffffffff)
#define DMA_CH11_AL3_WRITE_ADDR_RESET "-"
-#define DMA_CH11_AL3_WRITE_ADDR_MSB _U(31)
-#define DMA_CH11_AL3_WRITE_ADDR_LSB _U(0)
+#define DMA_CH11_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH11_AL3_WRITE_ADDR_LSB _u(0)
#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH11_AL3_TRANS_COUNT
// Description : Alias for channel 11 TRANS_COUNT register
-#define DMA_CH11_AL3_TRANS_COUNT_OFFSET _U(0x000002f8)
-#define DMA_CH11_AL3_TRANS_COUNT_BITS _U(0xffffffff)
+#define DMA_CH11_AL3_TRANS_COUNT_OFFSET _u(0x000002f8)
+#define DMA_CH11_AL3_TRANS_COUNT_BITS _u(0xffffffff)
#define DMA_CH11_AL3_TRANS_COUNT_RESET "-"
-#define DMA_CH11_AL3_TRANS_COUNT_MSB _U(31)
-#define DMA_CH11_AL3_TRANS_COUNT_LSB _U(0)
+#define DMA_CH11_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH11_AL3_TRANS_COUNT_LSB _u(0)
#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RO"
// =============================================================================
// Register : DMA_CH11_AL3_READ_ADDR_TRIG
// Description : Alias for channel 11 READ_ADDR register
// This is a trigger register (0xc). Writing a nonzero value will
// reload the channel counter and start the channel.
-#define DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET _U(0x000002fc)
-#define DMA_CH11_AL3_READ_ADDR_TRIG_BITS _U(0xffffffff)
+#define DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002fc)
+#define DMA_CH11_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
#define DMA_CH11_AL3_READ_ADDR_TRIG_RESET "-"
-#define DMA_CH11_AL3_READ_ADDR_TRIG_MSB _U(31)
-#define DMA_CH11_AL3_READ_ADDR_TRIG_LSB _U(0)
+#define DMA_CH11_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH11_AL3_READ_ADDR_TRIG_LSB _u(0)
#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RO"
// =============================================================================
// Register : DMA_INTR
@@ -4697,32 +4697,32 @@
//
// It is also valid to ignore this behaviour and just use
// INTE0/INTS0/IRQ 0.
-#define DMA_INTR_OFFSET _U(0x00000400)
-#define DMA_INTR_BITS _U(0x0000ffff)
-#define DMA_INTR_RESET _U(0x00000000)
-#define DMA_INTR_MSB _U(15)
-#define DMA_INTR_LSB _U(0)
+#define DMA_INTR_OFFSET _u(0x00000400)
+#define DMA_INTR_BITS _u(0x0000ffff)
+#define DMA_INTR_RESET _u(0x00000000)
+#define DMA_INTR_MSB _u(15)
+#define DMA_INTR_LSB _u(0)
#define DMA_INTR_ACCESS "RO"
// =============================================================================
// Register : DMA_INTE0
// Description : Interrupt Enables for IRQ 0
// Set bit n to pass interrupts from channel n to DMA IRQ 0.
-#define DMA_INTE0_OFFSET _U(0x00000404)
-#define DMA_INTE0_BITS _U(0x0000ffff)
-#define DMA_INTE0_RESET _U(0x00000000)
-#define DMA_INTE0_MSB _U(15)
-#define DMA_INTE0_LSB _U(0)
+#define DMA_INTE0_OFFSET _u(0x00000404)
+#define DMA_INTE0_BITS _u(0x0000ffff)
+#define DMA_INTE0_RESET _u(0x00000000)
+#define DMA_INTE0_MSB _u(15)
+#define DMA_INTE0_LSB _u(0)
#define DMA_INTE0_ACCESS "RW"
// =============================================================================
// Register : DMA_INTF0
// Description : Force Interrupts
// Write 1s to force the corresponding bits in INTE0. The
// interrupt remains asserted until INTF0 is cleared.
-#define DMA_INTF0_OFFSET _U(0x00000408)
-#define DMA_INTF0_BITS _U(0x0000ffff)
-#define DMA_INTF0_RESET _U(0x00000000)
-#define DMA_INTF0_MSB _U(15)
-#define DMA_INTF0_LSB _U(0)
+#define DMA_INTF0_OFFSET _u(0x00000408)
+#define DMA_INTF0_BITS _u(0x0000ffff)
+#define DMA_INTF0_RESET _u(0x00000000)
+#define DMA_INTF0_MSB _u(15)
+#define DMA_INTF0_LSB _u(0)
#define DMA_INTF0_ACCESS "RW"
// =============================================================================
// Register : DMA_INTS0
@@ -4730,32 +4730,32 @@
// Indicates active channel interrupt requests which are currently
// causing IRQ 0 to be asserted.
// Channel interrupts can be cleared by writing a bit mask here.
-#define DMA_INTS0_OFFSET _U(0x0000040c)
-#define DMA_INTS0_BITS _U(0x0000ffff)
-#define DMA_INTS0_RESET _U(0x00000000)
-#define DMA_INTS0_MSB _U(15)
-#define DMA_INTS0_LSB _U(0)
+#define DMA_INTS0_OFFSET _u(0x0000040c)
+#define DMA_INTS0_BITS _u(0x0000ffff)
+#define DMA_INTS0_RESET _u(0x00000000)
+#define DMA_INTS0_MSB _u(15)
+#define DMA_INTS0_LSB _u(0)
#define DMA_INTS0_ACCESS "WC"
// =============================================================================
// Register : DMA_INTE1
// Description : Interrupt Enables for IRQ 1
// Set bit n to pass interrupts from channel n to DMA IRQ 1.
-#define DMA_INTE1_OFFSET _U(0x00000414)
-#define DMA_INTE1_BITS _U(0x0000ffff)
-#define DMA_INTE1_RESET _U(0x00000000)
-#define DMA_INTE1_MSB _U(15)
-#define DMA_INTE1_LSB _U(0)
+#define DMA_INTE1_OFFSET _u(0x00000414)
+#define DMA_INTE1_BITS _u(0x0000ffff)
+#define DMA_INTE1_RESET _u(0x00000000)
+#define DMA_INTE1_MSB _u(15)
+#define DMA_INTE1_LSB _u(0)
#define DMA_INTE1_ACCESS "RW"
// =============================================================================
// Register : DMA_INTF1
// Description : Force Interrupts for IRQ 1
// Write 1s to force the corresponding bits in INTE0. The
// interrupt remains asserted until INTF0 is cleared.
-#define DMA_INTF1_OFFSET _U(0x00000418)
-#define DMA_INTF1_BITS _U(0x0000ffff)
-#define DMA_INTF1_RESET _U(0x00000000)
-#define DMA_INTF1_MSB _U(15)
-#define DMA_INTF1_LSB _U(0)
+#define DMA_INTF1_OFFSET _u(0x00000418)
+#define DMA_INTF1_BITS _u(0x0000ffff)
+#define DMA_INTF1_RESET _u(0x00000000)
+#define DMA_INTF1_MSB _u(15)
+#define DMA_INTF1_LSB _u(0)
#define DMA_INTF1_ACCESS "RW"
// =============================================================================
// Register : DMA_INTS1
@@ -4763,11 +4763,11 @@
// Indicates active channel interrupt requests which are currently
// causing IRQ 1 to be asserted.
// Channel interrupts can be cleared by writing a bit mask here.
-#define DMA_INTS1_OFFSET _U(0x0000041c)
-#define DMA_INTS1_BITS _U(0x0000ffff)
-#define DMA_INTS1_RESET _U(0x00000000)
-#define DMA_INTS1_MSB _U(15)
-#define DMA_INTS1_LSB _U(0)
+#define DMA_INTS1_OFFSET _u(0x0000041c)
+#define DMA_INTS1_BITS _u(0x0000ffff)
+#define DMA_INTS1_RESET _u(0x00000000)
+#define DMA_INTS1_MSB _u(15)
+#define DMA_INTS1_LSB _u(0)
#define DMA_INTS1_ACCESS "WC"
// =============================================================================
// Register : DMA_TIMER0
@@ -4776,26 +4776,26 @@
// ((X/Y) * sys_clk). This equation is evaluated every sys_clk
// cycles and therefore can only generate TREQs at a rate of 1 per
// sys_clk (i.e. permanent TREQ) or less.
-#define DMA_TIMER0_OFFSET _U(0x00000420)
-#define DMA_TIMER0_BITS _U(0xffffffff)
-#define DMA_TIMER0_RESET _U(0x00000000)
+#define DMA_TIMER0_OFFSET _u(0x00000420)
+#define DMA_TIMER0_BITS _u(0xffffffff)
+#define DMA_TIMER0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : DMA_TIMER0_X
// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y)
// fractional timer.
-#define DMA_TIMER0_X_RESET _U(0x0000)
-#define DMA_TIMER0_X_BITS _U(0xffff0000)
-#define DMA_TIMER0_X_MSB _U(31)
-#define DMA_TIMER0_X_LSB _U(16)
+#define DMA_TIMER0_X_RESET _u(0x0000)
+#define DMA_TIMER0_X_BITS _u(0xffff0000)
+#define DMA_TIMER0_X_MSB _u(31)
+#define DMA_TIMER0_X_LSB _u(16)
#define DMA_TIMER0_X_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_TIMER0_Y
// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y)
// fractional timer.
-#define DMA_TIMER0_Y_RESET _U(0x0000)
-#define DMA_TIMER0_Y_BITS _U(0x0000ffff)
-#define DMA_TIMER0_Y_MSB _U(15)
-#define DMA_TIMER0_Y_LSB _U(0)
+#define DMA_TIMER0_Y_RESET _u(0x0000)
+#define DMA_TIMER0_Y_BITS _u(0x0000ffff)
+#define DMA_TIMER0_Y_MSB _u(15)
+#define DMA_TIMER0_Y_LSB _u(0)
#define DMA_TIMER0_Y_ACCESS "RW"
// =============================================================================
// Register : DMA_TIMER1
@@ -4804,26 +4804,26 @@
// ((X/Y) * sys_clk). This equation is evaluated every sys_clk
// cycles and therefore can only generate TREQs at a rate of 1 per
// sys_clk (i.e. permanent TREQ) or less.
-#define DMA_TIMER1_OFFSET _U(0x00000424)
-#define DMA_TIMER1_BITS _U(0xffffffff)
-#define DMA_TIMER1_RESET _U(0x00000000)
+#define DMA_TIMER1_OFFSET _u(0x00000424)
+#define DMA_TIMER1_BITS _u(0xffffffff)
+#define DMA_TIMER1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : DMA_TIMER1_X
// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y)
// fractional timer.
-#define DMA_TIMER1_X_RESET _U(0x0000)
-#define DMA_TIMER1_X_BITS _U(0xffff0000)
-#define DMA_TIMER1_X_MSB _U(31)
-#define DMA_TIMER1_X_LSB _U(16)
+#define DMA_TIMER1_X_RESET _u(0x0000)
+#define DMA_TIMER1_X_BITS _u(0xffff0000)
+#define DMA_TIMER1_X_MSB _u(31)
+#define DMA_TIMER1_X_LSB _u(16)
#define DMA_TIMER1_X_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_TIMER1_Y
// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y)
// fractional timer.
-#define DMA_TIMER1_Y_RESET _U(0x0000)
-#define DMA_TIMER1_Y_BITS _U(0x0000ffff)
-#define DMA_TIMER1_Y_MSB _U(15)
-#define DMA_TIMER1_Y_LSB _U(0)
+#define DMA_TIMER1_Y_RESET _u(0x0000)
+#define DMA_TIMER1_Y_BITS _u(0x0000ffff)
+#define DMA_TIMER1_Y_MSB _u(15)
+#define DMA_TIMER1_Y_LSB _u(0)
#define DMA_TIMER1_Y_ACCESS "RW"
// =============================================================================
// Register : DMA_TIMER2
@@ -4832,26 +4832,26 @@
// ((X/Y) * sys_clk). This equation is evaluated every sys_clk
// cycles and therefore can only generate TREQs at a rate of 1 per
// sys_clk (i.e. permanent TREQ) or less.
-#define DMA_TIMER2_OFFSET _U(0x00000428)
-#define DMA_TIMER2_BITS _U(0xffffffff)
-#define DMA_TIMER2_RESET _U(0x00000000)
+#define DMA_TIMER2_OFFSET _u(0x00000428)
+#define DMA_TIMER2_BITS _u(0xffffffff)
+#define DMA_TIMER2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : DMA_TIMER2_X
// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y)
// fractional timer.
-#define DMA_TIMER2_X_RESET _U(0x0000)
-#define DMA_TIMER2_X_BITS _U(0xffff0000)
-#define DMA_TIMER2_X_MSB _U(31)
-#define DMA_TIMER2_X_LSB _U(16)
+#define DMA_TIMER2_X_RESET _u(0x0000)
+#define DMA_TIMER2_X_BITS _u(0xffff0000)
+#define DMA_TIMER2_X_MSB _u(31)
+#define DMA_TIMER2_X_LSB _u(16)
#define DMA_TIMER2_X_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_TIMER2_Y
// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y)
// fractional timer.
-#define DMA_TIMER2_Y_RESET _U(0x0000)
-#define DMA_TIMER2_Y_BITS _U(0x0000ffff)
-#define DMA_TIMER2_Y_MSB _U(15)
-#define DMA_TIMER2_Y_LSB _U(0)
+#define DMA_TIMER2_Y_RESET _u(0x0000)
+#define DMA_TIMER2_Y_BITS _u(0x0000ffff)
+#define DMA_TIMER2_Y_MSB _u(15)
+#define DMA_TIMER2_Y_LSB _u(0)
#define DMA_TIMER2_Y_ACCESS "RW"
// =============================================================================
// Register : DMA_TIMER3
@@ -4860,26 +4860,26 @@
// ((X/Y) * sys_clk). This equation is evaluated every sys_clk
// cycles and therefore can only generate TREQs at a rate of 1 per
// sys_clk (i.e. permanent TREQ) or less.
-#define DMA_TIMER3_OFFSET _U(0x0000042c)
-#define DMA_TIMER3_BITS _U(0xffffffff)
-#define DMA_TIMER3_RESET _U(0x00000000)
+#define DMA_TIMER3_OFFSET _u(0x0000042c)
+#define DMA_TIMER3_BITS _u(0xffffffff)
+#define DMA_TIMER3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : DMA_TIMER3_X
// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y)
// fractional timer.
-#define DMA_TIMER3_X_RESET _U(0x0000)
-#define DMA_TIMER3_X_BITS _U(0xffff0000)
-#define DMA_TIMER3_X_MSB _U(31)
-#define DMA_TIMER3_X_LSB _U(16)
+#define DMA_TIMER3_X_RESET _u(0x0000)
+#define DMA_TIMER3_X_BITS _u(0xffff0000)
+#define DMA_TIMER3_X_MSB _u(31)
+#define DMA_TIMER3_X_LSB _u(16)
#define DMA_TIMER3_X_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_TIMER3_Y
// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y)
// fractional timer.
-#define DMA_TIMER3_Y_RESET _U(0x0000)
-#define DMA_TIMER3_Y_BITS _U(0x0000ffff)
-#define DMA_TIMER3_Y_MSB _U(15)
-#define DMA_TIMER3_Y_LSB _U(0)
+#define DMA_TIMER3_Y_RESET _u(0x0000)
+#define DMA_TIMER3_Y_BITS _u(0x0000ffff)
+#define DMA_TIMER3_Y_MSB _u(15)
+#define DMA_TIMER3_Y_LSB _u(0)
#define DMA_TIMER3_Y_ACCESS "RW"
// =============================================================================
// Register : DMA_MULTI_CHAN_TRIGGER
@@ -4888,38 +4888,38 @@
// a 1 to the relevant bit is the same as writing to that
// channel's trigger register; the channel will start if it is
// currently enabled and not already busy.
-#define DMA_MULTI_CHAN_TRIGGER_OFFSET _U(0x00000430)
-#define DMA_MULTI_CHAN_TRIGGER_BITS _U(0x0000ffff)
-#define DMA_MULTI_CHAN_TRIGGER_RESET _U(0x00000000)
-#define DMA_MULTI_CHAN_TRIGGER_MSB _U(15)
-#define DMA_MULTI_CHAN_TRIGGER_LSB _U(0)
+#define DMA_MULTI_CHAN_TRIGGER_OFFSET _u(0x00000430)
+#define DMA_MULTI_CHAN_TRIGGER_BITS _u(0x0000ffff)
+#define DMA_MULTI_CHAN_TRIGGER_RESET _u(0x00000000)
+#define DMA_MULTI_CHAN_TRIGGER_MSB _u(15)
+#define DMA_MULTI_CHAN_TRIGGER_LSB _u(0)
#define DMA_MULTI_CHAN_TRIGGER_ACCESS "SC"
// =============================================================================
// Register : DMA_SNIFF_CTRL
// Description : Sniffer Control
-#define DMA_SNIFF_CTRL_OFFSET _U(0x00000434)
-#define DMA_SNIFF_CTRL_BITS _U(0x00000fff)
-#define DMA_SNIFF_CTRL_RESET _U(0x00000000)
+#define DMA_SNIFF_CTRL_OFFSET _u(0x00000434)
+#define DMA_SNIFF_CTRL_BITS _u(0x00000fff)
+#define DMA_SNIFF_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : DMA_SNIFF_CTRL_OUT_INV
// Description : If set, the result appears inverted (bitwise complement) when
// read. This does not affect the way the checksum is calculated;
// the result is transformed on-the-fly between the result
// register and the bus.
-#define DMA_SNIFF_CTRL_OUT_INV_RESET _U(0x0)
-#define DMA_SNIFF_CTRL_OUT_INV_BITS _U(0x00000800)
-#define DMA_SNIFF_CTRL_OUT_INV_MSB _U(11)
-#define DMA_SNIFF_CTRL_OUT_INV_LSB _U(11)
+#define DMA_SNIFF_CTRL_OUT_INV_RESET _u(0x0)
+#define DMA_SNIFF_CTRL_OUT_INV_BITS _u(0x00000800)
+#define DMA_SNIFF_CTRL_OUT_INV_MSB _u(11)
+#define DMA_SNIFF_CTRL_OUT_INV_LSB _u(11)
#define DMA_SNIFF_CTRL_OUT_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_SNIFF_CTRL_OUT_REV
// Description : If set, the result appears bit-reversed when read. This does
// not affect the way the checksum is calculated; the result is
// transformed on-the-fly between the result register and the bus.
-#define DMA_SNIFF_CTRL_OUT_REV_RESET _U(0x0)
-#define DMA_SNIFF_CTRL_OUT_REV_BITS _U(0x00000400)
-#define DMA_SNIFF_CTRL_OUT_REV_MSB _U(10)
-#define DMA_SNIFF_CTRL_OUT_REV_LSB _U(10)
+#define DMA_SNIFF_CTRL_OUT_REV_RESET _u(0x0)
+#define DMA_SNIFF_CTRL_OUT_REV_BITS _u(0x00000400)
+#define DMA_SNIFF_CTRL_OUT_REV_MSB _u(10)
+#define DMA_SNIFF_CTRL_OUT_REV_LSB _u(10)
#define DMA_SNIFF_CTRL_OUT_REV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_SNIFF_CTRL_BSWAP
@@ -4930,10 +4930,10 @@
// byteswap performed in the read master: if channel CTRL_BSWAP
// and SNIFF_CTRL_BSWAP are both enabled, their effects cancel
// from the sniffer's point of view.
-#define DMA_SNIFF_CTRL_BSWAP_RESET _U(0x0)
-#define DMA_SNIFF_CTRL_BSWAP_BITS _U(0x00000200)
-#define DMA_SNIFF_CTRL_BSWAP_MSB _U(9)
-#define DMA_SNIFF_CTRL_BSWAP_LSB _U(9)
+#define DMA_SNIFF_CTRL_BSWAP_RESET _u(0x0)
+#define DMA_SNIFF_CTRL_BSWAP_BITS _u(0x00000200)
+#define DMA_SNIFF_CTRL_BSWAP_MSB _u(9)
+#define DMA_SNIFF_CTRL_BSWAP_LSB _u(9)
#define DMA_SNIFF_CTRL_BSWAP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_SNIFF_CTRL_CALC
@@ -4946,32 +4946,32 @@
// population count is odd.
// 0xf -> Calculate a simple 32-bit checksum (addition with a 32
// bit accumulator)
-#define DMA_SNIFF_CTRL_CALC_RESET _U(0x0)
-#define DMA_SNIFF_CTRL_CALC_BITS _U(0x000001e0)
-#define DMA_SNIFF_CTRL_CALC_MSB _U(8)
-#define DMA_SNIFF_CTRL_CALC_LSB _U(5)
+#define DMA_SNIFF_CTRL_CALC_RESET _u(0x0)
+#define DMA_SNIFF_CTRL_CALC_BITS _u(0x000001e0)
+#define DMA_SNIFF_CTRL_CALC_MSB _u(8)
+#define DMA_SNIFF_CTRL_CALC_LSB _u(5)
#define DMA_SNIFF_CTRL_CALC_ACCESS "RW"
-#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 _U(0x0)
-#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R _U(0x1)
-#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 _U(0x2)
-#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R _U(0x3)
-#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN _U(0xe)
-#define DMA_SNIFF_CTRL_CALC_VALUE_SUM _U(0xf)
+#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 _u(0x0)
+#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R _u(0x1)
+#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 _u(0x2)
+#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R _u(0x3)
+#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN _u(0xe)
+#define DMA_SNIFF_CTRL_CALC_VALUE_SUM _u(0xf)
// -----------------------------------------------------------------------------
// Field : DMA_SNIFF_CTRL_DMACH
// Description : DMA channel for Sniffer to observe
-#define DMA_SNIFF_CTRL_DMACH_RESET _U(0x0)
-#define DMA_SNIFF_CTRL_DMACH_BITS _U(0x0000001e)
-#define DMA_SNIFF_CTRL_DMACH_MSB _U(4)
-#define DMA_SNIFF_CTRL_DMACH_LSB _U(1)
+#define DMA_SNIFF_CTRL_DMACH_RESET _u(0x0)
+#define DMA_SNIFF_CTRL_DMACH_BITS _u(0x0000001e)
+#define DMA_SNIFF_CTRL_DMACH_MSB _u(4)
+#define DMA_SNIFF_CTRL_DMACH_LSB _u(1)
#define DMA_SNIFF_CTRL_DMACH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : DMA_SNIFF_CTRL_EN
// Description : Enable sniffer
-#define DMA_SNIFF_CTRL_EN_RESET _U(0x0)
-#define DMA_SNIFF_CTRL_EN_BITS _U(0x00000001)
-#define DMA_SNIFF_CTRL_EN_MSB _U(0)
-#define DMA_SNIFF_CTRL_EN_LSB _U(0)
+#define DMA_SNIFF_CTRL_EN_RESET _u(0x0)
+#define DMA_SNIFF_CTRL_EN_BITS _u(0x00000001)
+#define DMA_SNIFF_CTRL_EN_MSB _u(0)
+#define DMA_SNIFF_CTRL_EN_LSB _u(0)
#define DMA_SNIFF_CTRL_EN_ACCESS "RW"
// =============================================================================
// Register : DMA_SNIFF_DATA
@@ -4981,41 +4981,41 @@
// update this register each time it observes a read from the
// indicated channel. Once the channel completes, the final result
// can be read from this register.
-#define DMA_SNIFF_DATA_OFFSET _U(0x00000438)
-#define DMA_SNIFF_DATA_BITS _U(0xffffffff)
-#define DMA_SNIFF_DATA_RESET _U(0x00000000)
-#define DMA_SNIFF_DATA_MSB _U(31)
-#define DMA_SNIFF_DATA_LSB _U(0)
+#define DMA_SNIFF_DATA_OFFSET _u(0x00000438)
+#define DMA_SNIFF_DATA_BITS _u(0xffffffff)
+#define DMA_SNIFF_DATA_RESET _u(0x00000000)
+#define DMA_SNIFF_DATA_MSB _u(31)
+#define DMA_SNIFF_DATA_LSB _u(0)
#define DMA_SNIFF_DATA_ACCESS "RW"
// =============================================================================
// Register : DMA_FIFO_LEVELS
// Description : Debug RAF, WAF, TDF levels
-#define DMA_FIFO_LEVELS_OFFSET _U(0x00000440)
-#define DMA_FIFO_LEVELS_BITS _U(0x00ffffff)
-#define DMA_FIFO_LEVELS_RESET _U(0x00000000)
+#define DMA_FIFO_LEVELS_OFFSET _u(0x00000440)
+#define DMA_FIFO_LEVELS_BITS _u(0x00ffffff)
+#define DMA_FIFO_LEVELS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : DMA_FIFO_LEVELS_RAF_LVL
// Description : Current Read-Address-FIFO fill level
-#define DMA_FIFO_LEVELS_RAF_LVL_RESET _U(0x00)
-#define DMA_FIFO_LEVELS_RAF_LVL_BITS _U(0x00ff0000)
-#define DMA_FIFO_LEVELS_RAF_LVL_MSB _U(23)
-#define DMA_FIFO_LEVELS_RAF_LVL_LSB _U(16)
+#define DMA_FIFO_LEVELS_RAF_LVL_RESET _u(0x00)
+#define DMA_FIFO_LEVELS_RAF_LVL_BITS _u(0x00ff0000)
+#define DMA_FIFO_LEVELS_RAF_LVL_MSB _u(23)
+#define DMA_FIFO_LEVELS_RAF_LVL_LSB _u(16)
#define DMA_FIFO_LEVELS_RAF_LVL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_FIFO_LEVELS_WAF_LVL
// Description : Current Write-Address-FIFO fill level
-#define DMA_FIFO_LEVELS_WAF_LVL_RESET _U(0x00)
-#define DMA_FIFO_LEVELS_WAF_LVL_BITS _U(0x0000ff00)
-#define DMA_FIFO_LEVELS_WAF_LVL_MSB _U(15)
-#define DMA_FIFO_LEVELS_WAF_LVL_LSB _U(8)
+#define DMA_FIFO_LEVELS_WAF_LVL_RESET _u(0x00)
+#define DMA_FIFO_LEVELS_WAF_LVL_BITS _u(0x0000ff00)
+#define DMA_FIFO_LEVELS_WAF_LVL_MSB _u(15)
+#define DMA_FIFO_LEVELS_WAF_LVL_LSB _u(8)
#define DMA_FIFO_LEVELS_WAF_LVL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : DMA_FIFO_LEVELS_TDF_LVL
// Description : Current Transfer-Data-FIFO fill level
-#define DMA_FIFO_LEVELS_TDF_LVL_RESET _U(0x00)
-#define DMA_FIFO_LEVELS_TDF_LVL_BITS _U(0x000000ff)
-#define DMA_FIFO_LEVELS_TDF_LVL_MSB _U(7)
-#define DMA_FIFO_LEVELS_TDF_LVL_LSB _U(0)
+#define DMA_FIFO_LEVELS_TDF_LVL_RESET _u(0x00)
+#define DMA_FIFO_LEVELS_TDF_LVL_BITS _u(0x000000ff)
+#define DMA_FIFO_LEVELS_TDF_LVL_MSB _u(7)
+#define DMA_FIFO_LEVELS_TDF_LVL_LSB _u(0)
#define DMA_FIFO_LEVELS_TDF_LVL_ACCESS "RO"
// =============================================================================
// Register : DMA_CHAN_ABORT
@@ -5028,22 +5028,22 @@
// After writing, this register must be polled until it returns
// all-zero. Until this point, it is unsafe to restart the
// channel.
-#define DMA_CHAN_ABORT_OFFSET _U(0x00000444)
-#define DMA_CHAN_ABORT_BITS _U(0x0000ffff)
-#define DMA_CHAN_ABORT_RESET _U(0x00000000)
-#define DMA_CHAN_ABORT_MSB _U(15)
-#define DMA_CHAN_ABORT_LSB _U(0)
+#define DMA_CHAN_ABORT_OFFSET _u(0x00000444)
+#define DMA_CHAN_ABORT_BITS _u(0x0000ffff)
+#define DMA_CHAN_ABORT_RESET _u(0x00000000)
+#define DMA_CHAN_ABORT_MSB _u(15)
+#define DMA_CHAN_ABORT_LSB _u(0)
#define DMA_CHAN_ABORT_ACCESS "SC"
// =============================================================================
// Register : DMA_N_CHANNELS
// Description : The number of channels this DMA instance is equipped with. This
// DMA supports up to 16 hardware channels, but can be configured
// with as few as one, to minimise silicon area.
-#define DMA_N_CHANNELS_OFFSET _U(0x00000448)
-#define DMA_N_CHANNELS_BITS _U(0x0000001f)
+#define DMA_N_CHANNELS_OFFSET _u(0x00000448)
+#define DMA_N_CHANNELS_BITS _u(0x0000001f)
#define DMA_N_CHANNELS_RESET "-"
-#define DMA_N_CHANNELS_MSB _U(4)
-#define DMA_N_CHANNELS_LSB _U(0)
+#define DMA_N_CHANNELS_MSB _u(4)
+#define DMA_N_CHANNELS_LSB _u(0)
#define DMA_N_CHANNELS_ACCESS "RO"
// =============================================================================
// Register : DMA_CH0_DBG_CTDREQ
@@ -5051,21 +5051,21 @@
// expects it can perform on the peripheral without
// overflow/underflow. Write any value: clears the counter, and
// cause channel to re-initiate DREQ handshake.
-#define DMA_CH0_DBG_CTDREQ_OFFSET _U(0x00000800)
-#define DMA_CH0_DBG_CTDREQ_BITS _U(0x0000003f)
-#define DMA_CH0_DBG_CTDREQ_RESET _U(0x00000000)
-#define DMA_CH0_DBG_CTDREQ_MSB _U(5)
-#define DMA_CH0_DBG_CTDREQ_LSB _U(0)
+#define DMA_CH0_DBG_CTDREQ_OFFSET _u(0x00000800)
+#define DMA_CH0_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH0_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH0_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH0_DBG_CTDREQ_LSB _u(0)
#define DMA_CH0_DBG_CTDREQ_ACCESS "RO"
// =============================================================================
// Register : DMA_CH0_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
// of the next transfer
-#define DMA_CH0_DBG_TCR_OFFSET _U(0x00000804)
-#define DMA_CH0_DBG_TCR_BITS _U(0xffffffff)
-#define DMA_CH0_DBG_TCR_RESET _U(0x00000000)
-#define DMA_CH0_DBG_TCR_MSB _U(31)
-#define DMA_CH0_DBG_TCR_LSB _U(0)
+#define DMA_CH0_DBG_TCR_OFFSET _u(0x00000804)
+#define DMA_CH0_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH0_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH0_DBG_TCR_MSB _u(31)
+#define DMA_CH0_DBG_TCR_LSB _u(0)
#define DMA_CH0_DBG_TCR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH1_DBG_CTDREQ
@@ -5073,21 +5073,21 @@
// expects it can perform on the peripheral without
// overflow/underflow. Write any value: clears the counter, and
// cause channel to re-initiate DREQ handshake.
-#define DMA_CH1_DBG_CTDREQ_OFFSET _U(0x00000840)
-#define DMA_CH1_DBG_CTDREQ_BITS _U(0x0000003f)
-#define DMA_CH1_DBG_CTDREQ_RESET _U(0x00000000)
-#define DMA_CH1_DBG_CTDREQ_MSB _U(5)
-#define DMA_CH1_DBG_CTDREQ_LSB _U(0)
+#define DMA_CH1_DBG_CTDREQ_OFFSET _u(0x00000840)
+#define DMA_CH1_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH1_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH1_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH1_DBG_CTDREQ_LSB _u(0)
#define DMA_CH1_DBG_CTDREQ_ACCESS "RO"
// =============================================================================
// Register : DMA_CH1_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
// of the next transfer
-#define DMA_CH1_DBG_TCR_OFFSET _U(0x00000844)
-#define DMA_CH1_DBG_TCR_BITS _U(0xffffffff)
-#define DMA_CH1_DBG_TCR_RESET _U(0x00000000)
-#define DMA_CH1_DBG_TCR_MSB _U(31)
-#define DMA_CH1_DBG_TCR_LSB _U(0)
+#define DMA_CH1_DBG_TCR_OFFSET _u(0x00000844)
+#define DMA_CH1_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH1_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH1_DBG_TCR_MSB _u(31)
+#define DMA_CH1_DBG_TCR_LSB _u(0)
#define DMA_CH1_DBG_TCR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH2_DBG_CTDREQ
@@ -5095,21 +5095,21 @@
// expects it can perform on the peripheral without
// overflow/underflow. Write any value: clears the counter, and
// cause channel to re-initiate DREQ handshake.
-#define DMA_CH2_DBG_CTDREQ_OFFSET _U(0x00000880)
-#define DMA_CH2_DBG_CTDREQ_BITS _U(0x0000003f)
-#define DMA_CH2_DBG_CTDREQ_RESET _U(0x00000000)
-#define DMA_CH2_DBG_CTDREQ_MSB _U(5)
-#define DMA_CH2_DBG_CTDREQ_LSB _U(0)
+#define DMA_CH2_DBG_CTDREQ_OFFSET _u(0x00000880)
+#define DMA_CH2_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH2_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH2_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH2_DBG_CTDREQ_LSB _u(0)
#define DMA_CH2_DBG_CTDREQ_ACCESS "RO"
// =============================================================================
// Register : DMA_CH2_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
// of the next transfer
-#define DMA_CH2_DBG_TCR_OFFSET _U(0x00000884)
-#define DMA_CH2_DBG_TCR_BITS _U(0xffffffff)
-#define DMA_CH2_DBG_TCR_RESET _U(0x00000000)
-#define DMA_CH2_DBG_TCR_MSB _U(31)
-#define DMA_CH2_DBG_TCR_LSB _U(0)
+#define DMA_CH2_DBG_TCR_OFFSET _u(0x00000884)
+#define DMA_CH2_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH2_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH2_DBG_TCR_MSB _u(31)
+#define DMA_CH2_DBG_TCR_LSB _u(0)
#define DMA_CH2_DBG_TCR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH3_DBG_CTDREQ
@@ -5117,21 +5117,21 @@
// expects it can perform on the peripheral without
// overflow/underflow. Write any value: clears the counter, and
// cause channel to re-initiate DREQ handshake.
-#define DMA_CH3_DBG_CTDREQ_OFFSET _U(0x000008c0)
-#define DMA_CH3_DBG_CTDREQ_BITS _U(0x0000003f)
-#define DMA_CH3_DBG_CTDREQ_RESET _U(0x00000000)
-#define DMA_CH3_DBG_CTDREQ_MSB _U(5)
-#define DMA_CH3_DBG_CTDREQ_LSB _U(0)
+#define DMA_CH3_DBG_CTDREQ_OFFSET _u(0x000008c0)
+#define DMA_CH3_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH3_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH3_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH3_DBG_CTDREQ_LSB _u(0)
#define DMA_CH3_DBG_CTDREQ_ACCESS "RO"
// =============================================================================
// Register : DMA_CH3_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
// of the next transfer
-#define DMA_CH3_DBG_TCR_OFFSET _U(0x000008c4)
-#define DMA_CH3_DBG_TCR_BITS _U(0xffffffff)
-#define DMA_CH3_DBG_TCR_RESET _U(0x00000000)
-#define DMA_CH3_DBG_TCR_MSB _U(31)
-#define DMA_CH3_DBG_TCR_LSB _U(0)
+#define DMA_CH3_DBG_TCR_OFFSET _u(0x000008c4)
+#define DMA_CH3_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH3_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH3_DBG_TCR_MSB _u(31)
+#define DMA_CH3_DBG_TCR_LSB _u(0)
#define DMA_CH3_DBG_TCR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH4_DBG_CTDREQ
@@ -5139,21 +5139,21 @@
// expects it can perform on the peripheral without
// overflow/underflow. Write any value: clears the counter, and
// cause channel to re-initiate DREQ handshake.
-#define DMA_CH4_DBG_CTDREQ_OFFSET _U(0x00000900)
-#define DMA_CH4_DBG_CTDREQ_BITS _U(0x0000003f)
-#define DMA_CH4_DBG_CTDREQ_RESET _U(0x00000000)
-#define DMA_CH4_DBG_CTDREQ_MSB _U(5)
-#define DMA_CH4_DBG_CTDREQ_LSB _U(0)
+#define DMA_CH4_DBG_CTDREQ_OFFSET _u(0x00000900)
+#define DMA_CH4_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH4_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH4_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH4_DBG_CTDREQ_LSB _u(0)
#define DMA_CH4_DBG_CTDREQ_ACCESS "RO"
// =============================================================================
// Register : DMA_CH4_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
// of the next transfer
-#define DMA_CH4_DBG_TCR_OFFSET _U(0x00000904)
-#define DMA_CH4_DBG_TCR_BITS _U(0xffffffff)
-#define DMA_CH4_DBG_TCR_RESET _U(0x00000000)
-#define DMA_CH4_DBG_TCR_MSB _U(31)
-#define DMA_CH4_DBG_TCR_LSB _U(0)
+#define DMA_CH4_DBG_TCR_OFFSET _u(0x00000904)
+#define DMA_CH4_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH4_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH4_DBG_TCR_MSB _u(31)
+#define DMA_CH4_DBG_TCR_LSB _u(0)
#define DMA_CH4_DBG_TCR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH5_DBG_CTDREQ
@@ -5161,21 +5161,21 @@
// expects it can perform on the peripheral without
// overflow/underflow. Write any value: clears the counter, and
// cause channel to re-initiate DREQ handshake.
-#define DMA_CH5_DBG_CTDREQ_OFFSET _U(0x00000940)
-#define DMA_CH5_DBG_CTDREQ_BITS _U(0x0000003f)
-#define DMA_CH5_DBG_CTDREQ_RESET _U(0x00000000)
-#define DMA_CH5_DBG_CTDREQ_MSB _U(5)
-#define DMA_CH5_DBG_CTDREQ_LSB _U(0)
+#define DMA_CH5_DBG_CTDREQ_OFFSET _u(0x00000940)
+#define DMA_CH5_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH5_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH5_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH5_DBG_CTDREQ_LSB _u(0)
#define DMA_CH5_DBG_CTDREQ_ACCESS "RO"
// =============================================================================
// Register : DMA_CH5_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
// of the next transfer
-#define DMA_CH5_DBG_TCR_OFFSET _U(0x00000944)
-#define DMA_CH5_DBG_TCR_BITS _U(0xffffffff)
-#define DMA_CH5_DBG_TCR_RESET _U(0x00000000)
-#define DMA_CH5_DBG_TCR_MSB _U(31)
-#define DMA_CH5_DBG_TCR_LSB _U(0)
+#define DMA_CH5_DBG_TCR_OFFSET _u(0x00000944)
+#define DMA_CH5_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH5_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH5_DBG_TCR_MSB _u(31)
+#define DMA_CH5_DBG_TCR_LSB _u(0)
#define DMA_CH5_DBG_TCR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH6_DBG_CTDREQ
@@ -5183,21 +5183,21 @@
// expects it can perform on the peripheral without
// overflow/underflow. Write any value: clears the counter, and
// cause channel to re-initiate DREQ handshake.
-#define DMA_CH6_DBG_CTDREQ_OFFSET _U(0x00000980)
-#define DMA_CH6_DBG_CTDREQ_BITS _U(0x0000003f)
-#define DMA_CH6_DBG_CTDREQ_RESET _U(0x00000000)
-#define DMA_CH6_DBG_CTDREQ_MSB _U(5)
-#define DMA_CH6_DBG_CTDREQ_LSB _U(0)
+#define DMA_CH6_DBG_CTDREQ_OFFSET _u(0x00000980)
+#define DMA_CH6_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH6_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH6_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH6_DBG_CTDREQ_LSB _u(0)
#define DMA_CH6_DBG_CTDREQ_ACCESS "RO"
// =============================================================================
// Register : DMA_CH6_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
// of the next transfer
-#define DMA_CH6_DBG_TCR_OFFSET _U(0x00000984)
-#define DMA_CH6_DBG_TCR_BITS _U(0xffffffff)
-#define DMA_CH6_DBG_TCR_RESET _U(0x00000000)
-#define DMA_CH6_DBG_TCR_MSB _U(31)
-#define DMA_CH6_DBG_TCR_LSB _U(0)
+#define DMA_CH6_DBG_TCR_OFFSET _u(0x00000984)
+#define DMA_CH6_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH6_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH6_DBG_TCR_MSB _u(31)
+#define DMA_CH6_DBG_TCR_LSB _u(0)
#define DMA_CH6_DBG_TCR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH7_DBG_CTDREQ
@@ -5205,21 +5205,21 @@
// expects it can perform on the peripheral without
// overflow/underflow. Write any value: clears the counter, and
// cause channel to re-initiate DREQ handshake.
-#define DMA_CH7_DBG_CTDREQ_OFFSET _U(0x000009c0)
-#define DMA_CH7_DBG_CTDREQ_BITS _U(0x0000003f)
-#define DMA_CH7_DBG_CTDREQ_RESET _U(0x00000000)
-#define DMA_CH7_DBG_CTDREQ_MSB _U(5)
-#define DMA_CH7_DBG_CTDREQ_LSB _U(0)
+#define DMA_CH7_DBG_CTDREQ_OFFSET _u(0x000009c0)
+#define DMA_CH7_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH7_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH7_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH7_DBG_CTDREQ_LSB _u(0)
#define DMA_CH7_DBG_CTDREQ_ACCESS "RO"
// =============================================================================
// Register : DMA_CH7_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
// of the next transfer
-#define DMA_CH7_DBG_TCR_OFFSET _U(0x000009c4)
-#define DMA_CH7_DBG_TCR_BITS _U(0xffffffff)
-#define DMA_CH7_DBG_TCR_RESET _U(0x00000000)
-#define DMA_CH7_DBG_TCR_MSB _U(31)
-#define DMA_CH7_DBG_TCR_LSB _U(0)
+#define DMA_CH7_DBG_TCR_OFFSET _u(0x000009c4)
+#define DMA_CH7_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH7_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH7_DBG_TCR_MSB _u(31)
+#define DMA_CH7_DBG_TCR_LSB _u(0)
#define DMA_CH7_DBG_TCR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH8_DBG_CTDREQ
@@ -5227,21 +5227,21 @@
// expects it can perform on the peripheral without
// overflow/underflow. Write any value: clears the counter, and
// cause channel to re-initiate DREQ handshake.
-#define DMA_CH8_DBG_CTDREQ_OFFSET _U(0x00000a00)
-#define DMA_CH8_DBG_CTDREQ_BITS _U(0x0000003f)
-#define DMA_CH8_DBG_CTDREQ_RESET _U(0x00000000)
-#define DMA_CH8_DBG_CTDREQ_MSB _U(5)
-#define DMA_CH8_DBG_CTDREQ_LSB _U(0)
+#define DMA_CH8_DBG_CTDREQ_OFFSET _u(0x00000a00)
+#define DMA_CH8_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH8_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH8_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH8_DBG_CTDREQ_LSB _u(0)
#define DMA_CH8_DBG_CTDREQ_ACCESS "RO"
// =============================================================================
// Register : DMA_CH8_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
// of the next transfer
-#define DMA_CH8_DBG_TCR_OFFSET _U(0x00000a04)
-#define DMA_CH8_DBG_TCR_BITS _U(0xffffffff)
-#define DMA_CH8_DBG_TCR_RESET _U(0x00000000)
-#define DMA_CH8_DBG_TCR_MSB _U(31)
-#define DMA_CH8_DBG_TCR_LSB _U(0)
+#define DMA_CH8_DBG_TCR_OFFSET _u(0x00000a04)
+#define DMA_CH8_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH8_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH8_DBG_TCR_MSB _u(31)
+#define DMA_CH8_DBG_TCR_LSB _u(0)
#define DMA_CH8_DBG_TCR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH9_DBG_CTDREQ
@@ -5249,21 +5249,21 @@
// expects it can perform on the peripheral without
// overflow/underflow. Write any value: clears the counter, and
// cause channel to re-initiate DREQ handshake.
-#define DMA_CH9_DBG_CTDREQ_OFFSET _U(0x00000a40)
-#define DMA_CH9_DBG_CTDREQ_BITS _U(0x0000003f)
-#define DMA_CH9_DBG_CTDREQ_RESET _U(0x00000000)
-#define DMA_CH9_DBG_CTDREQ_MSB _U(5)
-#define DMA_CH9_DBG_CTDREQ_LSB _U(0)
+#define DMA_CH9_DBG_CTDREQ_OFFSET _u(0x00000a40)
+#define DMA_CH9_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH9_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH9_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH9_DBG_CTDREQ_LSB _u(0)
#define DMA_CH9_DBG_CTDREQ_ACCESS "RO"
// =============================================================================
// Register : DMA_CH9_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
// of the next transfer
-#define DMA_CH9_DBG_TCR_OFFSET _U(0x00000a44)
-#define DMA_CH9_DBG_TCR_BITS _U(0xffffffff)
-#define DMA_CH9_DBG_TCR_RESET _U(0x00000000)
-#define DMA_CH9_DBG_TCR_MSB _U(31)
-#define DMA_CH9_DBG_TCR_LSB _U(0)
+#define DMA_CH9_DBG_TCR_OFFSET _u(0x00000a44)
+#define DMA_CH9_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH9_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH9_DBG_TCR_MSB _u(31)
+#define DMA_CH9_DBG_TCR_LSB _u(0)
#define DMA_CH9_DBG_TCR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH10_DBG_CTDREQ
@@ -5271,21 +5271,21 @@
// expects it can perform on the peripheral without
// overflow/underflow. Write any value: clears the counter, and
// cause channel to re-initiate DREQ handshake.
-#define DMA_CH10_DBG_CTDREQ_OFFSET _U(0x00000a80)
-#define DMA_CH10_DBG_CTDREQ_BITS _U(0x0000003f)
-#define DMA_CH10_DBG_CTDREQ_RESET _U(0x00000000)
-#define DMA_CH10_DBG_CTDREQ_MSB _U(5)
-#define DMA_CH10_DBG_CTDREQ_LSB _U(0)
+#define DMA_CH10_DBG_CTDREQ_OFFSET _u(0x00000a80)
+#define DMA_CH10_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH10_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH10_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH10_DBG_CTDREQ_LSB _u(0)
#define DMA_CH10_DBG_CTDREQ_ACCESS "RO"
// =============================================================================
// Register : DMA_CH10_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
// of the next transfer
-#define DMA_CH10_DBG_TCR_OFFSET _U(0x00000a84)
-#define DMA_CH10_DBG_TCR_BITS _U(0xffffffff)
-#define DMA_CH10_DBG_TCR_RESET _U(0x00000000)
-#define DMA_CH10_DBG_TCR_MSB _U(31)
-#define DMA_CH10_DBG_TCR_LSB _U(0)
+#define DMA_CH10_DBG_TCR_OFFSET _u(0x00000a84)
+#define DMA_CH10_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH10_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH10_DBG_TCR_MSB _u(31)
+#define DMA_CH10_DBG_TCR_LSB _u(0)
#define DMA_CH10_DBG_TCR_ACCESS "RO"
// =============================================================================
// Register : DMA_CH11_DBG_CTDREQ
@@ -5293,21 +5293,21 @@
// expects it can perform on the peripheral without
// overflow/underflow. Write any value: clears the counter, and
// cause channel to re-initiate DREQ handshake.
-#define DMA_CH11_DBG_CTDREQ_OFFSET _U(0x00000ac0)
-#define DMA_CH11_DBG_CTDREQ_BITS _U(0x0000003f)
-#define DMA_CH11_DBG_CTDREQ_RESET _U(0x00000000)
-#define DMA_CH11_DBG_CTDREQ_MSB _U(5)
-#define DMA_CH11_DBG_CTDREQ_LSB _U(0)
+#define DMA_CH11_DBG_CTDREQ_OFFSET _u(0x00000ac0)
+#define DMA_CH11_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH11_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH11_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH11_DBG_CTDREQ_LSB _u(0)
#define DMA_CH11_DBG_CTDREQ_ACCESS "RO"
// =============================================================================
// Register : DMA_CH11_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
// of the next transfer
-#define DMA_CH11_DBG_TCR_OFFSET _U(0x00000ac4)
-#define DMA_CH11_DBG_TCR_BITS _U(0xffffffff)
-#define DMA_CH11_DBG_TCR_RESET _U(0x00000000)
-#define DMA_CH11_DBG_TCR_MSB _U(31)
-#define DMA_CH11_DBG_TCR_LSB _U(0)
+#define DMA_CH11_DBG_TCR_OFFSET _u(0x00000ac4)
+#define DMA_CH11_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH11_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH11_DBG_TCR_MSB _u(31)
+#define DMA_CH11_DBG_TCR_LSB _u(0)
#define DMA_CH11_DBG_TCR_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_DMA_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/i2c.h b/src/rp2040/hardware_regs/include/hardware/regs/i2c.h
index 63b0fbf..f797044 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/i2c.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/i2c.h
@@ -21,17 +21,17 @@
// Read/Write Access: - bit 10 is read only. - bit 11 is read only
// - bit 16 is read only - bit 17 is read only - bits 18 and 19
// are read only.
-#define I2C_IC_CON_OFFSET _U(0x00000000)
-#define I2C_IC_CON_BITS _U(0x000007ff)
-#define I2C_IC_CON_RESET _U(0x00000065)
+#define I2C_IC_CON_OFFSET _u(0x00000000)
+#define I2C_IC_CON_BITS _u(0x000007ff)
+#define I2C_IC_CON_RESET _u(0x00000065)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE
// Description : Master issues the STOP_DET interrupt irrespective of whether
// master is active or not
-#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET _U(0x0)
-#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_BITS _U(0x00000400)
-#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB _U(10)
-#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB _U(10)
+#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET _u(0x0)
+#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_BITS _u(0x00000400)
+#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB _u(10)
+#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB _u(10)
#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL
@@ -42,13 +42,13 @@
// Reset value: 0x0.
// 0x0 -> Overflow when RX_FIFO is full
// 0x1 -> Hold bus when RX_FIFO is full
-#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET _U(0x0)
-#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS _U(0x00000200)
-#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB _U(9)
-#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB _U(9)
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET _u(0x0)
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS _u(0x00000200)
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB _u(9)
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB _u(9)
#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_ACCESS "RW"
-#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_DISABLED _U(0x0)
-#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED _U(0x1)
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_DISABLED _u(0x0)
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CON_TX_EMPTY_CTRL
// Description : This bit controls the generation of the TX_EMPTY interrupt, as
@@ -57,13 +57,13 @@
// Reset value: 0x0.
// 0x0 -> Default behaviour of TX_EMPTY interrupt
// 0x1 -> Controlled generation of TX_EMPTY interrupt
-#define I2C_IC_CON_TX_EMPTY_CTRL_RESET _U(0x0)
-#define I2C_IC_CON_TX_EMPTY_CTRL_BITS _U(0x00000100)
-#define I2C_IC_CON_TX_EMPTY_CTRL_MSB _U(8)
-#define I2C_IC_CON_TX_EMPTY_CTRL_LSB _U(8)
+#define I2C_IC_CON_TX_EMPTY_CTRL_RESET _u(0x0)
+#define I2C_IC_CON_TX_EMPTY_CTRL_BITS _u(0x00000100)
+#define I2C_IC_CON_TX_EMPTY_CTRL_MSB _u(8)
+#define I2C_IC_CON_TX_EMPTY_CTRL_LSB _u(8)
#define I2C_IC_CON_TX_EMPTY_CTRL_ACCESS "RW"
-#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_DISABLED _U(0x0)
-#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED _U(0x1)
+#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_DISABLED _u(0x0)
+#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CON_STOP_DET_IFADDRESSED
// Description : In slave mode: - 1'b1: issues the STOP_DET interrupt only when
@@ -77,13 +77,13 @@
// transmitted address matches the slave address (SAR).
// 0x0 -> slave issues STOP_DET intr always
// 0x1 -> slave issues STOP_DET intr only if addressed
-#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET _U(0x0)
-#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS _U(0x00000080)
-#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB _U(7)
-#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB _U(7)
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET _u(0x0)
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS _u(0x00000080)
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB _u(7)
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB _u(7)
#define I2C_IC_CON_STOP_DET_IFADDRESSED_ACCESS "RW"
-#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_DISABLED _U(0x0)
-#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED _U(0x1)
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_DISABLED _u(0x0)
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CON_IC_SLAVE_DISABLE
// Description : This bit controls whether I2C has its slave disabled, which
@@ -98,13 +98,13 @@
// 0, then bit 0 should also be written with a 0.
// 0x0 -> Slave mode is enabled
// 0x1 -> Slave mode is disabled
-#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET _U(0x1)
-#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS _U(0x00000040)
-#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB _U(6)
-#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB _U(6)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET _u(0x1)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS _u(0x00000040)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB _u(6)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB _u(6)
#define I2C_IC_CON_IC_SLAVE_DISABLE_ACCESS "RW"
-#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED _U(0x0)
-#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_DISABLED _U(0x1)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED _u(0x0)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_DISABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CON_IC_RESTART_EN
// Description : Determines whether RESTART conditions may be sent when acting
@@ -124,13 +124,13 @@
// Reset value: ENABLED
// 0x0 -> Master restart disabled
// 0x1 -> Master restart enabled
-#define I2C_IC_CON_IC_RESTART_EN_RESET _U(0x1)
-#define I2C_IC_CON_IC_RESTART_EN_BITS _U(0x00000020)
-#define I2C_IC_CON_IC_RESTART_EN_MSB _U(5)
-#define I2C_IC_CON_IC_RESTART_EN_LSB _U(5)
+#define I2C_IC_CON_IC_RESTART_EN_RESET _u(0x1)
+#define I2C_IC_CON_IC_RESTART_EN_BITS _u(0x00000020)
+#define I2C_IC_CON_IC_RESTART_EN_MSB _u(5)
+#define I2C_IC_CON_IC_RESTART_EN_LSB _u(5)
#define I2C_IC_CON_IC_RESTART_EN_ACCESS "RW"
-#define I2C_IC_CON_IC_RESTART_EN_VALUE_DISABLED _U(0x0)
-#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED _U(0x1)
+#define I2C_IC_CON_IC_RESTART_EN_VALUE_DISABLED _u(0x0)
+#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CON_IC_10BITADDR_MASTER
// Description : Controls whether the DW_apb_i2c starts its transfers in 7- or
@@ -138,13 +138,13 @@
// addressing - 1: 10-bit addressing
// 0x0 -> Master 7Bit addressing mode
// 0x1 -> Master 10Bit addressing mode
-#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET _U(0x0)
-#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS _U(0x00000010)
-#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB _U(4)
-#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB _U(4)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET _u(0x0)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS _u(0x00000010)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB _u(4)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB _u(4)
#define I2C_IC_CON_IC_10BITADDR_MASTER_ACCESS "RW"
-#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS _U(0x0)
-#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS _U(0x1)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS _u(0x0)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CON_IC_10BITADDR_SLAVE
// Description : When acting as a slave, this bit controls whether the
@@ -156,13 +156,13 @@
// that match the full 10 bits of the IC_SAR register.
// 0x0 -> Slave 7Bit addressing
// 0x1 -> Slave 10Bit addressing
-#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET _U(0x0)
-#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS _U(0x00000008)
-#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB _U(3)
-#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB _U(3)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET _u(0x0)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS _u(0x00000008)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB _u(3)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB _u(3)
#define I2C_IC_CON_IC_10BITADDR_SLAVE_ACCESS "RW"
-#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS _U(0x0)
-#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_10BITS _U(0x1)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS _u(0x0)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_10BITS _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CON_SPEED
// Description : These bits control at which speed the DW_apb_i2c operates; its
@@ -186,14 +186,14 @@
// 0x1 -> Standard Speed mode of operation
// 0x2 -> Fast or Fast Plus mode of operation
// 0x3 -> High Speed mode of operation
-#define I2C_IC_CON_SPEED_RESET _U(0x2)
-#define I2C_IC_CON_SPEED_BITS _U(0x00000006)
-#define I2C_IC_CON_SPEED_MSB _U(2)
-#define I2C_IC_CON_SPEED_LSB _U(1)
+#define I2C_IC_CON_SPEED_RESET _u(0x2)
+#define I2C_IC_CON_SPEED_BITS _u(0x00000006)
+#define I2C_IC_CON_SPEED_MSB _u(2)
+#define I2C_IC_CON_SPEED_LSB _u(1)
#define I2C_IC_CON_SPEED_ACCESS "RW"
-#define I2C_IC_CON_SPEED_VALUE_STANDARD _U(0x1)
-#define I2C_IC_CON_SPEED_VALUE_FAST _U(0x2)
-#define I2C_IC_CON_SPEED_VALUE_HIGH _U(0x3)
+#define I2C_IC_CON_SPEED_VALUE_STANDARD _u(0x1)
+#define I2C_IC_CON_SPEED_VALUE_FAST _u(0x2)
+#define I2C_IC_CON_SPEED_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CON_MASTER_MODE
// Description : This bit controls whether the DW_apb_i2c master is enabled.
@@ -202,13 +202,13 @@
// '1' then bit 6 should also be written with a '1'.
// 0x0 -> Master mode is disabled
// 0x1 -> Master mode is enabled
-#define I2C_IC_CON_MASTER_MODE_RESET _U(0x1)
-#define I2C_IC_CON_MASTER_MODE_BITS _U(0x00000001)
-#define I2C_IC_CON_MASTER_MODE_MSB _U(0)
-#define I2C_IC_CON_MASTER_MODE_LSB _U(0)
+#define I2C_IC_CON_MASTER_MODE_RESET _u(0x1)
+#define I2C_IC_CON_MASTER_MODE_BITS _u(0x00000001)
+#define I2C_IC_CON_MASTER_MODE_MSB _u(0)
+#define I2C_IC_CON_MASTER_MODE_LSB _u(0)
#define I2C_IC_CON_MASTER_MODE_ACCESS "RW"
-#define I2C_IC_CON_MASTER_MODE_VALUE_DISABLED _U(0x0)
-#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED _U(0x1)
+#define I2C_IC_CON_MASTER_MODE_VALUE_DISABLED _u(0x0)
+#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED _u(0x1)
// =============================================================================
// Register : I2C_IC_TAR
// Description : I2C Target Address Register
@@ -223,9 +223,9 @@
// address even while the Tx FIFO has entries (IC_STATUS[2]= 0). -
// It is not necessary to perform any write to this register if
// DW_apb_i2c is enabled as an I2C slave only.
-#define I2C_IC_TAR_OFFSET _U(0x00000004)
-#define I2C_IC_TAR_BITS _U(0x00000fff)
-#define I2C_IC_TAR_RESET _U(0x00000055)
+#define I2C_IC_TAR_OFFSET _u(0x00000004)
+#define I2C_IC_TAR_BITS _u(0x00000fff)
+#define I2C_IC_TAR_RESET _u(0x00000055)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TAR_SPECIAL
// Description : This bit indicates whether software performs a Device-ID or
@@ -237,13 +237,13 @@
// transmission
// 0x1 -> Enables programming of GENERAL_CALL or START_BYTE
// transmission
-#define I2C_IC_TAR_SPECIAL_RESET _U(0x0)
-#define I2C_IC_TAR_SPECIAL_BITS _U(0x00000800)
-#define I2C_IC_TAR_SPECIAL_MSB _U(11)
-#define I2C_IC_TAR_SPECIAL_LSB _U(11)
+#define I2C_IC_TAR_SPECIAL_RESET _u(0x0)
+#define I2C_IC_TAR_SPECIAL_BITS _u(0x00000800)
+#define I2C_IC_TAR_SPECIAL_MSB _u(11)
+#define I2C_IC_TAR_SPECIAL_LSB _u(11)
#define I2C_IC_TAR_SPECIAL_ACCESS "RW"
-#define I2C_IC_TAR_SPECIAL_VALUE_DISABLED _U(0x0)
-#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED _U(0x1)
+#define I2C_IC_TAR_SPECIAL_VALUE_DISABLED _u(0x0)
+#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TAR_GC_OR_START
// Description : If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to
@@ -256,13 +256,13 @@
// value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0
// 0x0 -> GENERAL_CALL byte transmission
// 0x1 -> START byte transmission
-#define I2C_IC_TAR_GC_OR_START_RESET _U(0x0)
-#define I2C_IC_TAR_GC_OR_START_BITS _U(0x00000400)
-#define I2C_IC_TAR_GC_OR_START_MSB _U(10)
-#define I2C_IC_TAR_GC_OR_START_LSB _U(10)
+#define I2C_IC_TAR_GC_OR_START_RESET _u(0x0)
+#define I2C_IC_TAR_GC_OR_START_BITS _u(0x00000400)
+#define I2C_IC_TAR_GC_OR_START_MSB _u(10)
+#define I2C_IC_TAR_GC_OR_START_LSB _u(10)
#define I2C_IC_TAR_GC_OR_START_ACCESS "RW"
-#define I2C_IC_TAR_GC_OR_START_VALUE_GENERAL_CALL _U(0x0)
-#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE _U(0x1)
+#define I2C_IC_TAR_GC_OR_START_VALUE_GENERAL_CALL _u(0x0)
+#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TAR_IC_TAR
// Description : This is the target address for any master transaction. When
@@ -275,17 +275,17 @@
// not feasible. Only one direction loopback mode is supported
// (simplex), not duplex. A master cannot transmit to itself; it
// can transmit to only a slave.
-#define I2C_IC_TAR_IC_TAR_RESET _U(0x055)
-#define I2C_IC_TAR_IC_TAR_BITS _U(0x000003ff)
-#define I2C_IC_TAR_IC_TAR_MSB _U(9)
-#define I2C_IC_TAR_IC_TAR_LSB _U(0)
+#define I2C_IC_TAR_IC_TAR_RESET _u(0x055)
+#define I2C_IC_TAR_IC_TAR_BITS _u(0x000003ff)
+#define I2C_IC_TAR_IC_TAR_MSB _u(9)
+#define I2C_IC_TAR_IC_TAR_LSB _u(0)
#define I2C_IC_TAR_IC_TAR_ACCESS "RW"
// =============================================================================
// Register : I2C_IC_SAR
// Description : I2C Slave Address Register
-#define I2C_IC_SAR_OFFSET _U(0x00000008)
-#define I2C_IC_SAR_BITS _U(0x000003ff)
-#define I2C_IC_SAR_RESET _U(0x00000055)
+#define I2C_IC_SAR_OFFSET _u(0x00000008)
+#define I2C_IC_SAR_BITS _u(0x000003ff)
+#define I2C_IC_SAR_RESET _u(0x00000055)
// -----------------------------------------------------------------------------
// Field : I2C_IC_SAR_IC_SAR
// Description : The IC_SAR holds the slave address when the I2C is operating as
@@ -301,10 +301,10 @@
// IC_SAR or IC_TAR to a reserved value. Refer to
// <<table_I2C_firstbyte_bit_defs>> for a complete list of these
// reserved values.
-#define I2C_IC_SAR_IC_SAR_RESET _U(0x055)
-#define I2C_IC_SAR_IC_SAR_BITS _U(0x000003ff)
-#define I2C_IC_SAR_IC_SAR_MSB _U(9)
-#define I2C_IC_SAR_IC_SAR_LSB _U(0)
+#define I2C_IC_SAR_IC_SAR_RESET _u(0x055)
+#define I2C_IC_SAR_IC_SAR_BITS _u(0x000003ff)
+#define I2C_IC_SAR_IC_SAR_MSB _u(9)
+#define I2C_IC_SAR_IC_SAR_LSB _u(0)
#define I2C_IC_SAR_IC_SAR_ACCESS "RW"
// =============================================================================
// Register : I2C_IC_DATA_CMD
@@ -321,9 +321,9 @@
// to continue acknowledging reads, a read command should be
// written for every byte that is to be received; otherwise the
// DW_apb_i2c will stop acknowledging.
-#define I2C_IC_DATA_CMD_OFFSET _U(0x00000010)
-#define I2C_IC_DATA_CMD_BITS _U(0x00000fff)
-#define I2C_IC_DATA_CMD_RESET _U(0x00000000)
+#define I2C_IC_DATA_CMD_OFFSET _u(0x00000010)
+#define I2C_IC_DATA_CMD_BITS _u(0x00000fff)
+#define I2C_IC_DATA_CMD_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_DATA_CMD_FIRST_DATA_BYTE
// Description : Indicates the first data byte received after the address phase
@@ -347,13 +347,13 @@
// FIRST_DATA_BYTE status.
// 0x0 -> Sequential data byte received
// 0x1 -> Non sequential data byte received
-#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET _U(0x0)
-#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS _U(0x00000800)
-#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB _U(11)
-#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB _U(11)
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET _u(0x0)
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS _u(0x00000800)
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB _u(11)
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB _u(11)
#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_ACCESS "RO"
-#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_DATA_CMD_RESTART
// Description : This bit controls whether a RESTART is issued before the byte
@@ -373,13 +373,13 @@
// Reset value: 0x0
// 0x0 -> Don't Issue RESTART before this command
// 0x1 -> Issue RESTART before this command
-#define I2C_IC_DATA_CMD_RESTART_RESET _U(0x0)
-#define I2C_IC_DATA_CMD_RESTART_BITS _U(0x00000400)
-#define I2C_IC_DATA_CMD_RESTART_MSB _U(10)
-#define I2C_IC_DATA_CMD_RESTART_LSB _U(10)
+#define I2C_IC_DATA_CMD_RESTART_RESET _u(0x0)
+#define I2C_IC_DATA_CMD_RESTART_BITS _u(0x00000400)
+#define I2C_IC_DATA_CMD_RESTART_MSB _u(10)
+#define I2C_IC_DATA_CMD_RESTART_LSB _u(10)
#define I2C_IC_DATA_CMD_RESTART_ACCESS "SC"
-#define I2C_IC_DATA_CMD_RESTART_VALUE_DISABLE _U(0x0)
-#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE _U(0x1)
+#define I2C_IC_DATA_CMD_RESTART_VALUE_DISABLE _u(0x0)
+#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_DATA_CMD_STOP
// Description : This bit controls whether a STOP is issued after the byte is
@@ -397,13 +397,13 @@
// is available in the Tx FIFO. Reset value: 0x0
// 0x0 -> Don't Issue STOP after this command
// 0x1 -> Issue STOP after this command
-#define I2C_IC_DATA_CMD_STOP_RESET _U(0x0)
-#define I2C_IC_DATA_CMD_STOP_BITS _U(0x00000200)
-#define I2C_IC_DATA_CMD_STOP_MSB _U(9)
-#define I2C_IC_DATA_CMD_STOP_LSB _U(9)
+#define I2C_IC_DATA_CMD_STOP_RESET _u(0x0)
+#define I2C_IC_DATA_CMD_STOP_BITS _u(0x00000200)
+#define I2C_IC_DATA_CMD_STOP_MSB _u(9)
+#define I2C_IC_DATA_CMD_STOP_LSB _u(9)
#define I2C_IC_DATA_CMD_STOP_ACCESS "SC"
-#define I2C_IC_DATA_CMD_STOP_VALUE_DISABLE _U(0x0)
-#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE _U(0x1)
+#define I2C_IC_DATA_CMD_STOP_VALUE_DISABLE _u(0x0)
+#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_DATA_CMD_CMD
// Description : This bit controls whether a read or a write is performed. This
@@ -428,13 +428,13 @@
// Reset value: 0x0
// 0x0 -> Master Write Command
// 0x1 -> Master Read Command
-#define I2C_IC_DATA_CMD_CMD_RESET _U(0x0)
-#define I2C_IC_DATA_CMD_CMD_BITS _U(0x00000100)
-#define I2C_IC_DATA_CMD_CMD_MSB _U(8)
-#define I2C_IC_DATA_CMD_CMD_LSB _U(8)
+#define I2C_IC_DATA_CMD_CMD_RESET _u(0x0)
+#define I2C_IC_DATA_CMD_CMD_BITS _u(0x00000100)
+#define I2C_IC_DATA_CMD_CMD_MSB _u(8)
+#define I2C_IC_DATA_CMD_CMD_LSB _u(8)
#define I2C_IC_DATA_CMD_CMD_ACCESS "SC"
-#define I2C_IC_DATA_CMD_CMD_VALUE_WRITE _U(0x0)
-#define I2C_IC_DATA_CMD_CMD_VALUE_READ _U(0x1)
+#define I2C_IC_DATA_CMD_CMD_VALUE_WRITE _u(0x0)
+#define I2C_IC_DATA_CMD_CMD_VALUE_READ _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_DATA_CMD_DAT
// Description : This register contains the data to be transmitted or received
@@ -444,17 +444,17 @@
// value of data received on the DW_apb_i2c interface.
//
// Reset value: 0x0
-#define I2C_IC_DATA_CMD_DAT_RESET _U(0x00)
-#define I2C_IC_DATA_CMD_DAT_BITS _U(0x000000ff)
-#define I2C_IC_DATA_CMD_DAT_MSB _U(7)
-#define I2C_IC_DATA_CMD_DAT_LSB _U(0)
+#define I2C_IC_DATA_CMD_DAT_RESET _u(0x00)
+#define I2C_IC_DATA_CMD_DAT_BITS _u(0x000000ff)
+#define I2C_IC_DATA_CMD_DAT_MSB _u(7)
+#define I2C_IC_DATA_CMD_DAT_LSB _u(0)
#define I2C_IC_DATA_CMD_DAT_ACCESS "RW"
// =============================================================================
// Register : I2C_IC_SS_SCL_HCNT
// Description : Standard Speed I2C Clock SCL High Count Register
-#define I2C_IC_SS_SCL_HCNT_OFFSET _U(0x00000014)
-#define I2C_IC_SS_SCL_HCNT_BITS _U(0x0000ffff)
-#define I2C_IC_SS_SCL_HCNT_RESET _U(0x00000028)
+#define I2C_IC_SS_SCL_HCNT_OFFSET _u(0x00000014)
+#define I2C_IC_SS_SCL_HCNT_BITS _u(0x0000ffff)
+#define I2C_IC_SS_SCL_HCNT_RESET _u(0x00000028)
// -----------------------------------------------------------------------------
// Field : I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT
// Description : This register must be set before any I2C bus transaction can
@@ -477,17 +477,17 @@
// than 65525, because DW_apb_i2c uses a 16-bit counter to flag an
// I2C bus idle condition when this counter reaches a value of
// IC_SS_SCL_HCNT + 10.
-#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET _U(0x0028)
-#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_BITS _U(0x0000ffff)
-#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB _U(15)
-#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB _U(0)
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET _u(0x0028)
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_BITS _u(0x0000ffff)
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB _u(15)
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB _u(0)
#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_ACCESS "RW"
// =============================================================================
// Register : I2C_IC_SS_SCL_LCNT
// Description : Standard Speed I2C Clock SCL Low Count Register
-#define I2C_IC_SS_SCL_LCNT_OFFSET _U(0x00000018)
-#define I2C_IC_SS_SCL_LCNT_BITS _U(0x0000ffff)
-#define I2C_IC_SS_SCL_LCNT_RESET _U(0x0000002f)
+#define I2C_IC_SS_SCL_LCNT_OFFSET _u(0x00000018)
+#define I2C_IC_SS_SCL_LCNT_BITS _u(0x0000ffff)
+#define I2C_IC_SS_SCL_LCNT_RESET _u(0x0000002f)
// -----------------------------------------------------------------------------
// Field : I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT
// Description : This register must be set before any I2C bus transaction can
@@ -505,17 +505,17 @@
// programming is important to ensure the correct operation of
// DW_apb_i2c. The lower byte must be programmed first, and then
// the upper byte is programmed.
-#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET _U(0x002f)
-#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_BITS _U(0x0000ffff)
-#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB _U(15)
-#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB _U(0)
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET _u(0x002f)
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_BITS _u(0x0000ffff)
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB _u(15)
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB _u(0)
#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_ACCESS "RW"
// =============================================================================
// Register : I2C_IC_FS_SCL_HCNT
// Description : Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
-#define I2C_IC_FS_SCL_HCNT_OFFSET _U(0x0000001c)
-#define I2C_IC_FS_SCL_HCNT_BITS _U(0x0000ffff)
-#define I2C_IC_FS_SCL_HCNT_RESET _U(0x00000006)
+#define I2C_IC_FS_SCL_HCNT_OFFSET _u(0x0000001c)
+#define I2C_IC_FS_SCL_HCNT_BITS _u(0x0000ffff)
+#define I2C_IC_FS_SCL_HCNT_RESET _u(0x00000006)
// -----------------------------------------------------------------------------
// Field : I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT
// Description : This register must be set before any I2C bus transaction can
@@ -537,17 +537,17 @@
// programming is important to ensure the correct operation of the
// DW_apb_i2c. The lower byte must be programmed first. Then the
// upper byte is programmed.
-#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET _U(0x0006)
-#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS _U(0x0000ffff)
-#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB _U(15)
-#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB _U(0)
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET _u(0x0006)
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS _u(0x0000ffff)
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB _u(15)
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB _u(0)
#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_ACCESS "RW"
// =============================================================================
// Register : I2C_IC_FS_SCL_LCNT
// Description : Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
-#define I2C_IC_FS_SCL_LCNT_OFFSET _U(0x00000020)
-#define I2C_IC_FS_SCL_LCNT_BITS _U(0x0000ffff)
-#define I2C_IC_FS_SCL_LCNT_RESET _U(0x0000000d)
+#define I2C_IC_FS_SCL_LCNT_OFFSET _u(0x00000020)
+#define I2C_IC_FS_SCL_LCNT_BITS _u(0x0000ffff)
+#define I2C_IC_FS_SCL_LCNT_RESET _u(0x0000000d)
// -----------------------------------------------------------------------------
// Field : I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT
// Description : This register must be set before any I2C bus transaction can
@@ -571,10 +571,10 @@
// DW_apb_i2c. The lower byte must be programmed first. Then the
// upper byte is programmed. If the value is less than 8 then the
// count value gets changed to 8.
-#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET _U(0x000d)
-#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS _U(0x0000ffff)
-#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB _U(15)
-#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB _U(0)
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET _u(0x000d)
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS _u(0x0000ffff)
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB _u(15)
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB _u(0)
#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_ACCESS "RW"
// =============================================================================
// Register : I2C_IC_INTR_STAT
@@ -584,9 +584,9 @@
// IC_INTR_MASK register. These bits are cleared by reading the
// matching interrupt clear register. The unmasked raw versions of
// these bits are available in the IC_RAW_INTR_STAT register.
-#define I2C_IC_INTR_STAT_OFFSET _U(0x0000002c)
-#define I2C_IC_INTR_STAT_BITS _U(0x00003fff)
-#define I2C_IC_INTR_STAT_RESET _U(0x00000000)
+#define I2C_IC_INTR_STAT_OFFSET _u(0x0000002c)
+#define I2C_IC_INTR_STAT_BITS _u(0x00003fff)
+#define I2C_IC_INTR_STAT_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_STAT_R_MASTER_ON_HOLD
// Description : See IC_RAW_INTR_STAT for a detailed description of
@@ -595,13 +595,13 @@
// Reset value: 0x0
// 0x0 -> R_MASTER_ON_HOLD interrupt is inactive
// 0x1 -> R_MASTER_ON_HOLD interrupt is active
-#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_RESET _U(0x0)
-#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_BITS _U(0x00002000)
-#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_MSB _U(13)
-#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_LSB _U(13)
+#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_BITS _u(0x00002000)
+#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_MSB _u(13)
+#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_LSB _u(13)
#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_ACCESS "RO"
-#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_STAT_R_RESTART_DET
// Description : See IC_RAW_INTR_STAT for a detailed description of
@@ -610,13 +610,13 @@
// Reset value: 0x0
// 0x0 -> R_RESTART_DET interrupt is inactive
// 0x1 -> R_RESTART_DET interrupt is active
-#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET _U(0x0)
-#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS _U(0x00001000)
-#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB _U(12)
-#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB _U(12)
+#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS _u(0x00001000)
+#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB _u(12)
+#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB _u(12)
#define I2C_IC_INTR_STAT_R_RESTART_DET_ACCESS "RO"
-#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_STAT_R_GEN_CALL
// Description : See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL
@@ -625,13 +625,13 @@
// Reset value: 0x0
// 0x0 -> R_GEN_CALL interrupt is inactive
// 0x1 -> R_GEN_CALL interrupt is active
-#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET _U(0x0)
-#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS _U(0x00000800)
-#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB _U(11)
-#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB _U(11)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS _u(0x00000800)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB _u(11)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB _u(11)
#define I2C_IC_INTR_STAT_R_GEN_CALL_ACCESS "RO"
-#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_STAT_R_START_DET
// Description : See IC_RAW_INTR_STAT for a detailed description of R_START_DET
@@ -640,13 +640,13 @@
// Reset value: 0x0
// 0x0 -> R_START_DET interrupt is inactive
// 0x1 -> R_START_DET interrupt is active
-#define I2C_IC_INTR_STAT_R_START_DET_RESET _U(0x0)
-#define I2C_IC_INTR_STAT_R_START_DET_BITS _U(0x00000400)
-#define I2C_IC_INTR_STAT_R_START_DET_MSB _U(10)
-#define I2C_IC_INTR_STAT_R_START_DET_LSB _U(10)
+#define I2C_IC_INTR_STAT_R_START_DET_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_START_DET_BITS _u(0x00000400)
+#define I2C_IC_INTR_STAT_R_START_DET_MSB _u(10)
+#define I2C_IC_INTR_STAT_R_START_DET_LSB _u(10)
#define I2C_IC_INTR_STAT_R_START_DET_ACCESS "RO"
-#define I2C_IC_INTR_STAT_R_START_DET_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_INTR_STAT_R_START_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_STAT_R_STOP_DET
// Description : See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET
@@ -655,13 +655,13 @@
// Reset value: 0x0
// 0x0 -> R_STOP_DET interrupt is inactive
// 0x1 -> R_STOP_DET interrupt is active
-#define I2C_IC_INTR_STAT_R_STOP_DET_RESET _U(0x0)
-#define I2C_IC_INTR_STAT_R_STOP_DET_BITS _U(0x00000200)
-#define I2C_IC_INTR_STAT_R_STOP_DET_MSB _U(9)
-#define I2C_IC_INTR_STAT_R_STOP_DET_LSB _U(9)
+#define I2C_IC_INTR_STAT_R_STOP_DET_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_STOP_DET_BITS _u(0x00000200)
+#define I2C_IC_INTR_STAT_R_STOP_DET_MSB _u(9)
+#define I2C_IC_INTR_STAT_R_STOP_DET_LSB _u(9)
#define I2C_IC_INTR_STAT_R_STOP_DET_ACCESS "RO"
-#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_STAT_R_ACTIVITY
// Description : See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY
@@ -670,13 +670,13 @@
// Reset value: 0x0
// 0x0 -> R_ACTIVITY interrupt is inactive
// 0x1 -> R_ACTIVITY interrupt is active
-#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET _U(0x0)
-#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS _U(0x00000100)
-#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB _U(8)
-#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB _U(8)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS _u(0x00000100)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB _u(8)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB _u(8)
#define I2C_IC_INTR_STAT_R_ACTIVITY_ACCESS "RO"
-#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_STAT_R_RX_DONE
// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE
@@ -685,13 +685,13 @@
// Reset value: 0x0
// 0x0 -> R_RX_DONE interrupt is inactive
// 0x1 -> R_RX_DONE interrupt is active
-#define I2C_IC_INTR_STAT_R_RX_DONE_RESET _U(0x0)
-#define I2C_IC_INTR_STAT_R_RX_DONE_BITS _U(0x00000080)
-#define I2C_IC_INTR_STAT_R_RX_DONE_MSB _U(7)
-#define I2C_IC_INTR_STAT_R_RX_DONE_LSB _U(7)
+#define I2C_IC_INTR_STAT_R_RX_DONE_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_DONE_BITS _u(0x00000080)
+#define I2C_IC_INTR_STAT_R_RX_DONE_MSB _u(7)
+#define I2C_IC_INTR_STAT_R_RX_DONE_LSB _u(7)
#define I2C_IC_INTR_STAT_R_RX_DONE_ACCESS "RO"
-#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_STAT_R_TX_ABRT
// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT
@@ -700,13 +700,13 @@
// Reset value: 0x0
// 0x0 -> R_TX_ABRT interrupt is inactive
// 0x1 -> R_TX_ABRT interrupt is active
-#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET _U(0x0)
-#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS _U(0x00000040)
-#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB _U(6)
-#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB _U(6)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS _u(0x00000040)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB _u(6)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB _u(6)
#define I2C_IC_INTR_STAT_R_TX_ABRT_ACCESS "RO"
-#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_STAT_R_RD_REQ
// Description : See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ
@@ -715,13 +715,13 @@
// Reset value: 0x0
// 0x0 -> R_RD_REQ interrupt is inactive
// 0x1 -> R_RD_REQ interrupt is active
-#define I2C_IC_INTR_STAT_R_RD_REQ_RESET _U(0x0)
-#define I2C_IC_INTR_STAT_R_RD_REQ_BITS _U(0x00000020)
-#define I2C_IC_INTR_STAT_R_RD_REQ_MSB _U(5)
-#define I2C_IC_INTR_STAT_R_RD_REQ_LSB _U(5)
+#define I2C_IC_INTR_STAT_R_RD_REQ_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_RD_REQ_BITS _u(0x00000020)
+#define I2C_IC_INTR_STAT_R_RD_REQ_MSB _u(5)
+#define I2C_IC_INTR_STAT_R_RD_REQ_LSB _u(5)
#define I2C_IC_INTR_STAT_R_RD_REQ_ACCESS "RO"
-#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_STAT_R_TX_EMPTY
// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY
@@ -730,13 +730,13 @@
// Reset value: 0x0
// 0x0 -> R_TX_EMPTY interrupt is inactive
// 0x1 -> R_TX_EMPTY interrupt is active
-#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET _U(0x0)
-#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS _U(0x00000010)
-#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB _U(4)
-#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB _U(4)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS _u(0x00000010)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB _u(4)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB _u(4)
#define I2C_IC_INTR_STAT_R_TX_EMPTY_ACCESS "RO"
-#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_STAT_R_TX_OVER
// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER
@@ -745,13 +745,13 @@
// Reset value: 0x0
// 0x0 -> R_TX_OVER interrupt is inactive
// 0x1 -> R_TX_OVER interrupt is active
-#define I2C_IC_INTR_STAT_R_TX_OVER_RESET _U(0x0)
-#define I2C_IC_INTR_STAT_R_TX_OVER_BITS _U(0x00000008)
-#define I2C_IC_INTR_STAT_R_TX_OVER_MSB _U(3)
-#define I2C_IC_INTR_STAT_R_TX_OVER_LSB _U(3)
+#define I2C_IC_INTR_STAT_R_TX_OVER_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_OVER_BITS _u(0x00000008)
+#define I2C_IC_INTR_STAT_R_TX_OVER_MSB _u(3)
+#define I2C_IC_INTR_STAT_R_TX_OVER_LSB _u(3)
#define I2C_IC_INTR_STAT_R_TX_OVER_ACCESS "RO"
-#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_STAT_R_RX_FULL
// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL
@@ -760,13 +760,13 @@
// Reset value: 0x0
// 0x0 -> R_RX_FULL interrupt is inactive
// 0x1 -> R_RX_FULL interrupt is active
-#define I2C_IC_INTR_STAT_R_RX_FULL_RESET _U(0x0)
-#define I2C_IC_INTR_STAT_R_RX_FULL_BITS _U(0x00000004)
-#define I2C_IC_INTR_STAT_R_RX_FULL_MSB _U(2)
-#define I2C_IC_INTR_STAT_R_RX_FULL_LSB _U(2)
+#define I2C_IC_INTR_STAT_R_RX_FULL_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_FULL_BITS _u(0x00000004)
+#define I2C_IC_INTR_STAT_R_RX_FULL_MSB _u(2)
+#define I2C_IC_INTR_STAT_R_RX_FULL_LSB _u(2)
#define I2C_IC_INTR_STAT_R_RX_FULL_ACCESS "RO"
-#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_STAT_R_RX_OVER
// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER
@@ -775,13 +775,13 @@
// Reset value: 0x0
// 0x0 -> R_RX_OVER interrupt is inactive
// 0x1 -> R_RX_OVER interrupt is active
-#define I2C_IC_INTR_STAT_R_RX_OVER_RESET _U(0x0)
-#define I2C_IC_INTR_STAT_R_RX_OVER_BITS _U(0x00000002)
-#define I2C_IC_INTR_STAT_R_RX_OVER_MSB _U(1)
-#define I2C_IC_INTR_STAT_R_RX_OVER_LSB _U(1)
+#define I2C_IC_INTR_STAT_R_RX_OVER_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_OVER_BITS _u(0x00000002)
+#define I2C_IC_INTR_STAT_R_RX_OVER_MSB _u(1)
+#define I2C_IC_INTR_STAT_R_RX_OVER_LSB _u(1)
#define I2C_IC_INTR_STAT_R_RX_OVER_ACCESS "RO"
-#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_STAT_R_RX_UNDER
// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER
@@ -790,13 +790,13 @@
// Reset value: 0x0
// 0x0 -> RX_UNDER interrupt is inactive
// 0x1 -> RX_UNDER interrupt is active
-#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET _U(0x0)
-#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS _U(0x00000001)
-#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB _U(0)
-#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB _U(0)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS _u(0x00000001)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB _u(0)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB _u(0)
#define I2C_IC_INTR_STAT_R_RX_UNDER_ACCESS "RO"
-#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE _u(0x1)
// =============================================================================
// Register : I2C_IC_INTR_MASK
// Description : I2C Interrupt Mask Register.
@@ -804,9 +804,9 @@
// These bits mask their corresponding interrupt status bits. This
// register is active low; a value of 0 masks the interrupt,
// whereas a value of 1 unmasks the interrupt.
-#define I2C_IC_INTR_MASK_OFFSET _U(0x00000030)
-#define I2C_IC_INTR_MASK_BITS _U(0x00003fff)
-#define I2C_IC_INTR_MASK_RESET _U(0x000008ff)
+#define I2C_IC_INTR_MASK_OFFSET _u(0x00000030)
+#define I2C_IC_INTR_MASK_BITS _u(0x00003fff)
+#define I2C_IC_INTR_MASK_RESET _u(0x000008ff)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY
// Description : This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD
@@ -815,13 +815,13 @@
// Reset value: 0x0
// 0x0 -> MASTER_ON_HOLD interrupt is masked
// 0x1 -> MASTER_ON_HOLD interrupt is unmasked
-#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_RESET _U(0x0)
-#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_BITS _U(0x00002000)
-#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_MSB _U(13)
-#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_LSB _U(13)
+#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_RESET _u(0x0)
+#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_BITS _u(0x00002000)
+#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_MSB _u(13)
+#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_LSB _u(13)
#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_ACCESS "RO"
-#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_VALUE_ENABLED _U(0x0)
-#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_VALUE_DISABLED _U(0x1)
+#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_VALUE_DISABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_MASK_M_RESTART_DET
// Description : This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT
@@ -830,13 +830,13 @@
// Reset value: 0x0
// 0x0 -> RESTART_DET interrupt is masked
// 0x1 -> RESTART_DET interrupt is unmasked
-#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET _U(0x0)
-#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS _U(0x00001000)
-#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB _U(12)
-#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB _U(12)
+#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET _u(0x0)
+#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS _u(0x00001000)
+#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB _u(12)
+#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB _u(12)
#define I2C_IC_INTR_MASK_M_RESTART_DET_ACCESS "RW"
-#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED _U(0x0)
-#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_DISABLED _U(0x1)
+#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_DISABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_MASK_M_GEN_CALL
// Description : This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT
@@ -845,13 +845,13 @@
// Reset value: 0x1
// 0x0 -> GEN_CALL interrupt is masked
// 0x1 -> GEN_CALL interrupt is unmasked
-#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET _U(0x1)
-#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS _U(0x00000800)
-#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB _U(11)
-#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB _U(11)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS _u(0x00000800)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB _u(11)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB _u(11)
#define I2C_IC_INTR_MASK_M_GEN_CALL_ACCESS "RW"
-#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED _U(0x0)
-#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_DISABLED _U(0x1)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_DISABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_MASK_M_START_DET
// Description : This bit masks the R_START_DET interrupt in IC_INTR_STAT
@@ -860,13 +860,13 @@
// Reset value: 0x0
// 0x0 -> START_DET interrupt is masked
// 0x1 -> START_DET interrupt is unmasked
-#define I2C_IC_INTR_MASK_M_START_DET_RESET _U(0x0)
-#define I2C_IC_INTR_MASK_M_START_DET_BITS _U(0x00000400)
-#define I2C_IC_INTR_MASK_M_START_DET_MSB _U(10)
-#define I2C_IC_INTR_MASK_M_START_DET_LSB _U(10)
+#define I2C_IC_INTR_MASK_M_START_DET_RESET _u(0x0)
+#define I2C_IC_INTR_MASK_M_START_DET_BITS _u(0x00000400)
+#define I2C_IC_INTR_MASK_M_START_DET_MSB _u(10)
+#define I2C_IC_INTR_MASK_M_START_DET_LSB _u(10)
#define I2C_IC_INTR_MASK_M_START_DET_ACCESS "RW"
-#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED _U(0x0)
-#define I2C_IC_INTR_MASK_M_START_DET_VALUE_DISABLED _U(0x1)
+#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_START_DET_VALUE_DISABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_MASK_M_STOP_DET
// Description : This bit masks the R_STOP_DET interrupt in IC_INTR_STAT
@@ -875,13 +875,13 @@
// Reset value: 0x0
// 0x0 -> STOP_DET interrupt is masked
// 0x1 -> STOP_DET interrupt is unmasked
-#define I2C_IC_INTR_MASK_M_STOP_DET_RESET _U(0x0)
-#define I2C_IC_INTR_MASK_M_STOP_DET_BITS _U(0x00000200)
-#define I2C_IC_INTR_MASK_M_STOP_DET_MSB _U(9)
-#define I2C_IC_INTR_MASK_M_STOP_DET_LSB _U(9)
+#define I2C_IC_INTR_MASK_M_STOP_DET_RESET _u(0x0)
+#define I2C_IC_INTR_MASK_M_STOP_DET_BITS _u(0x00000200)
+#define I2C_IC_INTR_MASK_M_STOP_DET_MSB _u(9)
+#define I2C_IC_INTR_MASK_M_STOP_DET_LSB _u(9)
#define I2C_IC_INTR_MASK_M_STOP_DET_ACCESS "RW"
-#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED _U(0x0)
-#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_DISABLED _U(0x1)
+#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_DISABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_MASK_M_ACTIVITY
// Description : This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT
@@ -890,13 +890,13 @@
// Reset value: 0x0
// 0x0 -> ACTIVITY interrupt is masked
// 0x1 -> ACTIVITY interrupt is unmasked
-#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET _U(0x0)
-#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS _U(0x00000100)
-#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB _U(8)
-#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB _U(8)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET _u(0x0)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS _u(0x00000100)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB _u(8)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB _u(8)
#define I2C_IC_INTR_MASK_M_ACTIVITY_ACCESS "RW"
-#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED _U(0x0)
-#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_DISABLED _U(0x1)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_DISABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_MASK_M_RX_DONE
// Description : This bit masks the R_RX_DONE interrupt in IC_INTR_STAT
@@ -905,13 +905,13 @@
// Reset value: 0x1
// 0x0 -> RX_DONE interrupt is masked
// 0x1 -> RX_DONE interrupt is unmasked
-#define I2C_IC_INTR_MASK_M_RX_DONE_RESET _U(0x1)
-#define I2C_IC_INTR_MASK_M_RX_DONE_BITS _U(0x00000080)
-#define I2C_IC_INTR_MASK_M_RX_DONE_MSB _U(7)
-#define I2C_IC_INTR_MASK_M_RX_DONE_LSB _U(7)
+#define I2C_IC_INTR_MASK_M_RX_DONE_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_RX_DONE_BITS _u(0x00000080)
+#define I2C_IC_INTR_MASK_M_RX_DONE_MSB _u(7)
+#define I2C_IC_INTR_MASK_M_RX_DONE_LSB _u(7)
#define I2C_IC_INTR_MASK_M_RX_DONE_ACCESS "RW"
-#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED _U(0x0)
-#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_DISABLED _U(0x1)
+#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_DISABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_MASK_M_TX_ABRT
// Description : This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT
@@ -920,13 +920,13 @@
// Reset value: 0x1
// 0x0 -> TX_ABORT interrupt is masked
// 0x1 -> TX_ABORT interrupt is unmasked
-#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET _U(0x1)
-#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS _U(0x00000040)
-#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB _U(6)
-#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB _U(6)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS _u(0x00000040)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB _u(6)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB _u(6)
#define I2C_IC_INTR_MASK_M_TX_ABRT_ACCESS "RW"
-#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED _U(0x0)
-#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_DISABLED _U(0x1)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_DISABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_MASK_M_RD_REQ
// Description : This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.
@@ -934,13 +934,13 @@
// Reset value: 0x1
// 0x0 -> RD_REQ interrupt is masked
// 0x1 -> RD_REQ interrupt is unmasked
-#define I2C_IC_INTR_MASK_M_RD_REQ_RESET _U(0x1)
-#define I2C_IC_INTR_MASK_M_RD_REQ_BITS _U(0x00000020)
-#define I2C_IC_INTR_MASK_M_RD_REQ_MSB _U(5)
-#define I2C_IC_INTR_MASK_M_RD_REQ_LSB _U(5)
+#define I2C_IC_INTR_MASK_M_RD_REQ_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_RD_REQ_BITS _u(0x00000020)
+#define I2C_IC_INTR_MASK_M_RD_REQ_MSB _u(5)
+#define I2C_IC_INTR_MASK_M_RD_REQ_LSB _u(5)
#define I2C_IC_INTR_MASK_M_RD_REQ_ACCESS "RW"
-#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED _U(0x0)
-#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_DISABLED _U(0x1)
+#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_DISABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_MASK_M_TX_EMPTY
// Description : This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT
@@ -949,13 +949,13 @@
// Reset value: 0x1
// 0x0 -> TX_EMPTY interrupt is masked
// 0x1 -> TX_EMPTY interrupt is unmasked
-#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET _U(0x1)
-#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS _U(0x00000010)
-#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB _U(4)
-#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB _U(4)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS _u(0x00000010)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB _u(4)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB _u(4)
#define I2C_IC_INTR_MASK_M_TX_EMPTY_ACCESS "RW"
-#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED _U(0x0)
-#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_DISABLED _U(0x1)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_DISABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_MASK_M_TX_OVER
// Description : This bit masks the R_TX_OVER interrupt in IC_INTR_STAT
@@ -964,13 +964,13 @@
// Reset value: 0x1
// 0x0 -> TX_OVER interrupt is masked
// 0x1 -> TX_OVER interrupt is unmasked
-#define I2C_IC_INTR_MASK_M_TX_OVER_RESET _U(0x1)
-#define I2C_IC_INTR_MASK_M_TX_OVER_BITS _U(0x00000008)
-#define I2C_IC_INTR_MASK_M_TX_OVER_MSB _U(3)
-#define I2C_IC_INTR_MASK_M_TX_OVER_LSB _U(3)
+#define I2C_IC_INTR_MASK_M_TX_OVER_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_TX_OVER_BITS _u(0x00000008)
+#define I2C_IC_INTR_MASK_M_TX_OVER_MSB _u(3)
+#define I2C_IC_INTR_MASK_M_TX_OVER_LSB _u(3)
#define I2C_IC_INTR_MASK_M_TX_OVER_ACCESS "RW"
-#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED _U(0x0)
-#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_DISABLED _U(0x1)
+#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_DISABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_MASK_M_RX_FULL
// Description : This bit masks the R_RX_FULL interrupt in IC_INTR_STAT
@@ -979,13 +979,13 @@
// Reset value: 0x1
// 0x0 -> RX_FULL interrupt is masked
// 0x1 -> RX_FULL interrupt is unmasked
-#define I2C_IC_INTR_MASK_M_RX_FULL_RESET _U(0x1)
-#define I2C_IC_INTR_MASK_M_RX_FULL_BITS _U(0x00000004)
-#define I2C_IC_INTR_MASK_M_RX_FULL_MSB _U(2)
-#define I2C_IC_INTR_MASK_M_RX_FULL_LSB _U(2)
+#define I2C_IC_INTR_MASK_M_RX_FULL_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_RX_FULL_BITS _u(0x00000004)
+#define I2C_IC_INTR_MASK_M_RX_FULL_MSB _u(2)
+#define I2C_IC_INTR_MASK_M_RX_FULL_LSB _u(2)
#define I2C_IC_INTR_MASK_M_RX_FULL_ACCESS "RW"
-#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED _U(0x0)
-#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_DISABLED _U(0x1)
+#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_DISABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_MASK_M_RX_OVER
// Description : This bit masks the R_RX_OVER interrupt in IC_INTR_STAT
@@ -994,13 +994,13 @@
// Reset value: 0x1
// 0x0 -> RX_OVER interrupt is masked
// 0x1 -> RX_OVER interrupt is unmasked
-#define I2C_IC_INTR_MASK_M_RX_OVER_RESET _U(0x1)
-#define I2C_IC_INTR_MASK_M_RX_OVER_BITS _U(0x00000002)
-#define I2C_IC_INTR_MASK_M_RX_OVER_MSB _U(1)
-#define I2C_IC_INTR_MASK_M_RX_OVER_LSB _U(1)
+#define I2C_IC_INTR_MASK_M_RX_OVER_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_RX_OVER_BITS _u(0x00000002)
+#define I2C_IC_INTR_MASK_M_RX_OVER_MSB _u(1)
+#define I2C_IC_INTR_MASK_M_RX_OVER_LSB _u(1)
#define I2C_IC_INTR_MASK_M_RX_OVER_ACCESS "RW"
-#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED _U(0x0)
-#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_DISABLED _U(0x1)
+#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_DISABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_INTR_MASK_M_RX_UNDER
// Description : This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT
@@ -1009,22 +1009,22 @@
// Reset value: 0x1
// 0x0 -> RX_UNDER interrupt is masked
// 0x1 -> RX_UNDER interrupt is unmasked
-#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET _U(0x1)
-#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS _U(0x00000001)
-#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB _U(0)
-#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB _U(0)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS _u(0x00000001)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB _u(0)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB _u(0)
#define I2C_IC_INTR_MASK_M_RX_UNDER_ACCESS "RW"
-#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED _U(0x0)
-#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_DISABLED _U(0x1)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_DISABLED _u(0x1)
// =============================================================================
// Register : I2C_IC_RAW_INTR_STAT
// Description : I2C Raw Interrupt Status Register
//
// Unlike the IC_INTR_STAT register, these bits are not masked so
// they always show the true status of the DW_apb_i2c.
-#define I2C_IC_RAW_INTR_STAT_OFFSET _U(0x00000034)
-#define I2C_IC_RAW_INTR_STAT_BITS _U(0x00003fff)
-#define I2C_IC_RAW_INTR_STAT_RESET _U(0x00000000)
+#define I2C_IC_RAW_INTR_STAT_OFFSET _u(0x00000034)
+#define I2C_IC_RAW_INTR_STAT_BITS _u(0x00003fff)
+#define I2C_IC_RAW_INTR_STAT_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD
// Description : Indicates whether master is holding the bus and TX FIFO is
@@ -1034,13 +1034,13 @@
// Reset value: 0x0
// 0x0 -> MASTER_ON_HOLD interrupt is inactive
// 0x1 -> MASTER_ON_HOLD interrupt is active
-#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_RESET _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_BITS _U(0x00002000)
-#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_MSB _U(13)
-#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_LSB _U(13)
+#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_BITS _u(0x00002000)
+#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_MSB _u(13)
+#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_LSB _u(13)
#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_ACCESS "RO"
-#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_RAW_INTR_STAT_RESTART_DET
// Description : Indicates whether a RESTART condition has occurred on the I2C
@@ -1057,13 +1057,13 @@
// Reset value: 0x0
// 0x0 -> RESTART_DET interrupt is inactive
// 0x1 -> RESTART_DET interrupt is active
-#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS _U(0x00001000)
-#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB _U(12)
-#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB _U(12)
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS _u(0x00001000)
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB _u(12)
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB _u(12)
#define I2C_IC_RAW_INTR_STAT_RESTART_DET_ACCESS "RO"
-#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_RAW_INTR_STAT_GEN_CALL
// Description : Set only when a General Call address is received and it is
@@ -1075,13 +1075,13 @@
// Reset value: 0x0
// 0x0 -> GEN_CALL interrupt is inactive
// 0x1 -> GEN_CALL interrupt is active
-#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS _U(0x00000800)
-#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB _U(11)
-#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB _U(11)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS _u(0x00000800)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB _u(11)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB _u(11)
#define I2C_IC_RAW_INTR_STAT_GEN_CALL_ACCESS "RO"
-#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_RAW_INTR_STAT_START_DET
// Description : Indicates whether a START or RESTART condition has occurred on
@@ -1091,13 +1091,13 @@
// Reset value: 0x0
// 0x0 -> START_DET interrupt is inactive
// 0x1 -> START_DET interrupt is active
-#define I2C_IC_RAW_INTR_STAT_START_DET_RESET _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_START_DET_BITS _U(0x00000400)
-#define I2C_IC_RAW_INTR_STAT_START_DET_MSB _U(10)
-#define I2C_IC_RAW_INTR_STAT_START_DET_LSB _U(10)
+#define I2C_IC_RAW_INTR_STAT_START_DET_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_START_DET_BITS _u(0x00000400)
+#define I2C_IC_RAW_INTR_STAT_START_DET_MSB _u(10)
+#define I2C_IC_RAW_INTR_STAT_START_DET_LSB _u(10)
#define I2C_IC_RAW_INTR_STAT_START_DET_ACCESS "RO"
-#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_RAW_INTR_STAT_STOP_DET
// Description : Indicates whether a STOP condition has occurred on the I2C
@@ -1120,13 +1120,13 @@
// Reset value: 0x0
// 0x0 -> STOP_DET interrupt is inactive
// 0x1 -> STOP_DET interrupt is active
-#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS _U(0x00000200)
-#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB _U(9)
-#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB _U(9)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS _u(0x00000200)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB _u(9)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB _u(9)
#define I2C_IC_RAW_INTR_STAT_STOP_DET_ACCESS "RO"
-#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_RAW_INTR_STAT_ACTIVITY
// Description : This bit captures DW_apb_i2c activity and stays set until it is
@@ -1140,13 +1140,13 @@
// Reset value: 0x0
// 0x0 -> RAW_INTR_ACTIVITY interrupt is inactive
// 0x1 -> RAW_INTR_ACTIVITY interrupt is active
-#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS _U(0x00000100)
-#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB _U(8)
-#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB _U(8)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS _u(0x00000100)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB _u(8)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB _u(8)
#define I2C_IC_RAW_INTR_STAT_ACTIVITY_ACCESS "RO"
-#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_RAW_INTR_STAT_RX_DONE
// Description : When the DW_apb_i2c is acting as a slave-transmitter, this bit
@@ -1157,13 +1157,13 @@
// Reset value: 0x0
// 0x0 -> RX_DONE interrupt is inactive
// 0x1 -> RX_DONE interrupt is active
-#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS _U(0x00000080)
-#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB _U(7)
-#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB _U(7)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS _u(0x00000080)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB _u(7)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB _u(7)
#define I2C_IC_RAW_INTR_STAT_RX_DONE_ACCESS "RO"
-#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_RAW_INTR_STAT_TX_ABRT
// Description : This bit indicates if DW_apb_i2c, as an I2C transmitter, is
@@ -1183,13 +1183,13 @@
// Reset value: 0x0
// 0x0 -> TX_ABRT interrupt is inactive
// 0x1 -> TX_ABRT interrupt is active
-#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS _U(0x00000040)
-#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB _U(6)
-#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB _U(6)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS _u(0x00000040)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB _u(6)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB _u(6)
#define I2C_IC_RAW_INTR_STAT_TX_ABRT_ACCESS "RO"
-#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_RAW_INTR_STAT_RD_REQ
// Description : This bit is set to 1 when DW_apb_i2c is acting as a slave and
@@ -1205,13 +1205,13 @@
// Reset value: 0x0
// 0x0 -> RD_REQ interrupt is inactive
// 0x1 -> RD_REQ interrupt is active
-#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS _U(0x00000020)
-#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB _U(5)
-#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB _U(5)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS _u(0x00000020)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB _u(5)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB _u(5)
#define I2C_IC_RAW_INTR_STAT_RD_REQ_ACCESS "RO"
-#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_RAW_INTR_STAT_TX_EMPTY
// Description : The behavior of the TX_EMPTY interrupt status differs based on
@@ -1233,13 +1233,13 @@
// Reset value: 0x0.
// 0x0 -> TX_EMPTY interrupt is inactive
// 0x1 -> TX_EMPTY interrupt is active
-#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS _U(0x00000010)
-#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB _U(4)
-#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB _U(4)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS _u(0x00000010)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB _u(4)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB _u(4)
#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_ACCESS "RO"
-#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_RAW_INTR_STAT_TX_OVER
// Description : Set during transmit if the transmit buffer is filled to
@@ -1252,13 +1252,13 @@
// Reset value: 0x0
// 0x0 -> TX_OVER interrupt is inactive
// 0x1 -> TX_OVER interrupt is active
-#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS _U(0x00000008)
-#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB _U(3)
-#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB _U(3)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS _u(0x00000008)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB _u(3)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB _u(3)
#define I2C_IC_RAW_INTR_STAT_TX_OVER_ACCESS "RO"
-#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_RAW_INTR_STAT_RX_FULL
// Description : Set when the receive buffer reaches or goes above the RX_TL
@@ -1272,13 +1272,13 @@
// Reset value: 0x0
// 0x0 -> RX_FULL interrupt is inactive
// 0x1 -> RX_FULL interrupt is active
-#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS _U(0x00000004)
-#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB _U(2)
-#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB _U(2)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS _u(0x00000004)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB _u(2)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB _u(2)
#define I2C_IC_RAW_INTR_STAT_RX_FULL_ACCESS "RO"
-#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_RAW_INTR_STAT_RX_OVER
// Description : Set if the receive buffer is completely filled to
@@ -1296,13 +1296,13 @@
// Reset value: 0x0
// 0x0 -> RX_OVER interrupt is inactive
// 0x1 -> RX_OVER interrupt is active
-#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS _U(0x00000002)
-#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB _U(1)
-#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB _U(1)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS _u(0x00000002)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB _u(1)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB _u(1)
#define I2C_IC_RAW_INTR_STAT_RX_OVER_ACCESS "RO"
-#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_RAW_INTR_STAT_RX_UNDER
// Description : Set if the processor attempts to read the receive buffer when
@@ -1314,19 +1314,19 @@
// Reset value: 0x0
// 0x0 -> RX_UNDER interrupt is inactive
// 0x1 -> RX_UNDER interrupt is active
-#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS _U(0x00000001)
-#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB _U(0)
-#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB _U(0)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS _u(0x00000001)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB _u(0)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB _u(0)
#define I2C_IC_RAW_INTR_STAT_RX_UNDER_ACCESS "RO"
-#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE _u(0x1)
// =============================================================================
// Register : I2C_IC_RX_TL
// Description : I2C Receive FIFO Threshold Register
-#define I2C_IC_RX_TL_OFFSET _U(0x00000038)
-#define I2C_IC_RX_TL_BITS _U(0x000000ff)
-#define I2C_IC_RX_TL_RESET _U(0x00000000)
+#define I2C_IC_RX_TL_OFFSET _u(0x00000038)
+#define I2C_IC_RX_TL_BITS _u(0x000000ff)
+#define I2C_IC_RX_TL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_RX_TL_RX_TL
// Description : Receive FIFO Threshold Level.
@@ -1339,17 +1339,17 @@
// the actual value set will be the maximum depth of the buffer. A
// value of 0 sets the threshold for 1 entry, and a value of 255
// sets the threshold for 256 entries.
-#define I2C_IC_RX_TL_RX_TL_RESET _U(0x00)
-#define I2C_IC_RX_TL_RX_TL_BITS _U(0x000000ff)
-#define I2C_IC_RX_TL_RX_TL_MSB _U(7)
-#define I2C_IC_RX_TL_RX_TL_LSB _U(0)
+#define I2C_IC_RX_TL_RX_TL_RESET _u(0x00)
+#define I2C_IC_RX_TL_RX_TL_BITS _u(0x000000ff)
+#define I2C_IC_RX_TL_RX_TL_MSB _u(7)
+#define I2C_IC_RX_TL_RX_TL_LSB _u(0)
#define I2C_IC_RX_TL_RX_TL_ACCESS "RW"
// =============================================================================
// Register : I2C_IC_TX_TL
// Description : I2C Transmit FIFO Threshold Register
-#define I2C_IC_TX_TL_OFFSET _U(0x0000003c)
-#define I2C_IC_TX_TL_BITS _U(0x000000ff)
-#define I2C_IC_TX_TL_RESET _U(0x00000000)
+#define I2C_IC_TX_TL_OFFSET _u(0x0000003c)
+#define I2C_IC_TX_TL_BITS _u(0x000000ff)
+#define I2C_IC_TX_TL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_TL_TX_TL
// Description : Transmit FIFO Threshold Level.
@@ -1362,17 +1362,17 @@
// maximum depth of the buffer. A value of 0 sets the threshold
// for 0 entries, and a value of 255 sets the threshold for 255
// entries.
-#define I2C_IC_TX_TL_TX_TL_RESET _U(0x00)
-#define I2C_IC_TX_TL_TX_TL_BITS _U(0x000000ff)
-#define I2C_IC_TX_TL_TX_TL_MSB _U(7)
-#define I2C_IC_TX_TL_TX_TL_LSB _U(0)
+#define I2C_IC_TX_TL_TX_TL_RESET _u(0x00)
+#define I2C_IC_TX_TL_TX_TL_BITS _u(0x000000ff)
+#define I2C_IC_TX_TL_TX_TL_MSB _u(7)
+#define I2C_IC_TX_TL_TX_TL_LSB _u(0)
#define I2C_IC_TX_TL_TX_TL_ACCESS "RW"
// =============================================================================
// Register : I2C_IC_CLR_INTR
// Description : Clear Combined and Individual Interrupt Register
-#define I2C_IC_CLR_INTR_OFFSET _U(0x00000040)
-#define I2C_IC_CLR_INTR_BITS _U(0x00000001)
-#define I2C_IC_CLR_INTR_RESET _U(0x00000000)
+#define I2C_IC_CLR_INTR_OFFSET _u(0x00000040)
+#define I2C_IC_CLR_INTR_BITS _u(0x00000001)
+#define I2C_IC_CLR_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CLR_INTR_CLR_INTR
// Description : Read this register to clear the combined interrupt, all
@@ -1382,85 +1382,85 @@
// register for an exception to clearing IC_TX_ABRT_SOURCE.
//
// Reset value: 0x0
-#define I2C_IC_CLR_INTR_CLR_INTR_RESET _U(0x0)
-#define I2C_IC_CLR_INTR_CLR_INTR_BITS _U(0x00000001)
-#define I2C_IC_CLR_INTR_CLR_INTR_MSB _U(0)
-#define I2C_IC_CLR_INTR_CLR_INTR_LSB _U(0)
+#define I2C_IC_CLR_INTR_CLR_INTR_RESET _u(0x0)
+#define I2C_IC_CLR_INTR_CLR_INTR_BITS _u(0x00000001)
+#define I2C_IC_CLR_INTR_CLR_INTR_MSB _u(0)
+#define I2C_IC_CLR_INTR_CLR_INTR_LSB _u(0)
#define I2C_IC_CLR_INTR_CLR_INTR_ACCESS "RO"
// =============================================================================
// Register : I2C_IC_CLR_RX_UNDER
// Description : Clear RX_UNDER Interrupt Register
-#define I2C_IC_CLR_RX_UNDER_OFFSET _U(0x00000044)
-#define I2C_IC_CLR_RX_UNDER_BITS _U(0x00000001)
-#define I2C_IC_CLR_RX_UNDER_RESET _U(0x00000000)
+#define I2C_IC_CLR_RX_UNDER_OFFSET _u(0x00000044)
+#define I2C_IC_CLR_RX_UNDER_BITS _u(0x00000001)
+#define I2C_IC_CLR_RX_UNDER_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER
// Description : Read this register to clear the RX_UNDER interrupt (bit 0) of
// the IC_RAW_INTR_STAT register.
//
// Reset value: 0x0
-#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_RESET _U(0x0)
-#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_BITS _U(0x00000001)
-#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MSB _U(0)
-#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_LSB _U(0)
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_RESET _u(0x0)
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_BITS _u(0x00000001)
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MSB _u(0)
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_LSB _u(0)
#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_ACCESS "RO"
// =============================================================================
// Register : I2C_IC_CLR_RX_OVER
// Description : Clear RX_OVER Interrupt Register
-#define I2C_IC_CLR_RX_OVER_OFFSET _U(0x00000048)
-#define I2C_IC_CLR_RX_OVER_BITS _U(0x00000001)
-#define I2C_IC_CLR_RX_OVER_RESET _U(0x00000000)
+#define I2C_IC_CLR_RX_OVER_OFFSET _u(0x00000048)
+#define I2C_IC_CLR_RX_OVER_BITS _u(0x00000001)
+#define I2C_IC_CLR_RX_OVER_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CLR_RX_OVER_CLR_RX_OVER
// Description : Read this register to clear the RX_OVER interrupt (bit 1) of
// the IC_RAW_INTR_STAT register.
//
// Reset value: 0x0
-#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_RESET _U(0x0)
-#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_BITS _U(0x00000001)
-#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MSB _U(0)
-#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_LSB _U(0)
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_RESET _u(0x0)
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_BITS _u(0x00000001)
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MSB _u(0)
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_LSB _u(0)
#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_ACCESS "RO"
// =============================================================================
// Register : I2C_IC_CLR_TX_OVER
// Description : Clear TX_OVER Interrupt Register
-#define I2C_IC_CLR_TX_OVER_OFFSET _U(0x0000004c)
-#define I2C_IC_CLR_TX_OVER_BITS _U(0x00000001)
-#define I2C_IC_CLR_TX_OVER_RESET _U(0x00000000)
+#define I2C_IC_CLR_TX_OVER_OFFSET _u(0x0000004c)
+#define I2C_IC_CLR_TX_OVER_BITS _u(0x00000001)
+#define I2C_IC_CLR_TX_OVER_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CLR_TX_OVER_CLR_TX_OVER
// Description : Read this register to clear the TX_OVER interrupt (bit 3) of
// the IC_RAW_INTR_STAT register.
//
// Reset value: 0x0
-#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_RESET _U(0x0)
-#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_BITS _U(0x00000001)
-#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MSB _U(0)
-#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_LSB _U(0)
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_RESET _u(0x0)
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_BITS _u(0x00000001)
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MSB _u(0)
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_LSB _u(0)
#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_ACCESS "RO"
// =============================================================================
// Register : I2C_IC_CLR_RD_REQ
// Description : Clear RD_REQ Interrupt Register
-#define I2C_IC_CLR_RD_REQ_OFFSET _U(0x00000050)
-#define I2C_IC_CLR_RD_REQ_BITS _U(0x00000001)
-#define I2C_IC_CLR_RD_REQ_RESET _U(0x00000000)
+#define I2C_IC_CLR_RD_REQ_OFFSET _u(0x00000050)
+#define I2C_IC_CLR_RD_REQ_BITS _u(0x00000001)
+#define I2C_IC_CLR_RD_REQ_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CLR_RD_REQ_CLR_RD_REQ
// Description : Read this register to clear the RD_REQ interrupt (bit 5) of the
// IC_RAW_INTR_STAT register.
//
// Reset value: 0x0
-#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_RESET _U(0x0)
-#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_BITS _U(0x00000001)
-#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MSB _U(0)
-#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_LSB _U(0)
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_RESET _u(0x0)
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_BITS _u(0x00000001)
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MSB _u(0)
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_LSB _u(0)
#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_ACCESS "RO"
// =============================================================================
// Register : I2C_IC_CLR_TX_ABRT
// Description : Clear TX_ABRT Interrupt Register
-#define I2C_IC_CLR_TX_ABRT_OFFSET _U(0x00000054)
-#define I2C_IC_CLR_TX_ABRT_BITS _U(0x00000001)
-#define I2C_IC_CLR_TX_ABRT_RESET _U(0x00000000)
+#define I2C_IC_CLR_TX_ABRT_OFFSET _u(0x00000054)
+#define I2C_IC_CLR_TX_ABRT_BITS _u(0x00000001)
+#define I2C_IC_CLR_TX_ABRT_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT
// Description : Read this register to clear the TX_ABRT interrupt (bit 6) of
@@ -1471,34 +1471,34 @@
// IC_TX_ABRT_SOURCE.
//
// Reset value: 0x0
-#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_RESET _U(0x0)
-#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_BITS _U(0x00000001)
-#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MSB _U(0)
-#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_LSB _U(0)
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_RESET _u(0x0)
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_BITS _u(0x00000001)
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MSB _u(0)
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_LSB _u(0)
#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_ACCESS "RO"
// =============================================================================
// Register : I2C_IC_CLR_RX_DONE
// Description : Clear RX_DONE Interrupt Register
-#define I2C_IC_CLR_RX_DONE_OFFSET _U(0x00000058)
-#define I2C_IC_CLR_RX_DONE_BITS _U(0x00000001)
-#define I2C_IC_CLR_RX_DONE_RESET _U(0x00000000)
+#define I2C_IC_CLR_RX_DONE_OFFSET _u(0x00000058)
+#define I2C_IC_CLR_RX_DONE_BITS _u(0x00000001)
+#define I2C_IC_CLR_RX_DONE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CLR_RX_DONE_CLR_RX_DONE
// Description : Read this register to clear the RX_DONE interrupt (bit 7) of
// the IC_RAW_INTR_STAT register.
//
// Reset value: 0x0
-#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_RESET _U(0x0)
-#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_BITS _U(0x00000001)
-#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MSB _U(0)
-#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_LSB _U(0)
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_RESET _u(0x0)
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_BITS _u(0x00000001)
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MSB _u(0)
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_LSB _u(0)
#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_ACCESS "RO"
// =============================================================================
// Register : I2C_IC_CLR_ACTIVITY
// Description : Clear ACTIVITY Interrupt Register
-#define I2C_IC_CLR_ACTIVITY_OFFSET _U(0x0000005c)
-#define I2C_IC_CLR_ACTIVITY_BITS _U(0x00000001)
-#define I2C_IC_CLR_ACTIVITY_RESET _U(0x00000000)
+#define I2C_IC_CLR_ACTIVITY_OFFSET _u(0x0000005c)
+#define I2C_IC_CLR_ACTIVITY_BITS _u(0x00000001)
+#define I2C_IC_CLR_ACTIVITY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY
// Description : Reading this register clears the ACTIVITY interrupt if the I2C
@@ -1510,68 +1510,68 @@
// of the IC_RAW_INTR_STAT register.
//
// Reset value: 0x0
-#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_RESET _U(0x0)
-#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_BITS _U(0x00000001)
-#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MSB _U(0)
-#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_LSB _U(0)
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_RESET _u(0x0)
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_BITS _u(0x00000001)
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MSB _u(0)
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_LSB _u(0)
#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_ACCESS "RO"
// =============================================================================
// Register : I2C_IC_CLR_STOP_DET
// Description : Clear STOP_DET Interrupt Register
-#define I2C_IC_CLR_STOP_DET_OFFSET _U(0x00000060)
-#define I2C_IC_CLR_STOP_DET_BITS _U(0x00000001)
-#define I2C_IC_CLR_STOP_DET_RESET _U(0x00000000)
+#define I2C_IC_CLR_STOP_DET_OFFSET _u(0x00000060)
+#define I2C_IC_CLR_STOP_DET_BITS _u(0x00000001)
+#define I2C_IC_CLR_STOP_DET_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CLR_STOP_DET_CLR_STOP_DET
// Description : Read this register to clear the STOP_DET interrupt (bit 9) of
// the IC_RAW_INTR_STAT register.
//
// Reset value: 0x0
-#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_RESET _U(0x0)
-#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_BITS _U(0x00000001)
-#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MSB _U(0)
-#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_LSB _U(0)
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_RESET _u(0x0)
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_BITS _u(0x00000001)
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MSB _u(0)
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_LSB _u(0)
#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_ACCESS "RO"
// =============================================================================
// Register : I2C_IC_CLR_START_DET
// Description : Clear START_DET Interrupt Register
-#define I2C_IC_CLR_START_DET_OFFSET _U(0x00000064)
-#define I2C_IC_CLR_START_DET_BITS _U(0x00000001)
-#define I2C_IC_CLR_START_DET_RESET _U(0x00000000)
+#define I2C_IC_CLR_START_DET_OFFSET _u(0x00000064)
+#define I2C_IC_CLR_START_DET_BITS _u(0x00000001)
+#define I2C_IC_CLR_START_DET_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CLR_START_DET_CLR_START_DET
// Description : Read this register to clear the START_DET interrupt (bit 10) of
// the IC_RAW_INTR_STAT register.
//
// Reset value: 0x0
-#define I2C_IC_CLR_START_DET_CLR_START_DET_RESET _U(0x0)
-#define I2C_IC_CLR_START_DET_CLR_START_DET_BITS _U(0x00000001)
-#define I2C_IC_CLR_START_DET_CLR_START_DET_MSB _U(0)
-#define I2C_IC_CLR_START_DET_CLR_START_DET_LSB _U(0)
+#define I2C_IC_CLR_START_DET_CLR_START_DET_RESET _u(0x0)
+#define I2C_IC_CLR_START_DET_CLR_START_DET_BITS _u(0x00000001)
+#define I2C_IC_CLR_START_DET_CLR_START_DET_MSB _u(0)
+#define I2C_IC_CLR_START_DET_CLR_START_DET_LSB _u(0)
#define I2C_IC_CLR_START_DET_CLR_START_DET_ACCESS "RO"
// =============================================================================
// Register : I2C_IC_CLR_GEN_CALL
// Description : Clear GEN_CALL Interrupt Register
-#define I2C_IC_CLR_GEN_CALL_OFFSET _U(0x00000068)
-#define I2C_IC_CLR_GEN_CALL_BITS _U(0x00000001)
-#define I2C_IC_CLR_GEN_CALL_RESET _U(0x00000000)
+#define I2C_IC_CLR_GEN_CALL_OFFSET _u(0x00000068)
+#define I2C_IC_CLR_GEN_CALL_BITS _u(0x00000001)
+#define I2C_IC_CLR_GEN_CALL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL
// Description : Read this register to clear the GEN_CALL interrupt (bit 11) of
// IC_RAW_INTR_STAT register.
//
// Reset value: 0x0
-#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_RESET _U(0x0)
-#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_BITS _U(0x00000001)
-#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MSB _U(0)
-#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_LSB _U(0)
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_RESET _u(0x0)
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_BITS _u(0x00000001)
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MSB _u(0)
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_LSB _u(0)
#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_ACCESS "RO"
// =============================================================================
// Register : I2C_IC_ENABLE
// Description : I2C Enable Register
-#define I2C_IC_ENABLE_OFFSET _U(0x0000006c)
-#define I2C_IC_ENABLE_BITS _U(0x00000007)
-#define I2C_IC_ENABLE_RESET _U(0x00000000)
+#define I2C_IC_ENABLE_OFFSET _u(0x0000006c)
+#define I2C_IC_ENABLE_BITS _u(0x00000007)
+#define I2C_IC_ENABLE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_ENABLE_TX_CMD_BLOCK
// Description : In Master mode: - 1'b1: Blocks the transmission of data on I2C
@@ -1585,13 +1585,13 @@
// value: IC_TX_CMD_BLOCK_DEFAULT
// 0x0 -> Tx Command execution not blocked
// 0x1 -> Tx Command execution blocked
-#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET _U(0x0)
-#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS _U(0x00000004)
-#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB _U(2)
-#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB _U(2)
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET _u(0x0)
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS _u(0x00000004)
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB _u(2)
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB _u(2)
#define I2C_IC_ENABLE_TX_CMD_BLOCK_ACCESS "RW"
-#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_NOT_BLOCKED _U(0x0)
-#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED _U(0x1)
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_NOT_BLOCKED _u(0x0)
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_ENABLE_ABORT
// Description : When set, the controller initiates the transfer abort. - 0:
@@ -1611,13 +1611,13 @@
// Reset value: 0x0
// 0x0 -> ABORT operation not in progress
// 0x1 -> ABORT operation in progress
-#define I2C_IC_ENABLE_ABORT_RESET _U(0x0)
-#define I2C_IC_ENABLE_ABORT_BITS _U(0x00000002)
-#define I2C_IC_ENABLE_ABORT_MSB _U(1)
-#define I2C_IC_ENABLE_ABORT_LSB _U(1)
+#define I2C_IC_ENABLE_ABORT_RESET _u(0x0)
+#define I2C_IC_ENABLE_ABORT_BITS _u(0x00000002)
+#define I2C_IC_ENABLE_ABORT_MSB _u(1)
+#define I2C_IC_ENABLE_ABORT_LSB _u(1)
#define I2C_IC_ENABLE_ABORT_ACCESS "RW"
-#define I2C_IC_ENABLE_ABORT_VALUE_DISABLE _U(0x0)
-#define I2C_IC_ENABLE_ABORT_VALUE_ENABLED _U(0x1)
+#define I2C_IC_ENABLE_ABORT_VALUE_DISABLE _u(0x0)
+#define I2C_IC_ENABLE_ABORT_VALUE_ENABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_ENABLE_ENABLE
// Description : Controls whether the DW_apb_i2c is enabled. - 0: Disables
@@ -1645,13 +1645,13 @@
// Reset value: 0x0
// 0x0 -> I2C is disabled
// 0x1 -> I2C is enabled
-#define I2C_IC_ENABLE_ENABLE_RESET _U(0x0)
-#define I2C_IC_ENABLE_ENABLE_BITS _U(0x00000001)
-#define I2C_IC_ENABLE_ENABLE_MSB _U(0)
-#define I2C_IC_ENABLE_ENABLE_LSB _U(0)
+#define I2C_IC_ENABLE_ENABLE_RESET _u(0x0)
+#define I2C_IC_ENABLE_ENABLE_BITS _u(0x00000001)
+#define I2C_IC_ENABLE_ENABLE_MSB _u(0)
+#define I2C_IC_ENABLE_ENABLE_LSB _u(0)
#define I2C_IC_ENABLE_ENABLE_ACCESS "RW"
-#define I2C_IC_ENABLE_ENABLE_VALUE_DISABLED _U(0x0)
-#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED _U(0x1)
+#define I2C_IC_ENABLE_ENABLE_VALUE_DISABLED _u(0x0)
+#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED _u(0x1)
// =============================================================================
// Register : I2C_IC_STATUS
// Description : I2C Status Register
@@ -1665,9 +1665,9 @@
// register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set
// to 0 When the master or slave state machines goes to idle and
// ic_en=0: - Bits 5 and 6 are set to 0
-#define I2C_IC_STATUS_OFFSET _U(0x00000070)
-#define I2C_IC_STATUS_BITS _U(0x0000007f)
-#define I2C_IC_STATUS_RESET _U(0x00000006)
+#define I2C_IC_STATUS_OFFSET _u(0x00000070)
+#define I2C_IC_STATUS_BITS _u(0x0000007f)
+#define I2C_IC_STATUS_RESET _u(0x00000006)
// -----------------------------------------------------------------------------
// Field : I2C_IC_STATUS_SLV_ACTIVITY
// Description : Slave FSM Activity Status. When the Slave Finite State Machine
@@ -1677,13 +1677,13 @@
// DW_apb_i2c is Active Reset value: 0x0
// 0x0 -> Slave is idle
// 0x1 -> Slave not idle
-#define I2C_IC_STATUS_SLV_ACTIVITY_RESET _U(0x0)
-#define I2C_IC_STATUS_SLV_ACTIVITY_BITS _U(0x00000040)
-#define I2C_IC_STATUS_SLV_ACTIVITY_MSB _U(6)
-#define I2C_IC_STATUS_SLV_ACTIVITY_LSB _U(6)
+#define I2C_IC_STATUS_SLV_ACTIVITY_RESET _u(0x0)
+#define I2C_IC_STATUS_SLV_ACTIVITY_BITS _u(0x00000040)
+#define I2C_IC_STATUS_SLV_ACTIVITY_MSB _u(6)
+#define I2C_IC_STATUS_SLV_ACTIVITY_LSB _u(6)
#define I2C_IC_STATUS_SLV_ACTIVITY_ACCESS "RO"
-#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE _U(0x0)
-#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE _u(0x0)
+#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_STATUS_MST_ACTIVITY
// Description : Master FSM Activity Status. When the Master Finite State
@@ -1696,13 +1696,13 @@
// Reset value: 0x0
// 0x0 -> Master is idle
// 0x1 -> Master not idle
-#define I2C_IC_STATUS_MST_ACTIVITY_RESET _U(0x0)
-#define I2C_IC_STATUS_MST_ACTIVITY_BITS _U(0x00000020)
-#define I2C_IC_STATUS_MST_ACTIVITY_MSB _U(5)
-#define I2C_IC_STATUS_MST_ACTIVITY_LSB _U(5)
+#define I2C_IC_STATUS_MST_ACTIVITY_RESET _u(0x0)
+#define I2C_IC_STATUS_MST_ACTIVITY_BITS _u(0x00000020)
+#define I2C_IC_STATUS_MST_ACTIVITY_MSB _u(5)
+#define I2C_IC_STATUS_MST_ACTIVITY_LSB _u(5)
#define I2C_IC_STATUS_MST_ACTIVITY_ACCESS "RO"
-#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE _U(0x0)
-#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE _u(0x0)
+#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_STATUS_RFF
// Description : Receive FIFO Completely Full. When the receive FIFO is
@@ -1712,13 +1712,13 @@
// 0x0
// 0x0 -> Rx FIFO not full
// 0x1 -> Rx FIFO is full
-#define I2C_IC_STATUS_RFF_RESET _U(0x0)
-#define I2C_IC_STATUS_RFF_BITS _U(0x00000010)
-#define I2C_IC_STATUS_RFF_MSB _U(4)
-#define I2C_IC_STATUS_RFF_LSB _U(4)
+#define I2C_IC_STATUS_RFF_RESET _u(0x0)
+#define I2C_IC_STATUS_RFF_BITS _u(0x00000010)
+#define I2C_IC_STATUS_RFF_MSB _u(4)
+#define I2C_IC_STATUS_RFF_LSB _u(4)
#define I2C_IC_STATUS_RFF_ACCESS "RO"
-#define I2C_IC_STATUS_RFF_VALUE_NOT_FULL _U(0x0)
-#define I2C_IC_STATUS_RFF_VALUE_FULL _U(0x1)
+#define I2C_IC_STATUS_RFF_VALUE_NOT_FULL _u(0x0)
+#define I2C_IC_STATUS_RFF_VALUE_FULL _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_STATUS_RFNE
// Description : Receive FIFO Not Empty. This bit is set when the receive FIFO
@@ -1727,13 +1727,13 @@
// not empty Reset value: 0x0
// 0x0 -> Rx FIFO is empty
// 0x1 -> Rx FIFO not empty
-#define I2C_IC_STATUS_RFNE_RESET _U(0x0)
-#define I2C_IC_STATUS_RFNE_BITS _U(0x00000008)
-#define I2C_IC_STATUS_RFNE_MSB _U(3)
-#define I2C_IC_STATUS_RFNE_LSB _U(3)
+#define I2C_IC_STATUS_RFNE_RESET _u(0x0)
+#define I2C_IC_STATUS_RFNE_BITS _u(0x00000008)
+#define I2C_IC_STATUS_RFNE_MSB _u(3)
+#define I2C_IC_STATUS_RFNE_LSB _u(3)
#define I2C_IC_STATUS_RFNE_ACCESS "RO"
-#define I2C_IC_STATUS_RFNE_VALUE_EMPTY _U(0x0)
-#define I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY _U(0x1)
+#define I2C_IC_STATUS_RFNE_VALUE_EMPTY _u(0x0)
+#define I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_STATUS_TFE
// Description : Transmit FIFO Completely Empty. When the transmit FIFO is
@@ -1743,13 +1743,13 @@
// Transmit FIFO is empty Reset value: 0x1
// 0x0 -> Tx FIFO not empty
// 0x1 -> Tx FIFO is empty
-#define I2C_IC_STATUS_TFE_RESET _U(0x1)
-#define I2C_IC_STATUS_TFE_BITS _U(0x00000004)
-#define I2C_IC_STATUS_TFE_MSB _U(2)
-#define I2C_IC_STATUS_TFE_LSB _U(2)
+#define I2C_IC_STATUS_TFE_RESET _u(0x1)
+#define I2C_IC_STATUS_TFE_BITS _u(0x00000004)
+#define I2C_IC_STATUS_TFE_MSB _u(2)
+#define I2C_IC_STATUS_TFE_LSB _u(2)
#define I2C_IC_STATUS_TFE_ACCESS "RO"
-#define I2C_IC_STATUS_TFE_VALUE_NON_EMPTY _U(0x0)
-#define I2C_IC_STATUS_TFE_VALUE_EMPTY _U(0x1)
+#define I2C_IC_STATUS_TFE_VALUE_NON_EMPTY _u(0x0)
+#define I2C_IC_STATUS_TFE_VALUE_EMPTY _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_STATUS_TFNF
// Description : Transmit FIFO Not Full. Set when the transmit FIFO contains one
@@ -1758,25 +1758,25 @@
// value: 0x1
// 0x0 -> Tx FIFO is full
// 0x1 -> Tx FIFO not full
-#define I2C_IC_STATUS_TFNF_RESET _U(0x1)
-#define I2C_IC_STATUS_TFNF_BITS _U(0x00000002)
-#define I2C_IC_STATUS_TFNF_MSB _U(1)
-#define I2C_IC_STATUS_TFNF_LSB _U(1)
+#define I2C_IC_STATUS_TFNF_RESET _u(0x1)
+#define I2C_IC_STATUS_TFNF_BITS _u(0x00000002)
+#define I2C_IC_STATUS_TFNF_MSB _u(1)
+#define I2C_IC_STATUS_TFNF_LSB _u(1)
#define I2C_IC_STATUS_TFNF_ACCESS "RO"
-#define I2C_IC_STATUS_TFNF_VALUE_FULL _U(0x0)
-#define I2C_IC_STATUS_TFNF_VALUE_NOT_FULL _U(0x1)
+#define I2C_IC_STATUS_TFNF_VALUE_FULL _u(0x0)
+#define I2C_IC_STATUS_TFNF_VALUE_NOT_FULL _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_STATUS_ACTIVITY
// Description : I2C Activity Status. Reset value: 0x0
// 0x0 -> I2C is idle
// 0x1 -> I2C is active
-#define I2C_IC_STATUS_ACTIVITY_RESET _U(0x0)
-#define I2C_IC_STATUS_ACTIVITY_BITS _U(0x00000001)
-#define I2C_IC_STATUS_ACTIVITY_MSB _U(0)
-#define I2C_IC_STATUS_ACTIVITY_LSB _U(0)
+#define I2C_IC_STATUS_ACTIVITY_RESET _u(0x0)
+#define I2C_IC_STATUS_ACTIVITY_BITS _u(0x00000001)
+#define I2C_IC_STATUS_ACTIVITY_MSB _u(0)
+#define I2C_IC_STATUS_ACTIVITY_LSB _u(0)
#define I2C_IC_STATUS_ACTIVITY_ACCESS "RO"
-#define I2C_IC_STATUS_ACTIVITY_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_STATUS_ACTIVITY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE _u(0x1)
// =============================================================================
// Register : I2C_IC_TXFLR
// Description : I2C Transmit FIFO Level Register This register contains the
@@ -1786,19 +1786,19 @@
// register - The slave bulk transmit mode is aborted The register
// increments whenever data is placed into the transmit FIFO and
// decrements when data is taken from the transmit FIFO.
-#define I2C_IC_TXFLR_OFFSET _U(0x00000074)
-#define I2C_IC_TXFLR_BITS _U(0x0000001f)
-#define I2C_IC_TXFLR_RESET _U(0x00000000)
+#define I2C_IC_TXFLR_OFFSET _u(0x00000074)
+#define I2C_IC_TXFLR_BITS _u(0x0000001f)
+#define I2C_IC_TXFLR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TXFLR_TXFLR
// Description : Transmit FIFO Level. Contains the number of valid data entries
// in the transmit FIFO.
//
// Reset value: 0x0
-#define I2C_IC_TXFLR_TXFLR_RESET _U(0x00)
-#define I2C_IC_TXFLR_TXFLR_BITS _U(0x0000001f)
-#define I2C_IC_TXFLR_TXFLR_MSB _U(4)
-#define I2C_IC_TXFLR_TXFLR_LSB _U(0)
+#define I2C_IC_TXFLR_TXFLR_RESET _u(0x00)
+#define I2C_IC_TXFLR_TXFLR_BITS _u(0x0000001f)
+#define I2C_IC_TXFLR_TXFLR_MSB _u(4)
+#define I2C_IC_TXFLR_TXFLR_LSB _u(0)
#define I2C_IC_TXFLR_TXFLR_ACCESS "RO"
// =============================================================================
// Register : I2C_IC_RXFLR
@@ -1809,19 +1809,19 @@
// IC_TX_ABRT_SOURCE The register increments whenever data is
// placed into the receive FIFO and decrements when data is taken
// from the receive FIFO.
-#define I2C_IC_RXFLR_OFFSET _U(0x00000078)
-#define I2C_IC_RXFLR_BITS _U(0x0000001f)
-#define I2C_IC_RXFLR_RESET _U(0x00000000)
+#define I2C_IC_RXFLR_OFFSET _u(0x00000078)
+#define I2C_IC_RXFLR_BITS _u(0x0000001f)
+#define I2C_IC_RXFLR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_RXFLR_RXFLR
// Description : Receive FIFO Level. Contains the number of valid data entries
// in the receive FIFO.
//
// Reset value: 0x0
-#define I2C_IC_RXFLR_RXFLR_RESET _U(0x00)
-#define I2C_IC_RXFLR_RXFLR_BITS _U(0x0000001f)
-#define I2C_IC_RXFLR_RXFLR_MSB _U(4)
-#define I2C_IC_RXFLR_RXFLR_LSB _U(0)
+#define I2C_IC_RXFLR_RXFLR_RESET _u(0x00)
+#define I2C_IC_RXFLR_RXFLR_BITS _u(0x0000001f)
+#define I2C_IC_RXFLR_RXFLR_MSB _u(4)
+#define I2C_IC_RXFLR_RXFLR_LSB _u(0)
#define I2C_IC_RXFLR_RXFLR_ACCESS "RO"
// =============================================================================
// Register : I2C_IC_SDA_HOLD
@@ -1847,19 +1847,19 @@
// Therefore the programmed value cannot be larger than
// N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of
// the scl period measured in ic_clk cycles.
-#define I2C_IC_SDA_HOLD_OFFSET _U(0x0000007c)
-#define I2C_IC_SDA_HOLD_BITS _U(0x00ffffff)
-#define I2C_IC_SDA_HOLD_RESET _U(0x00000001)
+#define I2C_IC_SDA_HOLD_OFFSET _u(0x0000007c)
+#define I2C_IC_SDA_HOLD_BITS _u(0x00ffffff)
+#define I2C_IC_SDA_HOLD_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD
// Description : Sets the required SDA hold time in units of ic_clk period, when
// DW_apb_i2c acts as a receiver.
//
// Reset value: IC_DEFAULT_SDA_HOLD[23:16].
-#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_RESET _U(0x00)
-#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_BITS _U(0x00ff0000)
-#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MSB _U(23)
-#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_LSB _U(16)
+#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_RESET _u(0x00)
+#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_BITS _u(0x00ff0000)
+#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MSB _u(23)
+#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_LSB _u(16)
#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD
@@ -1867,10 +1867,10 @@
// DW_apb_i2c acts as a transmitter.
//
// Reset value: IC_DEFAULT_SDA_HOLD[15:0].
-#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_RESET _U(0x0001)
-#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS _U(0x0000ffff)
-#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MSB _U(15)
-#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB _U(0)
+#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_RESET _u(0x0001)
+#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS _u(0x0000ffff)
+#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MSB _u(15)
+#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB _u(0)
#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_ACCESS "RW"
// =============================================================================
// Register : I2C_IC_TX_ABRT_SOURCE
@@ -1889,9 +1889,9 @@
// register. If the source of the ABRT_SBYTE_NORSTRT is not fixed
// before attempting to clear this bit, Bit 9 clears for one cycle
// and is then re-asserted.
-#define I2C_IC_TX_ABRT_SOURCE_OFFSET _U(0x00000080)
-#define I2C_IC_TX_ABRT_SOURCE_BITS _U(0xff81ffff)
-#define I2C_IC_TX_ABRT_SOURCE_RESET _U(0x00000000)
+#define I2C_IC_TX_ABRT_SOURCE_OFFSET _u(0x00000080)
+#define I2C_IC_TX_ABRT_SOURCE_BITS _u(0xff81ffff)
+#define I2C_IC_TX_ABRT_SOURCE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT
// Description : This field indicates the number of Tx FIFO Data Commands which
@@ -1901,10 +1901,10 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
-#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_RESET _U(0x000)
-#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_BITS _U(0xff800000)
-#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MSB _U(31)
-#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_LSB _U(23)
+#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_RESET _u(0x000)
+#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_BITS _u(0xff800000)
+#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MSB _u(31)
+#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_LSB _u(23)
#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT
@@ -1916,13 +1916,13 @@
// Role of DW_apb_i2c: Master-Transmitter
// 0x0 -> Transfer abort detected by master- scenario not present
// 0x1 -> Transfer abort detected by master
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS _U(0x00010000)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB _U(16)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB _U(16)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS _u(0x00010000)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB _u(16)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB _u(16)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_GENERATED _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_GENERATED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX
// Description : 1: When the processor side responds to a slave mode request for
@@ -1935,13 +1935,13 @@
// 0x0 -> Slave trying to transmit to remote master in read mode-
// scenario not present
// 0x1 -> Slave trying to transmit to remote master in read mode
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _U(0x00008000)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB _U(15)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB _U(15)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _u(0x00008000)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB _u(15)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB _u(15)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_GENERATED _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_GENERATED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST
// Description : This field indicates that a Slave has lost the bus while
@@ -1959,13 +1959,13 @@
// 0x0 -> Slave lost arbitration to remote master- scenario not
// present
// 0x1 -> Slave lost arbitration to remote master
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS _U(0x00004000)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB _U(14)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB _U(14)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS _u(0x00004000)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB _u(14)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB _u(14)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_GENERATED _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_GENERATED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO
// Description : This field specifies that the Slave has received a read command
@@ -1979,13 +1979,13 @@
// command- scenario not present
// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read
// command
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _U(0x00002000)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _U(13)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB _U(13)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _u(0x00002000)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _u(13)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB _u(13)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_GENERATED _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_GENERATED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ARB_LOST
// Description : This field specifies that the Master has lost arbitration, or
@@ -1998,13 +1998,13 @@
// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario
// not present
// 0x1 -> Master or Slave-Transmitter lost arbitration
-#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _U(0x00001000)
-#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB _U(12)
-#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB _U(12)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _u(0x00001000)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB _u(12)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB _u(12)
#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_GENERATED _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_GENERATED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS
// Description : This field indicates that the User tries to initiate a Master
@@ -2016,13 +2016,13 @@
// 0x0 -> User initiating master operation when MASTER disabled-
// scenario not present
// 0x1 -> User initiating master operation when MASTER disabled
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _U(0x00000800)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB _U(11)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB _U(11)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _u(0x00000800)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB _u(11)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB _u(11)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_GENERATED _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_GENERATED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT
// Description : This field indicates that the restart is disabled
@@ -2036,13 +2036,13 @@
// RESTART disabled
// 0x1 -> Master trying to read in 10Bit addressing mode when
// RESTART disabled
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _U(0x00000400)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _U(10)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB _U(10)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _u(0x00000400)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _u(10)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB _u(10)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_GENERATED _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_GENERATED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT
// Description : To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be
@@ -2063,13 +2063,13 @@
// 0x0 -> User trying to send START byte when RESTART disabled-
// scenario not present
// 0x1 -> User trying to send START byte when RESTART disabled
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _U(0x00000200)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB _U(9)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB _U(9)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _u(0x00000200)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB _u(9)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB _u(9)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_GENERATED _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_GENERATED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT
// Description : This field indicates that the restart is disabled
@@ -2083,13 +2083,13 @@
// disabled- scenario not present
// 0x1 -> User trying to switch Master to HS mode when RESTART
// disabled
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _U(0x00000100)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB _U(8)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB _U(8)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _u(0x00000100)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB _u(8)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB _u(8)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_GENERATED _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_GENERATED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET
// Description : This field indicates that the Master has sent a START Byte and
@@ -2100,13 +2100,13 @@
// Role of DW_apb_i2c: Master
// 0x0 -> ACK detected for START byte- scenario not present
// 0x1 -> ACK detected for START byte
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS _U(0x00000080)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB _U(7)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB _U(7)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS _u(0x00000080)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB _u(7)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB _u(7)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_GENERATED _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_GENERATED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET
// Description : This field indicates that the Master is in High Speed mode and
@@ -2117,13 +2117,13 @@
// Role of DW_apb_i2c: Master
// 0x0 -> HS Master code ACKed in HS Mode- scenario not present
// 0x1 -> HS Master code ACKed in HS Mode
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS _U(0x00000040)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB _U(6)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB _U(6)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS _u(0x00000040)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB _u(6)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB _u(6)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_GENERATED _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_GENERATED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ
// Description : This field indicates that DW_apb_i2c in the master mode has
@@ -2136,13 +2136,13 @@
// Role of DW_apb_i2c: Master-Transmitter
// 0x0 -> GCALL is followed by read from bus-scenario not present
// 0x1 -> GCALL is followed by read from bus
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS _U(0x00000020)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB _U(5)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB _U(5)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS _u(0x00000020)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB _u(5)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB _u(5)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_GENERATED _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_GENERATED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK
// Description : This field indicates that DW_apb_i2c in master mode has sent a
@@ -2154,13 +2154,13 @@
// Role of DW_apb_i2c: Master-Transmitter
// 0x0 -> GCALL not ACKed by any slave-scenario not present
// 0x1 -> GCALL not ACKed by any slave
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS _U(0x00000010)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB _U(4)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB _U(4)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS _u(0x00000010)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB _u(4)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB _u(4)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_GENERATED _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_GENERATED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK
// Description : This field indicates the master-mode only bit. When the master
@@ -2174,13 +2174,13 @@
// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario
// not present
// 0x1 -> Transmitted data not ACKed by addressed slave
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _U(0x00000008)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB _U(3)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB _U(3)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _u(0x00000008)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB _u(3)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB _u(3)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_GENERATED _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_GENERATED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK
// Description : This field indicates that the Master is in 10-bit address mode
@@ -2192,13 +2192,13 @@
// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
// 0x0 -> This abort is not generated
// 0x1 -> Byte 2 of 10Bit Address not ACKed by any slave
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS _U(0x00000004)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB _U(2)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB _U(2)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS _u(0x00000004)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB _u(2)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB _u(2)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK
// Description : This field indicates that the Master is in 10-bit address mode
@@ -2210,13 +2210,13 @@
// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
// 0x0 -> This abort is not generated
// 0x1 -> Byte 1 of 10Bit Address not ACKed by any slave
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS _U(0x00000002)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB _U(1)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB _U(1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS _u(0x00000002)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB _u(1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB _u(1)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK
// Description : This field indicates that the Master is in 7-bit addressing
@@ -2228,13 +2228,13 @@
// 0x0 -> This abort is not generated
// 0x1 -> This abort is generated because of NOACK for 7-bit
// address
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS _U(0x00000001)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB _U(0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB _U(0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS _u(0x00000001)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB _u(0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB _u(0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACCESS "RO"
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE _u(0x1)
// =============================================================================
// Register : I2C_IC_SLV_DATA_NACK_ONLY
// Description : Generate Slave Data NACK Register
@@ -2251,9 +2251,9 @@
// IC_STATUS[6] is a register read-back location for the internal
// slv_activity signal; the user should poll this before writing
// the ic_slv_data_nack_only bit.
-#define I2C_IC_SLV_DATA_NACK_ONLY_OFFSET _U(0x00000084)
-#define I2C_IC_SLV_DATA_NACK_ONLY_BITS _U(0x00000001)
-#define I2C_IC_SLV_DATA_NACK_ONLY_RESET _U(0x00000000)
+#define I2C_IC_SLV_DATA_NACK_ONLY_OFFSET _u(0x00000084)
+#define I2C_IC_SLV_DATA_NACK_ONLY_BITS _u(0x00000001)
+#define I2C_IC_SLV_DATA_NACK_ONLY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_SLV_DATA_NACK_ONLY_NACK
// Description : Generate NACK. This NACK generation only occurs when DW_apb_i2c
@@ -2268,13 +2268,13 @@
// value: 0x0
// 0x0 -> Slave receiver generates NACK normally
// 0x1 -> Slave receiver generates NACK upon data reception only
-#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET _U(0x0)
-#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS _U(0x00000001)
-#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB _U(0)
-#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB _U(0)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET _u(0x0)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS _u(0x00000001)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB _u(0)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB _u(0)
#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_ACCESS "RW"
-#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_DISABLED _U(0x0)
-#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED _U(0x1)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_DISABLED _u(0x0)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED _u(0x1)
// =============================================================================
// Register : I2C_IC_DMA_CR
// Description : DMA Control Register
@@ -2282,41 +2282,41 @@
// The register is used to enable the DMA Controller interface
// operation. There is a separate bit for transmit and receive.
// This can be programmed regardless of the state of IC_ENABLE.
-#define I2C_IC_DMA_CR_OFFSET _U(0x00000088)
-#define I2C_IC_DMA_CR_BITS _U(0x00000003)
-#define I2C_IC_DMA_CR_RESET _U(0x00000000)
+#define I2C_IC_DMA_CR_OFFSET _u(0x00000088)
+#define I2C_IC_DMA_CR_BITS _u(0x00000003)
+#define I2C_IC_DMA_CR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_DMA_CR_TDMAE
// Description : Transmit DMA Enable. This bit enables/disables the transmit
// FIFO DMA channel. Reset value: 0x0
// 0x0 -> transmit FIFO DMA channel disabled
// 0x1 -> Transmit FIFO DMA channel enabled
-#define I2C_IC_DMA_CR_TDMAE_RESET _U(0x0)
-#define I2C_IC_DMA_CR_TDMAE_BITS _U(0x00000002)
-#define I2C_IC_DMA_CR_TDMAE_MSB _U(1)
-#define I2C_IC_DMA_CR_TDMAE_LSB _U(1)
+#define I2C_IC_DMA_CR_TDMAE_RESET _u(0x0)
+#define I2C_IC_DMA_CR_TDMAE_BITS _u(0x00000002)
+#define I2C_IC_DMA_CR_TDMAE_MSB _u(1)
+#define I2C_IC_DMA_CR_TDMAE_LSB _u(1)
#define I2C_IC_DMA_CR_TDMAE_ACCESS "RW"
-#define I2C_IC_DMA_CR_TDMAE_VALUE_DISABLED _U(0x0)
-#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED _U(0x1)
+#define I2C_IC_DMA_CR_TDMAE_VALUE_DISABLED _u(0x0)
+#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_DMA_CR_RDMAE
// Description : Receive DMA Enable. This bit enables/disables the receive FIFO
// DMA channel. Reset value: 0x0
// 0x0 -> Receive FIFO DMA channel disabled
// 0x1 -> Receive FIFO DMA channel enabled
-#define I2C_IC_DMA_CR_RDMAE_RESET _U(0x0)
-#define I2C_IC_DMA_CR_RDMAE_BITS _U(0x00000001)
-#define I2C_IC_DMA_CR_RDMAE_MSB _U(0)
-#define I2C_IC_DMA_CR_RDMAE_LSB _U(0)
+#define I2C_IC_DMA_CR_RDMAE_RESET _u(0x0)
+#define I2C_IC_DMA_CR_RDMAE_BITS _u(0x00000001)
+#define I2C_IC_DMA_CR_RDMAE_MSB _u(0)
+#define I2C_IC_DMA_CR_RDMAE_LSB _u(0)
#define I2C_IC_DMA_CR_RDMAE_ACCESS "RW"
-#define I2C_IC_DMA_CR_RDMAE_VALUE_DISABLED _U(0x0)
-#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED _U(0x1)
+#define I2C_IC_DMA_CR_RDMAE_VALUE_DISABLED _u(0x0)
+#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED _u(0x1)
// =============================================================================
// Register : I2C_IC_DMA_TDLR
// Description : DMA Transmit Data Level Register
-#define I2C_IC_DMA_TDLR_OFFSET _U(0x0000008c)
-#define I2C_IC_DMA_TDLR_BITS _U(0x0000000f)
-#define I2C_IC_DMA_TDLR_RESET _U(0x00000000)
+#define I2C_IC_DMA_TDLR_OFFSET _u(0x0000008c)
+#define I2C_IC_DMA_TDLR_BITS _u(0x0000000f)
+#define I2C_IC_DMA_TDLR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_DMA_TDLR_DMATDL
// Description : Transmit Data Level. This bit field controls the level at which
@@ -2326,17 +2326,17 @@
// equal to or below this field value, and TDMAE = 1.
//
// Reset value: 0x0
-#define I2C_IC_DMA_TDLR_DMATDL_RESET _U(0x0)
-#define I2C_IC_DMA_TDLR_DMATDL_BITS _U(0x0000000f)
-#define I2C_IC_DMA_TDLR_DMATDL_MSB _U(3)
-#define I2C_IC_DMA_TDLR_DMATDL_LSB _U(0)
+#define I2C_IC_DMA_TDLR_DMATDL_RESET _u(0x0)
+#define I2C_IC_DMA_TDLR_DMATDL_BITS _u(0x0000000f)
+#define I2C_IC_DMA_TDLR_DMATDL_MSB _u(3)
+#define I2C_IC_DMA_TDLR_DMATDL_LSB _u(0)
#define I2C_IC_DMA_TDLR_DMATDL_ACCESS "RW"
// =============================================================================
// Register : I2C_IC_DMA_RDLR
// Description : I2C Receive Data Level Register
-#define I2C_IC_DMA_RDLR_OFFSET _U(0x00000090)
-#define I2C_IC_DMA_RDLR_BITS _U(0x0000000f)
-#define I2C_IC_DMA_RDLR_RESET _U(0x00000000)
+#define I2C_IC_DMA_RDLR_OFFSET _u(0x00000090)
+#define I2C_IC_DMA_RDLR_BITS _u(0x0000000f)
+#define I2C_IC_DMA_RDLR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_DMA_RDLR_DMARDL
// Description : Receive Data Level. This bit field controls the level at which
@@ -2348,10 +2348,10 @@
// are present in the receive FIFO.
//
// Reset value: 0x0
-#define I2C_IC_DMA_RDLR_DMARDL_RESET _U(0x0)
-#define I2C_IC_DMA_RDLR_DMARDL_BITS _U(0x0000000f)
-#define I2C_IC_DMA_RDLR_DMARDL_MSB _U(3)
-#define I2C_IC_DMA_RDLR_DMARDL_LSB _U(0)
+#define I2C_IC_DMA_RDLR_DMARDL_RESET _u(0x0)
+#define I2C_IC_DMA_RDLR_DMARDL_BITS _u(0x0000000f)
+#define I2C_IC_DMA_RDLR_DMARDL_MSB _u(3)
+#define I2C_IC_DMA_RDLR_DMARDL_LSB _u(0)
#define I2C_IC_DMA_RDLR_DMARDL_ACCESS "RW"
// =============================================================================
// Register : I2C_IC_SDA_SETUP
@@ -2372,19 +2372,19 @@
// 10 ic_clk periods of setup time, they should program a value of
// 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c
// when operating as a slave transmitter.
-#define I2C_IC_SDA_SETUP_OFFSET _U(0x00000094)
-#define I2C_IC_SDA_SETUP_BITS _U(0x000000ff)
-#define I2C_IC_SDA_SETUP_RESET _U(0x00000064)
+#define I2C_IC_SDA_SETUP_OFFSET _u(0x00000094)
+#define I2C_IC_SDA_SETUP_BITS _u(0x000000ff)
+#define I2C_IC_SDA_SETUP_RESET _u(0x00000064)
// -----------------------------------------------------------------------------
// Field : I2C_IC_SDA_SETUP_SDA_SETUP
// Description : SDA Setup. It is recommended that if the required delay is
// 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP
// should be programmed to a value of 11. IC_SDA_SETUP must be
// programmed with a minimum value of 2.
-#define I2C_IC_SDA_SETUP_SDA_SETUP_RESET _U(0x64)
-#define I2C_IC_SDA_SETUP_SDA_SETUP_BITS _U(0x000000ff)
-#define I2C_IC_SDA_SETUP_SDA_SETUP_MSB _U(7)
-#define I2C_IC_SDA_SETUP_SDA_SETUP_LSB _U(0)
+#define I2C_IC_SDA_SETUP_SDA_SETUP_RESET _u(0x64)
+#define I2C_IC_SDA_SETUP_SDA_SETUP_BITS _u(0x000000ff)
+#define I2C_IC_SDA_SETUP_SDA_SETUP_MSB _u(7)
+#define I2C_IC_SDA_SETUP_SDA_SETUP_LSB _u(0)
#define I2C_IC_SDA_SETUP_SDA_SETUP_ACCESS "RW"
// =============================================================================
// Register : I2C_IC_ACK_GENERAL_CALL
@@ -2395,9 +2395,9 @@
//
// This register is applicable only when the DW_apb_i2c is in
// slave mode.
-#define I2C_IC_ACK_GENERAL_CALL_OFFSET _U(0x00000098)
-#define I2C_IC_ACK_GENERAL_CALL_BITS _U(0x00000001)
-#define I2C_IC_ACK_GENERAL_CALL_RESET _U(0x00000001)
+#define I2C_IC_ACK_GENERAL_CALL_OFFSET _u(0x00000098)
+#define I2C_IC_ACK_GENERAL_CALL_BITS _u(0x00000001)
+#define I2C_IC_ACK_GENERAL_CALL_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL
// Description : ACK General Call. When set to 1, DW_apb_i2c responds with a ACK
@@ -2406,13 +2406,13 @@
// ic_data_oe).
// 0x0 -> Generate NACK for a General Call
// 0x1 -> Generate ACK for a General Call
-#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET _U(0x1)
-#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS _U(0x00000001)
-#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB _U(0)
-#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB _U(0)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET _u(0x1)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS _u(0x00000001)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB _u(0)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB _u(0)
#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ACCESS "RW"
-#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_DISABLED _U(0x0)
-#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED _U(0x1)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_DISABLED _u(0x0)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED _u(0x1)
// =============================================================================
// Register : I2C_IC_ENABLE_STATUS
// Description : I2C Enable Status Register
@@ -2430,9 +2430,9 @@
// Note: When IC_ENABLE[0] has been set to 0, a delay occurs for
// bit 0 to be read as 0 because disabling the DW_apb_i2c depends
// on I2C bus activities.
-#define I2C_IC_ENABLE_STATUS_OFFSET _U(0x0000009c)
-#define I2C_IC_ENABLE_STATUS_BITS _U(0x00000007)
-#define I2C_IC_ENABLE_STATUS_RESET _U(0x00000000)
+#define I2C_IC_ENABLE_STATUS_OFFSET _u(0x0000009c)
+#define I2C_IC_ENABLE_STATUS_BITS _u(0x00000007)
+#define I2C_IC_ENABLE_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST
// Description : Slave Received Data Lost. This bit indicates if a
@@ -2459,13 +2459,13 @@
// Reset value: 0x0
// 0x0 -> Slave RX Data is not lost
// 0x1 -> Slave RX Data is lost
-#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET _U(0x0)
-#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS _U(0x00000004)
-#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB _U(2)
-#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB _U(2)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET _u(0x0)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS _u(0x00000004)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB _u(2)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB _u(2)
#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACCESS "RO"
-#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY
// Description : Slave Disabled While Busy (Transmit, Receive). This bit
@@ -2502,13 +2502,13 @@
// Reset value: 0x0
// 0x0 -> Slave is disabled when it is idle
// 0x1 -> Slave is disabled when it is active
-#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET _U(0x0)
-#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS _U(0x00000002)
-#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB _U(1)
-#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB _U(1)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET _u(0x0)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS _u(0x00000002)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB _u(1)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB _u(1)
#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACCESS "RO"
-#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_INACTIVE _U(0x0)
-#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE _U(0x1)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE _u(0x1)
// -----------------------------------------------------------------------------
// Field : I2C_IC_ENABLE_STATUS_IC_EN
// Description : ic_en Status. This bit always reflects the value driven on the
@@ -2521,13 +2521,13 @@
// Reset value: 0x0
// 0x0 -> I2C disabled
// 0x1 -> I2C enabled
-#define I2C_IC_ENABLE_STATUS_IC_EN_RESET _U(0x0)
-#define I2C_IC_ENABLE_STATUS_IC_EN_BITS _U(0x00000001)
-#define I2C_IC_ENABLE_STATUS_IC_EN_MSB _U(0)
-#define I2C_IC_ENABLE_STATUS_IC_EN_LSB _U(0)
+#define I2C_IC_ENABLE_STATUS_IC_EN_RESET _u(0x0)
+#define I2C_IC_ENABLE_STATUS_IC_EN_BITS _u(0x00000001)
+#define I2C_IC_ENABLE_STATUS_IC_EN_MSB _u(0)
+#define I2C_IC_ENABLE_STATUS_IC_EN_LSB _u(0)
#define I2C_IC_ENABLE_STATUS_IC_EN_ACCESS "RO"
-#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_DISABLED _U(0x0)
-#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED _U(0x1)
+#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_DISABLED _u(0x0)
+#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED _u(0x1)
// =============================================================================
// Register : I2C_IC_FS_SPKLEN
// Description : I2C SS, FS or FM+ spike suppression limit
@@ -2538,9 +2538,9 @@
// FM+ modes. The relevant I2C requirement is tSP (table 4) as
// detailed in the I2C Bus Specification. This register must be
// programmed with a minimum value of 1.
-#define I2C_IC_FS_SPKLEN_OFFSET _U(0x000000a0)
-#define I2C_IC_FS_SPKLEN_BITS _U(0x000000ff)
-#define I2C_IC_FS_SPKLEN_RESET _U(0x00000007)
+#define I2C_IC_FS_SPKLEN_OFFSET _u(0x000000a0)
+#define I2C_IC_FS_SPKLEN_BITS _u(0x000000ff)
+#define I2C_IC_FS_SPKLEN_RESET _u(0x00000007)
// -----------------------------------------------------------------------------
// Field : I2C_IC_FS_SPKLEN_IC_FS_SPKLEN
// Description : This register must be set before any I2C bus transaction can
@@ -2553,27 +2553,27 @@
// The minimum valid value is 1; hardware prevents values less
// than this being written, and if attempted results in 1 being
// set. or more information, refer to 'Spike Suppression'.
-#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_RESET _U(0x07)
-#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_BITS _U(0x000000ff)
-#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MSB _U(7)
-#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_LSB _U(0)
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_RESET _u(0x07)
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_BITS _u(0x000000ff)
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MSB _u(7)
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_LSB _u(0)
#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_ACCESS "RW"
// =============================================================================
// Register : I2C_IC_CLR_RESTART_DET
// Description : Clear RESTART_DET Interrupt Register
-#define I2C_IC_CLR_RESTART_DET_OFFSET _U(0x000000a8)
-#define I2C_IC_CLR_RESTART_DET_BITS _U(0x00000001)
-#define I2C_IC_CLR_RESTART_DET_RESET _U(0x00000000)
+#define I2C_IC_CLR_RESTART_DET_OFFSET _u(0x000000a8)
+#define I2C_IC_CLR_RESTART_DET_BITS _u(0x00000001)
+#define I2C_IC_CLR_RESTART_DET_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET
// Description : Read this register to clear the RESTART_DET interrupt (bit 12)
// of IC_RAW_INTR_STAT register.
//
// Reset value: 0x0
-#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_RESET _U(0x0)
-#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_BITS _U(0x00000001)
-#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_MSB _U(0)
-#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_LSB _U(0)
+#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_RESET _u(0x0)
+#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_BITS _u(0x00000001)
+#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_MSB _u(0)
+#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_LSB _u(0)
#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_ACCESS "RO"
// =============================================================================
// Register : I2C_IC_COMP_PARAM_1
@@ -2584,102 +2584,102 @@
// that contains encoded information about the component's
// parameter settings. Fields shown below are the settings for
// those parameters
-#define I2C_IC_COMP_PARAM_1_OFFSET _U(0x000000f4)
-#define I2C_IC_COMP_PARAM_1_BITS _U(0x00ffffff)
-#define I2C_IC_COMP_PARAM_1_RESET _U(0x00000000)
+#define I2C_IC_COMP_PARAM_1_OFFSET _u(0x000000f4)
+#define I2C_IC_COMP_PARAM_1_BITS _u(0x00ffffff)
+#define I2C_IC_COMP_PARAM_1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH
// Description : TX Buffer Depth = 16
-#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_RESET _U(0x00)
-#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_BITS _U(0x00ff0000)
-#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MSB _U(23)
-#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_LSB _U(16)
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_RESET _u(0x00)
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_BITS _u(0x00ff0000)
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MSB _u(23)
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_LSB _u(16)
#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH
// Description : RX Buffer Depth = 16
-#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_RESET _U(0x00)
-#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_BITS _U(0x0000ff00)
-#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MSB _U(15)
-#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_LSB _U(8)
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_RESET _u(0x00)
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_BITS _u(0x0000ff00)
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MSB _u(15)
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_LSB _u(8)
#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS
// Description : Encoded parameters not visible
-#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_RESET _U(0x0)
-#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_BITS _U(0x00000080)
-#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MSB _U(7)
-#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_LSB _U(7)
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_RESET _u(0x0)
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_BITS _u(0x00000080)
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MSB _u(7)
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_LSB _u(7)
#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : I2C_IC_COMP_PARAM_1_HAS_DMA
// Description : DMA handshaking signals are enabled
-#define I2C_IC_COMP_PARAM_1_HAS_DMA_RESET _U(0x0)
-#define I2C_IC_COMP_PARAM_1_HAS_DMA_BITS _U(0x00000040)
-#define I2C_IC_COMP_PARAM_1_HAS_DMA_MSB _U(6)
-#define I2C_IC_COMP_PARAM_1_HAS_DMA_LSB _U(6)
+#define I2C_IC_COMP_PARAM_1_HAS_DMA_RESET _u(0x0)
+#define I2C_IC_COMP_PARAM_1_HAS_DMA_BITS _u(0x00000040)
+#define I2C_IC_COMP_PARAM_1_HAS_DMA_MSB _u(6)
+#define I2C_IC_COMP_PARAM_1_HAS_DMA_LSB _u(6)
#define I2C_IC_COMP_PARAM_1_HAS_DMA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : I2C_IC_COMP_PARAM_1_INTR_IO
// Description : COMBINED Interrupt outputs
-#define I2C_IC_COMP_PARAM_1_INTR_IO_RESET _U(0x0)
-#define I2C_IC_COMP_PARAM_1_INTR_IO_BITS _U(0x00000020)
-#define I2C_IC_COMP_PARAM_1_INTR_IO_MSB _U(5)
-#define I2C_IC_COMP_PARAM_1_INTR_IO_LSB _U(5)
+#define I2C_IC_COMP_PARAM_1_INTR_IO_RESET _u(0x0)
+#define I2C_IC_COMP_PARAM_1_INTR_IO_BITS _u(0x00000020)
+#define I2C_IC_COMP_PARAM_1_INTR_IO_MSB _u(5)
+#define I2C_IC_COMP_PARAM_1_INTR_IO_LSB _u(5)
#define I2C_IC_COMP_PARAM_1_INTR_IO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES
// Description : Programmable count values for each mode.
-#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_RESET _U(0x0)
-#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_BITS _U(0x00000010)
-#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MSB _U(4)
-#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_LSB _U(4)
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_RESET _u(0x0)
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_BITS _u(0x00000010)
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MSB _u(4)
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_LSB _u(4)
#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE
// Description : MAX SPEED MODE = FAST MODE
-#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_RESET _U(0x0)
-#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_BITS _U(0x0000000c)
-#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MSB _U(3)
-#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_LSB _U(2)
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_RESET _u(0x0)
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_BITS _u(0x0000000c)
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MSB _u(3)
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_LSB _u(2)
#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH
// Description : APB data bus width is 32 bits
-#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_RESET _U(0x0)
-#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_BITS _U(0x00000003)
-#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MSB _U(1)
-#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_LSB _U(0)
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_RESET _u(0x0)
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_BITS _u(0x00000003)
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MSB _u(1)
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_LSB _u(0)
#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_ACCESS "RO"
// =============================================================================
// Register : I2C_IC_COMP_VERSION
// Description : I2C Component Version Register
-#define I2C_IC_COMP_VERSION_OFFSET _U(0x000000f8)
-#define I2C_IC_COMP_VERSION_BITS _U(0xffffffff)
-#define I2C_IC_COMP_VERSION_RESET _U(0x3230312a)
+#define I2C_IC_COMP_VERSION_OFFSET _u(0x000000f8)
+#define I2C_IC_COMP_VERSION_BITS _u(0xffffffff)
+#define I2C_IC_COMP_VERSION_RESET _u(0x3230312a)
// -----------------------------------------------------------------------------
// Field : I2C_IC_COMP_VERSION_IC_COMP_VERSION
// Description : None
-#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET _U(0x3230312a)
-#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS _U(0xffffffff)
-#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB _U(31)
-#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_LSB _U(0)
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET _u(0x3230312a)
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS _u(0xffffffff)
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB _u(31)
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_LSB _u(0)
#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_ACCESS "RO"
// =============================================================================
// Register : I2C_IC_COMP_TYPE
// Description : I2C Component Type Register
-#define I2C_IC_COMP_TYPE_OFFSET _U(0x000000fc)
-#define I2C_IC_COMP_TYPE_BITS _U(0xffffffff)
-#define I2C_IC_COMP_TYPE_RESET _U(0x44570140)
+#define I2C_IC_COMP_TYPE_OFFSET _u(0x000000fc)
+#define I2C_IC_COMP_TYPE_BITS _u(0xffffffff)
+#define I2C_IC_COMP_TYPE_RESET _u(0x44570140)
// -----------------------------------------------------------------------------
// Field : I2C_IC_COMP_TYPE_IC_COMP_TYPE
// Description : Designware Component Type number = 0x44_57_01_40. This assigned
// unique hex value is constant and is derived from the two ASCII
// letters 'DW' followed by a 16-bit unsigned number.
-#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_RESET _U(0x44570140)
-#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_BITS _U(0xffffffff)
-#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_MSB _U(31)
-#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB _U(0)
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_RESET _u(0x44570140)
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_BITS _u(0xffffffff)
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_MSB _u(31)
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB _u(0)
#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_I2C_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h b/src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h
index 1add65a..26f139e 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h
@@ -14,111 +14,111 @@
// =============================================================================
// Register : IO_BANK0_GPIO0_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO0_STATUS_OFFSET _U(0x00000000)
-#define IO_BANK0_GPIO0_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO0_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO0_STATUS_OFFSET _u(0x00000000)
+#define IO_BANK0_GPIO0_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO0_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO0_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO0_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO0_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO0_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO0_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO0_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO0_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO0_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO0_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO0_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO0_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO0_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO0_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO0_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO0_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO0_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO0_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO0_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO0_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO0_CTRL_OFFSET _U(0x00000004)
-#define IO_BANK0_GPIO0_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO0_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO0_CTRL_OFFSET _u(0x00000004)
+#define IO_BANK0_GPIO0_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO0_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO0_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO0_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO0_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO0_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO0_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO0_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO0_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO0_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO0_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO0_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -127,15 +127,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO0_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -143,15 +143,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO0_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -166,129 +166,129 @@
// 0x07 -> pio1_0
// 0x09 -> usb_muxing_overcurr_detect
// 0x1f -> null
-#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK _U(0x00)
-#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX _U(0x01)
-#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _U(0x02)
-#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _U(0x03)
-#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _U(0x04)
-#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 _U(0x05)
-#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _U(0x06)
-#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _U(0x07)
-#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _U(0x09)
-#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK _u(0x00)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 _u(0x05)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _u(0x06)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _u(0x07)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO1_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO1_STATUS_OFFSET _U(0x00000008)
-#define IO_BANK0_GPIO1_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO1_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO1_STATUS_OFFSET _u(0x00000008)
+#define IO_BANK0_GPIO1_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO1_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO1_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO1_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO1_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO1_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO1_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO1_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO1_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO1_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO1_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO1_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO1_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO1_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO1_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO1_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO1_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO1_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO1_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO1_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO1_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO1_CTRL_OFFSET _U(0x0000000c)
-#define IO_BANK0_GPIO1_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO1_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO1_CTRL_OFFSET _u(0x0000000c)
+#define IO_BANK0_GPIO1_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO1_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO1_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO1_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO1_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO1_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO1_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO1_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO1_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO1_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO1_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO1_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -297,15 +297,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO1_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -313,15 +313,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO1_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -336,129 +336,129 @@
// 0x07 -> pio1_1
// 0x09 -> usb_muxing_vbus_detect
// 0x1f -> null
-#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS _U(0x00)
-#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N _U(0x01)
-#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _U(0x02)
-#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _U(0x03)
-#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _U(0x04)
-#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 _U(0x05)
-#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _U(0x06)
-#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _U(0x07)
-#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _U(0x09)
-#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS _u(0x00)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 _u(0x05)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _u(0x06)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _u(0x07)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO2_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO2_STATUS_OFFSET _U(0x00000010)
-#define IO_BANK0_GPIO2_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO2_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO2_STATUS_OFFSET _u(0x00000010)
+#define IO_BANK0_GPIO2_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO2_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO2_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO2_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO2_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO2_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO2_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO2_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO2_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO2_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO2_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO2_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO2_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO2_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO2_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO2_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO2_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO2_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO2_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO2_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO2_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO2_CTRL_OFFSET _U(0x00000014)
-#define IO_BANK0_GPIO2_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO2_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO2_CTRL_OFFSET _u(0x00000014)
+#define IO_BANK0_GPIO2_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO2_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO2_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO2_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO2_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO2_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO2_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO2_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO2_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO2_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO2_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO2_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -467,15 +467,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO2_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -483,15 +483,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO2_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -506,129 +506,129 @@
// 0x07 -> pio1_2
// 0x09 -> usb_muxing_vbus_en
// 0x1f -> null
-#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI _U(0x00)
-#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK _U(0x01)
-#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _U(0x02)
-#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _U(0x03)
-#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _U(0x04)
-#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 _U(0x05)
-#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _U(0x06)
-#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _U(0x07)
-#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _U(0x09)
-#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI _u(0x00)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 _u(0x05)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _u(0x06)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _u(0x07)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO3_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO3_STATUS_OFFSET _U(0x00000018)
-#define IO_BANK0_GPIO3_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO3_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO3_STATUS_OFFSET _u(0x00000018)
+#define IO_BANK0_GPIO3_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO3_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO3_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO3_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO3_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO3_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO3_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO3_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO3_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO3_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO3_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO3_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO3_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO3_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO3_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO3_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO3_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO3_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO3_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO3_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO3_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO3_CTRL_OFFSET _U(0x0000001c)
-#define IO_BANK0_GPIO3_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO3_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO3_CTRL_OFFSET _u(0x0000001c)
+#define IO_BANK0_GPIO3_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO3_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO3_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO3_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO3_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO3_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO3_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO3_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO3_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO3_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO3_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO3_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -637,15 +637,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO3_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -653,15 +653,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO3_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -676,129 +676,129 @@
// 0x07 -> pio1_3
// 0x09 -> usb_muxing_overcurr_detect
// 0x1f -> null
-#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO _U(0x00)
-#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX _U(0x01)
-#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _U(0x02)
-#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _U(0x03)
-#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _U(0x04)
-#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 _U(0x05)
-#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _U(0x06)
-#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _U(0x07)
-#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _U(0x09)
-#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO _u(0x00)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 _u(0x05)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _u(0x06)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _u(0x07)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO4_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO4_STATUS_OFFSET _U(0x00000020)
-#define IO_BANK0_GPIO4_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO4_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO4_STATUS_OFFSET _u(0x00000020)
+#define IO_BANK0_GPIO4_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO4_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO4_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO4_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO4_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO4_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO4_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO4_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO4_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO4_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO4_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO4_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO4_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO4_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO4_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO4_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO4_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO4_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO4_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO4_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO4_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO4_CTRL_OFFSET _U(0x00000024)
-#define IO_BANK0_GPIO4_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO4_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO4_CTRL_OFFSET _u(0x00000024)
+#define IO_BANK0_GPIO4_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO4_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO4_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO4_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO4_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO4_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO4_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO4_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO4_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO4_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO4_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO4_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -807,15 +807,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO4_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -823,15 +823,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO4_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -845,128 +845,128 @@
// 0x07 -> pio1_4
// 0x09 -> usb_muxing_vbus_detect
// 0x1f -> null
-#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX _U(0x01)
-#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _U(0x02)
-#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _U(0x03)
-#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _U(0x04)
-#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 _U(0x05)
-#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _U(0x06)
-#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _U(0x07)
-#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _U(0x09)
-#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 _u(0x05)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _u(0x06)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _u(0x07)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO5_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO5_STATUS_OFFSET _U(0x00000028)
-#define IO_BANK0_GPIO5_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO5_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO5_STATUS_OFFSET _u(0x00000028)
+#define IO_BANK0_GPIO5_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO5_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO5_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO5_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO5_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO5_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO5_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO5_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO5_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO5_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO5_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO5_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO5_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO5_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO5_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO5_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO5_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO5_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO5_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO5_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO5_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO5_CTRL_OFFSET _U(0x0000002c)
-#define IO_BANK0_GPIO5_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO5_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO5_CTRL_OFFSET _u(0x0000002c)
+#define IO_BANK0_GPIO5_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO5_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO5_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO5_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO5_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO5_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO5_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO5_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO5_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO5_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO5_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO5_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -975,15 +975,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO5_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -991,15 +991,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO5_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -1013,128 +1013,128 @@
// 0x07 -> pio1_5
// 0x09 -> usb_muxing_vbus_en
// 0x1f -> null
-#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N _U(0x01)
-#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _U(0x02)
-#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _U(0x03)
-#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _U(0x04)
-#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 _U(0x05)
-#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _U(0x06)
-#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _U(0x07)
-#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _U(0x09)
-#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 _u(0x05)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _u(0x06)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _u(0x07)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO6_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO6_STATUS_OFFSET _U(0x00000030)
-#define IO_BANK0_GPIO6_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO6_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO6_STATUS_OFFSET _u(0x00000030)
+#define IO_BANK0_GPIO6_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO6_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO6_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO6_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO6_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO6_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO6_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO6_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO6_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO6_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO6_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO6_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO6_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO6_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO6_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO6_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO6_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO6_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO6_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO6_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO6_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO6_CTRL_OFFSET _U(0x00000034)
-#define IO_BANK0_GPIO6_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO6_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO6_CTRL_OFFSET _u(0x00000034)
+#define IO_BANK0_GPIO6_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO6_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO6_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO6_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO6_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO6_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO6_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO6_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO6_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO6_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO6_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO6_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -1143,15 +1143,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO6_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -1159,15 +1159,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO6_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -1182,129 +1182,129 @@
// 0x08 -> usb_muxing_extphy_softcon
// 0x09 -> usb_muxing_overcurr_detect
// 0x1f -> null
-#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK _U(0x01)
-#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _U(0x02)
-#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _U(0x03)
-#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _U(0x04)
-#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 _U(0x05)
-#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _U(0x06)
-#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _U(0x07)
-#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON _U(0x08)
-#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _U(0x09)
-#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 _u(0x05)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _u(0x06)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _u(0x07)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON _u(0x08)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO7_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO7_STATUS_OFFSET _U(0x00000038)
-#define IO_BANK0_GPIO7_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO7_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO7_STATUS_OFFSET _u(0x00000038)
+#define IO_BANK0_GPIO7_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO7_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO7_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO7_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO7_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO7_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO7_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO7_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO7_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO7_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO7_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO7_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO7_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO7_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO7_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO7_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO7_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO7_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO7_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO7_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO7_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO7_CTRL_OFFSET _U(0x0000003c)
-#define IO_BANK0_GPIO7_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO7_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO7_CTRL_OFFSET _u(0x0000003c)
+#define IO_BANK0_GPIO7_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO7_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO7_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO7_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO7_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO7_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO7_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO7_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO7_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO7_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO7_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO7_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -1313,15 +1313,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO7_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -1329,15 +1329,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO7_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -1352,129 +1352,129 @@
// 0x08 -> usb_muxing_extphy_oe_n
// 0x09 -> usb_muxing_vbus_detect
// 0x1f -> null
-#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX _U(0x01)
-#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _U(0x02)
-#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _U(0x03)
-#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _U(0x04)
-#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 _U(0x05)
-#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _U(0x06)
-#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _U(0x07)
-#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_OE_N _U(0x08)
-#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _U(0x09)
-#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 _u(0x05)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _u(0x06)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _u(0x07)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_OE_N _u(0x08)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO8_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO8_STATUS_OFFSET _U(0x00000040)
-#define IO_BANK0_GPIO8_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO8_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO8_STATUS_OFFSET _u(0x00000040)
+#define IO_BANK0_GPIO8_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO8_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO8_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO8_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO8_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO8_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO8_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO8_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO8_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO8_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO8_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO8_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO8_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO8_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO8_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO8_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO8_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO8_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO8_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO8_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO8_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO8_CTRL_OFFSET _U(0x00000044)
-#define IO_BANK0_GPIO8_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO8_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO8_CTRL_OFFSET _u(0x00000044)
+#define IO_BANK0_GPIO8_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO8_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO8_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO8_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO8_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO8_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO8_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO8_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO8_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO8_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO8_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO8_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -1483,15 +1483,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO8_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -1499,15 +1499,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO8_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -1522,129 +1522,129 @@
// 0x08 -> usb_muxing_extphy_rcv
// 0x09 -> usb_muxing_vbus_en
// 0x1f -> null
-#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX _U(0x01)
-#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _U(0x02)
-#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _U(0x03)
-#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _U(0x04)
-#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 _U(0x05)
-#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _U(0x06)
-#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _U(0x07)
-#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_RCV _U(0x08)
-#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _U(0x09)
-#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 _u(0x05)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _u(0x06)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _u(0x07)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_RCV _u(0x08)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO9_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO9_STATUS_OFFSET _U(0x00000048)
-#define IO_BANK0_GPIO9_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO9_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO9_STATUS_OFFSET _u(0x00000048)
+#define IO_BANK0_GPIO9_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO9_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO9_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO9_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO9_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO9_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO9_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO9_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO9_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO9_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO9_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO9_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO9_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO9_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO9_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO9_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO9_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO9_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO9_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO9_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO9_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO9_CTRL_OFFSET _U(0x0000004c)
-#define IO_BANK0_GPIO9_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO9_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO9_CTRL_OFFSET _u(0x0000004c)
+#define IO_BANK0_GPIO9_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO9_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO9_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO9_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO9_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO9_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO9_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO9_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO9_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO9_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO9_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO9_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -1653,15 +1653,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO9_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -1669,15 +1669,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO9_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -1692,129 +1692,129 @@
// 0x08 -> usb_muxing_extphy_vp
// 0x09 -> usb_muxing_overcurr_detect
// 0x1f -> null
-#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N _U(0x01)
-#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _U(0x02)
-#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _U(0x03)
-#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _U(0x04)
-#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 _U(0x05)
-#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _U(0x06)
-#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _U(0x07)
-#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP _U(0x08)
-#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _U(0x09)
-#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 _u(0x05)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _u(0x06)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _u(0x07)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP _u(0x08)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO10_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO10_STATUS_OFFSET _U(0x00000050)
-#define IO_BANK0_GPIO10_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO10_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO10_STATUS_OFFSET _u(0x00000050)
+#define IO_BANK0_GPIO10_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO10_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO10_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO10_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO10_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO10_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO10_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO10_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO10_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO10_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO10_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO10_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO10_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO10_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO10_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO10_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO10_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO10_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO10_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO10_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO10_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO10_CTRL_OFFSET _U(0x00000054)
-#define IO_BANK0_GPIO10_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO10_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO10_CTRL_OFFSET _u(0x00000054)
+#define IO_BANK0_GPIO10_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO10_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO10_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO10_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO10_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO10_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO10_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO10_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO10_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO10_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO10_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO10_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -1823,15 +1823,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO10_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -1839,15 +1839,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO10_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -1862,129 +1862,129 @@
// 0x08 -> usb_muxing_extphy_vm
// 0x09 -> usb_muxing_vbus_detect
// 0x1f -> null
-#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK _U(0x01)
-#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _U(0x02)
-#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _U(0x03)
-#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _U(0x04)
-#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 _U(0x05)
-#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _U(0x06)
-#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _U(0x07)
-#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM _U(0x08)
-#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _U(0x09)
-#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 _u(0x05)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _u(0x06)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _u(0x07)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM _u(0x08)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO11_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO11_STATUS_OFFSET _U(0x00000058)
-#define IO_BANK0_GPIO11_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO11_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO11_STATUS_OFFSET _u(0x00000058)
+#define IO_BANK0_GPIO11_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO11_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO11_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO11_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO11_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO11_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO11_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO11_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO11_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO11_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO11_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO11_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO11_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO11_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO11_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO11_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO11_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO11_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO11_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO11_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO11_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO11_CTRL_OFFSET _U(0x0000005c)
-#define IO_BANK0_GPIO11_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO11_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO11_CTRL_OFFSET _u(0x0000005c)
+#define IO_BANK0_GPIO11_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO11_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO11_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO11_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO11_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO11_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO11_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO11_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO11_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO11_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO11_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO11_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -1993,15 +1993,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO11_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -2009,15 +2009,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO11_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -2032,129 +2032,129 @@
// 0x08 -> usb_muxing_extphy_suspnd
// 0x09 -> usb_muxing_vbus_en
// 0x1f -> null
-#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX _U(0x01)
-#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _U(0x02)
-#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _U(0x03)
-#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _U(0x04)
-#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 _U(0x05)
-#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _U(0x06)
-#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _U(0x07)
-#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SUSPND _U(0x08)
-#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _U(0x09)
-#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 _u(0x05)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _u(0x06)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _u(0x07)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SUSPND _u(0x08)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO12_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO12_STATUS_OFFSET _U(0x00000060)
-#define IO_BANK0_GPIO12_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO12_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO12_STATUS_OFFSET _u(0x00000060)
+#define IO_BANK0_GPIO12_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO12_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO12_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO12_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO12_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO12_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO12_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO12_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO12_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO12_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO12_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO12_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO12_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO12_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO12_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO12_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO12_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO12_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO12_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO12_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO12_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO12_CTRL_OFFSET _U(0x00000064)
-#define IO_BANK0_GPIO12_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO12_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO12_CTRL_OFFSET _u(0x00000064)
+#define IO_BANK0_GPIO12_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO12_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO12_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO12_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO12_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO12_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO12_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO12_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO12_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO12_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO12_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO12_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -2163,15 +2163,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO12_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -2179,15 +2179,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO12_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -2202,129 +2202,129 @@
// 0x08 -> usb_muxing_extphy_speed
// 0x09 -> usb_muxing_overcurr_detect
// 0x1f -> null
-#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX _U(0x01)
-#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _U(0x02)
-#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _U(0x03)
-#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _U(0x04)
-#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 _U(0x05)
-#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _U(0x06)
-#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _U(0x07)
-#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED _U(0x08)
-#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _U(0x09)
-#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 _u(0x05)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _u(0x06)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _u(0x07)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED _u(0x08)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO13_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO13_STATUS_OFFSET _U(0x00000068)
-#define IO_BANK0_GPIO13_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO13_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO13_STATUS_OFFSET _u(0x00000068)
+#define IO_BANK0_GPIO13_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO13_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO13_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO13_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO13_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO13_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO13_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO13_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO13_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO13_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO13_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO13_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO13_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO13_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO13_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO13_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO13_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO13_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO13_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO13_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO13_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO13_CTRL_OFFSET _U(0x0000006c)
-#define IO_BANK0_GPIO13_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO13_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO13_CTRL_OFFSET _u(0x0000006c)
+#define IO_BANK0_GPIO13_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO13_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO13_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO13_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO13_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO13_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO13_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO13_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO13_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO13_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO13_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO13_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -2333,15 +2333,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO13_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -2349,15 +2349,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO13_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -2372,129 +2372,129 @@
// 0x08 -> usb_muxing_extphy_vpo
// 0x09 -> usb_muxing_vbus_detect
// 0x1f -> null
-#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N _U(0x01)
-#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _U(0x02)
-#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _U(0x03)
-#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _U(0x04)
-#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 _U(0x05)
-#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _U(0x06)
-#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _U(0x07)
-#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO _U(0x08)
-#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _U(0x09)
-#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 _u(0x05)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _u(0x06)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _u(0x07)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO _u(0x08)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO14_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO14_STATUS_OFFSET _U(0x00000070)
-#define IO_BANK0_GPIO14_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO14_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO14_STATUS_OFFSET _u(0x00000070)
+#define IO_BANK0_GPIO14_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO14_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO14_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO14_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO14_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO14_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO14_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO14_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO14_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO14_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO14_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO14_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO14_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO14_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO14_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO14_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO14_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO14_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO14_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO14_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO14_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO14_CTRL_OFFSET _U(0x00000074)
-#define IO_BANK0_GPIO14_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO14_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO14_CTRL_OFFSET _u(0x00000074)
+#define IO_BANK0_GPIO14_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO14_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO14_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO14_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO14_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO14_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO14_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO14_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO14_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO14_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO14_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO14_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -2503,15 +2503,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO14_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -2519,15 +2519,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO14_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -2542,129 +2542,129 @@
// 0x08 -> usb_muxing_extphy_vmo
// 0x09 -> usb_muxing_vbus_en
// 0x1f -> null
-#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK _U(0x01)
-#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _U(0x02)
-#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _U(0x03)
-#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _U(0x04)
-#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 _U(0x05)
-#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _U(0x06)
-#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _U(0x07)
-#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VMO _U(0x08)
-#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _U(0x09)
-#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 _u(0x05)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _u(0x06)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _u(0x07)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VMO _u(0x08)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO15_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO15_STATUS_OFFSET _U(0x00000078)
-#define IO_BANK0_GPIO15_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO15_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO15_STATUS_OFFSET _u(0x00000078)
+#define IO_BANK0_GPIO15_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO15_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO15_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO15_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO15_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO15_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO15_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO15_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO15_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO15_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO15_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO15_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO15_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO15_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO15_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO15_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO15_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO15_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO15_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO15_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO15_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO15_CTRL_OFFSET _U(0x0000007c)
-#define IO_BANK0_GPIO15_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO15_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO15_CTRL_OFFSET _u(0x0000007c)
+#define IO_BANK0_GPIO15_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO15_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO15_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO15_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO15_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO15_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO15_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO15_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO15_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO15_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO15_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO15_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -2673,15 +2673,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO15_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -2689,15 +2689,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO15_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -2712,129 +2712,129 @@
// 0x08 -> usb_muxing_digital_dp
// 0x09 -> usb_muxing_overcurr_detect
// 0x1f -> null
-#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX _U(0x01)
-#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _U(0x02)
-#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _U(0x03)
-#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _U(0x04)
-#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 _U(0x05)
-#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _U(0x06)
-#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _U(0x07)
-#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP _U(0x08)
-#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _U(0x09)
-#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 _u(0x05)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _u(0x06)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _u(0x07)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP _u(0x08)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO16_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO16_STATUS_OFFSET _U(0x00000080)
-#define IO_BANK0_GPIO16_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO16_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO16_STATUS_OFFSET _u(0x00000080)
+#define IO_BANK0_GPIO16_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO16_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO16_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO16_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO16_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO16_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO16_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO16_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO16_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO16_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO16_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO16_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO16_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO16_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO16_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO16_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO16_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO16_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO16_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO16_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO16_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO16_CTRL_OFFSET _U(0x00000084)
-#define IO_BANK0_GPIO16_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO16_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO16_CTRL_OFFSET _u(0x00000084)
+#define IO_BANK0_GPIO16_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO16_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO16_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO16_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO16_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO16_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO16_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO16_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO16_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO16_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO16_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO16_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -2843,15 +2843,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO16_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -2859,15 +2859,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO16_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -2882,129 +2882,129 @@
// 0x08 -> usb_muxing_digital_dm
// 0x09 -> usb_muxing_vbus_detect
// 0x1f -> null
-#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX _U(0x01)
-#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _U(0x02)
-#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _U(0x03)
-#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _U(0x04)
-#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 _U(0x05)
-#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _U(0x06)
-#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _U(0x07)
-#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM _U(0x08)
-#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _U(0x09)
-#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 _u(0x05)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _u(0x06)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _u(0x07)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM _u(0x08)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO17_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO17_STATUS_OFFSET _U(0x00000088)
-#define IO_BANK0_GPIO17_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO17_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO17_STATUS_OFFSET _u(0x00000088)
+#define IO_BANK0_GPIO17_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO17_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO17_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO17_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO17_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO17_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO17_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO17_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO17_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO17_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO17_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO17_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO17_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO17_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO17_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO17_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO17_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO17_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO17_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO17_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO17_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO17_CTRL_OFFSET _U(0x0000008c)
-#define IO_BANK0_GPIO17_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO17_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO17_CTRL_OFFSET _u(0x0000008c)
+#define IO_BANK0_GPIO17_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO17_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO17_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO17_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO17_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO17_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO17_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO17_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO17_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO17_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO17_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO17_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -3013,15 +3013,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO17_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -3029,15 +3029,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO17_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -3051,128 +3051,128 @@
// 0x07 -> pio1_17
// 0x09 -> usb_muxing_vbus_en
// 0x1f -> null
-#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N _U(0x01)
-#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _U(0x02)
-#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _U(0x03)
-#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _U(0x04)
-#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 _U(0x05)
-#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _U(0x06)
-#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _U(0x07)
-#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _U(0x09)
-#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 _u(0x05)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _u(0x06)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _u(0x07)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO18_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO18_STATUS_OFFSET _U(0x00000090)
-#define IO_BANK0_GPIO18_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO18_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO18_STATUS_OFFSET _u(0x00000090)
+#define IO_BANK0_GPIO18_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO18_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO18_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO18_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO18_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO18_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO18_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO18_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO18_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO18_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO18_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO18_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO18_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO18_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO18_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO18_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO18_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO18_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO18_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO18_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO18_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO18_CTRL_OFFSET _U(0x00000094)
-#define IO_BANK0_GPIO18_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO18_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO18_CTRL_OFFSET _u(0x00000094)
+#define IO_BANK0_GPIO18_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO18_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO18_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO18_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO18_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO18_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO18_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO18_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO18_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO18_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO18_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO18_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -3181,15 +3181,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO18_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -3197,15 +3197,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO18_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -3219,128 +3219,128 @@
// 0x07 -> pio1_18
// 0x09 -> usb_muxing_overcurr_detect
// 0x1f -> null
-#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK _U(0x01)
-#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _U(0x02)
-#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _U(0x03)
-#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _U(0x04)
-#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 _U(0x05)
-#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _U(0x06)
-#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _U(0x07)
-#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _U(0x09)
-#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 _u(0x05)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _u(0x06)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _u(0x07)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO19_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO19_STATUS_OFFSET _U(0x00000098)
-#define IO_BANK0_GPIO19_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO19_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO19_STATUS_OFFSET _u(0x00000098)
+#define IO_BANK0_GPIO19_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO19_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO19_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO19_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO19_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO19_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO19_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO19_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO19_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO19_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO19_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO19_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO19_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO19_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO19_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO19_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO19_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO19_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO19_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO19_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO19_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO19_CTRL_OFFSET _U(0x0000009c)
-#define IO_BANK0_GPIO19_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO19_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO19_CTRL_OFFSET _u(0x0000009c)
+#define IO_BANK0_GPIO19_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO19_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO19_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO19_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO19_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO19_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO19_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO19_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO19_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO19_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO19_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO19_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -3349,15 +3349,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO19_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -3365,15 +3365,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO19_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -3387,128 +3387,128 @@
// 0x07 -> pio1_19
// 0x09 -> usb_muxing_vbus_detect
// 0x1f -> null
-#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX _U(0x01)
-#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _U(0x02)
-#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _U(0x03)
-#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _U(0x04)
-#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 _U(0x05)
-#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _U(0x06)
-#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _U(0x07)
-#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _U(0x09)
-#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 _u(0x05)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _u(0x06)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _u(0x07)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO20_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO20_STATUS_OFFSET _U(0x000000a0)
-#define IO_BANK0_GPIO20_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO20_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO20_STATUS_OFFSET _u(0x000000a0)
+#define IO_BANK0_GPIO20_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO20_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO20_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO20_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO20_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO20_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO20_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO20_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO20_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO20_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO20_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO20_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO20_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO20_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO20_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO20_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO20_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO20_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO20_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO20_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO20_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO20_CTRL_OFFSET _U(0x000000a4)
-#define IO_BANK0_GPIO20_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO20_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO20_CTRL_OFFSET _u(0x000000a4)
+#define IO_BANK0_GPIO20_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO20_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO20_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO20_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO20_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO20_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO20_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO20_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO20_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO20_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO20_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO20_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -3517,15 +3517,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO20_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -3533,15 +3533,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO20_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -3556,129 +3556,129 @@
// 0x08 -> clocks_gpin_0
// 0x09 -> usb_muxing_vbus_en
// 0x1f -> null
-#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX _U(0x01)
-#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _U(0x02)
-#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _U(0x03)
-#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _U(0x04)
-#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20 _U(0x05)
-#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _U(0x06)
-#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _U(0x07)
-#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _U(0x08)
-#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _U(0x09)
-#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20 _u(0x05)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _u(0x06)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _u(0x07)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x08)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO21_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO21_STATUS_OFFSET _U(0x000000a8)
-#define IO_BANK0_GPIO21_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO21_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO21_STATUS_OFFSET _u(0x000000a8)
+#define IO_BANK0_GPIO21_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO21_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO21_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO21_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO21_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO21_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO21_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO21_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO21_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO21_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO21_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO21_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO21_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO21_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO21_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO21_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO21_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO21_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO21_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO21_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO21_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO21_CTRL_OFFSET _U(0x000000ac)
-#define IO_BANK0_GPIO21_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO21_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO21_CTRL_OFFSET _u(0x000000ac)
+#define IO_BANK0_GPIO21_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO21_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO21_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO21_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO21_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO21_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO21_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO21_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO21_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO21_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO21_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO21_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -3687,15 +3687,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO21_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -3703,15 +3703,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO21_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -3726,129 +3726,129 @@
// 0x08 -> clocks_gpout_0
// 0x09 -> usb_muxing_overcurr_detect
// 0x1f -> null
-#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N _U(0x01)
-#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _U(0x02)
-#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _U(0x03)
-#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _U(0x04)
-#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21 _U(0x05)
-#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _U(0x06)
-#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _U(0x07)
-#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _U(0x08)
-#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _U(0x09)
-#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21 _u(0x05)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _u(0x06)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _u(0x07)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x08)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO22_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO22_STATUS_OFFSET _U(0x000000b0)
-#define IO_BANK0_GPIO22_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO22_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO22_STATUS_OFFSET _u(0x000000b0)
+#define IO_BANK0_GPIO22_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO22_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO22_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO22_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO22_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO22_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO22_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO22_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO22_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO22_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO22_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO22_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO22_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO22_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO22_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO22_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO22_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO22_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO22_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO22_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO22_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO22_CTRL_OFFSET _U(0x000000b4)
-#define IO_BANK0_GPIO22_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO22_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO22_CTRL_OFFSET _u(0x000000b4)
+#define IO_BANK0_GPIO22_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO22_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO22_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO22_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO22_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO22_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO22_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO22_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO22_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO22_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO22_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO22_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -3857,15 +3857,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO22_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -3873,15 +3873,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO22_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -3896,129 +3896,129 @@
// 0x08 -> clocks_gpin_1
// 0x09 -> usb_muxing_vbus_detect
// 0x1f -> null
-#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK _U(0x01)
-#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _U(0x02)
-#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _U(0x03)
-#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _U(0x04)
-#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22 _U(0x05)
-#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _U(0x06)
-#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _U(0x07)
-#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _U(0x08)
-#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _U(0x09)
-#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22 _u(0x05)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _u(0x06)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _u(0x07)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x08)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO23_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO23_STATUS_OFFSET _U(0x000000b8)
-#define IO_BANK0_GPIO23_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO23_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO23_STATUS_OFFSET _u(0x000000b8)
+#define IO_BANK0_GPIO23_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO23_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO23_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO23_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO23_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO23_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO23_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO23_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO23_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO23_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO23_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO23_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO23_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO23_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO23_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO23_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO23_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO23_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO23_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO23_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO23_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO23_CTRL_OFFSET _U(0x000000bc)
-#define IO_BANK0_GPIO23_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO23_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO23_CTRL_OFFSET _u(0x000000bc)
+#define IO_BANK0_GPIO23_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO23_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO23_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO23_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO23_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO23_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO23_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO23_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO23_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO23_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO23_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO23_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -4027,15 +4027,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO23_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -4043,15 +4043,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO23_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -4066,129 +4066,129 @@
// 0x08 -> clocks_gpout_1
// 0x09 -> usb_muxing_vbus_en
// 0x1f -> null
-#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX _U(0x01)
-#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS _U(0x02)
-#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL _U(0x03)
-#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 _U(0x04)
-#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23 _U(0x05)
-#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 _U(0x06)
-#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 _U(0x07)
-#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _U(0x08)
-#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _U(0x09)
-#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23 _u(0x05)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 _u(0x06)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 _u(0x07)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x08)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO24_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO24_STATUS_OFFSET _U(0x000000c0)
-#define IO_BANK0_GPIO24_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO24_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO24_STATUS_OFFSET _u(0x000000c0)
+#define IO_BANK0_GPIO24_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO24_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO24_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO24_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO24_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO24_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO24_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO24_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO24_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO24_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO24_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO24_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO24_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO24_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO24_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO24_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO24_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO24_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO24_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO24_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO24_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO24_CTRL_OFFSET _U(0x000000c4)
-#define IO_BANK0_GPIO24_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO24_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO24_CTRL_OFFSET _u(0x000000c4)
+#define IO_BANK0_GPIO24_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO24_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO24_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO24_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO24_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO24_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO24_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO24_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO24_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO24_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO24_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO24_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -4197,15 +4197,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO24_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -4213,15 +4213,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO24_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -4236,129 +4236,129 @@
// 0x08 -> clocks_gpout_2
// 0x09 -> usb_muxing_overcurr_detect
// 0x1f -> null
-#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX _U(0x01)
-#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX _U(0x02)
-#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA _U(0x03)
-#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 _U(0x04)
-#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24 _U(0x05)
-#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 _U(0x06)
-#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 _U(0x07)
-#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 _U(0x08)
-#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _U(0x09)
-#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24 _u(0x05)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 _u(0x06)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 _u(0x07)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 _u(0x08)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO25_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO25_STATUS_OFFSET _U(0x000000c8)
-#define IO_BANK0_GPIO25_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO25_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO25_STATUS_OFFSET _u(0x000000c8)
+#define IO_BANK0_GPIO25_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO25_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO25_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO25_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO25_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO25_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO25_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO25_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO25_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO25_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO25_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO25_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO25_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO25_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO25_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO25_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO25_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO25_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO25_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO25_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO25_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO25_CTRL_OFFSET _U(0x000000cc)
-#define IO_BANK0_GPIO25_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO25_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO25_CTRL_OFFSET _u(0x000000cc)
+#define IO_BANK0_GPIO25_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO25_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO25_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO25_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO25_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO25_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO25_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO25_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO25_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO25_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO25_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO25_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -4367,15 +4367,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO25_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -4383,15 +4383,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO25_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -4406,129 +4406,129 @@
// 0x08 -> clocks_gpout_3
// 0x09 -> usb_muxing_vbus_detect
// 0x1f -> null
-#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N _U(0x01)
-#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX _U(0x02)
-#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL _U(0x03)
-#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 _U(0x04)
-#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25 _U(0x05)
-#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 _U(0x06)
-#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 _U(0x07)
-#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 _U(0x08)
-#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _U(0x09)
-#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25 _u(0x05)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 _u(0x06)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 _u(0x07)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 _u(0x08)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO26_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO26_STATUS_OFFSET _U(0x000000d0)
-#define IO_BANK0_GPIO26_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO26_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO26_STATUS_OFFSET _u(0x000000d0)
+#define IO_BANK0_GPIO26_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO26_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO26_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO26_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO26_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO26_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO26_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO26_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO26_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO26_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO26_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO26_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO26_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO26_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO26_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO26_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO26_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO26_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO26_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO26_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO26_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO26_CTRL_OFFSET _U(0x000000d4)
-#define IO_BANK0_GPIO26_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO26_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO26_CTRL_OFFSET _u(0x000000d4)
+#define IO_BANK0_GPIO26_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO26_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO26_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO26_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO26_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO26_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO26_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO26_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO26_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO26_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO26_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO26_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -4537,15 +4537,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO26_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -4553,15 +4553,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO26_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -4575,128 +4575,128 @@
// 0x07 -> pio1_26
// 0x09 -> usb_muxing_vbus_en
// 0x1f -> null
-#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK _U(0x01)
-#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS _U(0x02)
-#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA _U(0x03)
-#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 _U(0x04)
-#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26 _U(0x05)
-#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 _U(0x06)
-#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 _U(0x07)
-#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _U(0x09)
-#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26 _u(0x05)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 _u(0x06)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 _u(0x07)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO27_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO27_STATUS_OFFSET _U(0x000000d8)
-#define IO_BANK0_GPIO27_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO27_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO27_STATUS_OFFSET _u(0x000000d8)
+#define IO_BANK0_GPIO27_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO27_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO27_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO27_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO27_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO27_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO27_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO27_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO27_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO27_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO27_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO27_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO27_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO27_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO27_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO27_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO27_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO27_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO27_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO27_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO27_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO27_CTRL_OFFSET _U(0x000000dc)
-#define IO_BANK0_GPIO27_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO27_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO27_CTRL_OFFSET _u(0x000000dc)
+#define IO_BANK0_GPIO27_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO27_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO27_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO27_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO27_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO27_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO27_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO27_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO27_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO27_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO27_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO27_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -4705,15 +4705,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO27_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -4721,15 +4721,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO27_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -4743,128 +4743,128 @@
// 0x07 -> pio1_27
// 0x09 -> usb_muxing_overcurr_detect
// 0x1f -> null
-#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX _U(0x01)
-#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS _U(0x02)
-#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL _U(0x03)
-#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 _U(0x04)
-#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27 _U(0x05)
-#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 _U(0x06)
-#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 _U(0x07)
-#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _U(0x09)
-#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27 _u(0x05)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 _u(0x06)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 _u(0x07)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO28_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO28_STATUS_OFFSET _U(0x000000e0)
-#define IO_BANK0_GPIO28_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO28_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO28_STATUS_OFFSET _u(0x000000e0)
+#define IO_BANK0_GPIO28_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO28_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO28_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO28_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO28_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO28_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO28_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO28_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO28_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO28_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO28_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO28_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO28_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO28_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO28_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO28_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO28_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO28_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO28_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO28_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO28_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO28_CTRL_OFFSET _U(0x000000e4)
-#define IO_BANK0_GPIO28_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO28_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO28_CTRL_OFFSET _u(0x000000e4)
+#define IO_BANK0_GPIO28_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO28_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO28_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO28_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO28_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO28_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO28_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO28_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO28_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO28_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO28_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO28_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -4873,15 +4873,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO28_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -4889,15 +4889,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO28_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -4911,128 +4911,128 @@
// 0x07 -> pio1_28
// 0x09 -> usb_muxing_vbus_detect
// 0x1f -> null
-#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX _U(0x01)
-#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX _U(0x02)
-#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA _U(0x03)
-#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 _U(0x04)
-#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28 _U(0x05)
-#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 _U(0x06)
-#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 _U(0x07)
-#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _U(0x09)
-#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28 _u(0x05)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 _u(0x06)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 _u(0x07)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_GPIO29_STATUS
// Description : GPIO status
-#define IO_BANK0_GPIO29_STATUS_OFFSET _U(0x000000e8)
-#define IO_BANK0_GPIO29_STATUS_BITS _U(0x050a3300)
-#define IO_BANK0_GPIO29_STATUS_RESET _U(0x00000000)
+#define IO_BANK0_GPIO29_STATUS_OFFSET _u(0x000000e8)
+#define IO_BANK0_GPIO29_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO29_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO29_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB _u(26)
#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO29_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO29_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_BANK0_GPIO29_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO29_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_BANK0_GPIO29_STATUS_INTOPERI_MSB _U(19)
-#define IO_BANK0_GPIO29_STATUS_INTOPERI_LSB _U(19)
+#define IO_BANK0_GPIO29_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO29_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO29_STATUS_INTOPERI_LSB _u(19)
#define IO_BANK0_GPIO29_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO29_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB _U(17)
-#define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB _U(17)
+#define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB _u(17)
#define IO_BANK0_GPIO29_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO29_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB _U(13)
-#define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB _U(13)
+#define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB _u(13)
#define IO_BANK0_GPIO29_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO29_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_LSB _u(12)
#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO29_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB _u(9)
#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO29_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_GPIO29_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_BANK0_GPIO29_CTRL_OFFSET _U(0x000000ec)
-#define IO_BANK0_GPIO29_CTRL_BITS _U(0x3003331f)
-#define IO_BANK0_GPIO29_CTRL_RESET _U(0x0000001f)
+#define IO_BANK0_GPIO29_CTRL_OFFSET _u(0x000000ec)
+#define IO_BANK0_GPIO29_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO29_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO29_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB _U(29)
-#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB _U(28)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB _u(28)
#define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS "RW"
-#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO29_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_BANK0_GPIO29_CTRL_INOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO29_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_BANK0_GPIO29_CTRL_INOVER_MSB _U(17)
-#define IO_BANK0_GPIO29_CTRL_INOVER_LSB _U(16)
+#define IO_BANK0_GPIO29_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO29_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO29_CTRL_INOVER_LSB _u(16)
#define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS "RW"
-#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO29_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -5041,15 +5041,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB _U(13)
-#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB _U(12)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB _u(12)
#define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS "RW"
-#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO29_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -5057,15 +5057,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB _U(9)
-#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB _U(8)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB _u(8)
#define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS "RW"
-#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_GPIO29_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -5079,9859 +5079,9859 @@
// 0x07 -> pio1_29
// 0x09 -> usb_muxing_vbus_en
// 0x1f -> null
-#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB _U(4)
-#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB _U(0)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB _u(0)
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N _U(0x01)
-#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX _U(0x02)
-#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL _U(0x03)
-#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 _U(0x04)
-#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29 _U(0x05)
-#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 _U(0x06)
-#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 _U(0x07)
-#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _U(0x09)
-#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29 _u(0x05)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 _u(0x06)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 _u(0x07)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_BANK0_INTR0
// Description : Raw Interrupts
-#define IO_BANK0_INTR0_OFFSET _U(0x000000f0)
-#define IO_BANK0_INTR0_BITS _U(0xffffffff)
-#define IO_BANK0_INTR0_RESET _U(0x00000000)
+#define IO_BANK0_INTR0_OFFSET _u(0x000000f0)
+#define IO_BANK0_INTR0_BITS _u(0xffffffff)
+#define IO_BANK0_INTR0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO7_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO7_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB _u(30)
#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO7_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO7_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO6_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO6_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB _u(26)
#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO6_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO6_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO5_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO5_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB _u(22)
#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO5_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO5_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO4_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO4_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB _u(18)
#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO4_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO4_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO3_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO3_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB _u(14)
#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO3_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO3_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO2_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO2_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB _u(10)
#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO2_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO2_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO1_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO1_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB _u(6)
#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO1_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO1_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO0_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO0_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB _u(2)
#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO0_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR0_GPIO0_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_INTR1
// Description : Raw Interrupts
-#define IO_BANK0_INTR1_OFFSET _U(0x000000f4)
-#define IO_BANK0_INTR1_BITS _U(0xffffffff)
-#define IO_BANK0_INTR1_RESET _U(0x00000000)
+#define IO_BANK0_INTR1_OFFSET _u(0x000000f4)
+#define IO_BANK0_INTR1_BITS _u(0xffffffff)
+#define IO_BANK0_INTR1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO15_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO15_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB _u(30)
#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO15_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO15_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO14_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO14_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB _u(26)
#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO14_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO14_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO13_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO13_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB _u(22)
#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO13_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO13_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO12_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO12_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB _u(18)
#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO12_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO12_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO11_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO11_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB _u(14)
#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO11_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO11_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO10_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO10_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB _u(10)
#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO10_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO10_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO9_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO9_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB _u(6)
#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO9_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO9_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO8_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO8_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB _u(2)
#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO8_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR1_GPIO8_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_INTR2
// Description : Raw Interrupts
-#define IO_BANK0_INTR2_OFFSET _U(0x000000f8)
-#define IO_BANK0_INTR2_BITS _U(0xffffffff)
-#define IO_BANK0_INTR2_RESET _U(0x00000000)
+#define IO_BANK0_INTR2_OFFSET _u(0x000000f8)
+#define IO_BANK0_INTR2_BITS _u(0xffffffff)
+#define IO_BANK0_INTR2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO23_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO23_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB _u(30)
#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO23_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO23_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO22_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO22_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB _u(26)
#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO22_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO22_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO21_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO21_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB _u(22)
#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO21_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO21_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO20_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO20_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB _u(18)
#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO20_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO20_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO19_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO19_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB _u(14)
#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO19_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO19_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO18_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO18_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB _u(10)
#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO18_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO18_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO17_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO17_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB _u(6)
#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO17_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO17_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO16_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO16_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB _u(2)
#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO16_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR2_GPIO16_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_INTR3
// Description : Raw Interrupts
-#define IO_BANK0_INTR3_OFFSET _U(0x000000fc)
-#define IO_BANK0_INTR3_BITS _U(0x00ffffff)
-#define IO_BANK0_INTR3_RESET _U(0x00000000)
+#define IO_BANK0_INTR3_OFFSET _u(0x000000fc)
+#define IO_BANK0_INTR3_BITS _u(0x00ffffff)
+#define IO_BANK0_INTR3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO29_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO29_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB _u(22)
#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO29_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO29_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO28_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO28_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB _u(18)
#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO28_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO28_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO27_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO27_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB _u(14)
#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO27_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO27_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO26_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO26_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB _u(10)
#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO26_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO26_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO25_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO25_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB _u(6)
#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO25_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO25_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO24_EDGE_HIGH
// Description : None
-#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO24_EDGE_LOW
// Description : None
-#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB _u(2)
#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO24_LEVEL_HIGH
// Description : None
-#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_INTR3_GPIO24_LEVEL_LOW
// Description : None
-#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_PROC0_INTE0
// Description : Interrupt Enable for proc0
-#define IO_BANK0_PROC0_INTE0_OFFSET _U(0x00000100)
-#define IO_BANK0_PROC0_INTE0_BITS _U(0xffffffff)
-#define IO_BANK0_PROC0_INTE0_RESET _U(0x00000000)
+#define IO_BANK0_PROC0_INTE0_OFFSET _u(0x00000100)
+#define IO_BANK0_PROC0_INTE0_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTE0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_PROC0_INTE1
// Description : Interrupt Enable for proc0
-#define IO_BANK0_PROC0_INTE1_OFFSET _U(0x00000104)
-#define IO_BANK0_PROC0_INTE1_BITS _U(0xffffffff)
-#define IO_BANK0_PROC0_INTE1_RESET _U(0x00000000)
+#define IO_BANK0_PROC0_INTE1_OFFSET _u(0x00000104)
+#define IO_BANK0_PROC0_INTE1_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTE1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_PROC0_INTE2
// Description : Interrupt Enable for proc0
-#define IO_BANK0_PROC0_INTE2_OFFSET _U(0x00000108)
-#define IO_BANK0_PROC0_INTE2_BITS _U(0xffffffff)
-#define IO_BANK0_PROC0_INTE2_RESET _U(0x00000000)
+#define IO_BANK0_PROC0_INTE2_OFFSET _u(0x00000108)
+#define IO_BANK0_PROC0_INTE2_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTE2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_PROC0_INTE3
// Description : Interrupt Enable for proc0
-#define IO_BANK0_PROC0_INTE3_OFFSET _U(0x0000010c)
-#define IO_BANK0_PROC0_INTE3_BITS _U(0x00ffffff)
-#define IO_BANK0_PROC0_INTE3_RESET _U(0x00000000)
+#define IO_BANK0_PROC0_INTE3_OFFSET _u(0x0000010c)
+#define IO_BANK0_PROC0_INTE3_BITS _u(0x00ffffff)
+#define IO_BANK0_PROC0_INTE3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_PROC0_INTF0
// Description : Interrupt Force for proc0
-#define IO_BANK0_PROC0_INTF0_OFFSET _U(0x00000110)
-#define IO_BANK0_PROC0_INTF0_BITS _U(0xffffffff)
-#define IO_BANK0_PROC0_INTF0_RESET _U(0x00000000)
+#define IO_BANK0_PROC0_INTF0_OFFSET _u(0x00000110)
+#define IO_BANK0_PROC0_INTF0_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTF0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_PROC0_INTF1
// Description : Interrupt Force for proc0
-#define IO_BANK0_PROC0_INTF1_OFFSET _U(0x00000114)
-#define IO_BANK0_PROC0_INTF1_BITS _U(0xffffffff)
-#define IO_BANK0_PROC0_INTF1_RESET _U(0x00000000)
+#define IO_BANK0_PROC0_INTF1_OFFSET _u(0x00000114)
+#define IO_BANK0_PROC0_INTF1_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTF1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_PROC0_INTF2
// Description : Interrupt Force for proc0
-#define IO_BANK0_PROC0_INTF2_OFFSET _U(0x00000118)
-#define IO_BANK0_PROC0_INTF2_BITS _U(0xffffffff)
-#define IO_BANK0_PROC0_INTF2_RESET _U(0x00000000)
+#define IO_BANK0_PROC0_INTF2_OFFSET _u(0x00000118)
+#define IO_BANK0_PROC0_INTF2_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTF2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_PROC0_INTF3
// Description : Interrupt Force for proc0
-#define IO_BANK0_PROC0_INTF3_OFFSET _U(0x0000011c)
-#define IO_BANK0_PROC0_INTF3_BITS _U(0x00ffffff)
-#define IO_BANK0_PROC0_INTF3_RESET _U(0x00000000)
+#define IO_BANK0_PROC0_INTF3_OFFSET _u(0x0000011c)
+#define IO_BANK0_PROC0_INTF3_BITS _u(0x00ffffff)
+#define IO_BANK0_PROC0_INTF3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_PROC0_INTS0
// Description : Interrupt status after masking & forcing for proc0
-#define IO_BANK0_PROC0_INTS0_OFFSET _U(0x00000120)
-#define IO_BANK0_PROC0_INTS0_BITS _U(0xffffffff)
-#define IO_BANK0_PROC0_INTS0_RESET _U(0x00000000)
+#define IO_BANK0_PROC0_INTS0_OFFSET _u(0x00000120)
+#define IO_BANK0_PROC0_INTS0_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTS0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_PROC0_INTS1
// Description : Interrupt status after masking & forcing for proc0
-#define IO_BANK0_PROC0_INTS1_OFFSET _U(0x00000124)
-#define IO_BANK0_PROC0_INTS1_BITS _U(0xffffffff)
-#define IO_BANK0_PROC0_INTS1_RESET _U(0x00000000)
+#define IO_BANK0_PROC0_INTS1_OFFSET _u(0x00000124)
+#define IO_BANK0_PROC0_INTS1_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTS1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_PROC0_INTS2
// Description : Interrupt status after masking & forcing for proc0
-#define IO_BANK0_PROC0_INTS2_OFFSET _U(0x00000128)
-#define IO_BANK0_PROC0_INTS2_BITS _U(0xffffffff)
-#define IO_BANK0_PROC0_INTS2_RESET _U(0x00000000)
+#define IO_BANK0_PROC0_INTS2_OFFSET _u(0x00000128)
+#define IO_BANK0_PROC0_INTS2_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTS2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_PROC0_INTS3
// Description : Interrupt status after masking & forcing for proc0
-#define IO_BANK0_PROC0_INTS3_OFFSET _U(0x0000012c)
-#define IO_BANK0_PROC0_INTS3_BITS _U(0x00ffffff)
-#define IO_BANK0_PROC0_INTS3_RESET _U(0x00000000)
+#define IO_BANK0_PROC0_INTS3_OFFSET _u(0x0000012c)
+#define IO_BANK0_PROC0_INTS3_BITS _u(0x00ffffff)
+#define IO_BANK0_PROC0_INTS3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_PROC1_INTE0
// Description : Interrupt Enable for proc1
-#define IO_BANK0_PROC1_INTE0_OFFSET _U(0x00000130)
-#define IO_BANK0_PROC1_INTE0_BITS _U(0xffffffff)
-#define IO_BANK0_PROC1_INTE0_RESET _U(0x00000000)
+#define IO_BANK0_PROC1_INTE0_OFFSET _u(0x00000130)
+#define IO_BANK0_PROC1_INTE0_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTE0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_PROC1_INTE1
// Description : Interrupt Enable for proc1
-#define IO_BANK0_PROC1_INTE1_OFFSET _U(0x00000134)
-#define IO_BANK0_PROC1_INTE1_BITS _U(0xffffffff)
-#define IO_BANK0_PROC1_INTE1_RESET _U(0x00000000)
+#define IO_BANK0_PROC1_INTE1_OFFSET _u(0x00000134)
+#define IO_BANK0_PROC1_INTE1_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTE1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_PROC1_INTE2
// Description : Interrupt Enable for proc1
-#define IO_BANK0_PROC1_INTE2_OFFSET _U(0x00000138)
-#define IO_BANK0_PROC1_INTE2_BITS _U(0xffffffff)
-#define IO_BANK0_PROC1_INTE2_RESET _U(0x00000000)
+#define IO_BANK0_PROC1_INTE2_OFFSET _u(0x00000138)
+#define IO_BANK0_PROC1_INTE2_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTE2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_PROC1_INTE3
// Description : Interrupt Enable for proc1
-#define IO_BANK0_PROC1_INTE3_OFFSET _U(0x0000013c)
-#define IO_BANK0_PROC1_INTE3_BITS _U(0x00ffffff)
-#define IO_BANK0_PROC1_INTE3_RESET _U(0x00000000)
+#define IO_BANK0_PROC1_INTE3_OFFSET _u(0x0000013c)
+#define IO_BANK0_PROC1_INTE3_BITS _u(0x00ffffff)
+#define IO_BANK0_PROC1_INTE3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_PROC1_INTF0
// Description : Interrupt Force for proc1
-#define IO_BANK0_PROC1_INTF0_OFFSET _U(0x00000140)
-#define IO_BANK0_PROC1_INTF0_BITS _U(0xffffffff)
-#define IO_BANK0_PROC1_INTF0_RESET _U(0x00000000)
+#define IO_BANK0_PROC1_INTF0_OFFSET _u(0x00000140)
+#define IO_BANK0_PROC1_INTF0_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTF0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_PROC1_INTF1
// Description : Interrupt Force for proc1
-#define IO_BANK0_PROC1_INTF1_OFFSET _U(0x00000144)
-#define IO_BANK0_PROC1_INTF1_BITS _U(0xffffffff)
-#define IO_BANK0_PROC1_INTF1_RESET _U(0x00000000)
+#define IO_BANK0_PROC1_INTF1_OFFSET _u(0x00000144)
+#define IO_BANK0_PROC1_INTF1_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTF1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_PROC1_INTF2
// Description : Interrupt Force for proc1
-#define IO_BANK0_PROC1_INTF2_OFFSET _U(0x00000148)
-#define IO_BANK0_PROC1_INTF2_BITS _U(0xffffffff)
-#define IO_BANK0_PROC1_INTF2_RESET _U(0x00000000)
+#define IO_BANK0_PROC1_INTF2_OFFSET _u(0x00000148)
+#define IO_BANK0_PROC1_INTF2_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTF2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_PROC1_INTF3
// Description : Interrupt Force for proc1
-#define IO_BANK0_PROC1_INTF3_OFFSET _U(0x0000014c)
-#define IO_BANK0_PROC1_INTF3_BITS _U(0x00ffffff)
-#define IO_BANK0_PROC1_INTF3_RESET _U(0x00000000)
+#define IO_BANK0_PROC1_INTF3_OFFSET _u(0x0000014c)
+#define IO_BANK0_PROC1_INTF3_BITS _u(0x00ffffff)
+#define IO_BANK0_PROC1_INTF3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_PROC1_INTS0
// Description : Interrupt status after masking & forcing for proc1
-#define IO_BANK0_PROC1_INTS0_OFFSET _U(0x00000150)
-#define IO_BANK0_PROC1_INTS0_BITS _U(0xffffffff)
-#define IO_BANK0_PROC1_INTS0_RESET _U(0x00000000)
+#define IO_BANK0_PROC1_INTS0_OFFSET _u(0x00000150)
+#define IO_BANK0_PROC1_INTS0_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTS0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_PROC1_INTS1
// Description : Interrupt status after masking & forcing for proc1
-#define IO_BANK0_PROC1_INTS1_OFFSET _U(0x00000154)
-#define IO_BANK0_PROC1_INTS1_BITS _U(0xffffffff)
-#define IO_BANK0_PROC1_INTS1_RESET _U(0x00000000)
+#define IO_BANK0_PROC1_INTS1_OFFSET _u(0x00000154)
+#define IO_BANK0_PROC1_INTS1_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTS1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_PROC1_INTS2
// Description : Interrupt status after masking & forcing for proc1
-#define IO_BANK0_PROC1_INTS2_OFFSET _U(0x00000158)
-#define IO_BANK0_PROC1_INTS2_BITS _U(0xffffffff)
-#define IO_BANK0_PROC1_INTS2_RESET _U(0x00000000)
+#define IO_BANK0_PROC1_INTS2_OFFSET _u(0x00000158)
+#define IO_BANK0_PROC1_INTS2_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTS2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB _u(30)
#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB _u(26)
#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_PROC1_INTS3
// Description : Interrupt status after masking & forcing for proc1
-#define IO_BANK0_PROC1_INTS3_OFFSET _U(0x0000015c)
-#define IO_BANK0_PROC1_INTS3_BITS _U(0x00ffffff)
-#define IO_BANK0_PROC1_INTS3_RESET _U(0x00000000)
+#define IO_BANK0_PROC1_INTS3_OFFSET _u(0x0000015c)
+#define IO_BANK0_PROC1_INTS3_BITS _u(0x00ffffff)
+#define IO_BANK0_PROC1_INTS3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB _u(22)
#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB _u(18)
#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB _u(14)
#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB _u(10)
#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB _u(6)
#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB _u(2)
#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW
// Description : None
-#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_DORMANT_WAKE_INTE0
// Description : Interrupt Enable for dormant_wake
-#define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET _U(0x00000160)
-#define IO_BANK0_DORMANT_WAKE_INTE0_BITS _U(0xffffffff)
-#define IO_BANK0_DORMANT_WAKE_INTE0_RESET _U(0x00000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET _u(0x00000160)
+#define IO_BANK0_DORMANT_WAKE_INTE0_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTE0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB _u(30)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB _u(26)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB _u(22)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB _u(18)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB _u(14)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB _u(10)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB _u(6)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB _u(2)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_DORMANT_WAKE_INTE1
// Description : Interrupt Enable for dormant_wake
-#define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET _U(0x00000164)
-#define IO_BANK0_DORMANT_WAKE_INTE1_BITS _U(0xffffffff)
-#define IO_BANK0_DORMANT_WAKE_INTE1_RESET _U(0x00000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET _u(0x00000164)
+#define IO_BANK0_DORMANT_WAKE_INTE1_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTE1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB _u(30)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB _u(26)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB _u(22)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB _u(18)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB _u(14)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB _u(10)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB _u(6)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB _u(2)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_DORMANT_WAKE_INTE2
// Description : Interrupt Enable for dormant_wake
-#define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET _U(0x00000168)
-#define IO_BANK0_DORMANT_WAKE_INTE2_BITS _U(0xffffffff)
-#define IO_BANK0_DORMANT_WAKE_INTE2_RESET _U(0x00000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET _u(0x00000168)
+#define IO_BANK0_DORMANT_WAKE_INTE2_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTE2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB _u(30)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB _u(26)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB _u(22)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB _u(18)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB _u(14)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB _u(10)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB _u(6)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB _u(2)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_DORMANT_WAKE_INTE3
// Description : Interrupt Enable for dormant_wake
-#define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET _U(0x0000016c)
-#define IO_BANK0_DORMANT_WAKE_INTE3_BITS _U(0x00ffffff)
-#define IO_BANK0_DORMANT_WAKE_INTE3_RESET _U(0x00000000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET _u(0x0000016c)
+#define IO_BANK0_DORMANT_WAKE_INTE3_BITS _u(0x00ffffff)
+#define IO_BANK0_DORMANT_WAKE_INTE3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB _u(22)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB _u(18)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB _u(14)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB _u(10)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB _u(6)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB _u(2)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_DORMANT_WAKE_INTF0
// Description : Interrupt Force for dormant_wake
-#define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET _U(0x00000170)
-#define IO_BANK0_DORMANT_WAKE_INTF0_BITS _U(0xffffffff)
-#define IO_BANK0_DORMANT_WAKE_INTF0_RESET _U(0x00000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET _u(0x00000170)
+#define IO_BANK0_DORMANT_WAKE_INTF0_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTF0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB _u(30)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB _u(26)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB _u(22)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB _u(18)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB _u(14)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB _u(10)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB _u(6)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB _u(2)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_DORMANT_WAKE_INTF1
// Description : Interrupt Force for dormant_wake
-#define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET _U(0x00000174)
-#define IO_BANK0_DORMANT_WAKE_INTF1_BITS _U(0xffffffff)
-#define IO_BANK0_DORMANT_WAKE_INTF1_RESET _U(0x00000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET _u(0x00000174)
+#define IO_BANK0_DORMANT_WAKE_INTF1_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTF1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB _u(30)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB _u(26)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB _u(22)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB _u(18)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB _u(14)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB _u(10)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB _u(6)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB _u(2)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_DORMANT_WAKE_INTF2
// Description : Interrupt Force for dormant_wake
-#define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET _U(0x00000178)
-#define IO_BANK0_DORMANT_WAKE_INTF2_BITS _U(0xffffffff)
-#define IO_BANK0_DORMANT_WAKE_INTF2_RESET _U(0x00000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET _u(0x00000178)
+#define IO_BANK0_DORMANT_WAKE_INTF2_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTF2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB _u(30)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB _u(26)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB _u(22)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB _u(18)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB _u(14)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB _u(10)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB _u(6)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB _u(2)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_DORMANT_WAKE_INTF3
// Description : Interrupt Force for dormant_wake
-#define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET _U(0x0000017c)
-#define IO_BANK0_DORMANT_WAKE_INTF3_BITS _U(0x00ffffff)
-#define IO_BANK0_DORMANT_WAKE_INTF3_RESET _U(0x00000000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET _u(0x0000017c)
+#define IO_BANK0_DORMANT_WAKE_INTF3_BITS _u(0x00ffffff)
+#define IO_BANK0_DORMANT_WAKE_INTF3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB _u(22)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB _u(18)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB _u(14)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB _u(10)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB _u(6)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB _u(2)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_BANK0_DORMANT_WAKE_INTS0
// Description : Interrupt status after masking & forcing for dormant_wake
-#define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET _U(0x00000180)
-#define IO_BANK0_DORMANT_WAKE_INTS0_BITS _U(0xffffffff)
-#define IO_BANK0_DORMANT_WAKE_INTS0_RESET _U(0x00000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET _u(0x00000180)
+#define IO_BANK0_DORMANT_WAKE_INTS0_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTS0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB _u(30)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB _u(26)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB _u(22)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB _u(18)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB _u(14)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB _u(10)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB _u(6)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB _u(2)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_DORMANT_WAKE_INTS1
// Description : Interrupt status after masking & forcing for dormant_wake
-#define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET _U(0x00000184)
-#define IO_BANK0_DORMANT_WAKE_INTS1_BITS _U(0xffffffff)
-#define IO_BANK0_DORMANT_WAKE_INTS1_RESET _U(0x00000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET _u(0x00000184)
+#define IO_BANK0_DORMANT_WAKE_INTS1_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTS1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB _u(30)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB _u(26)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB _u(22)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB _u(18)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB _u(14)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB _u(10)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB _u(6)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB _u(2)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_DORMANT_WAKE_INTS2
// Description : Interrupt status after masking & forcing for dormant_wake
-#define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET _U(0x00000188)
-#define IO_BANK0_DORMANT_WAKE_INTS2_BITS _U(0xffffffff)
-#define IO_BANK0_DORMANT_WAKE_INTS2_RESET _U(0x00000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET _u(0x00000188)
+#define IO_BANK0_DORMANT_WAKE_INTS2_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTS2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS _U(0x80000000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB _U(31)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB _U(31)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB _u(31)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS _U(0x40000000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB _U(30)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB _U(30)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB _u(30)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS _U(0x20000000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB _U(29)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB _U(29)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS _U(0x10000000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB _U(28)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB _U(28)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB _u(28)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS _U(0x08000000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB _U(27)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB _U(27)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB _u(27)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS _U(0x04000000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB _U(26)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB _U(26)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB _u(26)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS _U(0x02000000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB _U(25)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB _U(25)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS _U(0x01000000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB _U(24)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB _U(24)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB _u(24)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB _u(22)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB _u(18)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB _u(14)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB _u(10)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB _u(6)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB _u(2)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_BANK0_DORMANT_WAKE_INTS3
// Description : Interrupt status after masking & forcing for dormant_wake
-#define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET _U(0x0000018c)
-#define IO_BANK0_DORMANT_WAKE_INTS3_BITS _U(0x00ffffff)
-#define IO_BANK0_DORMANT_WAKE_INTS3_RESET _U(0x00000000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET _u(0x0000018c)
+#define IO_BANK0_DORMANT_WAKE_INTS3_BITS _u(0x00ffffff)
+#define IO_BANK0_DORMANT_WAKE_INTS3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB _U(23)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB _U(23)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB _u(23)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS _U(0x00400000)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB _U(22)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB _U(22)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB _u(22)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB _U(21)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB _U(21)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB _U(20)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB _U(20)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB _u(20)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB _U(19)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB _U(19)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB _u(19)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS _U(0x00040000)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB _U(18)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB _U(18)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB _u(18)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB _U(17)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB _U(17)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB _U(16)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB _U(16)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB _u(16)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB _U(15)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB _U(15)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB _u(15)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS _U(0x00004000)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB _U(14)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB _U(14)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB _u(14)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB _U(13)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB _U(13)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB _U(12)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB _U(12)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB _u(12)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB _U(11)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB _U(11)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB _u(11)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS _U(0x00000400)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB _U(10)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB _U(10)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB _u(10)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB _U(9)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB _U(9)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB _U(8)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB _U(8)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB _u(8)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB _U(7)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB _U(7)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB _u(7)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS _U(0x00000040)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB _U(6)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB _U(6)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB _u(6)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB _U(5)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB _U(5)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB _U(4)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB _U(4)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB _u(4)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB _U(3)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB _U(3)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB _u(3)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS _U(0x00000004)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB _U(2)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB _U(2)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB _u(2)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB _U(1)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB _U(1)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW
// Description : None
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET _U(0x0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB _U(0)
-#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB _U(0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB _u(0)
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_IO_BANK0_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h b/src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h
index b71188c..7c381b7 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h
@@ -14,111 +14,111 @@
// =============================================================================
// Register : IO_QSPI_GPIO_QSPI_SCLK_STATUS
// Description : GPIO status
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET _U(0x00000000)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS _U(0x050a3300)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET _U(0x00000000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET _u(0x00000000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB _u(26)
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_MSB _U(19)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_LSB _U(19)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_MSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_LSB _u(19)
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MSB _U(17)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_LSB _U(17)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_LSB _u(17)
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MSB _U(13)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_LSB _U(13)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_LSB _u(13)
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_LSB _u(12)
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_LSB _u(9)
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_QSPI_GPIO_QSPI_SCLK_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET _U(0x00000004)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_BITS _U(0x3003331f)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET _U(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET _u(0x00000004)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_BITS _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB _U(29)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB _U(28)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB _u(29)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB _u(28)
#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB _U(17)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB _U(16)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB _u(16)
#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -127,15 +127,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB _U(13)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB _U(12)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB _u(12)
#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -143,15 +143,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB _U(9)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB _U(8)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB _u(8)
#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -159,122 +159,122 @@
// 0x00 -> xip_sclk
// 0x05 -> sio_30
// 0x1f -> null
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB _U(4)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB _U(0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB _u(4)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB _u(0)
#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK _U(0x00)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_30 _U(0x05)
-#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_30 _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_QSPI_GPIO_QSPI_SS_STATUS
// Description : GPIO status
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET _U(0x00000008)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_BITS _U(0x050a3300)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_RESET _U(0x00000000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET _u(0x00000008)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_BITS _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_LSB _u(26)
#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_MSB _U(19)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_LSB _U(19)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_MSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_LSB _u(19)
#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MSB _U(17)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_LSB _U(17)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_LSB _u(17)
#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MSB _U(13)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_LSB _U(13)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_LSB _u(13)
#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_LSB _u(12)
#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_LSB _u(9)
#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_QSPI_GPIO_QSPI_SS_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET _U(0x0000000c)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_BITS _U(0x3003331f)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET _U(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET _u(0x0000000c)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_BITS _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB _U(29)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB _U(28)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB _u(29)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB _u(28)
#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB _U(17)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB _U(16)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB _u(16)
#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -283,15 +283,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB _U(13)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB _U(12)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB _u(12)
#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -299,15 +299,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB _U(9)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB _U(8)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB _u(8)
#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -315,122 +315,122 @@
// 0x00 -> xip_ss_n
// 0x05 -> sio_31
// 0x1f -> null
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB _U(4)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB _U(0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB _u(4)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB _u(0)
#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N _U(0x00)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_31 _U(0x05)
-#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_31 _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_QSPI_GPIO_QSPI_SD0_STATUS
// Description : GPIO status
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET _U(0x00000010)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_BITS _U(0x050a3300)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_RESET _U(0x00000000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET _u(0x00000010)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_BITS _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_LSB _u(26)
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_MSB _U(19)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_LSB _U(19)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_MSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_LSB _u(19)
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MSB _U(17)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_LSB _U(17)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_LSB _u(17)
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MSB _U(13)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_LSB _U(13)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_LSB _u(13)
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_LSB _u(12)
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_LSB _u(9)
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_QSPI_GPIO_QSPI_SD0_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET _U(0x00000014)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_BITS _U(0x3003331f)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET _U(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET _u(0x00000014)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_BITS _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB _U(29)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB _U(28)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB _u(29)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB _u(28)
#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB _U(17)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB _U(16)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB _u(16)
#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -439,15 +439,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB _U(13)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB _U(12)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB _u(12)
#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -455,15 +455,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB _U(9)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB _U(8)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB _u(8)
#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -471,122 +471,122 @@
// 0x00 -> xip_sd0
// 0x05 -> sio_32
// 0x1f -> null
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB _U(4)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB _U(0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB _u(4)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB _u(0)
#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 _U(0x00)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_32 _U(0x05)
-#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_32 _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_QSPI_GPIO_QSPI_SD1_STATUS
// Description : GPIO status
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET _U(0x00000018)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_BITS _U(0x050a3300)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_RESET _U(0x00000000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET _u(0x00000018)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_BITS _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_LSB _u(26)
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_MSB _U(19)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_LSB _U(19)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_MSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_LSB _u(19)
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MSB _U(17)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_LSB _U(17)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_LSB _u(17)
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MSB _U(13)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_LSB _U(13)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_LSB _u(13)
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_LSB _u(12)
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_LSB _u(9)
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_QSPI_GPIO_QSPI_SD1_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET _U(0x0000001c)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_BITS _U(0x3003331f)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET _U(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET _u(0x0000001c)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_BITS _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB _U(29)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB _U(28)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB _u(29)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB _u(28)
#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB _U(17)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB _U(16)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB _u(16)
#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -595,15 +595,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB _U(13)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB _U(12)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB _u(12)
#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -611,15 +611,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB _U(9)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB _U(8)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB _u(8)
#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -627,122 +627,122 @@
// 0x00 -> xip_sd1
// 0x05 -> sio_33
// 0x1f -> null
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB _U(4)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB _U(0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB _u(4)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB _u(0)
#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 _U(0x00)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_33 _U(0x05)
-#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_33 _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_QSPI_GPIO_QSPI_SD2_STATUS
// Description : GPIO status
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET _U(0x00000020)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_BITS _U(0x050a3300)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_RESET _U(0x00000000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET _u(0x00000020)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_BITS _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_LSB _u(26)
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_MSB _U(19)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_LSB _U(19)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_MSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_LSB _u(19)
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MSB _U(17)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_LSB _U(17)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_LSB _u(17)
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MSB _U(13)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_LSB _U(13)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_LSB _u(13)
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_LSB _u(12)
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_LSB _u(9)
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_QSPI_GPIO_QSPI_SD2_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET _U(0x00000024)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_BITS _U(0x3003331f)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET _U(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET _u(0x00000024)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_BITS _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB _U(29)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB _U(28)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB _u(29)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB _u(28)
#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB _U(17)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB _U(16)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB _u(16)
#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -751,15 +751,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB _U(13)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB _U(12)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB _u(12)
#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -767,15 +767,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB _U(9)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB _U(8)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB _u(8)
#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -783,122 +783,122 @@
// 0x00 -> xip_sd2
// 0x05 -> sio_34
// 0x1f -> null
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB _U(4)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB _U(0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB _u(4)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB _u(0)
#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 _U(0x00)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_34 _U(0x05)
-#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_34 _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_QSPI_GPIO_QSPI_SD3_STATUS
// Description : GPIO status
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET _U(0x00000028)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_BITS _U(0x050a3300)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_RESET _U(0x00000000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET _u(0x00000028)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_BITS _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC
// Description : interrupt to processors, after override is applied
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_BITS _U(0x04000000)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MSB _U(26)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_LSB _U(26)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_LSB _u(26)
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD
// Description : interrupt from pad before override is applied
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_BITS _U(0x01000000)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_MSB _U(24)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_LSB _U(24)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_LSB _u(24)
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI
// Description : input signal to peripheral, after override is applied
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_BITS _U(0x00080000)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_MSB _U(19)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_LSB _U(19)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_MSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_LSB _u(19)
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD
// Description : input signal from pad, before override is applied
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_BITS _U(0x00020000)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MSB _U(17)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_LSB _U(17)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_LSB _u(17)
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD
// Description : output enable to pad after register override is applied
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_BITS _U(0x00002000)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MSB _U(13)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_LSB _U(13)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_LSB _u(13)
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI
// Description : output enable from selected peripheral, before register
// override is applied
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_BITS _U(0x00001000)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_MSB _U(12)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_LSB _U(12)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_LSB _u(12)
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD
// Description : output signal to pad after register override is applied
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_BITS _U(0x00000200)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MSB _U(9)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_LSB _U(9)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_LSB _u(9)
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI
// Description : output signal from selected peripheral, before register
// override is applied
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_BITS _U(0x00000100)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_MSB _U(8)
-#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_LSB _U(8)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_LSB _u(8)
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_ACCESS "RO"
// =============================================================================
// Register : IO_QSPI_GPIO_QSPI_SD3_CTRL
// Description : GPIO control including function select and overrides.
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET _U(0x0000002c)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_BITS _U(0x3003331f)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET _U(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET _u(0x0000002c)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_BITS _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET _u(0x0000001f)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER
// Description : 0x0 -> don't invert the interrupt
// 0x1 -> invert the interrupt
// 0x2 -> drive interrupt low
// 0x3 -> drive interrupt high
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS _U(0x30000000)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB _U(29)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB _U(28)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB _u(29)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB _u(28)
#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER
// Description : 0x0 -> don't invert the peri input
// 0x1 -> invert the peri input
// 0x2 -> drive peri input low
// 0x3 -> drive peri input high
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS _U(0x00030000)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB _U(17)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB _U(16)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB _u(16)
#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER
// Description : 0x0 -> drive output enable from peripheral signal selected by
@@ -907,15 +907,15 @@
// selected by funcsel
// 0x2 -> disable output
// 0x3 -> enable output
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS _U(0x00003000)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB _U(13)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB _U(12)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB _u(12)
#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER
// Description : 0x0 -> drive output from peripheral signal selected by funcsel
@@ -923,15 +923,15 @@
// by funcsel
// 0x2 -> drive output low
// 0x3 -> drive output high
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS _U(0x00000300)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB _U(9)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB _U(8)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB _u(8)
#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL _U(0x0)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT _U(0x1)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW _U(0x2)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH _U(0x3)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL
// Description : 0-31 -> selects pin function according to the gpio table
@@ -939,1993 +939,1993 @@
// 0x00 -> xip_sd3
// 0x05 -> sio_35
// 0x1f -> null
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET _U(0x1f)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS _U(0x0000001f)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB _U(4)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB _U(0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB _u(4)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB _u(0)
#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS "RW"
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 _U(0x00)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_35 _U(0x05)
-#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL _U(0x1f)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_35 _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
// =============================================================================
// Register : IO_QSPI_INTR
// Description : Raw Interrupts
-#define IO_QSPI_INTR_OFFSET _U(0x00000030)
-#define IO_QSPI_INTR_BITS _U(0x00ffffff)
-#define IO_QSPI_INTR_RESET _U(0x00000000)
+#define IO_QSPI_INTR_OFFSET _u(0x00000030)
+#define IO_QSPI_INTR_BITS _u(0x00ffffff)
+#define IO_QSPI_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB _U(23)
-#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_LSB _U(23)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS _U(0x00400000)
-#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB _U(22)
-#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_LSB _U(22)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _U(21)
-#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _U(21)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB _U(20)
-#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_LSB _U(20)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB _U(19)
-#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_LSB _U(19)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS _U(0x00040000)
-#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB _U(18)
-#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_LSB _U(18)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _U(17)
-#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _U(17)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB _U(16)
-#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_LSB _U(16)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB _U(15)
-#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_LSB _U(15)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS _U(0x00004000)
-#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB _U(14)
-#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_LSB _U(14)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _U(13)
-#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _U(13)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB _U(12)
-#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_LSB _U(12)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB _U(11)
-#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_LSB _U(11)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS _U(0x00000400)
-#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB _U(10)
-#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_LSB _U(10)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _U(9)
-#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _U(9)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB _U(8)
-#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_LSB _U(8)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB _U(7)
-#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_LSB _U(7)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS _U(0x00000040)
-#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB _U(6)
-#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_LSB _U(6)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB _U(5)
-#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_LSB _U(5)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB _U(4)
-#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_LSB _U(4)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _U(3)
-#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _U(3)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS _U(0x00000004)
-#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB _U(2)
-#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_LSB _U(2)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _U(1)
-#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _U(1)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW
// Description : None
-#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _U(0)
-#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _U(0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_QSPI_PROC0_INTE
// Description : Interrupt Enable for proc0
-#define IO_QSPI_PROC0_INTE_OFFSET _U(0x00000034)
-#define IO_QSPI_PROC0_INTE_BITS _U(0x00ffffff)
-#define IO_QSPI_PROC0_INTE_RESET _U(0x00000000)
+#define IO_QSPI_PROC0_INTE_OFFSET _u(0x00000034)
+#define IO_QSPI_PROC0_INTE_BITS _u(0x00ffffff)
+#define IO_QSPI_PROC0_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _U(23)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _U(23)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _U(0x00400000)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _U(22)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _U(22)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _U(21)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _U(21)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _U(20)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _U(20)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _U(19)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _U(19)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _U(0x00040000)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _U(18)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _U(18)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _U(17)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _U(17)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _U(16)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _U(16)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _U(15)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _U(15)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _U(0x00004000)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _U(14)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _U(14)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _U(13)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _U(13)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _U(12)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _U(12)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _U(11)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _U(11)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _U(0x00000400)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _U(10)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _U(10)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _U(9)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _U(9)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _U(8)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _U(8)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _U(7)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _U(7)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _U(0x00000040)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _U(6)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _U(6)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _U(5)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _U(5)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _U(4)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _U(4)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _U(3)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _U(3)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _U(0x00000004)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _U(2)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _U(2)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _U(1)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _U(1)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _U(0)
-#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _U(0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_QSPI_PROC0_INTF
// Description : Interrupt Force for proc0
-#define IO_QSPI_PROC0_INTF_OFFSET _U(0x00000038)
-#define IO_QSPI_PROC0_INTF_BITS _U(0x00ffffff)
-#define IO_QSPI_PROC0_INTF_RESET _U(0x00000000)
+#define IO_QSPI_PROC0_INTF_OFFSET _u(0x00000038)
+#define IO_QSPI_PROC0_INTF_BITS _u(0x00ffffff)
+#define IO_QSPI_PROC0_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _U(23)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _U(23)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _U(0x00400000)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _U(22)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _U(22)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _U(21)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _U(21)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _U(20)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _U(20)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _U(19)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _U(19)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _U(0x00040000)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _U(18)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _U(18)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _U(17)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _U(17)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _U(16)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _U(16)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _U(15)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _U(15)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _U(0x00004000)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _U(14)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _U(14)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _U(13)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _U(13)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _U(12)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _U(12)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _U(11)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _U(11)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _U(0x00000400)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _U(10)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _U(10)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _U(9)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _U(9)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _U(8)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _U(8)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _U(7)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _U(7)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _U(0x00000040)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _U(6)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _U(6)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _U(5)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _U(5)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _U(4)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _U(4)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _U(3)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _U(3)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _U(0x00000004)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _U(2)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _U(2)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _U(1)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _U(1)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _U(0)
-#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _U(0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_QSPI_PROC0_INTS
// Description : Interrupt status after masking & forcing for proc0
-#define IO_QSPI_PROC0_INTS_OFFSET _U(0x0000003c)
-#define IO_QSPI_PROC0_INTS_BITS _U(0x00ffffff)
-#define IO_QSPI_PROC0_INTS_RESET _U(0x00000000)
+#define IO_QSPI_PROC0_INTS_OFFSET _u(0x0000003c)
+#define IO_QSPI_PROC0_INTS_BITS _u(0x00ffffff)
+#define IO_QSPI_PROC0_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _U(23)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _U(23)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _U(0x00400000)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _U(22)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _U(22)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _U(21)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _U(21)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _U(20)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _U(20)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _U(19)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _U(19)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _U(0x00040000)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _U(18)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _U(18)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _U(17)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _U(17)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _U(16)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _U(16)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _U(15)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _U(15)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _U(0x00004000)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _U(14)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _U(14)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _U(13)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _U(13)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _U(12)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _U(12)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _U(11)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _U(11)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _U(0x00000400)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _U(10)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _U(10)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _U(9)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _U(9)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _U(8)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _U(8)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _U(7)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _U(7)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _U(0x00000040)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _U(6)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _U(6)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _U(5)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _U(5)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _U(4)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _U(4)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _U(3)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _U(3)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _U(0x00000004)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _U(2)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _U(2)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _U(1)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _U(1)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _U(0)
-#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _U(0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_QSPI_PROC1_INTE
// Description : Interrupt Enable for proc1
-#define IO_QSPI_PROC1_INTE_OFFSET _U(0x00000040)
-#define IO_QSPI_PROC1_INTE_BITS _U(0x00ffffff)
-#define IO_QSPI_PROC1_INTE_RESET _U(0x00000000)
+#define IO_QSPI_PROC1_INTE_OFFSET _u(0x00000040)
+#define IO_QSPI_PROC1_INTE_BITS _u(0x00ffffff)
+#define IO_QSPI_PROC1_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _U(23)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _U(23)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _U(0x00400000)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _U(22)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _U(22)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _U(21)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _U(21)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _U(20)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _U(20)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _U(19)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _U(19)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _U(0x00040000)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _U(18)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _U(18)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _U(17)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _U(17)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _U(16)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _U(16)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _U(15)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _U(15)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _U(0x00004000)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _U(14)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _U(14)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _U(13)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _U(13)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _U(12)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _U(12)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _U(11)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _U(11)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _U(0x00000400)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _U(10)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _U(10)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _U(9)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _U(9)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _U(8)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _U(8)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _U(7)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _U(7)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _U(0x00000040)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _U(6)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _U(6)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _U(5)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _U(5)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _U(4)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _U(4)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _U(3)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _U(3)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _U(0x00000004)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _U(2)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _U(2)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _U(1)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _U(1)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _U(0)
-#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _U(0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_QSPI_PROC1_INTF
// Description : Interrupt Force for proc1
-#define IO_QSPI_PROC1_INTF_OFFSET _U(0x00000044)
-#define IO_QSPI_PROC1_INTF_BITS _U(0x00ffffff)
-#define IO_QSPI_PROC1_INTF_RESET _U(0x00000000)
+#define IO_QSPI_PROC1_INTF_OFFSET _u(0x00000044)
+#define IO_QSPI_PROC1_INTF_BITS _u(0x00ffffff)
+#define IO_QSPI_PROC1_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _U(23)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _U(23)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _U(0x00400000)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _U(22)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _U(22)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _U(21)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _U(21)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _U(20)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _U(20)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _U(19)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _U(19)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _U(0x00040000)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _U(18)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _U(18)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _U(17)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _U(17)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _U(16)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _U(16)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _U(15)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _U(15)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _U(0x00004000)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _U(14)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _U(14)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _U(13)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _U(13)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _U(12)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _U(12)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _U(11)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _U(11)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _U(0x00000400)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _U(10)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _U(10)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _U(9)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _U(9)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _U(8)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _U(8)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _U(7)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _U(7)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _U(0x00000040)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _U(6)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _U(6)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _U(5)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _U(5)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _U(4)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _U(4)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _U(3)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _U(3)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _U(0x00000004)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _U(2)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _U(2)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _U(1)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _U(1)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _U(0)
-#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _U(0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_QSPI_PROC1_INTS
// Description : Interrupt status after masking & forcing for proc1
-#define IO_QSPI_PROC1_INTS_OFFSET _U(0x00000048)
-#define IO_QSPI_PROC1_INTS_BITS _U(0x00ffffff)
-#define IO_QSPI_PROC1_INTS_RESET _U(0x00000000)
+#define IO_QSPI_PROC1_INTS_OFFSET _u(0x00000048)
+#define IO_QSPI_PROC1_INTS_BITS _u(0x00ffffff)
+#define IO_QSPI_PROC1_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _U(23)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _U(23)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _U(0x00400000)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _U(22)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _U(22)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _U(21)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _U(21)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _U(20)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _U(20)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _U(19)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _U(19)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _U(0x00040000)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _U(18)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _U(18)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _U(17)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _U(17)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _U(16)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _U(16)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _U(15)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _U(15)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _U(0x00004000)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _U(14)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _U(14)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _U(13)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _U(13)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _U(12)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _U(12)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _U(11)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _U(11)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _U(0x00000400)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _U(10)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _U(10)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _U(9)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _U(9)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _U(8)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _U(8)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _U(7)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _U(7)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _U(0x00000040)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _U(6)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _U(6)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _U(5)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _U(5)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _U(4)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _U(4)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _U(3)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _U(3)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _U(0x00000004)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _U(2)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _U(2)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _U(1)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _U(1)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW
// Description : None
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _U(0)
-#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _U(0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO"
// =============================================================================
// Register : IO_QSPI_DORMANT_WAKE_INTE
// Description : Interrupt Enable for dormant_wake
-#define IO_QSPI_DORMANT_WAKE_INTE_OFFSET _U(0x0000004c)
-#define IO_QSPI_DORMANT_WAKE_INTE_BITS _U(0x00ffffff)
-#define IO_QSPI_DORMANT_WAKE_INTE_RESET _U(0x00000000)
+#define IO_QSPI_DORMANT_WAKE_INTE_OFFSET _u(0x0000004c)
+#define IO_QSPI_DORMANT_WAKE_INTE_BITS _u(0x00ffffff)
+#define IO_QSPI_DORMANT_WAKE_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _U(23)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _U(23)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _U(0x00400000)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _U(22)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _U(22)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _U(21)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _U(21)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _U(20)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _U(20)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _U(19)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _U(19)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _U(0x00040000)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _U(18)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _U(18)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _U(17)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _U(17)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _U(16)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _U(16)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _U(15)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _U(15)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _U(0x00004000)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _U(14)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _U(14)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _U(13)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _U(13)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _U(12)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _U(12)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _U(11)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _U(11)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _U(0x00000400)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _U(10)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _U(10)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _U(9)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _U(9)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _U(8)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _U(8)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _U(7)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _U(7)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _U(0x00000040)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _U(6)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _U(6)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _U(5)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _U(5)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _U(4)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _U(4)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _U(3)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _U(3)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _U(0x00000004)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _U(2)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _U(2)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _U(1)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _U(1)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _U(0)
-#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _U(0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_QSPI_DORMANT_WAKE_INTF
// Description : Interrupt Force for dormant_wake
-#define IO_QSPI_DORMANT_WAKE_INTF_OFFSET _U(0x00000050)
-#define IO_QSPI_DORMANT_WAKE_INTF_BITS _U(0x00ffffff)
-#define IO_QSPI_DORMANT_WAKE_INTF_RESET _U(0x00000000)
+#define IO_QSPI_DORMANT_WAKE_INTF_OFFSET _u(0x00000050)
+#define IO_QSPI_DORMANT_WAKE_INTF_BITS _u(0x00ffffff)
+#define IO_QSPI_DORMANT_WAKE_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _U(23)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _U(23)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _U(0x00400000)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _U(22)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _U(22)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _U(21)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _U(21)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _U(20)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _U(20)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _U(19)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _U(19)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _U(0x00040000)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _U(18)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _U(18)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _U(17)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _U(17)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _U(16)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _U(16)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _U(15)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _U(15)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _U(0x00004000)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _U(14)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _U(14)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _U(13)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _U(13)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _U(12)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _U(12)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _U(11)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _U(11)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _U(0x00000400)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _U(10)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _U(10)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _U(9)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _U(9)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _U(8)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _U(8)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _U(7)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _U(7)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _U(0x00000040)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _U(6)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _U(6)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _U(5)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _U(5)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _U(4)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _U(4)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _U(3)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _U(3)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _U(0x00000004)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _U(2)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _U(2)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _U(1)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _U(1)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _U(0)
-#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _U(0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
// =============================================================================
// Register : IO_QSPI_DORMANT_WAKE_INTS
// Description : Interrupt status after masking & forcing for dormant_wake
-#define IO_QSPI_DORMANT_WAKE_INTS_OFFSET _U(0x00000054)
-#define IO_QSPI_DORMANT_WAKE_INTS_BITS _U(0x00ffffff)
-#define IO_QSPI_DORMANT_WAKE_INTS_RESET _U(0x00000000)
+#define IO_QSPI_DORMANT_WAKE_INTS_OFFSET _u(0x00000054)
+#define IO_QSPI_DORMANT_WAKE_INTS_BITS _u(0x00ffffff)
+#define IO_QSPI_DORMANT_WAKE_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _U(0x00800000)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _U(23)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _U(23)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _U(0x00400000)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _U(22)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _U(22)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _U(0x00200000)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _U(21)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _U(21)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _U(0x00100000)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _U(20)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _U(20)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _U(0x00080000)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _U(19)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _U(19)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _U(0x00040000)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _U(18)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _U(18)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _U(0x00020000)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _U(17)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _U(17)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _U(0x00010000)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _U(16)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _U(16)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _U(0x00008000)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _U(15)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _U(15)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _U(0x00004000)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _U(14)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _U(14)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _U(0x00002000)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _U(13)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _U(13)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _U(0x00001000)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _U(12)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _U(12)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _U(0x00000800)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _U(11)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _U(11)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _U(0x00000400)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _U(10)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _U(10)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _U(0x00000200)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _U(9)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _U(9)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _U(0x00000100)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _U(8)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _U(8)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _U(0x00000080)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _U(7)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _U(7)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _U(0x00000040)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _U(6)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _U(6)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _U(0x00000020)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _U(5)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _U(5)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _U(0x00000010)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _U(4)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _U(4)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _U(0x00000008)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _U(3)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _U(3)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _U(0x00000004)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _U(2)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _U(2)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _U(0x00000002)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _U(1)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _U(1)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW
// Description : None
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _U(0x0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _U(0x00000001)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _U(0)
-#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _U(0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_IO_QSPI_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/m0plus.h b/src/rp2040/hardware_regs/include/hardware/regs/m0plus.h
index d265a92..cef5ab0 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/m0plus.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/m0plus.h
@@ -15,17 +15,17 @@
// Register : M0PLUS_SYST_CSR
// Description : Use the SysTick Control and Status Register to enable the
// SysTick features.
-#define M0PLUS_SYST_CSR_OFFSET _U(0x0000e010)
-#define M0PLUS_SYST_CSR_BITS _U(0x00010007)
-#define M0PLUS_SYST_CSR_RESET _U(0x00000000)
+#define M0PLUS_SYST_CSR_OFFSET _u(0x0000e010)
+#define M0PLUS_SYST_CSR_BITS _u(0x00010007)
+#define M0PLUS_SYST_CSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_SYST_CSR_COUNTFLAG
// Description : Returns 1 if timer counted to 0 since last time this was read.
// Clears on read by application or debugger.
-#define M0PLUS_SYST_CSR_COUNTFLAG_RESET _U(0x0)
-#define M0PLUS_SYST_CSR_COUNTFLAG_BITS _U(0x00010000)
-#define M0PLUS_SYST_CSR_COUNTFLAG_MSB _U(16)
-#define M0PLUS_SYST_CSR_COUNTFLAG_LSB _U(16)
+#define M0PLUS_SYST_CSR_COUNTFLAG_RESET _u(0x0)
+#define M0PLUS_SYST_CSR_COUNTFLAG_BITS _u(0x00010000)
+#define M0PLUS_SYST_CSR_COUNTFLAG_MSB _u(16)
+#define M0PLUS_SYST_CSR_COUNTFLAG_LSB _u(16)
#define M0PLUS_SYST_CSR_COUNTFLAG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M0PLUS_SYST_CSR_CLKSOURCE
@@ -34,10 +34,10 @@
// Selects the SysTick timer clock source:
// 0 = External reference clock.
// 1 = Processor clock.
-#define M0PLUS_SYST_CSR_CLKSOURCE_RESET _U(0x0)
-#define M0PLUS_SYST_CSR_CLKSOURCE_BITS _U(0x00000004)
-#define M0PLUS_SYST_CSR_CLKSOURCE_MSB _U(2)
-#define M0PLUS_SYST_CSR_CLKSOURCE_LSB _U(2)
+#define M0PLUS_SYST_CSR_CLKSOURCE_RESET _u(0x0)
+#define M0PLUS_SYST_CSR_CLKSOURCE_BITS _u(0x00000004)
+#define M0PLUS_SYST_CSR_CLKSOURCE_MSB _u(2)
+#define M0PLUS_SYST_CSR_CLKSOURCE_LSB _u(2)
#define M0PLUS_SYST_CSR_CLKSOURCE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_SYST_CSR_TICKINT
@@ -46,20 +46,20 @@
// request.
// 1 = Counting down to zero to asserts the SysTick exception
// request.
-#define M0PLUS_SYST_CSR_TICKINT_RESET _U(0x0)
-#define M0PLUS_SYST_CSR_TICKINT_BITS _U(0x00000002)
-#define M0PLUS_SYST_CSR_TICKINT_MSB _U(1)
-#define M0PLUS_SYST_CSR_TICKINT_LSB _U(1)
+#define M0PLUS_SYST_CSR_TICKINT_RESET _u(0x0)
+#define M0PLUS_SYST_CSR_TICKINT_BITS _u(0x00000002)
+#define M0PLUS_SYST_CSR_TICKINT_MSB _u(1)
+#define M0PLUS_SYST_CSR_TICKINT_LSB _u(1)
#define M0PLUS_SYST_CSR_TICKINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_SYST_CSR_ENABLE
// Description : Enable SysTick counter:
// 0 = Counter disabled.
// 1 = Counter enabled.
-#define M0PLUS_SYST_CSR_ENABLE_RESET _U(0x0)
-#define M0PLUS_SYST_CSR_ENABLE_BITS _U(0x00000001)
-#define M0PLUS_SYST_CSR_ENABLE_MSB _U(0)
-#define M0PLUS_SYST_CSR_ENABLE_LSB _U(0)
+#define M0PLUS_SYST_CSR_ENABLE_RESET _u(0x0)
+#define M0PLUS_SYST_CSR_ENABLE_BITS _u(0x00000001)
+#define M0PLUS_SYST_CSR_ENABLE_MSB _u(0)
+#define M0PLUS_SYST_CSR_ENABLE_LSB _u(0)
#define M0PLUS_SYST_CSR_ENABLE_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_SYST_RVR
@@ -73,72 +73,72 @@
// clock cycles, use a RELOAD value of N-1. For example, if the
// SysTick interrupt is required every 100 clock pulses, set
// RELOAD to 99.
-#define M0PLUS_SYST_RVR_OFFSET _U(0x0000e014)
-#define M0PLUS_SYST_RVR_BITS _U(0x00ffffff)
-#define M0PLUS_SYST_RVR_RESET _U(0x00000000)
+#define M0PLUS_SYST_RVR_OFFSET _u(0x0000e014)
+#define M0PLUS_SYST_RVR_BITS _u(0x00ffffff)
+#define M0PLUS_SYST_RVR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_SYST_RVR_RELOAD
// Description : Value to load into the SysTick Current Value Register when the
// counter reaches 0.
-#define M0PLUS_SYST_RVR_RELOAD_RESET _U(0x000000)
-#define M0PLUS_SYST_RVR_RELOAD_BITS _U(0x00ffffff)
-#define M0PLUS_SYST_RVR_RELOAD_MSB _U(23)
-#define M0PLUS_SYST_RVR_RELOAD_LSB _U(0)
+#define M0PLUS_SYST_RVR_RELOAD_RESET _u(0x000000)
+#define M0PLUS_SYST_RVR_RELOAD_BITS _u(0x00ffffff)
+#define M0PLUS_SYST_RVR_RELOAD_MSB _u(23)
+#define M0PLUS_SYST_RVR_RELOAD_LSB _u(0)
#define M0PLUS_SYST_RVR_RELOAD_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_SYST_CVR
// Description : Use the SysTick Current Value Register to find the current
// value in the register. The reset value of this register is
// UNKNOWN.
-#define M0PLUS_SYST_CVR_OFFSET _U(0x0000e018)
-#define M0PLUS_SYST_CVR_BITS _U(0x00ffffff)
-#define M0PLUS_SYST_CVR_RESET _U(0x00000000)
+#define M0PLUS_SYST_CVR_OFFSET _u(0x0000e018)
+#define M0PLUS_SYST_CVR_BITS _u(0x00ffffff)
+#define M0PLUS_SYST_CVR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_SYST_CVR_CURRENT
// Description : Reads return the current value of the SysTick counter. This
// register is write-clear. Writing to it with any value clears
// the register to 0. Clearing this register also clears the
// COUNTFLAG bit of the SysTick Control and Status Register.
-#define M0PLUS_SYST_CVR_CURRENT_RESET _U(0x000000)
-#define M0PLUS_SYST_CVR_CURRENT_BITS _U(0x00ffffff)
-#define M0PLUS_SYST_CVR_CURRENT_MSB _U(23)
-#define M0PLUS_SYST_CVR_CURRENT_LSB _U(0)
+#define M0PLUS_SYST_CVR_CURRENT_RESET _u(0x000000)
+#define M0PLUS_SYST_CVR_CURRENT_BITS _u(0x00ffffff)
+#define M0PLUS_SYST_CVR_CURRENT_MSB _u(23)
+#define M0PLUS_SYST_CVR_CURRENT_LSB _u(0)
#define M0PLUS_SYST_CVR_CURRENT_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_SYST_CALIB
// Description : Use the SysTick Calibration Value Register to enable software
// to scale to any required speed using divide and multiply.
-#define M0PLUS_SYST_CALIB_OFFSET _U(0x0000e01c)
-#define M0PLUS_SYST_CALIB_BITS _U(0xc0ffffff)
-#define M0PLUS_SYST_CALIB_RESET _U(0x00000000)
+#define M0PLUS_SYST_CALIB_OFFSET _u(0x0000e01c)
+#define M0PLUS_SYST_CALIB_BITS _u(0xc0ffffff)
+#define M0PLUS_SYST_CALIB_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_SYST_CALIB_NOREF
// Description : If reads as 1, the Reference clock is not provided - the
// CLKSOURCE bit of the SysTick Control and Status register will
// be forced to 1 and cannot be cleared to 0.
-#define M0PLUS_SYST_CALIB_NOREF_RESET _U(0x0)
-#define M0PLUS_SYST_CALIB_NOREF_BITS _U(0x80000000)
-#define M0PLUS_SYST_CALIB_NOREF_MSB _U(31)
-#define M0PLUS_SYST_CALIB_NOREF_LSB _U(31)
+#define M0PLUS_SYST_CALIB_NOREF_RESET _u(0x0)
+#define M0PLUS_SYST_CALIB_NOREF_BITS _u(0x80000000)
+#define M0PLUS_SYST_CALIB_NOREF_MSB _u(31)
+#define M0PLUS_SYST_CALIB_NOREF_LSB _u(31)
#define M0PLUS_SYST_CALIB_NOREF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M0PLUS_SYST_CALIB_SKEW
// Description : If reads as 1, the calibration value for 10ms is inexact (due
// to clock frequency).
-#define M0PLUS_SYST_CALIB_SKEW_RESET _U(0x0)
-#define M0PLUS_SYST_CALIB_SKEW_BITS _U(0x40000000)
-#define M0PLUS_SYST_CALIB_SKEW_MSB _U(30)
-#define M0PLUS_SYST_CALIB_SKEW_LSB _U(30)
+#define M0PLUS_SYST_CALIB_SKEW_RESET _u(0x0)
+#define M0PLUS_SYST_CALIB_SKEW_BITS _u(0x40000000)
+#define M0PLUS_SYST_CALIB_SKEW_MSB _u(30)
+#define M0PLUS_SYST_CALIB_SKEW_LSB _u(30)
#define M0PLUS_SYST_CALIB_SKEW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M0PLUS_SYST_CALIB_TENMS
// Description : An optional Reload value to be used for 10ms (100Hz) timing,
// subject to system clock skew errors. If the value reads as 0,
// the calibration value is not known.
-#define M0PLUS_SYST_CALIB_TENMS_RESET _U(0x000000)
-#define M0PLUS_SYST_CALIB_TENMS_BITS _U(0x00ffffff)
-#define M0PLUS_SYST_CALIB_TENMS_MSB _U(23)
-#define M0PLUS_SYST_CALIB_TENMS_LSB _U(0)
+#define M0PLUS_SYST_CALIB_TENMS_RESET _u(0x000000)
+#define M0PLUS_SYST_CALIB_TENMS_BITS _u(0x00ffffff)
+#define M0PLUS_SYST_CALIB_TENMS_MSB _u(23)
+#define M0PLUS_SYST_CALIB_TENMS_LSB _u(0)
#define M0PLUS_SYST_CALIB_TENMS_ACCESS "RO"
// =============================================================================
// Register : M0PLUS_NVIC_ISER
@@ -149,9 +149,9 @@
// enabled, asserting its interrupt signal changes the interrupt
// state to pending, but the NVIC never activates the interrupt,
// regardless of its priority.
-#define M0PLUS_NVIC_ISER_OFFSET _U(0x0000e100)
-#define M0PLUS_NVIC_ISER_BITS _U(0xffffffff)
-#define M0PLUS_NVIC_ISER_RESET _U(0x00000000)
+#define M0PLUS_NVIC_ISER_OFFSET _u(0x0000e100)
+#define M0PLUS_NVIC_ISER_BITS _u(0xffffffff)
+#define M0PLUS_NVIC_ISER_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_ISER_SETENA
// Description : Interrupt set-enable bits.
@@ -161,18 +161,18 @@
// Read:
// 0 = Interrupt disabled.
// 1 = Interrupt enabled.
-#define M0PLUS_NVIC_ISER_SETENA_RESET _U(0x00000000)
-#define M0PLUS_NVIC_ISER_SETENA_BITS _U(0xffffffff)
-#define M0PLUS_NVIC_ISER_SETENA_MSB _U(31)
-#define M0PLUS_NVIC_ISER_SETENA_LSB _U(0)
+#define M0PLUS_NVIC_ISER_SETENA_RESET _u(0x00000000)
+#define M0PLUS_NVIC_ISER_SETENA_BITS _u(0xffffffff)
+#define M0PLUS_NVIC_ISER_SETENA_MSB _u(31)
+#define M0PLUS_NVIC_ISER_SETENA_LSB _u(0)
#define M0PLUS_NVIC_ISER_SETENA_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_NVIC_ICER
// Description : Use the Interrupt Clear-Enable Registers to disable interrupts
// and determine which interrupts are currently enabled.
-#define M0PLUS_NVIC_ICER_OFFSET _U(0x0000e180)
-#define M0PLUS_NVIC_ICER_BITS _U(0xffffffff)
-#define M0PLUS_NVIC_ICER_RESET _U(0x00000000)
+#define M0PLUS_NVIC_ICER_OFFSET _u(0x0000e180)
+#define M0PLUS_NVIC_ICER_BITS _u(0xffffffff)
+#define M0PLUS_NVIC_ICER_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_ICER_CLRENA
// Description : Interrupt clear-enable bits.
@@ -182,18 +182,18 @@
// Read:
// 0 = Interrupt disabled.
// 1 = Interrupt enabled.
-#define M0PLUS_NVIC_ICER_CLRENA_RESET _U(0x00000000)
-#define M0PLUS_NVIC_ICER_CLRENA_BITS _U(0xffffffff)
-#define M0PLUS_NVIC_ICER_CLRENA_MSB _U(31)
-#define M0PLUS_NVIC_ICER_CLRENA_LSB _U(0)
+#define M0PLUS_NVIC_ICER_CLRENA_RESET _u(0x00000000)
+#define M0PLUS_NVIC_ICER_CLRENA_BITS _u(0xffffffff)
+#define M0PLUS_NVIC_ICER_CLRENA_MSB _u(31)
+#define M0PLUS_NVIC_ICER_CLRENA_LSB _u(0)
#define M0PLUS_NVIC_ICER_CLRENA_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_NVIC_ISPR
// Description : The NVIC_ISPR forces interrupts into the pending state, and
// shows which interrupts are pending.
-#define M0PLUS_NVIC_ISPR_OFFSET _U(0x0000e200)
-#define M0PLUS_NVIC_ISPR_BITS _U(0xffffffff)
-#define M0PLUS_NVIC_ISPR_RESET _U(0x00000000)
+#define M0PLUS_NVIC_ISPR_OFFSET _u(0x0000e200)
+#define M0PLUS_NVIC_ISPR_BITS _u(0xffffffff)
+#define M0PLUS_NVIC_ISPR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_ISPR_SETPEND
// Description : Interrupt set-pending bits.
@@ -207,19 +207,19 @@
// An interrupt that is pending has no effect.
// A disabled interrupt sets the state of that interrupt to
// pending.
-#define M0PLUS_NVIC_ISPR_SETPEND_RESET _U(0x00000000)
-#define M0PLUS_NVIC_ISPR_SETPEND_BITS _U(0xffffffff)
-#define M0PLUS_NVIC_ISPR_SETPEND_MSB _U(31)
-#define M0PLUS_NVIC_ISPR_SETPEND_LSB _U(0)
+#define M0PLUS_NVIC_ISPR_SETPEND_RESET _u(0x00000000)
+#define M0PLUS_NVIC_ISPR_SETPEND_BITS _u(0xffffffff)
+#define M0PLUS_NVIC_ISPR_SETPEND_MSB _u(31)
+#define M0PLUS_NVIC_ISPR_SETPEND_LSB _u(0)
#define M0PLUS_NVIC_ISPR_SETPEND_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_NVIC_ICPR
// Description : Use the Interrupt Clear-Pending Register to clear pending
// interrupts and determine which interrupts are currently
// pending.
-#define M0PLUS_NVIC_ICPR_OFFSET _U(0x0000e280)
-#define M0PLUS_NVIC_ICPR_BITS _U(0xffffffff)
-#define M0PLUS_NVIC_ICPR_RESET _U(0x00000000)
+#define M0PLUS_NVIC_ICPR_OFFSET _u(0x0000e280)
+#define M0PLUS_NVIC_ICPR_BITS _u(0xffffffff)
+#define M0PLUS_NVIC_ICPR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_ICPR_CLRPEND
// Description : Interrupt clear-pending bits.
@@ -229,10 +229,10 @@
// Read:
// 0 = Interrupt is not pending.
// 1 = Interrupt is pending.
-#define M0PLUS_NVIC_ICPR_CLRPEND_RESET _U(0x00000000)
-#define M0PLUS_NVIC_ICPR_CLRPEND_BITS _U(0xffffffff)
-#define M0PLUS_NVIC_ICPR_CLRPEND_MSB _U(31)
-#define M0PLUS_NVIC_ICPR_CLRPEND_LSB _U(0)
+#define M0PLUS_NVIC_ICPR_CLRPEND_RESET _u(0x00000000)
+#define M0PLUS_NVIC_ICPR_CLRPEND_BITS _u(0xffffffff)
+#define M0PLUS_NVIC_ICPR_CLRPEND_MSB _u(31)
+#define M0PLUS_NVIC_ICPR_CLRPEND_LSB _u(0)
#define M0PLUS_NVIC_ICPR_CLRPEND_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_NVIC_IPR0
@@ -242,371 +242,371 @@
// Note: Writing 1 to an NVIC_ICPR bit does not affect the active
// state of the corresponding interrupt.
// These registers are only word-accessible
-#define M0PLUS_NVIC_IPR0_OFFSET _U(0x0000e400)
-#define M0PLUS_NVIC_IPR0_BITS _U(0xc0c0c0c0)
-#define M0PLUS_NVIC_IPR0_RESET _U(0x00000000)
+#define M0PLUS_NVIC_IPR0_OFFSET _u(0x0000e400)
+#define M0PLUS_NVIC_IPR0_BITS _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR0_IP_3
// Description : Priority of interrupt 3
-#define M0PLUS_NVIC_IPR0_IP_3_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR0_IP_3_BITS _U(0xc0000000)
-#define M0PLUS_NVIC_IPR0_IP_3_MSB _U(31)
-#define M0PLUS_NVIC_IPR0_IP_3_LSB _U(30)
+#define M0PLUS_NVIC_IPR0_IP_3_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR0_IP_3_BITS _u(0xc0000000)
+#define M0PLUS_NVIC_IPR0_IP_3_MSB _u(31)
+#define M0PLUS_NVIC_IPR0_IP_3_LSB _u(30)
#define M0PLUS_NVIC_IPR0_IP_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR0_IP_2
// Description : Priority of interrupt 2
-#define M0PLUS_NVIC_IPR0_IP_2_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR0_IP_2_BITS _U(0x00c00000)
-#define M0PLUS_NVIC_IPR0_IP_2_MSB _U(23)
-#define M0PLUS_NVIC_IPR0_IP_2_LSB _U(22)
+#define M0PLUS_NVIC_IPR0_IP_2_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR0_IP_2_BITS _u(0x00c00000)
+#define M0PLUS_NVIC_IPR0_IP_2_MSB _u(23)
+#define M0PLUS_NVIC_IPR0_IP_2_LSB _u(22)
#define M0PLUS_NVIC_IPR0_IP_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR0_IP_1
// Description : Priority of interrupt 1
-#define M0PLUS_NVIC_IPR0_IP_1_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR0_IP_1_BITS _U(0x0000c000)
-#define M0PLUS_NVIC_IPR0_IP_1_MSB _U(15)
-#define M0PLUS_NVIC_IPR0_IP_1_LSB _U(14)
+#define M0PLUS_NVIC_IPR0_IP_1_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR0_IP_1_BITS _u(0x0000c000)
+#define M0PLUS_NVIC_IPR0_IP_1_MSB _u(15)
+#define M0PLUS_NVIC_IPR0_IP_1_LSB _u(14)
#define M0PLUS_NVIC_IPR0_IP_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR0_IP_0
// Description : Priority of interrupt 0
-#define M0PLUS_NVIC_IPR0_IP_0_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR0_IP_0_BITS _U(0x000000c0)
-#define M0PLUS_NVIC_IPR0_IP_0_MSB _U(7)
-#define M0PLUS_NVIC_IPR0_IP_0_LSB _U(6)
+#define M0PLUS_NVIC_IPR0_IP_0_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR0_IP_0_BITS _u(0x000000c0)
+#define M0PLUS_NVIC_IPR0_IP_0_MSB _u(7)
+#define M0PLUS_NVIC_IPR0_IP_0_LSB _u(6)
#define M0PLUS_NVIC_IPR0_IP_0_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_NVIC_IPR1
// Description : Use the Interrupt Priority Registers to assign a priority from
// 0 to 3 to each of the available interrupts. 0 is the highest
// priority, and 3 is the lowest.
-#define M0PLUS_NVIC_IPR1_OFFSET _U(0x0000e404)
-#define M0PLUS_NVIC_IPR1_BITS _U(0xc0c0c0c0)
-#define M0PLUS_NVIC_IPR1_RESET _U(0x00000000)
+#define M0PLUS_NVIC_IPR1_OFFSET _u(0x0000e404)
+#define M0PLUS_NVIC_IPR1_BITS _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR1_IP_7
// Description : Priority of interrupt 7
-#define M0PLUS_NVIC_IPR1_IP_7_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR1_IP_7_BITS _U(0xc0000000)
-#define M0PLUS_NVIC_IPR1_IP_7_MSB _U(31)
-#define M0PLUS_NVIC_IPR1_IP_7_LSB _U(30)
+#define M0PLUS_NVIC_IPR1_IP_7_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR1_IP_7_BITS _u(0xc0000000)
+#define M0PLUS_NVIC_IPR1_IP_7_MSB _u(31)
+#define M0PLUS_NVIC_IPR1_IP_7_LSB _u(30)
#define M0PLUS_NVIC_IPR1_IP_7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR1_IP_6
// Description : Priority of interrupt 6
-#define M0PLUS_NVIC_IPR1_IP_6_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR1_IP_6_BITS _U(0x00c00000)
-#define M0PLUS_NVIC_IPR1_IP_6_MSB _U(23)
-#define M0PLUS_NVIC_IPR1_IP_6_LSB _U(22)
+#define M0PLUS_NVIC_IPR1_IP_6_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR1_IP_6_BITS _u(0x00c00000)
+#define M0PLUS_NVIC_IPR1_IP_6_MSB _u(23)
+#define M0PLUS_NVIC_IPR1_IP_6_LSB _u(22)
#define M0PLUS_NVIC_IPR1_IP_6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR1_IP_5
// Description : Priority of interrupt 5
-#define M0PLUS_NVIC_IPR1_IP_5_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR1_IP_5_BITS _U(0x0000c000)
-#define M0PLUS_NVIC_IPR1_IP_5_MSB _U(15)
-#define M0PLUS_NVIC_IPR1_IP_5_LSB _U(14)
+#define M0PLUS_NVIC_IPR1_IP_5_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR1_IP_5_BITS _u(0x0000c000)
+#define M0PLUS_NVIC_IPR1_IP_5_MSB _u(15)
+#define M0PLUS_NVIC_IPR1_IP_5_LSB _u(14)
#define M0PLUS_NVIC_IPR1_IP_5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR1_IP_4
// Description : Priority of interrupt 4
-#define M0PLUS_NVIC_IPR1_IP_4_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR1_IP_4_BITS _U(0x000000c0)
-#define M0PLUS_NVIC_IPR1_IP_4_MSB _U(7)
-#define M0PLUS_NVIC_IPR1_IP_4_LSB _U(6)
+#define M0PLUS_NVIC_IPR1_IP_4_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR1_IP_4_BITS _u(0x000000c0)
+#define M0PLUS_NVIC_IPR1_IP_4_MSB _u(7)
+#define M0PLUS_NVIC_IPR1_IP_4_LSB _u(6)
#define M0PLUS_NVIC_IPR1_IP_4_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_NVIC_IPR2
// Description : Use the Interrupt Priority Registers to assign a priority from
// 0 to 3 to each of the available interrupts. 0 is the highest
// priority, and 3 is the lowest.
-#define M0PLUS_NVIC_IPR2_OFFSET _U(0x0000e408)
-#define M0PLUS_NVIC_IPR2_BITS _U(0xc0c0c0c0)
-#define M0PLUS_NVIC_IPR2_RESET _U(0x00000000)
+#define M0PLUS_NVIC_IPR2_OFFSET _u(0x0000e408)
+#define M0PLUS_NVIC_IPR2_BITS _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR2_IP_11
// Description : Priority of interrupt 11
-#define M0PLUS_NVIC_IPR2_IP_11_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR2_IP_11_BITS _U(0xc0000000)
-#define M0PLUS_NVIC_IPR2_IP_11_MSB _U(31)
-#define M0PLUS_NVIC_IPR2_IP_11_LSB _U(30)
+#define M0PLUS_NVIC_IPR2_IP_11_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR2_IP_11_BITS _u(0xc0000000)
+#define M0PLUS_NVIC_IPR2_IP_11_MSB _u(31)
+#define M0PLUS_NVIC_IPR2_IP_11_LSB _u(30)
#define M0PLUS_NVIC_IPR2_IP_11_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR2_IP_10
// Description : Priority of interrupt 10
-#define M0PLUS_NVIC_IPR2_IP_10_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR2_IP_10_BITS _U(0x00c00000)
-#define M0PLUS_NVIC_IPR2_IP_10_MSB _U(23)
-#define M0PLUS_NVIC_IPR2_IP_10_LSB _U(22)
+#define M0PLUS_NVIC_IPR2_IP_10_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR2_IP_10_BITS _u(0x00c00000)
+#define M0PLUS_NVIC_IPR2_IP_10_MSB _u(23)
+#define M0PLUS_NVIC_IPR2_IP_10_LSB _u(22)
#define M0PLUS_NVIC_IPR2_IP_10_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR2_IP_9
// Description : Priority of interrupt 9
-#define M0PLUS_NVIC_IPR2_IP_9_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR2_IP_9_BITS _U(0x0000c000)
-#define M0PLUS_NVIC_IPR2_IP_9_MSB _U(15)
-#define M0PLUS_NVIC_IPR2_IP_9_LSB _U(14)
+#define M0PLUS_NVIC_IPR2_IP_9_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR2_IP_9_BITS _u(0x0000c000)
+#define M0PLUS_NVIC_IPR2_IP_9_MSB _u(15)
+#define M0PLUS_NVIC_IPR2_IP_9_LSB _u(14)
#define M0PLUS_NVIC_IPR2_IP_9_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR2_IP_8
// Description : Priority of interrupt 8
-#define M0PLUS_NVIC_IPR2_IP_8_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR2_IP_8_BITS _U(0x000000c0)
-#define M0PLUS_NVIC_IPR2_IP_8_MSB _U(7)
-#define M0PLUS_NVIC_IPR2_IP_8_LSB _U(6)
+#define M0PLUS_NVIC_IPR2_IP_8_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR2_IP_8_BITS _u(0x000000c0)
+#define M0PLUS_NVIC_IPR2_IP_8_MSB _u(7)
+#define M0PLUS_NVIC_IPR2_IP_8_LSB _u(6)
#define M0PLUS_NVIC_IPR2_IP_8_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_NVIC_IPR3
// Description : Use the Interrupt Priority Registers to assign a priority from
// 0 to 3 to each of the available interrupts. 0 is the highest
// priority, and 3 is the lowest.
-#define M0PLUS_NVIC_IPR3_OFFSET _U(0x0000e40c)
-#define M0PLUS_NVIC_IPR3_BITS _U(0xc0c0c0c0)
-#define M0PLUS_NVIC_IPR3_RESET _U(0x00000000)
+#define M0PLUS_NVIC_IPR3_OFFSET _u(0x0000e40c)
+#define M0PLUS_NVIC_IPR3_BITS _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR3_IP_15
// Description : Priority of interrupt 15
-#define M0PLUS_NVIC_IPR3_IP_15_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR3_IP_15_BITS _U(0xc0000000)
-#define M0PLUS_NVIC_IPR3_IP_15_MSB _U(31)
-#define M0PLUS_NVIC_IPR3_IP_15_LSB _U(30)
+#define M0PLUS_NVIC_IPR3_IP_15_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR3_IP_15_BITS _u(0xc0000000)
+#define M0PLUS_NVIC_IPR3_IP_15_MSB _u(31)
+#define M0PLUS_NVIC_IPR3_IP_15_LSB _u(30)
#define M0PLUS_NVIC_IPR3_IP_15_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR3_IP_14
// Description : Priority of interrupt 14
-#define M0PLUS_NVIC_IPR3_IP_14_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR3_IP_14_BITS _U(0x00c00000)
-#define M0PLUS_NVIC_IPR3_IP_14_MSB _U(23)
-#define M0PLUS_NVIC_IPR3_IP_14_LSB _U(22)
+#define M0PLUS_NVIC_IPR3_IP_14_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR3_IP_14_BITS _u(0x00c00000)
+#define M0PLUS_NVIC_IPR3_IP_14_MSB _u(23)
+#define M0PLUS_NVIC_IPR3_IP_14_LSB _u(22)
#define M0PLUS_NVIC_IPR3_IP_14_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR3_IP_13
// Description : Priority of interrupt 13
-#define M0PLUS_NVIC_IPR3_IP_13_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR3_IP_13_BITS _U(0x0000c000)
-#define M0PLUS_NVIC_IPR3_IP_13_MSB _U(15)
-#define M0PLUS_NVIC_IPR3_IP_13_LSB _U(14)
+#define M0PLUS_NVIC_IPR3_IP_13_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR3_IP_13_BITS _u(0x0000c000)
+#define M0PLUS_NVIC_IPR3_IP_13_MSB _u(15)
+#define M0PLUS_NVIC_IPR3_IP_13_LSB _u(14)
#define M0PLUS_NVIC_IPR3_IP_13_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR3_IP_12
// Description : Priority of interrupt 12
-#define M0PLUS_NVIC_IPR3_IP_12_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR3_IP_12_BITS _U(0x000000c0)
-#define M0PLUS_NVIC_IPR3_IP_12_MSB _U(7)
-#define M0PLUS_NVIC_IPR3_IP_12_LSB _U(6)
+#define M0PLUS_NVIC_IPR3_IP_12_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR3_IP_12_BITS _u(0x000000c0)
+#define M0PLUS_NVIC_IPR3_IP_12_MSB _u(7)
+#define M0PLUS_NVIC_IPR3_IP_12_LSB _u(6)
#define M0PLUS_NVIC_IPR3_IP_12_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_NVIC_IPR4
// Description : Use the Interrupt Priority Registers to assign a priority from
// 0 to 3 to each of the available interrupts. 0 is the highest
// priority, and 3 is the lowest.
-#define M0PLUS_NVIC_IPR4_OFFSET _U(0x0000e410)
-#define M0PLUS_NVIC_IPR4_BITS _U(0xc0c0c0c0)
-#define M0PLUS_NVIC_IPR4_RESET _U(0x00000000)
+#define M0PLUS_NVIC_IPR4_OFFSET _u(0x0000e410)
+#define M0PLUS_NVIC_IPR4_BITS _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR4_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR4_IP_19
// Description : Priority of interrupt 19
-#define M0PLUS_NVIC_IPR4_IP_19_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR4_IP_19_BITS _U(0xc0000000)
-#define M0PLUS_NVIC_IPR4_IP_19_MSB _U(31)
-#define M0PLUS_NVIC_IPR4_IP_19_LSB _U(30)
+#define M0PLUS_NVIC_IPR4_IP_19_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR4_IP_19_BITS _u(0xc0000000)
+#define M0PLUS_NVIC_IPR4_IP_19_MSB _u(31)
+#define M0PLUS_NVIC_IPR4_IP_19_LSB _u(30)
#define M0PLUS_NVIC_IPR4_IP_19_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR4_IP_18
// Description : Priority of interrupt 18
-#define M0PLUS_NVIC_IPR4_IP_18_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR4_IP_18_BITS _U(0x00c00000)
-#define M0PLUS_NVIC_IPR4_IP_18_MSB _U(23)
-#define M0PLUS_NVIC_IPR4_IP_18_LSB _U(22)
+#define M0PLUS_NVIC_IPR4_IP_18_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR4_IP_18_BITS _u(0x00c00000)
+#define M0PLUS_NVIC_IPR4_IP_18_MSB _u(23)
+#define M0PLUS_NVIC_IPR4_IP_18_LSB _u(22)
#define M0PLUS_NVIC_IPR4_IP_18_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR4_IP_17
// Description : Priority of interrupt 17
-#define M0PLUS_NVIC_IPR4_IP_17_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR4_IP_17_BITS _U(0x0000c000)
-#define M0PLUS_NVIC_IPR4_IP_17_MSB _U(15)
-#define M0PLUS_NVIC_IPR4_IP_17_LSB _U(14)
+#define M0PLUS_NVIC_IPR4_IP_17_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR4_IP_17_BITS _u(0x0000c000)
+#define M0PLUS_NVIC_IPR4_IP_17_MSB _u(15)
+#define M0PLUS_NVIC_IPR4_IP_17_LSB _u(14)
#define M0PLUS_NVIC_IPR4_IP_17_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR4_IP_16
// Description : Priority of interrupt 16
-#define M0PLUS_NVIC_IPR4_IP_16_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR4_IP_16_BITS _U(0x000000c0)
-#define M0PLUS_NVIC_IPR4_IP_16_MSB _U(7)
-#define M0PLUS_NVIC_IPR4_IP_16_LSB _U(6)
+#define M0PLUS_NVIC_IPR4_IP_16_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR4_IP_16_BITS _u(0x000000c0)
+#define M0PLUS_NVIC_IPR4_IP_16_MSB _u(7)
+#define M0PLUS_NVIC_IPR4_IP_16_LSB _u(6)
#define M0PLUS_NVIC_IPR4_IP_16_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_NVIC_IPR5
// Description : Use the Interrupt Priority Registers to assign a priority from
// 0 to 3 to each of the available interrupts. 0 is the highest
// priority, and 3 is the lowest.
-#define M0PLUS_NVIC_IPR5_OFFSET _U(0x0000e414)
-#define M0PLUS_NVIC_IPR5_BITS _U(0xc0c0c0c0)
-#define M0PLUS_NVIC_IPR5_RESET _U(0x00000000)
+#define M0PLUS_NVIC_IPR5_OFFSET _u(0x0000e414)
+#define M0PLUS_NVIC_IPR5_BITS _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR5_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR5_IP_23
// Description : Priority of interrupt 23
-#define M0PLUS_NVIC_IPR5_IP_23_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR5_IP_23_BITS _U(0xc0000000)
-#define M0PLUS_NVIC_IPR5_IP_23_MSB _U(31)
-#define M0PLUS_NVIC_IPR5_IP_23_LSB _U(30)
+#define M0PLUS_NVIC_IPR5_IP_23_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR5_IP_23_BITS _u(0xc0000000)
+#define M0PLUS_NVIC_IPR5_IP_23_MSB _u(31)
+#define M0PLUS_NVIC_IPR5_IP_23_LSB _u(30)
#define M0PLUS_NVIC_IPR5_IP_23_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR5_IP_22
// Description : Priority of interrupt 22
-#define M0PLUS_NVIC_IPR5_IP_22_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR5_IP_22_BITS _U(0x00c00000)
-#define M0PLUS_NVIC_IPR5_IP_22_MSB _U(23)
-#define M0PLUS_NVIC_IPR5_IP_22_LSB _U(22)
+#define M0PLUS_NVIC_IPR5_IP_22_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR5_IP_22_BITS _u(0x00c00000)
+#define M0PLUS_NVIC_IPR5_IP_22_MSB _u(23)
+#define M0PLUS_NVIC_IPR5_IP_22_LSB _u(22)
#define M0PLUS_NVIC_IPR5_IP_22_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR5_IP_21
// Description : Priority of interrupt 21
-#define M0PLUS_NVIC_IPR5_IP_21_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR5_IP_21_BITS _U(0x0000c000)
-#define M0PLUS_NVIC_IPR5_IP_21_MSB _U(15)
-#define M0PLUS_NVIC_IPR5_IP_21_LSB _U(14)
+#define M0PLUS_NVIC_IPR5_IP_21_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR5_IP_21_BITS _u(0x0000c000)
+#define M0PLUS_NVIC_IPR5_IP_21_MSB _u(15)
+#define M0PLUS_NVIC_IPR5_IP_21_LSB _u(14)
#define M0PLUS_NVIC_IPR5_IP_21_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR5_IP_20
// Description : Priority of interrupt 20
-#define M0PLUS_NVIC_IPR5_IP_20_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR5_IP_20_BITS _U(0x000000c0)
-#define M0PLUS_NVIC_IPR5_IP_20_MSB _U(7)
-#define M0PLUS_NVIC_IPR5_IP_20_LSB _U(6)
+#define M0PLUS_NVIC_IPR5_IP_20_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR5_IP_20_BITS _u(0x000000c0)
+#define M0PLUS_NVIC_IPR5_IP_20_MSB _u(7)
+#define M0PLUS_NVIC_IPR5_IP_20_LSB _u(6)
#define M0PLUS_NVIC_IPR5_IP_20_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_NVIC_IPR6
// Description : Use the Interrupt Priority Registers to assign a priority from
// 0 to 3 to each of the available interrupts. 0 is the highest
// priority, and 3 is the lowest.
-#define M0PLUS_NVIC_IPR6_OFFSET _U(0x0000e418)
-#define M0PLUS_NVIC_IPR6_BITS _U(0xc0c0c0c0)
-#define M0PLUS_NVIC_IPR6_RESET _U(0x00000000)
+#define M0PLUS_NVIC_IPR6_OFFSET _u(0x0000e418)
+#define M0PLUS_NVIC_IPR6_BITS _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR6_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR6_IP_27
// Description : Priority of interrupt 27
-#define M0PLUS_NVIC_IPR6_IP_27_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR6_IP_27_BITS _U(0xc0000000)
-#define M0PLUS_NVIC_IPR6_IP_27_MSB _U(31)
-#define M0PLUS_NVIC_IPR6_IP_27_LSB _U(30)
+#define M0PLUS_NVIC_IPR6_IP_27_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR6_IP_27_BITS _u(0xc0000000)
+#define M0PLUS_NVIC_IPR6_IP_27_MSB _u(31)
+#define M0PLUS_NVIC_IPR6_IP_27_LSB _u(30)
#define M0PLUS_NVIC_IPR6_IP_27_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR6_IP_26
// Description : Priority of interrupt 26
-#define M0PLUS_NVIC_IPR6_IP_26_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR6_IP_26_BITS _U(0x00c00000)
-#define M0PLUS_NVIC_IPR6_IP_26_MSB _U(23)
-#define M0PLUS_NVIC_IPR6_IP_26_LSB _U(22)
+#define M0PLUS_NVIC_IPR6_IP_26_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR6_IP_26_BITS _u(0x00c00000)
+#define M0PLUS_NVIC_IPR6_IP_26_MSB _u(23)
+#define M0PLUS_NVIC_IPR6_IP_26_LSB _u(22)
#define M0PLUS_NVIC_IPR6_IP_26_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR6_IP_25
// Description : Priority of interrupt 25
-#define M0PLUS_NVIC_IPR6_IP_25_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR6_IP_25_BITS _U(0x0000c000)
-#define M0PLUS_NVIC_IPR6_IP_25_MSB _U(15)
-#define M0PLUS_NVIC_IPR6_IP_25_LSB _U(14)
+#define M0PLUS_NVIC_IPR6_IP_25_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR6_IP_25_BITS _u(0x0000c000)
+#define M0PLUS_NVIC_IPR6_IP_25_MSB _u(15)
+#define M0PLUS_NVIC_IPR6_IP_25_LSB _u(14)
#define M0PLUS_NVIC_IPR6_IP_25_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR6_IP_24
// Description : Priority of interrupt 24
-#define M0PLUS_NVIC_IPR6_IP_24_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR6_IP_24_BITS _U(0x000000c0)
-#define M0PLUS_NVIC_IPR6_IP_24_MSB _U(7)
-#define M0PLUS_NVIC_IPR6_IP_24_LSB _U(6)
+#define M0PLUS_NVIC_IPR6_IP_24_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR6_IP_24_BITS _u(0x000000c0)
+#define M0PLUS_NVIC_IPR6_IP_24_MSB _u(7)
+#define M0PLUS_NVIC_IPR6_IP_24_LSB _u(6)
#define M0PLUS_NVIC_IPR6_IP_24_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_NVIC_IPR7
// Description : Use the Interrupt Priority Registers to assign a priority from
// 0 to 3 to each of the available interrupts. 0 is the highest
// priority, and 3 is the lowest.
-#define M0PLUS_NVIC_IPR7_OFFSET _U(0x0000e41c)
-#define M0PLUS_NVIC_IPR7_BITS _U(0xc0c0c0c0)
-#define M0PLUS_NVIC_IPR7_RESET _U(0x00000000)
+#define M0PLUS_NVIC_IPR7_OFFSET _u(0x0000e41c)
+#define M0PLUS_NVIC_IPR7_BITS _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR7_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR7_IP_31
// Description : Priority of interrupt 31
-#define M0PLUS_NVIC_IPR7_IP_31_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR7_IP_31_BITS _U(0xc0000000)
-#define M0PLUS_NVIC_IPR7_IP_31_MSB _U(31)
-#define M0PLUS_NVIC_IPR7_IP_31_LSB _U(30)
+#define M0PLUS_NVIC_IPR7_IP_31_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR7_IP_31_BITS _u(0xc0000000)
+#define M0PLUS_NVIC_IPR7_IP_31_MSB _u(31)
+#define M0PLUS_NVIC_IPR7_IP_31_LSB _u(30)
#define M0PLUS_NVIC_IPR7_IP_31_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR7_IP_30
// Description : Priority of interrupt 30
-#define M0PLUS_NVIC_IPR7_IP_30_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR7_IP_30_BITS _U(0x00c00000)
-#define M0PLUS_NVIC_IPR7_IP_30_MSB _U(23)
-#define M0PLUS_NVIC_IPR7_IP_30_LSB _U(22)
+#define M0PLUS_NVIC_IPR7_IP_30_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR7_IP_30_BITS _u(0x00c00000)
+#define M0PLUS_NVIC_IPR7_IP_30_MSB _u(23)
+#define M0PLUS_NVIC_IPR7_IP_30_LSB _u(22)
#define M0PLUS_NVIC_IPR7_IP_30_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR7_IP_29
// Description : Priority of interrupt 29
-#define M0PLUS_NVIC_IPR7_IP_29_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR7_IP_29_BITS _U(0x0000c000)
-#define M0PLUS_NVIC_IPR7_IP_29_MSB _U(15)
-#define M0PLUS_NVIC_IPR7_IP_29_LSB _U(14)
+#define M0PLUS_NVIC_IPR7_IP_29_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR7_IP_29_BITS _u(0x0000c000)
+#define M0PLUS_NVIC_IPR7_IP_29_MSB _u(15)
+#define M0PLUS_NVIC_IPR7_IP_29_LSB _u(14)
#define M0PLUS_NVIC_IPR7_IP_29_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_NVIC_IPR7_IP_28
// Description : Priority of interrupt 28
-#define M0PLUS_NVIC_IPR7_IP_28_RESET _U(0x0)
-#define M0PLUS_NVIC_IPR7_IP_28_BITS _U(0x000000c0)
-#define M0PLUS_NVIC_IPR7_IP_28_MSB _U(7)
-#define M0PLUS_NVIC_IPR7_IP_28_LSB _U(6)
+#define M0PLUS_NVIC_IPR7_IP_28_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR7_IP_28_BITS _u(0x000000c0)
+#define M0PLUS_NVIC_IPR7_IP_28_MSB _u(7)
+#define M0PLUS_NVIC_IPR7_IP_28_LSB _u(6)
#define M0PLUS_NVIC_IPR7_IP_28_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_CPUID
// Description : Read the CPU ID Base Register to determine: the ID number of
// the processor core, the version number of the processor core,
// the implementation details of the processor core.
-#define M0PLUS_CPUID_OFFSET _U(0x0000ed00)
-#define M0PLUS_CPUID_BITS _U(0xffffffff)
-#define M0PLUS_CPUID_RESET _U(0x410cc601)
+#define M0PLUS_CPUID_OFFSET _u(0x0000ed00)
+#define M0PLUS_CPUID_BITS _u(0xffffffff)
+#define M0PLUS_CPUID_RESET _u(0x410cc601)
// -----------------------------------------------------------------------------
// Field : M0PLUS_CPUID_IMPLEMENTER
// Description : Implementor code: 0x41 = ARM
-#define M0PLUS_CPUID_IMPLEMENTER_RESET _U(0x41)
-#define M0PLUS_CPUID_IMPLEMENTER_BITS _U(0xff000000)
-#define M0PLUS_CPUID_IMPLEMENTER_MSB _U(31)
-#define M0PLUS_CPUID_IMPLEMENTER_LSB _U(24)
+#define M0PLUS_CPUID_IMPLEMENTER_RESET _u(0x41)
+#define M0PLUS_CPUID_IMPLEMENTER_BITS _u(0xff000000)
+#define M0PLUS_CPUID_IMPLEMENTER_MSB _u(31)
+#define M0PLUS_CPUID_IMPLEMENTER_LSB _u(24)
#define M0PLUS_CPUID_IMPLEMENTER_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M0PLUS_CPUID_VARIANT
// Description : Major revision number n in the rnpm revision status:
// 0x0 = Revision 0.
-#define M0PLUS_CPUID_VARIANT_RESET _U(0x0)
-#define M0PLUS_CPUID_VARIANT_BITS _U(0x00f00000)
-#define M0PLUS_CPUID_VARIANT_MSB _U(23)
-#define M0PLUS_CPUID_VARIANT_LSB _U(20)
+#define M0PLUS_CPUID_VARIANT_RESET _u(0x0)
+#define M0PLUS_CPUID_VARIANT_BITS _u(0x00f00000)
+#define M0PLUS_CPUID_VARIANT_MSB _u(23)
+#define M0PLUS_CPUID_VARIANT_LSB _u(20)
#define M0PLUS_CPUID_VARIANT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M0PLUS_CPUID_ARCHITECTURE
// Description : Constant that defines the architecture of the processor:
// 0xC = ARMv6-M architecture.
-#define M0PLUS_CPUID_ARCHITECTURE_RESET _U(0xc)
-#define M0PLUS_CPUID_ARCHITECTURE_BITS _U(0x000f0000)
-#define M0PLUS_CPUID_ARCHITECTURE_MSB _U(19)
-#define M0PLUS_CPUID_ARCHITECTURE_LSB _U(16)
+#define M0PLUS_CPUID_ARCHITECTURE_RESET _u(0xc)
+#define M0PLUS_CPUID_ARCHITECTURE_BITS _u(0x000f0000)
+#define M0PLUS_CPUID_ARCHITECTURE_MSB _u(19)
+#define M0PLUS_CPUID_ARCHITECTURE_LSB _u(16)
#define M0PLUS_CPUID_ARCHITECTURE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M0PLUS_CPUID_PARTNO
// Description : Number of processor within family: 0xC60 = Cortex-M0+
-#define M0PLUS_CPUID_PARTNO_RESET _U(0xc60)
-#define M0PLUS_CPUID_PARTNO_BITS _U(0x0000fff0)
-#define M0PLUS_CPUID_PARTNO_MSB _U(15)
-#define M0PLUS_CPUID_PARTNO_LSB _U(4)
+#define M0PLUS_CPUID_PARTNO_RESET _u(0xc60)
+#define M0PLUS_CPUID_PARTNO_BITS _u(0x0000fff0)
+#define M0PLUS_CPUID_PARTNO_MSB _u(15)
+#define M0PLUS_CPUID_PARTNO_LSB _u(4)
#define M0PLUS_CPUID_PARTNO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M0PLUS_CPUID_REVISION
// Description : Minor revision number m in the rnpm revision status:
// 0x1 = Patch 1.
-#define M0PLUS_CPUID_REVISION_RESET _U(0x1)
-#define M0PLUS_CPUID_REVISION_BITS _U(0x0000000f)
-#define M0PLUS_CPUID_REVISION_MSB _U(3)
-#define M0PLUS_CPUID_REVISION_LSB _U(0)
+#define M0PLUS_CPUID_REVISION_RESET _u(0x1)
+#define M0PLUS_CPUID_REVISION_BITS _u(0x0000000f)
+#define M0PLUS_CPUID_REVISION_MSB _u(3)
+#define M0PLUS_CPUID_REVISION_LSB _u(0)
#define M0PLUS_CPUID_REVISION_ACCESS "RO"
// =============================================================================
// Register : M0PLUS_ICSR
@@ -615,9 +615,9 @@
// set or clear a pending SysTick, check for pending exceptions,
// check the vector number of the highest priority pended
// exception, check the vector number of the active exception.
-#define M0PLUS_ICSR_OFFSET _U(0x0000ed04)
-#define M0PLUS_ICSR_BITS _U(0x9edff1ff)
-#define M0PLUS_ICSR_RESET _U(0x00000000)
+#define M0PLUS_ICSR_OFFSET _u(0x0000ed04)
+#define M0PLUS_ICSR_BITS _u(0x9edff1ff)
+#define M0PLUS_ICSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_ICSR_NMIPENDSET
// Description : Setting this bit will activate an NMI. Since NMI is the highest
@@ -638,10 +638,10 @@
// exception handler returns 1 only if the
// NMI signal is reasserted while the processor is executing that
// handler.
-#define M0PLUS_ICSR_NMIPENDSET_RESET _U(0x0)
-#define M0PLUS_ICSR_NMIPENDSET_BITS _U(0x80000000)
-#define M0PLUS_ICSR_NMIPENDSET_MSB _U(31)
-#define M0PLUS_ICSR_NMIPENDSET_LSB _U(31)
+#define M0PLUS_ICSR_NMIPENDSET_RESET _u(0x0)
+#define M0PLUS_ICSR_NMIPENDSET_BITS _u(0x80000000)
+#define M0PLUS_ICSR_NMIPENDSET_MSB _u(31)
+#define M0PLUS_ICSR_NMIPENDSET_LSB _u(31)
#define M0PLUS_ICSR_NMIPENDSET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_ICSR_PENDSVSET
@@ -654,10 +654,10 @@
// 1 = PendSV exception is pending.
// Writing 1 to this bit is the only way to set the PendSV
// exception state to pending.
-#define M0PLUS_ICSR_PENDSVSET_RESET _U(0x0)
-#define M0PLUS_ICSR_PENDSVSET_BITS _U(0x10000000)
-#define M0PLUS_ICSR_PENDSVSET_MSB _U(28)
-#define M0PLUS_ICSR_PENDSVSET_LSB _U(28)
+#define M0PLUS_ICSR_PENDSVSET_RESET _u(0x0)
+#define M0PLUS_ICSR_PENDSVSET_BITS _u(0x10000000)
+#define M0PLUS_ICSR_PENDSVSET_MSB _u(28)
+#define M0PLUS_ICSR_PENDSVSET_LSB _u(28)
#define M0PLUS_ICSR_PENDSVSET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_ICSR_PENDSVCLR
@@ -665,10 +665,10 @@
// Write:
// 0 = No effect.
// 1 = Removes the pending state from the PendSV exception.
-#define M0PLUS_ICSR_PENDSVCLR_RESET _U(0x0)
-#define M0PLUS_ICSR_PENDSVCLR_BITS _U(0x08000000)
-#define M0PLUS_ICSR_PENDSVCLR_MSB _U(27)
-#define M0PLUS_ICSR_PENDSVCLR_LSB _U(27)
+#define M0PLUS_ICSR_PENDSVCLR_RESET _u(0x0)
+#define M0PLUS_ICSR_PENDSVCLR_BITS _u(0x08000000)
+#define M0PLUS_ICSR_PENDSVCLR_MSB _u(27)
+#define M0PLUS_ICSR_PENDSVCLR_LSB _u(27)
#define M0PLUS_ICSR_PENDSVCLR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_ICSR_PENDSTSET
@@ -679,10 +679,10 @@
// Read:
// 0 = SysTick exception is not pending.
// 1 = SysTick exception is pending.
-#define M0PLUS_ICSR_PENDSTSET_RESET _U(0x0)
-#define M0PLUS_ICSR_PENDSTSET_BITS _U(0x04000000)
-#define M0PLUS_ICSR_PENDSTSET_MSB _U(26)
-#define M0PLUS_ICSR_PENDSTSET_LSB _U(26)
+#define M0PLUS_ICSR_PENDSTSET_RESET _u(0x0)
+#define M0PLUS_ICSR_PENDSTSET_BITS _u(0x04000000)
+#define M0PLUS_ICSR_PENDSTSET_MSB _u(26)
+#define M0PLUS_ICSR_PENDSTSET_LSB _u(26)
#define M0PLUS_ICSR_PENDSTSET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_ICSR_PENDSTCLR
@@ -691,10 +691,10 @@
// 0 = No effect.
// 1 = Removes the pending state from the SysTick exception.
// This bit is WO. On a register read its value is Unknown.
-#define M0PLUS_ICSR_PENDSTCLR_RESET _U(0x0)
-#define M0PLUS_ICSR_PENDSTCLR_BITS _U(0x02000000)
-#define M0PLUS_ICSR_PENDSTCLR_MSB _U(25)
-#define M0PLUS_ICSR_PENDSTCLR_LSB _U(25)
+#define M0PLUS_ICSR_PENDSTCLR_RESET _u(0x0)
+#define M0PLUS_ICSR_PENDSTCLR_BITS _u(0x02000000)
+#define M0PLUS_ICSR_PENDSTCLR_MSB _u(25)
+#define M0PLUS_ICSR_PENDSTCLR_LSB _u(25)
#define M0PLUS_ICSR_PENDSTCLR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_ICSR_ISRPREEMPT
@@ -702,18 +702,18 @@
// indicates that a pending interrupt is to be taken in the next
// running cycle. If C_MASKINTS is clear in the Debug Halting
// Control and Status Register, the interrupt is serviced.
-#define M0PLUS_ICSR_ISRPREEMPT_RESET _U(0x0)
-#define M0PLUS_ICSR_ISRPREEMPT_BITS _U(0x00800000)
-#define M0PLUS_ICSR_ISRPREEMPT_MSB _U(23)
-#define M0PLUS_ICSR_ISRPREEMPT_LSB _U(23)
+#define M0PLUS_ICSR_ISRPREEMPT_RESET _u(0x0)
+#define M0PLUS_ICSR_ISRPREEMPT_BITS _u(0x00800000)
+#define M0PLUS_ICSR_ISRPREEMPT_MSB _u(23)
+#define M0PLUS_ICSR_ISRPREEMPT_LSB _u(23)
#define M0PLUS_ICSR_ISRPREEMPT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M0PLUS_ICSR_ISRPENDING
// Description : External interrupt pending flag
-#define M0PLUS_ICSR_ISRPENDING_RESET _U(0x0)
-#define M0PLUS_ICSR_ISRPENDING_BITS _U(0x00400000)
-#define M0PLUS_ICSR_ISRPENDING_MSB _U(22)
-#define M0PLUS_ICSR_ISRPENDING_LSB _U(22)
+#define M0PLUS_ICSR_ISRPENDING_RESET _u(0x0)
+#define M0PLUS_ICSR_ISRPENDING_BITS _u(0x00400000)
+#define M0PLUS_ICSR_ISRPENDING_MSB _u(22)
+#define M0PLUS_ICSR_ISRPENDING_LSB _u(22)
#define M0PLUS_ICSR_ISRPENDING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M0PLUS_ICSR_VECTPENDING
@@ -722,61 +722,61 @@
// state includes the effect of memory-mapped enable and mask
// registers. It does not include the PRIMASK special-purpose
// register qualifier.
-#define M0PLUS_ICSR_VECTPENDING_RESET _U(0x000)
-#define M0PLUS_ICSR_VECTPENDING_BITS _U(0x001ff000)
-#define M0PLUS_ICSR_VECTPENDING_MSB _U(20)
-#define M0PLUS_ICSR_VECTPENDING_LSB _U(12)
+#define M0PLUS_ICSR_VECTPENDING_RESET _u(0x000)
+#define M0PLUS_ICSR_VECTPENDING_BITS _u(0x001ff000)
+#define M0PLUS_ICSR_VECTPENDING_MSB _u(20)
+#define M0PLUS_ICSR_VECTPENDING_LSB _u(12)
#define M0PLUS_ICSR_VECTPENDING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M0PLUS_ICSR_VECTACTIVE
// Description : Active exception number field. Reset clears the VECTACTIVE
// field.
-#define M0PLUS_ICSR_VECTACTIVE_RESET _U(0x000)
-#define M0PLUS_ICSR_VECTACTIVE_BITS _U(0x000001ff)
-#define M0PLUS_ICSR_VECTACTIVE_MSB _U(8)
-#define M0PLUS_ICSR_VECTACTIVE_LSB _U(0)
+#define M0PLUS_ICSR_VECTACTIVE_RESET _u(0x000)
+#define M0PLUS_ICSR_VECTACTIVE_BITS _u(0x000001ff)
+#define M0PLUS_ICSR_VECTACTIVE_MSB _u(8)
+#define M0PLUS_ICSR_VECTACTIVE_LSB _u(0)
#define M0PLUS_ICSR_VECTACTIVE_ACCESS "RO"
// =============================================================================
// Register : M0PLUS_VTOR
// Description : The VTOR holds the vector table offset address.
-#define M0PLUS_VTOR_OFFSET _U(0x0000ed08)
-#define M0PLUS_VTOR_BITS _U(0xffffff00)
-#define M0PLUS_VTOR_RESET _U(0x00000000)
+#define M0PLUS_VTOR_OFFSET _u(0x0000ed08)
+#define M0PLUS_VTOR_BITS _u(0xffffff00)
+#define M0PLUS_VTOR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_VTOR_TBLOFF
// Description : Bits [31:8] of the indicate the vector table offset address.
-#define M0PLUS_VTOR_TBLOFF_RESET _U(0x000000)
-#define M0PLUS_VTOR_TBLOFF_BITS _U(0xffffff00)
-#define M0PLUS_VTOR_TBLOFF_MSB _U(31)
-#define M0PLUS_VTOR_TBLOFF_LSB _U(8)
+#define M0PLUS_VTOR_TBLOFF_RESET _u(0x000000)
+#define M0PLUS_VTOR_TBLOFF_BITS _u(0xffffff00)
+#define M0PLUS_VTOR_TBLOFF_MSB _u(31)
+#define M0PLUS_VTOR_TBLOFF_LSB _u(8)
#define M0PLUS_VTOR_TBLOFF_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_AIRCR
// Description : Use the Application Interrupt and Reset Control Register to:
// determine data endianness, clear all active state information
// from debug halt mode, request a system reset.
-#define M0PLUS_AIRCR_OFFSET _U(0x0000ed0c)
-#define M0PLUS_AIRCR_BITS _U(0xffff8006)
-#define M0PLUS_AIRCR_RESET _U(0x00000000)
+#define M0PLUS_AIRCR_OFFSET _u(0x0000ed0c)
+#define M0PLUS_AIRCR_BITS _u(0xffff8006)
+#define M0PLUS_AIRCR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_AIRCR_VECTKEY
// Description : Register key:
// Reads as Unknown
// On writes, write 0x05FA to VECTKEY, otherwise the write is
// ignored.
-#define M0PLUS_AIRCR_VECTKEY_RESET _U(0x0000)
-#define M0PLUS_AIRCR_VECTKEY_BITS _U(0xffff0000)
-#define M0PLUS_AIRCR_VECTKEY_MSB _U(31)
-#define M0PLUS_AIRCR_VECTKEY_LSB _U(16)
+#define M0PLUS_AIRCR_VECTKEY_RESET _u(0x0000)
+#define M0PLUS_AIRCR_VECTKEY_BITS _u(0xffff0000)
+#define M0PLUS_AIRCR_VECTKEY_MSB _u(31)
+#define M0PLUS_AIRCR_VECTKEY_LSB _u(16)
#define M0PLUS_AIRCR_VECTKEY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_AIRCR_ENDIANESS
// Description : Data endianness implemented:
// 0 = Little-endian.
-#define M0PLUS_AIRCR_ENDIANESS_RESET _U(0x0)
-#define M0PLUS_AIRCR_ENDIANESS_BITS _U(0x00008000)
-#define M0PLUS_AIRCR_ENDIANESS_MSB _U(15)
-#define M0PLUS_AIRCR_ENDIANESS_LSB _U(15)
+#define M0PLUS_AIRCR_ENDIANESS_RESET _u(0x0)
+#define M0PLUS_AIRCR_ENDIANESS_BITS _u(0x00008000)
+#define M0PLUS_AIRCR_ENDIANESS_MSB _u(15)
+#define M0PLUS_AIRCR_ENDIANESS_LSB _u(15)
#define M0PLUS_AIRCR_ENDIANESS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M0PLUS_AIRCR_SYSRESETREQ
@@ -786,10 +786,10 @@
// for debug. The C_HALT bit in the DHCSR is cleared as a result
// of the system reset requested. The debugger does not lose
// contact with the device.
-#define M0PLUS_AIRCR_SYSRESETREQ_RESET _U(0x0)
-#define M0PLUS_AIRCR_SYSRESETREQ_BITS _U(0x00000004)
-#define M0PLUS_AIRCR_SYSRESETREQ_MSB _U(2)
-#define M0PLUS_AIRCR_SYSRESETREQ_LSB _U(2)
+#define M0PLUS_AIRCR_SYSRESETREQ_RESET _u(0x0)
+#define M0PLUS_AIRCR_SYSRESETREQ_BITS _u(0x00000004)
+#define M0PLUS_AIRCR_SYSRESETREQ_MSB _u(2)
+#define M0PLUS_AIRCR_SYSRESETREQ_LSB _u(2)
#define M0PLUS_AIRCR_SYSRESETREQ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_AIRCR_VECTCLRACTIVE
@@ -799,10 +799,10 @@
// exception status of the processor, forces a return to Thread
// mode, forces an IPSR of 0. A debugger must re-initialize the
// stack.
-#define M0PLUS_AIRCR_VECTCLRACTIVE_RESET _U(0x0)
-#define M0PLUS_AIRCR_VECTCLRACTIVE_BITS _U(0x00000002)
-#define M0PLUS_AIRCR_VECTCLRACTIVE_MSB _U(1)
-#define M0PLUS_AIRCR_VECTCLRACTIVE_LSB _U(1)
+#define M0PLUS_AIRCR_VECTCLRACTIVE_RESET _u(0x0)
+#define M0PLUS_AIRCR_VECTCLRACTIVE_BITS _u(0x00000002)
+#define M0PLUS_AIRCR_VECTCLRACTIVE_MSB _u(1)
+#define M0PLUS_AIRCR_VECTCLRACTIVE_LSB _u(1)
#define M0PLUS_AIRCR_VECTCLRACTIVE_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_SCR
@@ -810,9 +810,9 @@
// power-management functions: signal to the system when the
// processor can enter a low power state, control how the
// processor enters and exits low power states.
-#define M0PLUS_SCR_OFFSET _U(0x0000ed10)
-#define M0PLUS_SCR_BITS _U(0x00000016)
-#define M0PLUS_SCR_RESET _U(0x00000000)
+#define M0PLUS_SCR_OFFSET _u(0x0000ed10)
+#define M0PLUS_SCR_BITS _u(0x00000016)
+#define M0PLUS_SCR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_SCR_SEVONPEND
// Description : Send Event on Pending bit:
@@ -826,10 +826,10 @@
// and affects the next WFE.
// The processor also wakes up on execution of an SEV instruction
// or an external event.
-#define M0PLUS_SCR_SEVONPEND_RESET _U(0x0)
-#define M0PLUS_SCR_SEVONPEND_BITS _U(0x00000010)
-#define M0PLUS_SCR_SEVONPEND_MSB _U(4)
-#define M0PLUS_SCR_SEVONPEND_LSB _U(4)
+#define M0PLUS_SCR_SEVONPEND_RESET _u(0x0)
+#define M0PLUS_SCR_SEVONPEND_BITS _u(0x00000010)
+#define M0PLUS_SCR_SEVONPEND_MSB _u(4)
+#define M0PLUS_SCR_SEVONPEND_LSB _u(4)
#define M0PLUS_SCR_SEVONPEND_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_SCR_SLEEPDEEP
@@ -837,10 +837,10 @@
// low power mode:
// 0 = Sleep.
// 1 = Deep sleep.
-#define M0PLUS_SCR_SLEEPDEEP_RESET _U(0x0)
-#define M0PLUS_SCR_SLEEPDEEP_BITS _U(0x00000004)
-#define M0PLUS_SCR_SLEEPDEEP_MSB _U(2)
-#define M0PLUS_SCR_SLEEPDEEP_LSB _U(2)
+#define M0PLUS_SCR_SLEEPDEEP_RESET _u(0x0)
+#define M0PLUS_SCR_SLEEPDEEP_BITS _u(0x00000004)
+#define M0PLUS_SCR_SLEEPDEEP_MSB _u(2)
+#define M0PLUS_SCR_SLEEPDEEP_LSB _u(2)
#define M0PLUS_SCR_SLEEPDEEP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_SCR_SLEEPONEXIT
@@ -851,19 +851,19 @@
// mode.
// Setting this bit to 1 enables an interrupt driven application
// to avoid returning to an empty main application.
-#define M0PLUS_SCR_SLEEPONEXIT_RESET _U(0x0)
-#define M0PLUS_SCR_SLEEPONEXIT_BITS _U(0x00000002)
-#define M0PLUS_SCR_SLEEPONEXIT_MSB _U(1)
-#define M0PLUS_SCR_SLEEPONEXIT_LSB _U(1)
+#define M0PLUS_SCR_SLEEPONEXIT_RESET _u(0x0)
+#define M0PLUS_SCR_SLEEPONEXIT_BITS _u(0x00000002)
+#define M0PLUS_SCR_SLEEPONEXIT_MSB _u(1)
+#define M0PLUS_SCR_SLEEPONEXIT_LSB _u(1)
#define M0PLUS_SCR_SLEEPONEXIT_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_CCR
// Description : The Configuration and Control Register permanently enables
// stack alignment and causes unaligned accesses to result in a
// Hard Fault.
-#define M0PLUS_CCR_OFFSET _U(0x0000ed14)
-#define M0PLUS_CCR_BITS _U(0x00000208)
-#define M0PLUS_CCR_RESET _U(0x00000000)
+#define M0PLUS_CCR_OFFSET _u(0x0000ed14)
+#define M0PLUS_CCR_BITS _u(0x00000208)
+#define M0PLUS_CCR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_CCR_STKALIGN
// Description : Always reads as one, indicates 8-byte stack alignment on
@@ -871,19 +871,19 @@
// of the stacked PSR to indicate the stack alignment. On return
// from the exception it uses this stacked bit to restore the
// correct stack alignment.
-#define M0PLUS_CCR_STKALIGN_RESET _U(0x0)
-#define M0PLUS_CCR_STKALIGN_BITS _U(0x00000200)
-#define M0PLUS_CCR_STKALIGN_MSB _U(9)
-#define M0PLUS_CCR_STKALIGN_LSB _U(9)
+#define M0PLUS_CCR_STKALIGN_RESET _u(0x0)
+#define M0PLUS_CCR_STKALIGN_BITS _u(0x00000200)
+#define M0PLUS_CCR_STKALIGN_MSB _u(9)
+#define M0PLUS_CCR_STKALIGN_LSB _u(9)
#define M0PLUS_CCR_STKALIGN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M0PLUS_CCR_UNALIGN_TRP
// Description : Always reads as one, indicates that all unaligned accesses
// generate a HardFault.
-#define M0PLUS_CCR_UNALIGN_TRP_RESET _U(0x0)
-#define M0PLUS_CCR_UNALIGN_TRP_BITS _U(0x00000008)
-#define M0PLUS_CCR_UNALIGN_TRP_MSB _U(3)
-#define M0PLUS_CCR_UNALIGN_TRP_LSB _U(3)
+#define M0PLUS_CCR_UNALIGN_TRP_RESET _u(0x0)
+#define M0PLUS_CCR_UNALIGN_TRP_BITS _u(0x00000008)
+#define M0PLUS_CCR_UNALIGN_TRP_MSB _u(3)
+#define M0PLUS_CCR_UNALIGN_TRP_LSB _u(3)
#define M0PLUS_CCR_UNALIGN_TRP_ACCESS "RO"
// =============================================================================
// Register : M0PLUS_SHPR2
@@ -891,16 +891,16 @@
// can have their priority set to any of the priority levels. Use
// the System Handler Priority Register 2 to set the priority of
// SVCall.
-#define M0PLUS_SHPR2_OFFSET _U(0x0000ed1c)
-#define M0PLUS_SHPR2_BITS _U(0xc0000000)
-#define M0PLUS_SHPR2_RESET _U(0x00000000)
+#define M0PLUS_SHPR2_OFFSET _u(0x0000ed1c)
+#define M0PLUS_SHPR2_BITS _u(0xc0000000)
+#define M0PLUS_SHPR2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_SHPR2_PRI_11
// Description : Priority of system handler 11, SVCall
-#define M0PLUS_SHPR2_PRI_11_RESET _U(0x0)
-#define M0PLUS_SHPR2_PRI_11_BITS _U(0xc0000000)
-#define M0PLUS_SHPR2_PRI_11_MSB _U(31)
-#define M0PLUS_SHPR2_PRI_11_LSB _U(30)
+#define M0PLUS_SHPR2_PRI_11_RESET _u(0x0)
+#define M0PLUS_SHPR2_PRI_11_BITS _u(0xc0000000)
+#define M0PLUS_SHPR2_PRI_11_MSB _u(31)
+#define M0PLUS_SHPR2_PRI_11_LSB _u(30)
#define M0PLUS_SHPR2_PRI_11_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_SHPR3
@@ -908,73 +908,73 @@
// can have their priority set to any of the priority levels. Use
// the System Handler Priority Register 3 to set the priority of
// PendSV and SysTick.
-#define M0PLUS_SHPR3_OFFSET _U(0x0000ed20)
-#define M0PLUS_SHPR3_BITS _U(0xc0c00000)
-#define M0PLUS_SHPR3_RESET _U(0x00000000)
+#define M0PLUS_SHPR3_OFFSET _u(0x0000ed20)
+#define M0PLUS_SHPR3_BITS _u(0xc0c00000)
+#define M0PLUS_SHPR3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_SHPR3_PRI_15
// Description : Priority of system handler 15, SysTick
-#define M0PLUS_SHPR3_PRI_15_RESET _U(0x0)
-#define M0PLUS_SHPR3_PRI_15_BITS _U(0xc0000000)
-#define M0PLUS_SHPR3_PRI_15_MSB _U(31)
-#define M0PLUS_SHPR3_PRI_15_LSB _U(30)
+#define M0PLUS_SHPR3_PRI_15_RESET _u(0x0)
+#define M0PLUS_SHPR3_PRI_15_BITS _u(0xc0000000)
+#define M0PLUS_SHPR3_PRI_15_MSB _u(31)
+#define M0PLUS_SHPR3_PRI_15_LSB _u(30)
#define M0PLUS_SHPR3_PRI_15_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_SHPR3_PRI_14
// Description : Priority of system handler 14, PendSV
-#define M0PLUS_SHPR3_PRI_14_RESET _U(0x0)
-#define M0PLUS_SHPR3_PRI_14_BITS _U(0x00c00000)
-#define M0PLUS_SHPR3_PRI_14_MSB _U(23)
-#define M0PLUS_SHPR3_PRI_14_LSB _U(22)
+#define M0PLUS_SHPR3_PRI_14_RESET _u(0x0)
+#define M0PLUS_SHPR3_PRI_14_BITS _u(0x00c00000)
+#define M0PLUS_SHPR3_PRI_14_MSB _u(23)
+#define M0PLUS_SHPR3_PRI_14_LSB _u(22)
#define M0PLUS_SHPR3_PRI_14_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_SHCSR
// Description : Use the System Handler Control and State Register to determine
// or clear the pending status of SVCall.
-#define M0PLUS_SHCSR_OFFSET _U(0x0000ed24)
-#define M0PLUS_SHCSR_BITS _U(0x00008000)
-#define M0PLUS_SHCSR_RESET _U(0x00000000)
+#define M0PLUS_SHCSR_OFFSET _u(0x0000ed24)
+#define M0PLUS_SHCSR_BITS _u(0x00008000)
+#define M0PLUS_SHCSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_SHCSR_SVCALLPENDED
// Description : Reads as 1 if SVCall is Pending. Write 1 to set pending
// SVCall, write 0 to clear pending SVCall.
-#define M0PLUS_SHCSR_SVCALLPENDED_RESET _U(0x0)
-#define M0PLUS_SHCSR_SVCALLPENDED_BITS _U(0x00008000)
-#define M0PLUS_SHCSR_SVCALLPENDED_MSB _U(15)
-#define M0PLUS_SHCSR_SVCALLPENDED_LSB _U(15)
+#define M0PLUS_SHCSR_SVCALLPENDED_RESET _u(0x0)
+#define M0PLUS_SHCSR_SVCALLPENDED_BITS _u(0x00008000)
+#define M0PLUS_SHCSR_SVCALLPENDED_MSB _u(15)
+#define M0PLUS_SHCSR_SVCALLPENDED_LSB _u(15)
#define M0PLUS_SHCSR_SVCALLPENDED_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_MPU_TYPE
// Description : Read the MPU Type Register to determine if the processor
// implements an MPU, and how many regions the MPU supports.
-#define M0PLUS_MPU_TYPE_OFFSET _U(0x0000ed90)
-#define M0PLUS_MPU_TYPE_BITS _U(0x00ffff01)
-#define M0PLUS_MPU_TYPE_RESET _U(0x00000800)
+#define M0PLUS_MPU_TYPE_OFFSET _u(0x0000ed90)
+#define M0PLUS_MPU_TYPE_BITS _u(0x00ffff01)
+#define M0PLUS_MPU_TYPE_RESET _u(0x00000800)
// -----------------------------------------------------------------------------
// Field : M0PLUS_MPU_TYPE_IREGION
// Description : Instruction region. Reads as zero as ARMv6-M only supports a
// unified MPU.
-#define M0PLUS_MPU_TYPE_IREGION_RESET _U(0x00)
-#define M0PLUS_MPU_TYPE_IREGION_BITS _U(0x00ff0000)
-#define M0PLUS_MPU_TYPE_IREGION_MSB _U(23)
-#define M0PLUS_MPU_TYPE_IREGION_LSB _U(16)
+#define M0PLUS_MPU_TYPE_IREGION_RESET _u(0x00)
+#define M0PLUS_MPU_TYPE_IREGION_BITS _u(0x00ff0000)
+#define M0PLUS_MPU_TYPE_IREGION_MSB _u(23)
+#define M0PLUS_MPU_TYPE_IREGION_LSB _u(16)
#define M0PLUS_MPU_TYPE_IREGION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M0PLUS_MPU_TYPE_DREGION
// Description : Number of regions supported by the MPU.
-#define M0PLUS_MPU_TYPE_DREGION_RESET _U(0x08)
-#define M0PLUS_MPU_TYPE_DREGION_BITS _U(0x0000ff00)
-#define M0PLUS_MPU_TYPE_DREGION_MSB _U(15)
-#define M0PLUS_MPU_TYPE_DREGION_LSB _U(8)
+#define M0PLUS_MPU_TYPE_DREGION_RESET _u(0x08)
+#define M0PLUS_MPU_TYPE_DREGION_BITS _u(0x0000ff00)
+#define M0PLUS_MPU_TYPE_DREGION_MSB _u(15)
+#define M0PLUS_MPU_TYPE_DREGION_LSB _u(8)
#define M0PLUS_MPU_TYPE_DREGION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M0PLUS_MPU_TYPE_SEPARATE
// Description : Indicates support for separate instruction and data address
// maps. Reads as 0 as ARMv6-M only supports a unified MPU.
-#define M0PLUS_MPU_TYPE_SEPARATE_RESET _U(0x0)
-#define M0PLUS_MPU_TYPE_SEPARATE_BITS _U(0x00000001)
-#define M0PLUS_MPU_TYPE_SEPARATE_MSB _U(0)
-#define M0PLUS_MPU_TYPE_SEPARATE_LSB _U(0)
+#define M0PLUS_MPU_TYPE_SEPARATE_RESET _u(0x0)
+#define M0PLUS_MPU_TYPE_SEPARATE_BITS _u(0x00000001)
+#define M0PLUS_MPU_TYPE_SEPARATE_MSB _u(0)
+#define M0PLUS_MPU_TYPE_SEPARATE_LSB _u(0)
#define M0PLUS_MPU_TYPE_SEPARATE_ACCESS "RO"
// =============================================================================
// Register : M0PLUS_MPU_CTRL
@@ -982,9 +982,9 @@
// to control whether the default memory map is enabled as a
// background region for privileged accesses, and whether the MPU
// is enabled for HardFaults and NMIs.
-#define M0PLUS_MPU_CTRL_OFFSET _U(0x0000ed94)
-#define M0PLUS_MPU_CTRL_BITS _U(0x00000007)
-#define M0PLUS_MPU_CTRL_RESET _U(0x00000000)
+#define M0PLUS_MPU_CTRL_OFFSET _u(0x0000ed94)
+#define M0PLUS_MPU_CTRL_BITS _u(0x00000007)
+#define M0PLUS_MPU_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_MPU_CTRL_PRIVDEFENA
// Description : Controls whether the default memory map is enabled as a
@@ -998,10 +998,10 @@
// When enabled, the background region acts as if it is region
// number -1. Any region that is defined and enabled has priority
// over this default map.
-#define M0PLUS_MPU_CTRL_PRIVDEFENA_RESET _U(0x0)
-#define M0PLUS_MPU_CTRL_PRIVDEFENA_BITS _U(0x00000004)
-#define M0PLUS_MPU_CTRL_PRIVDEFENA_MSB _U(2)
-#define M0PLUS_MPU_CTRL_PRIVDEFENA_LSB _U(2)
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_RESET _u(0x0)
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_BITS _u(0x00000004)
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_MSB _u(2)
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_LSB _u(2)
#define M0PLUS_MPU_CTRL_PRIVDEFENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_MPU_CTRL_HFNMIENA
@@ -1012,10 +1012,10 @@
// 0 = MPU is disabled during HardFault and NMI handlers,
// regardless of the value of the ENABLE bit.
// 1 = the MPU is enabled during HardFault and NMI handlers.
-#define M0PLUS_MPU_CTRL_HFNMIENA_RESET _U(0x0)
-#define M0PLUS_MPU_CTRL_HFNMIENA_BITS _U(0x00000002)
-#define M0PLUS_MPU_CTRL_HFNMIENA_MSB _U(1)
-#define M0PLUS_MPU_CTRL_HFNMIENA_LSB _U(1)
+#define M0PLUS_MPU_CTRL_HFNMIENA_RESET _u(0x0)
+#define M0PLUS_MPU_CTRL_HFNMIENA_BITS _u(0x00000002)
+#define M0PLUS_MPU_CTRL_HFNMIENA_MSB _u(1)
+#define M0PLUS_MPU_CTRL_HFNMIENA_LSB _u(1)
#define M0PLUS_MPU_CTRL_HFNMIENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_MPU_CTRL_ENABLE
@@ -1023,28 +1023,28 @@
// unprivileged accesses use the default memory map.
// 0 = MPU disabled.
// 1 = MPU enabled.
-#define M0PLUS_MPU_CTRL_ENABLE_RESET _U(0x0)
-#define M0PLUS_MPU_CTRL_ENABLE_BITS _U(0x00000001)
-#define M0PLUS_MPU_CTRL_ENABLE_MSB _U(0)
-#define M0PLUS_MPU_CTRL_ENABLE_LSB _U(0)
+#define M0PLUS_MPU_CTRL_ENABLE_RESET _u(0x0)
+#define M0PLUS_MPU_CTRL_ENABLE_BITS _u(0x00000001)
+#define M0PLUS_MPU_CTRL_ENABLE_MSB _u(0)
+#define M0PLUS_MPU_CTRL_ENABLE_LSB _u(0)
#define M0PLUS_MPU_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_MPU_RNR
// Description : Use the MPU Region Number Register to select the region
// currently accessed by MPU_RBAR and MPU_RASR.
-#define M0PLUS_MPU_RNR_OFFSET _U(0x0000ed98)
-#define M0PLUS_MPU_RNR_BITS _U(0x0000000f)
-#define M0PLUS_MPU_RNR_RESET _U(0x00000000)
+#define M0PLUS_MPU_RNR_OFFSET _u(0x0000ed98)
+#define M0PLUS_MPU_RNR_BITS _u(0x0000000f)
+#define M0PLUS_MPU_RNR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_MPU_RNR_REGION
// Description : Indicates the MPU region referenced by the MPU_RBAR and
// MPU_RASR registers.
// The MPU supports 8 memory regions, so the permitted values of
// this field are 0-7.
-#define M0PLUS_MPU_RNR_REGION_RESET _U(0x0)
-#define M0PLUS_MPU_RNR_REGION_BITS _U(0x0000000f)
-#define M0PLUS_MPU_RNR_REGION_MSB _U(3)
-#define M0PLUS_MPU_RNR_REGION_LSB _U(0)
+#define M0PLUS_MPU_RNR_REGION_RESET _u(0x0)
+#define M0PLUS_MPU_RNR_REGION_BITS _u(0x0000000f)
+#define M0PLUS_MPU_RNR_REGION_MSB _u(3)
+#define M0PLUS_MPU_RNR_REGION_LSB _u(0)
#define M0PLUS_MPU_RNR_REGION_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_MPU_RBAR
@@ -1052,16 +1052,16 @@
// address of the region identified by MPU_RNR. Write to update
// the base address of said region or that of a specified region,
// with whose number MPU_RNR will also be updated.
-#define M0PLUS_MPU_RBAR_OFFSET _U(0x0000ed9c)
-#define M0PLUS_MPU_RBAR_BITS _U(0xffffff1f)
-#define M0PLUS_MPU_RBAR_RESET _U(0x00000000)
+#define M0PLUS_MPU_RBAR_OFFSET _u(0x0000ed9c)
+#define M0PLUS_MPU_RBAR_BITS _u(0xffffff1f)
+#define M0PLUS_MPU_RBAR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_MPU_RBAR_ADDR
// Description : Base address of the region.
-#define M0PLUS_MPU_RBAR_ADDR_RESET _U(0x000000)
-#define M0PLUS_MPU_RBAR_ADDR_BITS _U(0xffffff00)
-#define M0PLUS_MPU_RBAR_ADDR_MSB _U(31)
-#define M0PLUS_MPU_RBAR_ADDR_LSB _U(8)
+#define M0PLUS_MPU_RBAR_ADDR_RESET _u(0x000000)
+#define M0PLUS_MPU_RBAR_ADDR_BITS _u(0xffffff00)
+#define M0PLUS_MPU_RBAR_ADDR_MSB _u(31)
+#define M0PLUS_MPU_RBAR_ADDR_LSB _u(8)
#define M0PLUS_MPU_RBAR_ADDR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_MPU_RBAR_VALID
@@ -1079,29 +1079,29 @@
// Updates the base address for the region specified in the REGION
// field.
// Always reads as zero.
-#define M0PLUS_MPU_RBAR_VALID_RESET _U(0x0)
-#define M0PLUS_MPU_RBAR_VALID_BITS _U(0x00000010)
-#define M0PLUS_MPU_RBAR_VALID_MSB _U(4)
-#define M0PLUS_MPU_RBAR_VALID_LSB _U(4)
+#define M0PLUS_MPU_RBAR_VALID_RESET _u(0x0)
+#define M0PLUS_MPU_RBAR_VALID_BITS _u(0x00000010)
+#define M0PLUS_MPU_RBAR_VALID_MSB _u(4)
+#define M0PLUS_MPU_RBAR_VALID_LSB _u(4)
#define M0PLUS_MPU_RBAR_VALID_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_MPU_RBAR_REGION
// Description : On writes, specifies the number of the region whose base
// address to update provided VALID is set written as 1. On reads,
// returns bits [3:0] of MPU_RNR.
-#define M0PLUS_MPU_RBAR_REGION_RESET _U(0x0)
-#define M0PLUS_MPU_RBAR_REGION_BITS _U(0x0000000f)
-#define M0PLUS_MPU_RBAR_REGION_MSB _U(3)
-#define M0PLUS_MPU_RBAR_REGION_LSB _U(0)
+#define M0PLUS_MPU_RBAR_REGION_RESET _u(0x0)
+#define M0PLUS_MPU_RBAR_REGION_BITS _u(0x0000000f)
+#define M0PLUS_MPU_RBAR_REGION_MSB _u(3)
+#define M0PLUS_MPU_RBAR_REGION_LSB _u(0)
#define M0PLUS_MPU_RBAR_REGION_ACCESS "RW"
// =============================================================================
// Register : M0PLUS_MPU_RASR
// Description : Use the MPU Region Attribute and Size Register to define the
// size, access behaviour and memory type of the region identified
// by MPU_RNR, and enable that region.
-#define M0PLUS_MPU_RASR_OFFSET _U(0x0000eda0)
-#define M0PLUS_MPU_RASR_BITS _U(0xffffff3f)
-#define M0PLUS_MPU_RASR_RESET _U(0x00000000)
+#define M0PLUS_MPU_RASR_OFFSET _u(0x0000eda0)
+#define M0PLUS_MPU_RASR_BITS _u(0xffffff3f)
+#define M0PLUS_MPU_RASR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : M0PLUS_MPU_RASR_ATTRS
// Description : The MPU Region Attribute field. Use to define the region
@@ -1113,37 +1113,37 @@
// 18 = S: Shareable bit
// 17 = C: Cacheable bit
// 16 = B: Bufferable bit
-#define M0PLUS_MPU_RASR_ATTRS_RESET _U(0x0000)
-#define M0PLUS_MPU_RASR_ATTRS_BITS _U(0xffff0000)
-#define M0PLUS_MPU_RASR_ATTRS_MSB _U(31)
-#define M0PLUS_MPU_RASR_ATTRS_LSB _U(16)
+#define M0PLUS_MPU_RASR_ATTRS_RESET _u(0x0000)
+#define M0PLUS_MPU_RASR_ATTRS_BITS _u(0xffff0000)
+#define M0PLUS_MPU_RASR_ATTRS_MSB _u(31)
+#define M0PLUS_MPU_RASR_ATTRS_LSB _u(16)
#define M0PLUS_MPU_RASR_ATTRS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_MPU_RASR_SRD
// Description : Subregion Disable. For regions of 256 bytes or larger, each bit
// of this field controls whether one of the eight equal
// subregions is enabled.
-#define M0PLUS_MPU_RASR_SRD_RESET _U(0x00)
-#define M0PLUS_MPU_RASR_SRD_BITS _U(0x0000ff00)
-#define M0PLUS_MPU_RASR_SRD_MSB _U(15)
-#define M0PLUS_MPU_RASR_SRD_LSB _U(8)
+#define M0PLUS_MPU_RASR_SRD_RESET _u(0x00)
+#define M0PLUS_MPU_RASR_SRD_BITS _u(0x0000ff00)
+#define M0PLUS_MPU_RASR_SRD_MSB _u(15)
+#define M0PLUS_MPU_RASR_SRD_LSB _u(8)
#define M0PLUS_MPU_RASR_SRD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_MPU_RASR_SIZE
// Description : Indicates the region size. Region size in bytes = 2^(SIZE+1).
// The minimum permitted value is 7 (b00111) = 256Bytes
-#define M0PLUS_MPU_RASR_SIZE_RESET _U(0x00)
-#define M0PLUS_MPU_RASR_SIZE_BITS _U(0x0000003e)
-#define M0PLUS_MPU_RASR_SIZE_MSB _U(5)
-#define M0PLUS_MPU_RASR_SIZE_LSB _U(1)
+#define M0PLUS_MPU_RASR_SIZE_RESET _u(0x00)
+#define M0PLUS_MPU_RASR_SIZE_BITS _u(0x0000003e)
+#define M0PLUS_MPU_RASR_SIZE_MSB _u(5)
+#define M0PLUS_MPU_RASR_SIZE_LSB _u(1)
#define M0PLUS_MPU_RASR_SIZE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M0PLUS_MPU_RASR_ENABLE
// Description : Enables the region.
-#define M0PLUS_MPU_RASR_ENABLE_RESET _U(0x0)
-#define M0PLUS_MPU_RASR_ENABLE_BITS _U(0x00000001)
-#define M0PLUS_MPU_RASR_ENABLE_MSB _U(0)
-#define M0PLUS_MPU_RASR_ENABLE_LSB _U(0)
+#define M0PLUS_MPU_RASR_ENABLE_RESET _u(0x0)
+#define M0PLUS_MPU_RASR_ENABLE_BITS _u(0x00000001)
+#define M0PLUS_MPU_RASR_ENABLE_MSB _u(0)
+#define M0PLUS_MPU_RASR_ENABLE_LSB _u(0)
#define M0PLUS_MPU_RASR_ENABLE_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_M0PLUS_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h b/src/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h
index 18ed841..06102ac 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h
@@ -16,36 +16,36 @@
// Description : Voltage select. Per bank control
// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5)
// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8)
-#define PADS_BANK0_VOLTAGE_SELECT_OFFSET _U(0x00000000)
-#define PADS_BANK0_VOLTAGE_SELECT_BITS _U(0x00000001)
-#define PADS_BANK0_VOLTAGE_SELECT_RESET _U(0x00000000)
-#define PADS_BANK0_VOLTAGE_SELECT_MSB _U(0)
-#define PADS_BANK0_VOLTAGE_SELECT_LSB _U(0)
+#define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000)
+#define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001)
+#define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000)
+#define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0)
+#define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0)
#define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW"
-#define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _U(0x0)
-#define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _U(0x1)
+#define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)
+#define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)
// =============================================================================
// Register : PADS_BANK0_GPIO0
// Description : Pad control register
-#define PADS_BANK0_GPIO0_OFFSET _U(0x00000004)
-#define PADS_BANK0_GPIO0_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO0_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO0_OFFSET _u(0x00000004)
+#define PADS_BANK0_GPIO0_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO0_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO0_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO0_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO0_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO0_OD_MSB _U(7)
-#define PADS_BANK0_GPIO0_OD_LSB _U(7)
+#define PADS_BANK0_GPIO0_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO0_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO0_OD_MSB _u(7)
+#define PADS_BANK0_GPIO0_OD_LSB _u(7)
#define PADS_BANK0_GPIO0_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO0_IE
// Description : Input enable
-#define PADS_BANK0_GPIO0_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO0_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO0_IE_MSB _U(6)
-#define PADS_BANK0_GPIO0_IE_LSB _U(6)
+#define PADS_BANK0_GPIO0_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO0_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO0_IE_MSB _u(6)
+#define PADS_BANK0_GPIO0_IE_LSB _u(6)
#define PADS_BANK0_GPIO0_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO0_DRIVE
@@ -54,69 +54,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO0_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO0_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO0_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO0_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO0_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO0_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO0_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO0_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO0_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO0_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO0_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO0_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO0_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO0_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO0_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO0_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO0_PUE_LSB _u(3)
#define PADS_BANK0_GPIO0_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO0_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO0_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO0_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO0_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO0_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO0_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO0_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO0_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO0_PDE_LSB _u(2)
#define PADS_BANK0_GPIO0_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO0_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO0_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO0_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO0_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO0_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO0_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO0_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO0_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO0_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO0_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO0_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO0_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO0_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO0_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO0_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO0_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO0_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO0_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO0_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO0_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO1
// Description : Pad control register
-#define PADS_BANK0_GPIO1_OFFSET _U(0x00000008)
-#define PADS_BANK0_GPIO1_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO1_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO1_OFFSET _u(0x00000008)
+#define PADS_BANK0_GPIO1_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO1_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO1_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO1_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO1_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO1_OD_MSB _U(7)
-#define PADS_BANK0_GPIO1_OD_LSB _U(7)
+#define PADS_BANK0_GPIO1_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO1_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO1_OD_MSB _u(7)
+#define PADS_BANK0_GPIO1_OD_LSB _u(7)
#define PADS_BANK0_GPIO1_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO1_IE
// Description : Input enable
-#define PADS_BANK0_GPIO1_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO1_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO1_IE_MSB _U(6)
-#define PADS_BANK0_GPIO1_IE_LSB _U(6)
+#define PADS_BANK0_GPIO1_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO1_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO1_IE_MSB _u(6)
+#define PADS_BANK0_GPIO1_IE_LSB _u(6)
#define PADS_BANK0_GPIO1_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO1_DRIVE
@@ -125,69 +125,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO1_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO1_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO1_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO1_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO1_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO1_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO1_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO1_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO1_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO1_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO1_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO1_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO1_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO1_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO1_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO1_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO1_PUE_LSB _u(3)
#define PADS_BANK0_GPIO1_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO1_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO1_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO1_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO1_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO1_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO1_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO1_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO1_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO1_PDE_LSB _u(2)
#define PADS_BANK0_GPIO1_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO1_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO1_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO1_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO1_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO1_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO1_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO1_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO1_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO1_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO1_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO1_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO1_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO1_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO1_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO1_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO1_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO1_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO1_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO1_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO1_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO2
// Description : Pad control register
-#define PADS_BANK0_GPIO2_OFFSET _U(0x0000000c)
-#define PADS_BANK0_GPIO2_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO2_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO2_OFFSET _u(0x0000000c)
+#define PADS_BANK0_GPIO2_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO2_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO2_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO2_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO2_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO2_OD_MSB _U(7)
-#define PADS_BANK0_GPIO2_OD_LSB _U(7)
+#define PADS_BANK0_GPIO2_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO2_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO2_OD_MSB _u(7)
+#define PADS_BANK0_GPIO2_OD_LSB _u(7)
#define PADS_BANK0_GPIO2_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO2_IE
// Description : Input enable
-#define PADS_BANK0_GPIO2_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO2_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO2_IE_MSB _U(6)
-#define PADS_BANK0_GPIO2_IE_LSB _U(6)
+#define PADS_BANK0_GPIO2_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO2_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO2_IE_MSB _u(6)
+#define PADS_BANK0_GPIO2_IE_LSB _u(6)
#define PADS_BANK0_GPIO2_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO2_DRIVE
@@ -196,69 +196,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO2_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO2_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO2_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO2_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO2_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO2_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO2_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO2_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO2_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO2_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO2_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO2_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO2_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO2_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO2_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO2_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO2_PUE_LSB _u(3)
#define PADS_BANK0_GPIO2_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO2_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO2_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO2_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO2_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO2_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO2_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO2_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO2_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO2_PDE_LSB _u(2)
#define PADS_BANK0_GPIO2_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO2_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO2_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO2_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO2_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO2_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO2_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO2_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO2_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO2_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO2_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO2_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO2_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO2_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO2_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO2_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO2_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO2_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO2_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO2_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO2_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO3
// Description : Pad control register
-#define PADS_BANK0_GPIO3_OFFSET _U(0x00000010)
-#define PADS_BANK0_GPIO3_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO3_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO3_OFFSET _u(0x00000010)
+#define PADS_BANK0_GPIO3_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO3_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO3_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO3_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO3_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO3_OD_MSB _U(7)
-#define PADS_BANK0_GPIO3_OD_LSB _U(7)
+#define PADS_BANK0_GPIO3_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO3_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO3_OD_MSB _u(7)
+#define PADS_BANK0_GPIO3_OD_LSB _u(7)
#define PADS_BANK0_GPIO3_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO3_IE
// Description : Input enable
-#define PADS_BANK0_GPIO3_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO3_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO3_IE_MSB _U(6)
-#define PADS_BANK0_GPIO3_IE_LSB _U(6)
+#define PADS_BANK0_GPIO3_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO3_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO3_IE_MSB _u(6)
+#define PADS_BANK0_GPIO3_IE_LSB _u(6)
#define PADS_BANK0_GPIO3_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO3_DRIVE
@@ -267,69 +267,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO3_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO3_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO3_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO3_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO3_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO3_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO3_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO3_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO3_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO3_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO3_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO3_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO3_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO3_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO3_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO3_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO3_PUE_LSB _u(3)
#define PADS_BANK0_GPIO3_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO3_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO3_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO3_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO3_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO3_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO3_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO3_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO3_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO3_PDE_LSB _u(2)
#define PADS_BANK0_GPIO3_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO3_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO3_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO3_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO3_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO3_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO3_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO3_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO3_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO3_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO3_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO3_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO3_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO3_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO3_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO3_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO3_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO3_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO3_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO3_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO3_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO4
// Description : Pad control register
-#define PADS_BANK0_GPIO4_OFFSET _U(0x00000014)
-#define PADS_BANK0_GPIO4_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO4_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO4_OFFSET _u(0x00000014)
+#define PADS_BANK0_GPIO4_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO4_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO4_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO4_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO4_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO4_OD_MSB _U(7)
-#define PADS_BANK0_GPIO4_OD_LSB _U(7)
+#define PADS_BANK0_GPIO4_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO4_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO4_OD_MSB _u(7)
+#define PADS_BANK0_GPIO4_OD_LSB _u(7)
#define PADS_BANK0_GPIO4_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO4_IE
// Description : Input enable
-#define PADS_BANK0_GPIO4_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO4_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO4_IE_MSB _U(6)
-#define PADS_BANK0_GPIO4_IE_LSB _U(6)
+#define PADS_BANK0_GPIO4_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO4_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO4_IE_MSB _u(6)
+#define PADS_BANK0_GPIO4_IE_LSB _u(6)
#define PADS_BANK0_GPIO4_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO4_DRIVE
@@ -338,69 +338,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO4_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO4_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO4_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO4_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO4_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO4_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO4_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO4_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO4_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO4_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO4_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO4_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO4_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO4_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO4_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO4_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO4_PUE_LSB _u(3)
#define PADS_BANK0_GPIO4_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO4_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO4_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO4_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO4_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO4_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO4_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO4_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO4_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO4_PDE_LSB _u(2)
#define PADS_BANK0_GPIO4_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO4_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO4_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO4_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO4_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO4_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO4_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO4_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO4_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO4_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO4_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO4_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO4_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO4_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO4_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO4_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO4_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO4_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO4_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO4_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO4_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO5
// Description : Pad control register
-#define PADS_BANK0_GPIO5_OFFSET _U(0x00000018)
-#define PADS_BANK0_GPIO5_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO5_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO5_OFFSET _u(0x00000018)
+#define PADS_BANK0_GPIO5_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO5_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO5_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO5_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO5_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO5_OD_MSB _U(7)
-#define PADS_BANK0_GPIO5_OD_LSB _U(7)
+#define PADS_BANK0_GPIO5_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO5_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO5_OD_MSB _u(7)
+#define PADS_BANK0_GPIO5_OD_LSB _u(7)
#define PADS_BANK0_GPIO5_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO5_IE
// Description : Input enable
-#define PADS_BANK0_GPIO5_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO5_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO5_IE_MSB _U(6)
-#define PADS_BANK0_GPIO5_IE_LSB _U(6)
+#define PADS_BANK0_GPIO5_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO5_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO5_IE_MSB _u(6)
+#define PADS_BANK0_GPIO5_IE_LSB _u(6)
#define PADS_BANK0_GPIO5_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO5_DRIVE
@@ -409,69 +409,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO5_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO5_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO5_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO5_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO5_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO5_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO5_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO5_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO5_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO5_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO5_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO5_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO5_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO5_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO5_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO5_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO5_PUE_LSB _u(3)
#define PADS_BANK0_GPIO5_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO5_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO5_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO5_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO5_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO5_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO5_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO5_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO5_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO5_PDE_LSB _u(2)
#define PADS_BANK0_GPIO5_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO5_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO5_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO5_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO5_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO5_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO5_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO5_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO5_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO5_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO5_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO5_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO5_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO5_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO5_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO5_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO5_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO5_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO5_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO5_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO5_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO6
// Description : Pad control register
-#define PADS_BANK0_GPIO6_OFFSET _U(0x0000001c)
-#define PADS_BANK0_GPIO6_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO6_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO6_OFFSET _u(0x0000001c)
+#define PADS_BANK0_GPIO6_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO6_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO6_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO6_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO6_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO6_OD_MSB _U(7)
-#define PADS_BANK0_GPIO6_OD_LSB _U(7)
+#define PADS_BANK0_GPIO6_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO6_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO6_OD_MSB _u(7)
+#define PADS_BANK0_GPIO6_OD_LSB _u(7)
#define PADS_BANK0_GPIO6_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO6_IE
// Description : Input enable
-#define PADS_BANK0_GPIO6_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO6_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO6_IE_MSB _U(6)
-#define PADS_BANK0_GPIO6_IE_LSB _U(6)
+#define PADS_BANK0_GPIO6_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO6_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO6_IE_MSB _u(6)
+#define PADS_BANK0_GPIO6_IE_LSB _u(6)
#define PADS_BANK0_GPIO6_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO6_DRIVE
@@ -480,69 +480,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO6_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO6_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO6_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO6_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO6_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO6_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO6_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO6_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO6_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO6_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO6_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO6_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO6_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO6_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO6_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO6_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO6_PUE_LSB _u(3)
#define PADS_BANK0_GPIO6_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO6_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO6_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO6_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO6_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO6_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO6_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO6_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO6_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO6_PDE_LSB _u(2)
#define PADS_BANK0_GPIO6_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO6_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO6_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO6_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO6_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO6_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO6_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO6_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO6_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO6_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO6_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO6_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO6_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO6_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO6_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO6_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO6_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO6_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO6_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO6_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO6_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO7
// Description : Pad control register
-#define PADS_BANK0_GPIO7_OFFSET _U(0x00000020)
-#define PADS_BANK0_GPIO7_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO7_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO7_OFFSET _u(0x00000020)
+#define PADS_BANK0_GPIO7_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO7_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO7_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO7_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO7_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO7_OD_MSB _U(7)
-#define PADS_BANK0_GPIO7_OD_LSB _U(7)
+#define PADS_BANK0_GPIO7_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO7_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO7_OD_MSB _u(7)
+#define PADS_BANK0_GPIO7_OD_LSB _u(7)
#define PADS_BANK0_GPIO7_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO7_IE
// Description : Input enable
-#define PADS_BANK0_GPIO7_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO7_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO7_IE_MSB _U(6)
-#define PADS_BANK0_GPIO7_IE_LSB _U(6)
+#define PADS_BANK0_GPIO7_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO7_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO7_IE_MSB _u(6)
+#define PADS_BANK0_GPIO7_IE_LSB _u(6)
#define PADS_BANK0_GPIO7_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO7_DRIVE
@@ -551,69 +551,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO7_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO7_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO7_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO7_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO7_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO7_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO7_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO7_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO7_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO7_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO7_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO7_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO7_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO7_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO7_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO7_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO7_PUE_LSB _u(3)
#define PADS_BANK0_GPIO7_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO7_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO7_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO7_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO7_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO7_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO7_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO7_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO7_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO7_PDE_LSB _u(2)
#define PADS_BANK0_GPIO7_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO7_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO7_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO7_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO7_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO7_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO7_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO7_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO7_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO7_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO7_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO7_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO7_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO7_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO7_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO7_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO7_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO7_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO7_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO7_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO7_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO8
// Description : Pad control register
-#define PADS_BANK0_GPIO8_OFFSET _U(0x00000024)
-#define PADS_BANK0_GPIO8_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO8_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO8_OFFSET _u(0x00000024)
+#define PADS_BANK0_GPIO8_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO8_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO8_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO8_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO8_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO8_OD_MSB _U(7)
-#define PADS_BANK0_GPIO8_OD_LSB _U(7)
+#define PADS_BANK0_GPIO8_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO8_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO8_OD_MSB _u(7)
+#define PADS_BANK0_GPIO8_OD_LSB _u(7)
#define PADS_BANK0_GPIO8_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO8_IE
// Description : Input enable
-#define PADS_BANK0_GPIO8_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO8_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO8_IE_MSB _U(6)
-#define PADS_BANK0_GPIO8_IE_LSB _U(6)
+#define PADS_BANK0_GPIO8_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO8_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO8_IE_MSB _u(6)
+#define PADS_BANK0_GPIO8_IE_LSB _u(6)
#define PADS_BANK0_GPIO8_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO8_DRIVE
@@ -622,69 +622,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO8_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO8_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO8_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO8_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO8_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO8_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO8_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO8_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO8_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO8_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO8_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO8_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO8_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO8_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO8_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO8_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO8_PUE_LSB _u(3)
#define PADS_BANK0_GPIO8_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO8_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO8_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO8_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO8_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO8_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO8_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO8_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO8_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO8_PDE_LSB _u(2)
#define PADS_BANK0_GPIO8_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO8_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO8_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO8_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO8_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO8_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO8_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO8_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO8_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO8_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO8_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO8_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO8_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO8_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO8_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO8_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO8_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO8_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO8_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO8_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO8_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO9
// Description : Pad control register
-#define PADS_BANK0_GPIO9_OFFSET _U(0x00000028)
-#define PADS_BANK0_GPIO9_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO9_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO9_OFFSET _u(0x00000028)
+#define PADS_BANK0_GPIO9_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO9_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO9_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO9_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO9_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO9_OD_MSB _U(7)
-#define PADS_BANK0_GPIO9_OD_LSB _U(7)
+#define PADS_BANK0_GPIO9_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO9_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO9_OD_MSB _u(7)
+#define PADS_BANK0_GPIO9_OD_LSB _u(7)
#define PADS_BANK0_GPIO9_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO9_IE
// Description : Input enable
-#define PADS_BANK0_GPIO9_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO9_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO9_IE_MSB _U(6)
-#define PADS_BANK0_GPIO9_IE_LSB _U(6)
+#define PADS_BANK0_GPIO9_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO9_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO9_IE_MSB _u(6)
+#define PADS_BANK0_GPIO9_IE_LSB _u(6)
#define PADS_BANK0_GPIO9_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO9_DRIVE
@@ -693,69 +693,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO9_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO9_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO9_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO9_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO9_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO9_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO9_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO9_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO9_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO9_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO9_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO9_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO9_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO9_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO9_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO9_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO9_PUE_LSB _u(3)
#define PADS_BANK0_GPIO9_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO9_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO9_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO9_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO9_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO9_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO9_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO9_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO9_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO9_PDE_LSB _u(2)
#define PADS_BANK0_GPIO9_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO9_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO9_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO9_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO9_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO9_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO9_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO9_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO9_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO9_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO9_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO9_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO9_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO9_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO9_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO9_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO9_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO9_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO9_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO9_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO9_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO10
// Description : Pad control register
-#define PADS_BANK0_GPIO10_OFFSET _U(0x0000002c)
-#define PADS_BANK0_GPIO10_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO10_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO10_OFFSET _u(0x0000002c)
+#define PADS_BANK0_GPIO10_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO10_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO10_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO10_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO10_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO10_OD_MSB _U(7)
-#define PADS_BANK0_GPIO10_OD_LSB _U(7)
+#define PADS_BANK0_GPIO10_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO10_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO10_OD_MSB _u(7)
+#define PADS_BANK0_GPIO10_OD_LSB _u(7)
#define PADS_BANK0_GPIO10_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO10_IE
// Description : Input enable
-#define PADS_BANK0_GPIO10_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO10_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO10_IE_MSB _U(6)
-#define PADS_BANK0_GPIO10_IE_LSB _U(6)
+#define PADS_BANK0_GPIO10_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO10_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO10_IE_MSB _u(6)
+#define PADS_BANK0_GPIO10_IE_LSB _u(6)
#define PADS_BANK0_GPIO10_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO10_DRIVE
@@ -764,69 +764,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO10_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO10_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO10_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO10_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO10_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO10_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO10_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO10_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO10_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO10_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO10_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO10_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO10_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO10_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO10_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO10_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO10_PUE_LSB _u(3)
#define PADS_BANK0_GPIO10_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO10_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO10_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO10_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO10_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO10_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO10_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO10_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO10_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO10_PDE_LSB _u(2)
#define PADS_BANK0_GPIO10_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO10_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO10_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO10_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO10_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO10_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO10_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO10_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO10_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO10_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO10_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO10_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO10_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO10_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO10_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO10_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO10_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO10_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO10_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO10_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO10_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO11
// Description : Pad control register
-#define PADS_BANK0_GPIO11_OFFSET _U(0x00000030)
-#define PADS_BANK0_GPIO11_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO11_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO11_OFFSET _u(0x00000030)
+#define PADS_BANK0_GPIO11_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO11_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO11_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO11_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO11_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO11_OD_MSB _U(7)
-#define PADS_BANK0_GPIO11_OD_LSB _U(7)
+#define PADS_BANK0_GPIO11_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO11_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO11_OD_MSB _u(7)
+#define PADS_BANK0_GPIO11_OD_LSB _u(7)
#define PADS_BANK0_GPIO11_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO11_IE
// Description : Input enable
-#define PADS_BANK0_GPIO11_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO11_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO11_IE_MSB _U(6)
-#define PADS_BANK0_GPIO11_IE_LSB _U(6)
+#define PADS_BANK0_GPIO11_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO11_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO11_IE_MSB _u(6)
+#define PADS_BANK0_GPIO11_IE_LSB _u(6)
#define PADS_BANK0_GPIO11_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO11_DRIVE
@@ -835,69 +835,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO11_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO11_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO11_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO11_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO11_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO11_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO11_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO11_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO11_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO11_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO11_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO11_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO11_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO11_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO11_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO11_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO11_PUE_LSB _u(3)
#define PADS_BANK0_GPIO11_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO11_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO11_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO11_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO11_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO11_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO11_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO11_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO11_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO11_PDE_LSB _u(2)
#define PADS_BANK0_GPIO11_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO11_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO11_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO11_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO11_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO11_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO11_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO11_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO11_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO11_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO11_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO11_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO11_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO11_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO11_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO11_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO11_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO11_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO11_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO11_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO11_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO12
// Description : Pad control register
-#define PADS_BANK0_GPIO12_OFFSET _U(0x00000034)
-#define PADS_BANK0_GPIO12_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO12_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO12_OFFSET _u(0x00000034)
+#define PADS_BANK0_GPIO12_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO12_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO12_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO12_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO12_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO12_OD_MSB _U(7)
-#define PADS_BANK0_GPIO12_OD_LSB _U(7)
+#define PADS_BANK0_GPIO12_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO12_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO12_OD_MSB _u(7)
+#define PADS_BANK0_GPIO12_OD_LSB _u(7)
#define PADS_BANK0_GPIO12_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO12_IE
// Description : Input enable
-#define PADS_BANK0_GPIO12_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO12_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO12_IE_MSB _U(6)
-#define PADS_BANK0_GPIO12_IE_LSB _U(6)
+#define PADS_BANK0_GPIO12_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO12_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO12_IE_MSB _u(6)
+#define PADS_BANK0_GPIO12_IE_LSB _u(6)
#define PADS_BANK0_GPIO12_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO12_DRIVE
@@ -906,69 +906,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO12_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO12_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO12_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO12_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO12_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO12_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO12_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO12_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO12_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO12_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO12_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO12_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO12_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO12_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO12_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO12_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO12_PUE_LSB _u(3)
#define PADS_BANK0_GPIO12_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO12_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO12_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO12_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO12_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO12_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO12_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO12_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO12_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO12_PDE_LSB _u(2)
#define PADS_BANK0_GPIO12_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO12_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO12_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO12_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO12_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO12_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO12_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO12_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO12_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO12_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO12_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO12_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO12_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO12_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO12_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO12_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO12_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO12_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO12_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO12_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO12_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO13
// Description : Pad control register
-#define PADS_BANK0_GPIO13_OFFSET _U(0x00000038)
-#define PADS_BANK0_GPIO13_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO13_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO13_OFFSET _u(0x00000038)
+#define PADS_BANK0_GPIO13_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO13_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO13_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO13_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO13_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO13_OD_MSB _U(7)
-#define PADS_BANK0_GPIO13_OD_LSB _U(7)
+#define PADS_BANK0_GPIO13_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO13_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO13_OD_MSB _u(7)
+#define PADS_BANK0_GPIO13_OD_LSB _u(7)
#define PADS_BANK0_GPIO13_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO13_IE
// Description : Input enable
-#define PADS_BANK0_GPIO13_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO13_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO13_IE_MSB _U(6)
-#define PADS_BANK0_GPIO13_IE_LSB _U(6)
+#define PADS_BANK0_GPIO13_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO13_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO13_IE_MSB _u(6)
+#define PADS_BANK0_GPIO13_IE_LSB _u(6)
#define PADS_BANK0_GPIO13_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO13_DRIVE
@@ -977,69 +977,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO13_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO13_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO13_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO13_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO13_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO13_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO13_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO13_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO13_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO13_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO13_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO13_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO13_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO13_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO13_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO13_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO13_PUE_LSB _u(3)
#define PADS_BANK0_GPIO13_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO13_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO13_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO13_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO13_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO13_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO13_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO13_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO13_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO13_PDE_LSB _u(2)
#define PADS_BANK0_GPIO13_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO13_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO13_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO13_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO13_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO13_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO13_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO13_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO13_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO13_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO13_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO13_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO13_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO13_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO13_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO13_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO13_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO13_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO13_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO13_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO13_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO14
// Description : Pad control register
-#define PADS_BANK0_GPIO14_OFFSET _U(0x0000003c)
-#define PADS_BANK0_GPIO14_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO14_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO14_OFFSET _u(0x0000003c)
+#define PADS_BANK0_GPIO14_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO14_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO14_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO14_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO14_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO14_OD_MSB _U(7)
-#define PADS_BANK0_GPIO14_OD_LSB _U(7)
+#define PADS_BANK0_GPIO14_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO14_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO14_OD_MSB _u(7)
+#define PADS_BANK0_GPIO14_OD_LSB _u(7)
#define PADS_BANK0_GPIO14_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO14_IE
// Description : Input enable
-#define PADS_BANK0_GPIO14_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO14_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO14_IE_MSB _U(6)
-#define PADS_BANK0_GPIO14_IE_LSB _U(6)
+#define PADS_BANK0_GPIO14_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO14_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO14_IE_MSB _u(6)
+#define PADS_BANK0_GPIO14_IE_LSB _u(6)
#define PADS_BANK0_GPIO14_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO14_DRIVE
@@ -1048,69 +1048,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO14_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO14_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO14_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO14_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO14_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO14_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO14_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO14_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO14_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO14_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO14_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO14_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO14_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO14_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO14_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO14_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO14_PUE_LSB _u(3)
#define PADS_BANK0_GPIO14_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO14_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO14_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO14_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO14_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO14_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO14_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO14_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO14_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO14_PDE_LSB _u(2)
#define PADS_BANK0_GPIO14_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO14_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO14_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO14_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO14_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO14_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO14_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO14_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO14_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO14_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO14_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO14_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO14_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO14_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO14_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO14_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO14_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO14_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO14_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO14_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO14_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO15
// Description : Pad control register
-#define PADS_BANK0_GPIO15_OFFSET _U(0x00000040)
-#define PADS_BANK0_GPIO15_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO15_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO15_OFFSET _u(0x00000040)
+#define PADS_BANK0_GPIO15_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO15_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO15_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO15_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO15_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO15_OD_MSB _U(7)
-#define PADS_BANK0_GPIO15_OD_LSB _U(7)
+#define PADS_BANK0_GPIO15_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO15_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO15_OD_MSB _u(7)
+#define PADS_BANK0_GPIO15_OD_LSB _u(7)
#define PADS_BANK0_GPIO15_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO15_IE
// Description : Input enable
-#define PADS_BANK0_GPIO15_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO15_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO15_IE_MSB _U(6)
-#define PADS_BANK0_GPIO15_IE_LSB _U(6)
+#define PADS_BANK0_GPIO15_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO15_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO15_IE_MSB _u(6)
+#define PADS_BANK0_GPIO15_IE_LSB _u(6)
#define PADS_BANK0_GPIO15_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO15_DRIVE
@@ -1119,69 +1119,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO15_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO15_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO15_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO15_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO15_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO15_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO15_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO15_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO15_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO15_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO15_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO15_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO15_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO15_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO15_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO15_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO15_PUE_LSB _u(3)
#define PADS_BANK0_GPIO15_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO15_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO15_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO15_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO15_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO15_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO15_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO15_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO15_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO15_PDE_LSB _u(2)
#define PADS_BANK0_GPIO15_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO15_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO15_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO15_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO15_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO15_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO15_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO15_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO15_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO15_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO15_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO15_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO15_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO15_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO15_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO15_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO15_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO15_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO15_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO15_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO15_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO16
// Description : Pad control register
-#define PADS_BANK0_GPIO16_OFFSET _U(0x00000044)
-#define PADS_BANK0_GPIO16_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO16_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO16_OFFSET _u(0x00000044)
+#define PADS_BANK0_GPIO16_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO16_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO16_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO16_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO16_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO16_OD_MSB _U(7)
-#define PADS_BANK0_GPIO16_OD_LSB _U(7)
+#define PADS_BANK0_GPIO16_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO16_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO16_OD_MSB _u(7)
+#define PADS_BANK0_GPIO16_OD_LSB _u(7)
#define PADS_BANK0_GPIO16_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO16_IE
// Description : Input enable
-#define PADS_BANK0_GPIO16_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO16_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO16_IE_MSB _U(6)
-#define PADS_BANK0_GPIO16_IE_LSB _U(6)
+#define PADS_BANK0_GPIO16_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO16_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO16_IE_MSB _u(6)
+#define PADS_BANK0_GPIO16_IE_LSB _u(6)
#define PADS_BANK0_GPIO16_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO16_DRIVE
@@ -1190,69 +1190,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO16_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO16_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO16_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO16_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO16_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO16_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO16_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO16_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO16_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO16_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO16_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO16_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO16_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO16_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO16_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO16_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO16_PUE_LSB _u(3)
#define PADS_BANK0_GPIO16_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO16_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO16_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO16_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO16_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO16_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO16_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO16_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO16_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO16_PDE_LSB _u(2)
#define PADS_BANK0_GPIO16_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO16_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO16_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO16_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO16_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO16_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO16_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO16_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO16_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO16_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO16_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO16_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO16_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO16_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO16_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO16_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO16_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO16_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO16_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO16_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO16_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO17
// Description : Pad control register
-#define PADS_BANK0_GPIO17_OFFSET _U(0x00000048)
-#define PADS_BANK0_GPIO17_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO17_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO17_OFFSET _u(0x00000048)
+#define PADS_BANK0_GPIO17_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO17_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO17_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO17_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO17_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO17_OD_MSB _U(7)
-#define PADS_BANK0_GPIO17_OD_LSB _U(7)
+#define PADS_BANK0_GPIO17_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO17_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO17_OD_MSB _u(7)
+#define PADS_BANK0_GPIO17_OD_LSB _u(7)
#define PADS_BANK0_GPIO17_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO17_IE
// Description : Input enable
-#define PADS_BANK0_GPIO17_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO17_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO17_IE_MSB _U(6)
-#define PADS_BANK0_GPIO17_IE_LSB _U(6)
+#define PADS_BANK0_GPIO17_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO17_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO17_IE_MSB _u(6)
+#define PADS_BANK0_GPIO17_IE_LSB _u(6)
#define PADS_BANK0_GPIO17_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO17_DRIVE
@@ -1261,69 +1261,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO17_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO17_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO17_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO17_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO17_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO17_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO17_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO17_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO17_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO17_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO17_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO17_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO17_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO17_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO17_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO17_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO17_PUE_LSB _u(3)
#define PADS_BANK0_GPIO17_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO17_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO17_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO17_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO17_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO17_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO17_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO17_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO17_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO17_PDE_LSB _u(2)
#define PADS_BANK0_GPIO17_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO17_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO17_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO17_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO17_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO17_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO17_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO17_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO17_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO17_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO17_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO17_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO17_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO17_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO17_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO17_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO17_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO17_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO17_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO17_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO17_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO18
// Description : Pad control register
-#define PADS_BANK0_GPIO18_OFFSET _U(0x0000004c)
-#define PADS_BANK0_GPIO18_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO18_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO18_OFFSET _u(0x0000004c)
+#define PADS_BANK0_GPIO18_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO18_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO18_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO18_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO18_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO18_OD_MSB _U(7)
-#define PADS_BANK0_GPIO18_OD_LSB _U(7)
+#define PADS_BANK0_GPIO18_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO18_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO18_OD_MSB _u(7)
+#define PADS_BANK0_GPIO18_OD_LSB _u(7)
#define PADS_BANK0_GPIO18_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO18_IE
// Description : Input enable
-#define PADS_BANK0_GPIO18_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO18_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO18_IE_MSB _U(6)
-#define PADS_BANK0_GPIO18_IE_LSB _U(6)
+#define PADS_BANK0_GPIO18_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO18_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO18_IE_MSB _u(6)
+#define PADS_BANK0_GPIO18_IE_LSB _u(6)
#define PADS_BANK0_GPIO18_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO18_DRIVE
@@ -1332,69 +1332,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO18_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO18_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO18_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO18_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO18_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO18_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO18_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO18_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO18_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO18_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO18_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO18_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO18_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO18_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO18_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO18_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO18_PUE_LSB _u(3)
#define PADS_BANK0_GPIO18_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO18_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO18_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO18_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO18_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO18_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO18_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO18_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO18_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO18_PDE_LSB _u(2)
#define PADS_BANK0_GPIO18_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO18_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO18_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO18_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO18_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO18_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO18_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO18_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO18_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO18_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO18_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO18_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO18_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO18_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO18_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO18_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO18_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO18_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO18_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO18_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO18_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO19
// Description : Pad control register
-#define PADS_BANK0_GPIO19_OFFSET _U(0x00000050)
-#define PADS_BANK0_GPIO19_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO19_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO19_OFFSET _u(0x00000050)
+#define PADS_BANK0_GPIO19_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO19_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO19_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO19_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO19_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO19_OD_MSB _U(7)
-#define PADS_BANK0_GPIO19_OD_LSB _U(7)
+#define PADS_BANK0_GPIO19_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO19_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO19_OD_MSB _u(7)
+#define PADS_BANK0_GPIO19_OD_LSB _u(7)
#define PADS_BANK0_GPIO19_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO19_IE
// Description : Input enable
-#define PADS_BANK0_GPIO19_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO19_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO19_IE_MSB _U(6)
-#define PADS_BANK0_GPIO19_IE_LSB _U(6)
+#define PADS_BANK0_GPIO19_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO19_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO19_IE_MSB _u(6)
+#define PADS_BANK0_GPIO19_IE_LSB _u(6)
#define PADS_BANK0_GPIO19_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO19_DRIVE
@@ -1403,69 +1403,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO19_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO19_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO19_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO19_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO19_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO19_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO19_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO19_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO19_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO19_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO19_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO19_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO19_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO19_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO19_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO19_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO19_PUE_LSB _u(3)
#define PADS_BANK0_GPIO19_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO19_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO19_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO19_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO19_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO19_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO19_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO19_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO19_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO19_PDE_LSB _u(2)
#define PADS_BANK0_GPIO19_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO19_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO19_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO19_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO19_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO19_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO19_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO19_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO19_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO19_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO19_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO19_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO19_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO19_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO19_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO19_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO19_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO19_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO19_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO19_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO19_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO20
// Description : Pad control register
-#define PADS_BANK0_GPIO20_OFFSET _U(0x00000054)
-#define PADS_BANK0_GPIO20_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO20_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO20_OFFSET _u(0x00000054)
+#define PADS_BANK0_GPIO20_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO20_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO20_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO20_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO20_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO20_OD_MSB _U(7)
-#define PADS_BANK0_GPIO20_OD_LSB _U(7)
+#define PADS_BANK0_GPIO20_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO20_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO20_OD_MSB _u(7)
+#define PADS_BANK0_GPIO20_OD_LSB _u(7)
#define PADS_BANK0_GPIO20_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO20_IE
// Description : Input enable
-#define PADS_BANK0_GPIO20_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO20_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO20_IE_MSB _U(6)
-#define PADS_BANK0_GPIO20_IE_LSB _U(6)
+#define PADS_BANK0_GPIO20_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO20_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO20_IE_MSB _u(6)
+#define PADS_BANK0_GPIO20_IE_LSB _u(6)
#define PADS_BANK0_GPIO20_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO20_DRIVE
@@ -1474,69 +1474,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO20_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO20_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO20_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO20_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO20_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO20_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO20_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO20_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO20_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO20_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO20_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO20_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO20_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO20_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO20_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO20_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO20_PUE_LSB _u(3)
#define PADS_BANK0_GPIO20_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO20_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO20_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO20_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO20_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO20_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO20_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO20_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO20_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO20_PDE_LSB _u(2)
#define PADS_BANK0_GPIO20_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO20_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO20_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO20_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO20_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO20_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO20_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO20_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO20_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO20_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO20_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO20_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO20_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO20_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO20_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO20_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO20_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO20_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO20_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO20_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO20_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO21
// Description : Pad control register
-#define PADS_BANK0_GPIO21_OFFSET _U(0x00000058)
-#define PADS_BANK0_GPIO21_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO21_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO21_OFFSET _u(0x00000058)
+#define PADS_BANK0_GPIO21_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO21_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO21_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO21_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO21_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO21_OD_MSB _U(7)
-#define PADS_BANK0_GPIO21_OD_LSB _U(7)
+#define PADS_BANK0_GPIO21_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO21_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO21_OD_MSB _u(7)
+#define PADS_BANK0_GPIO21_OD_LSB _u(7)
#define PADS_BANK0_GPIO21_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO21_IE
// Description : Input enable
-#define PADS_BANK0_GPIO21_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO21_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO21_IE_MSB _U(6)
-#define PADS_BANK0_GPIO21_IE_LSB _U(6)
+#define PADS_BANK0_GPIO21_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO21_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO21_IE_MSB _u(6)
+#define PADS_BANK0_GPIO21_IE_LSB _u(6)
#define PADS_BANK0_GPIO21_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO21_DRIVE
@@ -1545,69 +1545,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO21_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO21_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO21_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO21_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO21_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO21_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO21_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO21_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO21_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO21_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO21_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO21_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO21_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO21_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO21_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO21_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO21_PUE_LSB _u(3)
#define PADS_BANK0_GPIO21_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO21_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO21_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO21_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO21_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO21_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO21_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO21_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO21_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO21_PDE_LSB _u(2)
#define PADS_BANK0_GPIO21_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO21_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO21_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO21_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO21_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO21_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO21_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO21_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO21_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO21_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO21_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO21_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO21_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO21_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO21_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO21_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO21_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO21_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO21_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO21_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO21_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO22
// Description : Pad control register
-#define PADS_BANK0_GPIO22_OFFSET _U(0x0000005c)
-#define PADS_BANK0_GPIO22_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO22_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO22_OFFSET _u(0x0000005c)
+#define PADS_BANK0_GPIO22_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO22_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO22_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO22_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO22_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO22_OD_MSB _U(7)
-#define PADS_BANK0_GPIO22_OD_LSB _U(7)
+#define PADS_BANK0_GPIO22_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO22_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO22_OD_MSB _u(7)
+#define PADS_BANK0_GPIO22_OD_LSB _u(7)
#define PADS_BANK0_GPIO22_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO22_IE
// Description : Input enable
-#define PADS_BANK0_GPIO22_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO22_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO22_IE_MSB _U(6)
-#define PADS_BANK0_GPIO22_IE_LSB _U(6)
+#define PADS_BANK0_GPIO22_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO22_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO22_IE_MSB _u(6)
+#define PADS_BANK0_GPIO22_IE_LSB _u(6)
#define PADS_BANK0_GPIO22_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO22_DRIVE
@@ -1616,69 +1616,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO22_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO22_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO22_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO22_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO22_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO22_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO22_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO22_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO22_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO22_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO22_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO22_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO22_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO22_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO22_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO22_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO22_PUE_LSB _u(3)
#define PADS_BANK0_GPIO22_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO22_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO22_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO22_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO22_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO22_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO22_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO22_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO22_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO22_PDE_LSB _u(2)
#define PADS_BANK0_GPIO22_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO22_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO22_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO22_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO22_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO22_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO22_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO22_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO22_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO22_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO22_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO22_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO22_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO22_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO22_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO22_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO22_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO22_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO22_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO22_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO22_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO23
// Description : Pad control register
-#define PADS_BANK0_GPIO23_OFFSET _U(0x00000060)
-#define PADS_BANK0_GPIO23_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO23_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO23_OFFSET _u(0x00000060)
+#define PADS_BANK0_GPIO23_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO23_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO23_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO23_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO23_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO23_OD_MSB _U(7)
-#define PADS_BANK0_GPIO23_OD_LSB _U(7)
+#define PADS_BANK0_GPIO23_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO23_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO23_OD_MSB _u(7)
+#define PADS_BANK0_GPIO23_OD_LSB _u(7)
#define PADS_BANK0_GPIO23_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO23_IE
// Description : Input enable
-#define PADS_BANK0_GPIO23_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO23_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO23_IE_MSB _U(6)
-#define PADS_BANK0_GPIO23_IE_LSB _U(6)
+#define PADS_BANK0_GPIO23_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO23_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO23_IE_MSB _u(6)
+#define PADS_BANK0_GPIO23_IE_LSB _u(6)
#define PADS_BANK0_GPIO23_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO23_DRIVE
@@ -1687,69 +1687,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO23_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO23_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO23_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO23_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO23_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO23_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO23_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO23_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO23_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO23_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO23_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO23_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO23_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO23_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO23_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO23_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO23_PUE_LSB _u(3)
#define PADS_BANK0_GPIO23_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO23_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO23_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO23_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO23_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO23_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO23_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO23_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO23_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO23_PDE_LSB _u(2)
#define PADS_BANK0_GPIO23_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO23_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO23_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO23_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO23_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO23_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO23_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO23_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO23_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO23_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO23_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO23_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO23_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO23_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO23_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO23_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO23_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO23_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO23_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO23_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO23_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO24
// Description : Pad control register
-#define PADS_BANK0_GPIO24_OFFSET _U(0x00000064)
-#define PADS_BANK0_GPIO24_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO24_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO24_OFFSET _u(0x00000064)
+#define PADS_BANK0_GPIO24_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO24_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO24_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO24_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO24_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO24_OD_MSB _U(7)
-#define PADS_BANK0_GPIO24_OD_LSB _U(7)
+#define PADS_BANK0_GPIO24_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO24_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO24_OD_MSB _u(7)
+#define PADS_BANK0_GPIO24_OD_LSB _u(7)
#define PADS_BANK0_GPIO24_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO24_IE
// Description : Input enable
-#define PADS_BANK0_GPIO24_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO24_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO24_IE_MSB _U(6)
-#define PADS_BANK0_GPIO24_IE_LSB _U(6)
+#define PADS_BANK0_GPIO24_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO24_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO24_IE_MSB _u(6)
+#define PADS_BANK0_GPIO24_IE_LSB _u(6)
#define PADS_BANK0_GPIO24_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO24_DRIVE
@@ -1758,69 +1758,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO24_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO24_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO24_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO24_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO24_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO24_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO24_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO24_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO24_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO24_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO24_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO24_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO24_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO24_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO24_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO24_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO24_PUE_LSB _u(3)
#define PADS_BANK0_GPIO24_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO24_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO24_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO24_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO24_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO24_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO24_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO24_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO24_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO24_PDE_LSB _u(2)
#define PADS_BANK0_GPIO24_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO24_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO24_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO24_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO24_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO24_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO24_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO24_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO24_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO24_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO24_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO24_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO24_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO24_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO24_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO24_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO24_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO24_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO24_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO24_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO24_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO25
// Description : Pad control register
-#define PADS_BANK0_GPIO25_OFFSET _U(0x00000068)
-#define PADS_BANK0_GPIO25_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO25_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO25_OFFSET _u(0x00000068)
+#define PADS_BANK0_GPIO25_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO25_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO25_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO25_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO25_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO25_OD_MSB _U(7)
-#define PADS_BANK0_GPIO25_OD_LSB _U(7)
+#define PADS_BANK0_GPIO25_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO25_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO25_OD_MSB _u(7)
+#define PADS_BANK0_GPIO25_OD_LSB _u(7)
#define PADS_BANK0_GPIO25_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO25_IE
// Description : Input enable
-#define PADS_BANK0_GPIO25_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO25_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO25_IE_MSB _U(6)
-#define PADS_BANK0_GPIO25_IE_LSB _U(6)
+#define PADS_BANK0_GPIO25_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO25_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO25_IE_MSB _u(6)
+#define PADS_BANK0_GPIO25_IE_LSB _u(6)
#define PADS_BANK0_GPIO25_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO25_DRIVE
@@ -1829,69 +1829,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO25_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO25_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO25_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO25_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO25_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO25_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO25_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO25_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO25_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO25_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO25_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO25_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO25_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO25_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO25_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO25_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO25_PUE_LSB _u(3)
#define PADS_BANK0_GPIO25_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO25_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO25_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO25_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO25_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO25_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO25_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO25_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO25_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO25_PDE_LSB _u(2)
#define PADS_BANK0_GPIO25_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO25_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO25_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO25_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO25_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO25_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO25_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO25_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO25_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO25_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO25_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO25_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO25_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO25_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO25_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO25_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO25_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO25_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO25_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO25_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO25_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO26
// Description : Pad control register
-#define PADS_BANK0_GPIO26_OFFSET _U(0x0000006c)
-#define PADS_BANK0_GPIO26_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO26_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO26_OFFSET _u(0x0000006c)
+#define PADS_BANK0_GPIO26_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO26_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO26_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO26_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO26_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO26_OD_MSB _U(7)
-#define PADS_BANK0_GPIO26_OD_LSB _U(7)
+#define PADS_BANK0_GPIO26_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO26_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO26_OD_MSB _u(7)
+#define PADS_BANK0_GPIO26_OD_LSB _u(7)
#define PADS_BANK0_GPIO26_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO26_IE
// Description : Input enable
-#define PADS_BANK0_GPIO26_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO26_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO26_IE_MSB _U(6)
-#define PADS_BANK0_GPIO26_IE_LSB _U(6)
+#define PADS_BANK0_GPIO26_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO26_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO26_IE_MSB _u(6)
+#define PADS_BANK0_GPIO26_IE_LSB _u(6)
#define PADS_BANK0_GPIO26_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO26_DRIVE
@@ -1900,69 +1900,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO26_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO26_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO26_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO26_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO26_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO26_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO26_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO26_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO26_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO26_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO26_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO26_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO26_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO26_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO26_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO26_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO26_PUE_LSB _u(3)
#define PADS_BANK0_GPIO26_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO26_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO26_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO26_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO26_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO26_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO26_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO26_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO26_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO26_PDE_LSB _u(2)
#define PADS_BANK0_GPIO26_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO26_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO26_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO26_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO26_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO26_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO26_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO26_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO26_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO26_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO26_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO26_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO26_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO26_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO26_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO26_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO26_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO26_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO26_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO26_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO26_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO27
// Description : Pad control register
-#define PADS_BANK0_GPIO27_OFFSET _U(0x00000070)
-#define PADS_BANK0_GPIO27_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO27_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO27_OFFSET _u(0x00000070)
+#define PADS_BANK0_GPIO27_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO27_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO27_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO27_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO27_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO27_OD_MSB _U(7)
-#define PADS_BANK0_GPIO27_OD_LSB _U(7)
+#define PADS_BANK0_GPIO27_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO27_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO27_OD_MSB _u(7)
+#define PADS_BANK0_GPIO27_OD_LSB _u(7)
#define PADS_BANK0_GPIO27_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO27_IE
// Description : Input enable
-#define PADS_BANK0_GPIO27_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO27_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO27_IE_MSB _U(6)
-#define PADS_BANK0_GPIO27_IE_LSB _U(6)
+#define PADS_BANK0_GPIO27_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO27_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO27_IE_MSB _u(6)
+#define PADS_BANK0_GPIO27_IE_LSB _u(6)
#define PADS_BANK0_GPIO27_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO27_DRIVE
@@ -1971,69 +1971,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO27_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO27_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO27_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO27_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO27_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO27_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO27_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO27_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO27_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO27_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO27_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO27_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO27_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO27_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO27_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO27_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO27_PUE_LSB _u(3)
#define PADS_BANK0_GPIO27_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO27_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO27_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO27_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO27_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO27_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO27_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO27_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO27_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO27_PDE_LSB _u(2)
#define PADS_BANK0_GPIO27_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO27_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO27_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO27_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO27_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO27_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO27_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO27_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO27_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO27_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO27_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO27_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO27_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO27_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO27_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO27_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO27_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO27_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO27_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO27_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO27_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO28
// Description : Pad control register
-#define PADS_BANK0_GPIO28_OFFSET _U(0x00000074)
-#define PADS_BANK0_GPIO28_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO28_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO28_OFFSET _u(0x00000074)
+#define PADS_BANK0_GPIO28_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO28_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO28_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO28_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO28_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO28_OD_MSB _U(7)
-#define PADS_BANK0_GPIO28_OD_LSB _U(7)
+#define PADS_BANK0_GPIO28_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO28_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO28_OD_MSB _u(7)
+#define PADS_BANK0_GPIO28_OD_LSB _u(7)
#define PADS_BANK0_GPIO28_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO28_IE
// Description : Input enable
-#define PADS_BANK0_GPIO28_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO28_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO28_IE_MSB _U(6)
-#define PADS_BANK0_GPIO28_IE_LSB _U(6)
+#define PADS_BANK0_GPIO28_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO28_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO28_IE_MSB _u(6)
+#define PADS_BANK0_GPIO28_IE_LSB _u(6)
#define PADS_BANK0_GPIO28_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO28_DRIVE
@@ -2042,69 +2042,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO28_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO28_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO28_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO28_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO28_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO28_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO28_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO28_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO28_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO28_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO28_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO28_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO28_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO28_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO28_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO28_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO28_PUE_LSB _u(3)
#define PADS_BANK0_GPIO28_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO28_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO28_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO28_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO28_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO28_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO28_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO28_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO28_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO28_PDE_LSB _u(2)
#define PADS_BANK0_GPIO28_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO28_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO28_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO28_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO28_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO28_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO28_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO28_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO28_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO28_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO28_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO28_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO28_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO28_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO28_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO28_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO28_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO28_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO28_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO28_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO28_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_GPIO29
// Description : Pad control register
-#define PADS_BANK0_GPIO29_OFFSET _U(0x00000078)
-#define PADS_BANK0_GPIO29_BITS _U(0x000000ff)
-#define PADS_BANK0_GPIO29_RESET _U(0x00000056)
+#define PADS_BANK0_GPIO29_OFFSET _u(0x00000078)
+#define PADS_BANK0_GPIO29_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO29_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO29_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_GPIO29_OD_RESET _U(0x0)
-#define PADS_BANK0_GPIO29_OD_BITS _U(0x00000080)
-#define PADS_BANK0_GPIO29_OD_MSB _U(7)
-#define PADS_BANK0_GPIO29_OD_LSB _U(7)
+#define PADS_BANK0_GPIO29_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO29_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO29_OD_MSB _u(7)
+#define PADS_BANK0_GPIO29_OD_LSB _u(7)
#define PADS_BANK0_GPIO29_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO29_IE
// Description : Input enable
-#define PADS_BANK0_GPIO29_IE_RESET _U(0x1)
-#define PADS_BANK0_GPIO29_IE_BITS _U(0x00000040)
-#define PADS_BANK0_GPIO29_IE_MSB _U(6)
-#define PADS_BANK0_GPIO29_IE_LSB _U(6)
+#define PADS_BANK0_GPIO29_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO29_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO29_IE_MSB _u(6)
+#define PADS_BANK0_GPIO29_IE_LSB _u(6)
#define PADS_BANK0_GPIO29_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO29_DRIVE
@@ -2113,69 +2113,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_GPIO29_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_GPIO29_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_GPIO29_DRIVE_MSB _U(5)
-#define PADS_BANK0_GPIO29_DRIVE_LSB _U(4)
+#define PADS_BANK0_GPIO29_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO29_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO29_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO29_DRIVE_LSB _u(4)
#define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW"
-#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO29_PUE
// Description : Pull up enable
-#define PADS_BANK0_GPIO29_PUE_RESET _U(0x0)
-#define PADS_BANK0_GPIO29_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_GPIO29_PUE_MSB _U(3)
-#define PADS_BANK0_GPIO29_PUE_LSB _U(3)
+#define PADS_BANK0_GPIO29_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO29_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO29_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO29_PUE_LSB _u(3)
#define PADS_BANK0_GPIO29_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO29_PDE
// Description : Pull down enable
-#define PADS_BANK0_GPIO29_PDE_RESET _U(0x1)
-#define PADS_BANK0_GPIO29_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_GPIO29_PDE_MSB _U(2)
-#define PADS_BANK0_GPIO29_PDE_LSB _U(2)
+#define PADS_BANK0_GPIO29_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO29_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO29_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO29_PDE_LSB _u(2)
#define PADS_BANK0_GPIO29_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO29_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_GPIO29_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_GPIO29_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_GPIO29_SCHMITT_MSB _U(1)
-#define PADS_BANK0_GPIO29_SCHMITT_LSB _U(1)
+#define PADS_BANK0_GPIO29_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO29_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO29_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO29_SCHMITT_LSB _u(1)
#define PADS_BANK0_GPIO29_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_GPIO29_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_GPIO29_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_GPIO29_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_GPIO29_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_GPIO29_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_GPIO29_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO29_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO29_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO29_SLEWFAST_LSB _u(0)
#define PADS_BANK0_GPIO29_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_SWCLK
// Description : Pad control register
-#define PADS_BANK0_SWCLK_OFFSET _U(0x0000007c)
-#define PADS_BANK0_SWCLK_BITS _U(0x000000ff)
-#define PADS_BANK0_SWCLK_RESET _U(0x000000da)
+#define PADS_BANK0_SWCLK_OFFSET _u(0x0000007c)
+#define PADS_BANK0_SWCLK_BITS _u(0x000000ff)
+#define PADS_BANK0_SWCLK_RESET _u(0x000000da)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_SWCLK_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_SWCLK_OD_RESET _U(0x1)
-#define PADS_BANK0_SWCLK_OD_BITS _U(0x00000080)
-#define PADS_BANK0_SWCLK_OD_MSB _U(7)
-#define PADS_BANK0_SWCLK_OD_LSB _U(7)
+#define PADS_BANK0_SWCLK_OD_RESET _u(0x1)
+#define PADS_BANK0_SWCLK_OD_BITS _u(0x00000080)
+#define PADS_BANK0_SWCLK_OD_MSB _u(7)
+#define PADS_BANK0_SWCLK_OD_LSB _u(7)
#define PADS_BANK0_SWCLK_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_SWCLK_IE
// Description : Input enable
-#define PADS_BANK0_SWCLK_IE_RESET _U(0x1)
-#define PADS_BANK0_SWCLK_IE_BITS _U(0x00000040)
-#define PADS_BANK0_SWCLK_IE_MSB _U(6)
-#define PADS_BANK0_SWCLK_IE_LSB _U(6)
+#define PADS_BANK0_SWCLK_IE_RESET _u(0x1)
+#define PADS_BANK0_SWCLK_IE_BITS _u(0x00000040)
+#define PADS_BANK0_SWCLK_IE_MSB _u(6)
+#define PADS_BANK0_SWCLK_IE_LSB _u(6)
#define PADS_BANK0_SWCLK_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_SWCLK_DRIVE
@@ -2184,69 +2184,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_SWCLK_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_SWCLK_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_SWCLK_DRIVE_MSB _U(5)
-#define PADS_BANK0_SWCLK_DRIVE_LSB _U(4)
+#define PADS_BANK0_SWCLK_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_SWCLK_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_SWCLK_DRIVE_MSB _u(5)
+#define PADS_BANK0_SWCLK_DRIVE_LSB _u(4)
#define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW"
-#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_SWCLK_PUE
// Description : Pull up enable
-#define PADS_BANK0_SWCLK_PUE_RESET _U(0x1)
-#define PADS_BANK0_SWCLK_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_SWCLK_PUE_MSB _U(3)
-#define PADS_BANK0_SWCLK_PUE_LSB _U(3)
+#define PADS_BANK0_SWCLK_PUE_RESET _u(0x1)
+#define PADS_BANK0_SWCLK_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_SWCLK_PUE_MSB _u(3)
+#define PADS_BANK0_SWCLK_PUE_LSB _u(3)
#define PADS_BANK0_SWCLK_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_SWCLK_PDE
// Description : Pull down enable
-#define PADS_BANK0_SWCLK_PDE_RESET _U(0x0)
-#define PADS_BANK0_SWCLK_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_SWCLK_PDE_MSB _U(2)
-#define PADS_BANK0_SWCLK_PDE_LSB _U(2)
+#define PADS_BANK0_SWCLK_PDE_RESET _u(0x0)
+#define PADS_BANK0_SWCLK_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_SWCLK_PDE_MSB _u(2)
+#define PADS_BANK0_SWCLK_PDE_LSB _u(2)
#define PADS_BANK0_SWCLK_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_SWCLK_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_SWCLK_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_SWCLK_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_SWCLK_SCHMITT_MSB _U(1)
-#define PADS_BANK0_SWCLK_SCHMITT_LSB _U(1)
+#define PADS_BANK0_SWCLK_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_SWCLK_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_SWCLK_SCHMITT_MSB _u(1)
+#define PADS_BANK0_SWCLK_SCHMITT_LSB _u(1)
#define PADS_BANK0_SWCLK_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_SWCLK_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_SWCLK_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_SWCLK_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_SWCLK_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_SWCLK_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_SWCLK_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_SWCLK_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_SWCLK_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_SWCLK_SLEWFAST_LSB _u(0)
#define PADS_BANK0_SWCLK_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_BANK0_SWD
// Description : Pad control register
-#define PADS_BANK0_SWD_OFFSET _U(0x00000080)
-#define PADS_BANK0_SWD_BITS _U(0x000000ff)
-#define PADS_BANK0_SWD_RESET _U(0x0000005a)
+#define PADS_BANK0_SWD_OFFSET _u(0x00000080)
+#define PADS_BANK0_SWD_BITS _u(0x000000ff)
+#define PADS_BANK0_SWD_RESET _u(0x0000005a)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_SWD_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_BANK0_SWD_OD_RESET _U(0x0)
-#define PADS_BANK0_SWD_OD_BITS _U(0x00000080)
-#define PADS_BANK0_SWD_OD_MSB _U(7)
-#define PADS_BANK0_SWD_OD_LSB _U(7)
+#define PADS_BANK0_SWD_OD_RESET _u(0x0)
+#define PADS_BANK0_SWD_OD_BITS _u(0x00000080)
+#define PADS_BANK0_SWD_OD_MSB _u(7)
+#define PADS_BANK0_SWD_OD_LSB _u(7)
#define PADS_BANK0_SWD_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_SWD_IE
// Description : Input enable
-#define PADS_BANK0_SWD_IE_RESET _U(0x1)
-#define PADS_BANK0_SWD_IE_BITS _U(0x00000040)
-#define PADS_BANK0_SWD_IE_MSB _U(6)
-#define PADS_BANK0_SWD_IE_LSB _U(6)
+#define PADS_BANK0_SWD_IE_RESET _u(0x1)
+#define PADS_BANK0_SWD_IE_BITS _u(0x00000040)
+#define PADS_BANK0_SWD_IE_MSB _u(6)
+#define PADS_BANK0_SWD_IE_LSB _u(6)
#define PADS_BANK0_SWD_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_SWD_DRIVE
@@ -2255,46 +2255,46 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_BANK0_SWD_DRIVE_RESET _U(0x1)
-#define PADS_BANK0_SWD_DRIVE_BITS _U(0x00000030)
-#define PADS_BANK0_SWD_DRIVE_MSB _U(5)
-#define PADS_BANK0_SWD_DRIVE_LSB _U(4)
+#define PADS_BANK0_SWD_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_SWD_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_SWD_DRIVE_MSB _u(5)
+#define PADS_BANK0_SWD_DRIVE_LSB _u(4)
#define PADS_BANK0_SWD_DRIVE_ACCESS "RW"
-#define PADS_BANK0_SWD_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_BANK0_SWD_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_BANK0_SWD_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_BANK0_SWD_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_BANK0_SWD_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_SWD_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_SWD_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_SWD_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_SWD_PUE
// Description : Pull up enable
-#define PADS_BANK0_SWD_PUE_RESET _U(0x1)
-#define PADS_BANK0_SWD_PUE_BITS _U(0x00000008)
-#define PADS_BANK0_SWD_PUE_MSB _U(3)
-#define PADS_BANK0_SWD_PUE_LSB _U(3)
+#define PADS_BANK0_SWD_PUE_RESET _u(0x1)
+#define PADS_BANK0_SWD_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_SWD_PUE_MSB _u(3)
+#define PADS_BANK0_SWD_PUE_LSB _u(3)
#define PADS_BANK0_SWD_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_SWD_PDE
// Description : Pull down enable
-#define PADS_BANK0_SWD_PDE_RESET _U(0x0)
-#define PADS_BANK0_SWD_PDE_BITS _U(0x00000004)
-#define PADS_BANK0_SWD_PDE_MSB _U(2)
-#define PADS_BANK0_SWD_PDE_LSB _U(2)
+#define PADS_BANK0_SWD_PDE_RESET _u(0x0)
+#define PADS_BANK0_SWD_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_SWD_PDE_MSB _u(2)
+#define PADS_BANK0_SWD_PDE_LSB _u(2)
#define PADS_BANK0_SWD_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_SWD_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_BANK0_SWD_SCHMITT_RESET _U(0x1)
-#define PADS_BANK0_SWD_SCHMITT_BITS _U(0x00000002)
-#define PADS_BANK0_SWD_SCHMITT_MSB _U(1)
-#define PADS_BANK0_SWD_SCHMITT_LSB _U(1)
+#define PADS_BANK0_SWD_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_SWD_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_SWD_SCHMITT_MSB _u(1)
+#define PADS_BANK0_SWD_SCHMITT_LSB _u(1)
#define PADS_BANK0_SWD_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_BANK0_SWD_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_BANK0_SWD_SLEWFAST_RESET _U(0x0)
-#define PADS_BANK0_SWD_SLEWFAST_BITS _U(0x00000001)
-#define PADS_BANK0_SWD_SLEWFAST_MSB _U(0)
-#define PADS_BANK0_SWD_SLEWFAST_LSB _U(0)
+#define PADS_BANK0_SWD_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_SWD_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_SWD_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_SWD_SLEWFAST_LSB _u(0)
#define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_PADS_BANK0_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h b/src/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h
index 5253e5d..b3a09e9 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h
@@ -16,36 +16,36 @@
// Description : Voltage select. Per bank control
// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5)
// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8)
-#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _U(0x00000000)
-#define PADS_QSPI_VOLTAGE_SELECT_BITS _U(0x00000001)
-#define PADS_QSPI_VOLTAGE_SELECT_RESET _U(0x00000000)
-#define PADS_QSPI_VOLTAGE_SELECT_MSB _U(0)
-#define PADS_QSPI_VOLTAGE_SELECT_LSB _U(0)
+#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000)
+#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001)
+#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000)
+#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0)
+#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0)
#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW"
-#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _U(0x0)
-#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _U(0x1)
+#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)
+#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SCLK
// Description : Pad control register
-#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _U(0x00000004)
-#define PADS_QSPI_GPIO_QSPI_SCLK_BITS _U(0x000000ff)
-#define PADS_QSPI_GPIO_QSPI_SCLK_RESET _U(0x00000056)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SCLK_BITS _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SCLK_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _U(0x00000080)
-#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _U(7)
-#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _U(7)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_IE
// Description : Input enable
-#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _U(0x00000040)
-#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _U(6)
-#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _U(6)
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE
@@ -54,69 +54,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _U(0x00000030)
-#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _U(5)
-#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _U(4)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW"
-#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE
// Description : Pull up enable
-#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _U(0x00000008)
-#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _U(3)
-#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _U(3)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE
// Description : Pull down enable
-#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _U(0x00000004)
-#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _U(2)
-#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _U(2)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _U(0x00000002)
-#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _U(1)
-#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _U(1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _U(0x00000001)
-#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _U(0)
-#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _U(0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD0
// Description : Pad control register
-#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _U(0x00000008)
-#define PADS_QSPI_GPIO_QSPI_SD0_BITS _U(0x000000ff)
-#define PADS_QSPI_GPIO_QSPI_SD0_RESET _U(0x00000052)
+#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD0_BITS _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SD0_RESET _u(0x00000052)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _U(0x00000080)
-#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _U(7)
-#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _U(7)
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_IE
// Description : Input enable
-#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _U(0x00000040)
-#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _U(6)
-#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _U(6)
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE
@@ -125,69 +125,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _U(0x00000030)
-#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _U(5)
-#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _U(4)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW"
-#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_PUE
// Description : Pull up enable
-#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _U(0x00000008)
-#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _U(3)
-#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _U(3)
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_PDE
// Description : Pull down enable
-#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _U(0x00000004)
-#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _U(2)
-#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _U(2)
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _U(0x00000002)
-#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _U(1)
-#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _U(1)
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _U(0x00000001)
-#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _U(0)
-#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _U(0)
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD1
// Description : Pad control register
-#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _U(0x0000000c)
-#define PADS_QSPI_GPIO_QSPI_SD1_BITS _U(0x000000ff)
-#define PADS_QSPI_GPIO_QSPI_SD1_RESET _U(0x00000052)
+#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c)
+#define PADS_QSPI_GPIO_QSPI_SD1_BITS _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SD1_RESET _u(0x00000052)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _U(0x00000080)
-#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _U(7)
-#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _U(7)
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_IE
// Description : Input enable
-#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _U(0x00000040)
-#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _U(6)
-#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _U(6)
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE
@@ -196,69 +196,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _U(0x00000030)
-#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _U(5)
-#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _U(4)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW"
-#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_PUE
// Description : Pull up enable
-#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _U(0x00000008)
-#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _U(3)
-#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _U(3)
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_PDE
// Description : Pull down enable
-#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _U(0x00000004)
-#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _U(2)
-#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _U(2)
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _U(0x00000002)
-#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _U(1)
-#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _U(1)
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _U(0x00000001)
-#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _U(0)
-#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _U(0)
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD2
// Description : Pad control register
-#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _U(0x00000010)
-#define PADS_QSPI_GPIO_QSPI_SD2_BITS _U(0x000000ff)
-#define PADS_QSPI_GPIO_QSPI_SD2_RESET _U(0x00000052)
+#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010)
+#define PADS_QSPI_GPIO_QSPI_SD2_BITS _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SD2_RESET _u(0x00000052)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _U(0x00000080)
-#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _U(7)
-#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _U(7)
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_IE
// Description : Input enable
-#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _U(0x00000040)
-#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _U(6)
-#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _U(6)
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE
@@ -267,69 +267,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _U(0x00000030)
-#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _U(5)
-#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _U(4)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW"
-#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_PUE
// Description : Pull up enable
-#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _U(0x00000008)
-#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _U(3)
-#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _U(3)
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_PDE
// Description : Pull down enable
-#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _U(0x00000004)
-#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _U(2)
-#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _U(2)
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _U(0x00000002)
-#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _U(1)
-#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _U(1)
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _U(0x00000001)
-#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _U(0)
-#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _U(0)
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD3
// Description : Pad control register
-#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _U(0x00000014)
-#define PADS_QSPI_GPIO_QSPI_SD3_BITS _U(0x000000ff)
-#define PADS_QSPI_GPIO_QSPI_SD3_RESET _U(0x00000052)
+#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014)
+#define PADS_QSPI_GPIO_QSPI_SD3_BITS _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SD3_RESET _u(0x00000052)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _U(0x00000080)
-#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _U(7)
-#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _U(7)
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_IE
// Description : Input enable
-#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _U(0x00000040)
-#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _U(6)
-#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _U(6)
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE
@@ -338,69 +338,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _U(0x00000030)
-#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _U(5)
-#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _U(4)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW"
-#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_PUE
// Description : Pull up enable
-#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _U(0x00000008)
-#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _U(3)
-#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _U(3)
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_PDE
// Description : Pull down enable
-#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _U(0x00000004)
-#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _U(2)
-#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _U(2)
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _U(0x00000002)
-#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _U(1)
-#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _U(1)
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _U(0x00000001)
-#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _U(0)
-#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _U(0)
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SS
// Description : Pad control register
-#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _U(0x00000018)
-#define PADS_QSPI_GPIO_QSPI_SS_BITS _U(0x000000ff)
-#define PADS_QSPI_GPIO_QSPI_SS_RESET _U(0x0000005a)
+#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018)
+#define PADS_QSPI_GPIO_QSPI_SS_BITS _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SS_RESET _u(0x0000005a)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_OD
// Description : Output disable. Has priority over output enable from
// peripherals
-#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _U(0x00000080)
-#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _U(7)
-#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _U(7)
+#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_IE
// Description : Input enable
-#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _U(0x00000040)
-#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _U(6)
-#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _U(6)
+#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE
@@ -409,46 +409,46 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
-#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _U(0x00000030)
-#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _U(5)
-#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _U(4)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW"
-#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _U(0x2)
-#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _U(0x3)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_PUE
// Description : Pull up enable
-#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _U(0x00000008)
-#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _U(3)
-#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _U(3)
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_PDE
// Description : Pull down enable
-#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _U(0x00000004)
-#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _U(2)
-#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _U(2)
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT
// Description : Enable schmitt trigger
-#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _U(0x1)
-#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _U(0x00000002)
-#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _U(1)
-#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _U(1)
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
-#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _U(0x0)
-#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _U(0x00000001)
-#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _U(0)
-#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _U(0)
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_PADS_QSPI_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pio.h b/src/rp2040/hardware_regs/include/hardware/regs/pio.h
index e21d8ea..8b4829f 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/pio.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/pio.h
@@ -14,9 +14,9 @@
// =============================================================================
// Register : PIO_CTRL
// Description : PIO control register
-#define PIO_CTRL_OFFSET _U(0x00000000)
-#define PIO_CTRL_BITS _U(0x00000fff)
-#define PIO_CTRL_RESET _U(0x00000000)
+#define PIO_CTRL_OFFSET _u(0x00000000)
+#define PIO_CTRL_BITS _u(0x00000fff)
+#define PIO_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_CTRL_CLKDIV_RESTART
// Description : Restart a state machine's clock divider from an initial phase
@@ -37,10 +37,10 @@
// state machine is running, and this is useful to resynchronise
// clock dividers after the divisors (SMx_CLKDIV) have been
// changed on-the-fly.
-#define PIO_CTRL_CLKDIV_RESTART_RESET _U(0x0)
-#define PIO_CTRL_CLKDIV_RESTART_BITS _U(0x00000f00)
-#define PIO_CTRL_CLKDIV_RESTART_MSB _U(11)
-#define PIO_CTRL_CLKDIV_RESTART_LSB _U(8)
+#define PIO_CTRL_CLKDIV_RESTART_RESET _u(0x0)
+#define PIO_CTRL_CLKDIV_RESTART_BITS _u(0x00000f00)
+#define PIO_CTRL_CLKDIV_RESTART_MSB _u(11)
+#define PIO_CTRL_CLKDIV_RESTART_LSB _u(8)
#define PIO_CTRL_CLKDIV_RESTART_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PIO_CTRL_SM_RESTART
@@ -52,10 +52,10 @@
// counter; the waiting-on-IRQ state; any stalled instruction
// written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left
// asserted due to OUT_STICKY.
-#define PIO_CTRL_SM_RESTART_RESET _U(0x0)
-#define PIO_CTRL_SM_RESTART_BITS _U(0x000000f0)
-#define PIO_CTRL_SM_RESTART_MSB _U(7)
-#define PIO_CTRL_SM_RESTART_LSB _U(4)
+#define PIO_CTRL_SM_RESTART_RESET _u(0x0)
+#define PIO_CTRL_SM_RESTART_BITS _u(0x000000f0)
+#define PIO_CTRL_SM_RESTART_MSB _u(7)
+#define PIO_CTRL_SM_RESTART_LSB _u(4)
#define PIO_CTRL_SM_RESTART_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PIO_CTRL_SM_ENABLE
@@ -64,63 +64,63 @@
// cease executing instructions, except those written directly to
// SMx_INSTR by the system. Multiple bits can be set/cleared at
// once to run/halt multiple state machines simultaneously.
-#define PIO_CTRL_SM_ENABLE_RESET _U(0x0)
-#define PIO_CTRL_SM_ENABLE_BITS _U(0x0000000f)
-#define PIO_CTRL_SM_ENABLE_MSB _U(3)
-#define PIO_CTRL_SM_ENABLE_LSB _U(0)
+#define PIO_CTRL_SM_ENABLE_RESET _u(0x0)
+#define PIO_CTRL_SM_ENABLE_BITS _u(0x0000000f)
+#define PIO_CTRL_SM_ENABLE_MSB _u(3)
+#define PIO_CTRL_SM_ENABLE_LSB _u(0)
#define PIO_CTRL_SM_ENABLE_ACCESS "RW"
// =============================================================================
// Register : PIO_FSTAT
// Description : FIFO status register
-#define PIO_FSTAT_OFFSET _U(0x00000004)
-#define PIO_FSTAT_BITS _U(0x0f0f0f0f)
-#define PIO_FSTAT_RESET _U(0x0f000f00)
+#define PIO_FSTAT_OFFSET _u(0x00000004)
+#define PIO_FSTAT_BITS _u(0x0f0f0f0f)
+#define PIO_FSTAT_RESET _u(0x0f000f00)
// -----------------------------------------------------------------------------
// Field : PIO_FSTAT_TXEMPTY
// Description : State machine TX FIFO is empty
-#define PIO_FSTAT_TXEMPTY_RESET _U(0xf)
-#define PIO_FSTAT_TXEMPTY_BITS _U(0x0f000000)
-#define PIO_FSTAT_TXEMPTY_MSB _U(27)
-#define PIO_FSTAT_TXEMPTY_LSB _U(24)
+#define PIO_FSTAT_TXEMPTY_RESET _u(0xf)
+#define PIO_FSTAT_TXEMPTY_BITS _u(0x0f000000)
+#define PIO_FSTAT_TXEMPTY_MSB _u(27)
+#define PIO_FSTAT_TXEMPTY_LSB _u(24)
#define PIO_FSTAT_TXEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FSTAT_TXFULL
// Description : State machine TX FIFO is full
-#define PIO_FSTAT_TXFULL_RESET _U(0x0)
-#define PIO_FSTAT_TXFULL_BITS _U(0x000f0000)
-#define PIO_FSTAT_TXFULL_MSB _U(19)
-#define PIO_FSTAT_TXFULL_LSB _U(16)
+#define PIO_FSTAT_TXFULL_RESET _u(0x0)
+#define PIO_FSTAT_TXFULL_BITS _u(0x000f0000)
+#define PIO_FSTAT_TXFULL_MSB _u(19)
+#define PIO_FSTAT_TXFULL_LSB _u(16)
#define PIO_FSTAT_TXFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FSTAT_RXEMPTY
// Description : State machine RX FIFO is empty
-#define PIO_FSTAT_RXEMPTY_RESET _U(0xf)
-#define PIO_FSTAT_RXEMPTY_BITS _U(0x00000f00)
-#define PIO_FSTAT_RXEMPTY_MSB _U(11)
-#define PIO_FSTAT_RXEMPTY_LSB _U(8)
+#define PIO_FSTAT_RXEMPTY_RESET _u(0xf)
+#define PIO_FSTAT_RXEMPTY_BITS _u(0x00000f00)
+#define PIO_FSTAT_RXEMPTY_MSB _u(11)
+#define PIO_FSTAT_RXEMPTY_LSB _u(8)
#define PIO_FSTAT_RXEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FSTAT_RXFULL
// Description : State machine RX FIFO is full
-#define PIO_FSTAT_RXFULL_RESET _U(0x0)
-#define PIO_FSTAT_RXFULL_BITS _U(0x0000000f)
-#define PIO_FSTAT_RXFULL_MSB _U(3)
-#define PIO_FSTAT_RXFULL_LSB _U(0)
+#define PIO_FSTAT_RXFULL_RESET _u(0x0)
+#define PIO_FSTAT_RXFULL_BITS _u(0x0000000f)
+#define PIO_FSTAT_RXFULL_MSB _u(3)
+#define PIO_FSTAT_RXFULL_LSB _u(0)
#define PIO_FSTAT_RXFULL_ACCESS "RO"
// =============================================================================
// Register : PIO_FDEBUG
// Description : FIFO debug register
-#define PIO_FDEBUG_OFFSET _U(0x00000008)
-#define PIO_FDEBUG_BITS _U(0x0f0f0f0f)
-#define PIO_FDEBUG_RESET _U(0x00000000)
+#define PIO_FDEBUG_OFFSET _u(0x00000008)
+#define PIO_FDEBUG_BITS _u(0x0f0f0f0f)
+#define PIO_FDEBUG_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_FDEBUG_TXSTALL
// Description : State machine has stalled on empty TX FIFO during a blocking
// PULL, or an OUT with autopull enabled. Write 1 to clear.
-#define PIO_FDEBUG_TXSTALL_RESET _U(0x0)
-#define PIO_FDEBUG_TXSTALL_BITS _U(0x0f000000)
-#define PIO_FDEBUG_TXSTALL_MSB _U(27)
-#define PIO_FDEBUG_TXSTALL_LSB _U(24)
+#define PIO_FDEBUG_TXSTALL_RESET _u(0x0)
+#define PIO_FDEBUG_TXSTALL_BITS _u(0x0f000000)
+#define PIO_FDEBUG_TXSTALL_MSB _u(27)
+#define PIO_FDEBUG_TXSTALL_LSB _u(24)
#define PIO_FDEBUG_TXSTALL_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PIO_FDEBUG_TXOVER
@@ -130,10 +130,10 @@
// data that the system attempted to write is dropped, so if this
// flag is set, your software has quite likely dropped some data
// on the floor.
-#define PIO_FDEBUG_TXOVER_RESET _U(0x0)
-#define PIO_FDEBUG_TXOVER_BITS _U(0x000f0000)
-#define PIO_FDEBUG_TXOVER_MSB _U(19)
-#define PIO_FDEBUG_TXOVER_LSB _U(16)
+#define PIO_FDEBUG_TXOVER_RESET _u(0x0)
+#define PIO_FDEBUG_TXOVER_BITS _u(0x000f0000)
+#define PIO_FDEBUG_TXOVER_MSB _u(19)
+#define PIO_FDEBUG_TXOVER_LSB _u(16)
#define PIO_FDEBUG_TXOVER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PIO_FDEBUG_RXUNDER
@@ -142,10 +142,10 @@
// perturb the state of the FIFO in any way, but the data returned
// by reading from an empty FIFO is undefined, so this flag
// generally only becomes set due to some kind of software error.
-#define PIO_FDEBUG_RXUNDER_RESET _U(0x0)
-#define PIO_FDEBUG_RXUNDER_BITS _U(0x00000f00)
-#define PIO_FDEBUG_RXUNDER_MSB _U(11)
-#define PIO_FDEBUG_RXUNDER_LSB _U(8)
+#define PIO_FDEBUG_RXUNDER_RESET _u(0x0)
+#define PIO_FDEBUG_RXUNDER_BITS _u(0x00000f00)
+#define PIO_FDEBUG_RXUNDER_MSB _u(11)
+#define PIO_FDEBUG_RXUNDER_LSB _u(8)
#define PIO_FDEBUG_RXUNDER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PIO_FDEBUG_RXSTALL
@@ -153,80 +153,80 @@
// PUSH, or an IN with autopush enabled. This flag is also set
// when a nonblocking PUSH to a full FIFO took place, in which
// case the state machine has dropped data. Write 1 to clear.
-#define PIO_FDEBUG_RXSTALL_RESET _U(0x0)
-#define PIO_FDEBUG_RXSTALL_BITS _U(0x0000000f)
-#define PIO_FDEBUG_RXSTALL_MSB _U(3)
-#define PIO_FDEBUG_RXSTALL_LSB _U(0)
+#define PIO_FDEBUG_RXSTALL_RESET _u(0x0)
+#define PIO_FDEBUG_RXSTALL_BITS _u(0x0000000f)
+#define PIO_FDEBUG_RXSTALL_MSB _u(3)
+#define PIO_FDEBUG_RXSTALL_LSB _u(0)
#define PIO_FDEBUG_RXSTALL_ACCESS "WC"
// =============================================================================
// Register : PIO_FLEVEL
// Description : FIFO levels
-#define PIO_FLEVEL_OFFSET _U(0x0000000c)
-#define PIO_FLEVEL_BITS _U(0xffffffff)
-#define PIO_FLEVEL_RESET _U(0x00000000)
+#define PIO_FLEVEL_OFFSET _u(0x0000000c)
+#define PIO_FLEVEL_BITS _u(0xffffffff)
+#define PIO_FLEVEL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_FLEVEL_RX3
// Description : None
-#define PIO_FLEVEL_RX3_RESET _U(0x0)
-#define PIO_FLEVEL_RX3_BITS _U(0xf0000000)
-#define PIO_FLEVEL_RX3_MSB _U(31)
-#define PIO_FLEVEL_RX3_LSB _U(28)
+#define PIO_FLEVEL_RX3_RESET _u(0x0)
+#define PIO_FLEVEL_RX3_BITS _u(0xf0000000)
+#define PIO_FLEVEL_RX3_MSB _u(31)
+#define PIO_FLEVEL_RX3_LSB _u(28)
#define PIO_FLEVEL_RX3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FLEVEL_TX3
// Description : None
-#define PIO_FLEVEL_TX3_RESET _U(0x0)
-#define PIO_FLEVEL_TX3_BITS _U(0x0f000000)
-#define PIO_FLEVEL_TX3_MSB _U(27)
-#define PIO_FLEVEL_TX3_LSB _U(24)
+#define PIO_FLEVEL_TX3_RESET _u(0x0)
+#define PIO_FLEVEL_TX3_BITS _u(0x0f000000)
+#define PIO_FLEVEL_TX3_MSB _u(27)
+#define PIO_FLEVEL_TX3_LSB _u(24)
#define PIO_FLEVEL_TX3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FLEVEL_RX2
// Description : None
-#define PIO_FLEVEL_RX2_RESET _U(0x0)
-#define PIO_FLEVEL_RX2_BITS _U(0x00f00000)
-#define PIO_FLEVEL_RX2_MSB _U(23)
-#define PIO_FLEVEL_RX2_LSB _U(20)
+#define PIO_FLEVEL_RX2_RESET _u(0x0)
+#define PIO_FLEVEL_RX2_BITS _u(0x00f00000)
+#define PIO_FLEVEL_RX2_MSB _u(23)
+#define PIO_FLEVEL_RX2_LSB _u(20)
#define PIO_FLEVEL_RX2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FLEVEL_TX2
// Description : None
-#define PIO_FLEVEL_TX2_RESET _U(0x0)
-#define PIO_FLEVEL_TX2_BITS _U(0x000f0000)
-#define PIO_FLEVEL_TX2_MSB _U(19)
-#define PIO_FLEVEL_TX2_LSB _U(16)
+#define PIO_FLEVEL_TX2_RESET _u(0x0)
+#define PIO_FLEVEL_TX2_BITS _u(0x000f0000)
+#define PIO_FLEVEL_TX2_MSB _u(19)
+#define PIO_FLEVEL_TX2_LSB _u(16)
#define PIO_FLEVEL_TX2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FLEVEL_RX1
// Description : None
-#define PIO_FLEVEL_RX1_RESET _U(0x0)
-#define PIO_FLEVEL_RX1_BITS _U(0x0000f000)
-#define PIO_FLEVEL_RX1_MSB _U(15)
-#define PIO_FLEVEL_RX1_LSB _U(12)
+#define PIO_FLEVEL_RX1_RESET _u(0x0)
+#define PIO_FLEVEL_RX1_BITS _u(0x0000f000)
+#define PIO_FLEVEL_RX1_MSB _u(15)
+#define PIO_FLEVEL_RX1_LSB _u(12)
#define PIO_FLEVEL_RX1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FLEVEL_TX1
// Description : None
-#define PIO_FLEVEL_TX1_RESET _U(0x0)
-#define PIO_FLEVEL_TX1_BITS _U(0x00000f00)
-#define PIO_FLEVEL_TX1_MSB _U(11)
-#define PIO_FLEVEL_TX1_LSB _U(8)
+#define PIO_FLEVEL_TX1_RESET _u(0x0)
+#define PIO_FLEVEL_TX1_BITS _u(0x00000f00)
+#define PIO_FLEVEL_TX1_MSB _u(11)
+#define PIO_FLEVEL_TX1_LSB _u(8)
#define PIO_FLEVEL_TX1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FLEVEL_RX0
// Description : None
-#define PIO_FLEVEL_RX0_RESET _U(0x0)
-#define PIO_FLEVEL_RX0_BITS _U(0x000000f0)
-#define PIO_FLEVEL_RX0_MSB _U(7)
-#define PIO_FLEVEL_RX0_LSB _U(4)
+#define PIO_FLEVEL_RX0_RESET _u(0x0)
+#define PIO_FLEVEL_RX0_BITS _u(0x000000f0)
+#define PIO_FLEVEL_RX0_MSB _u(7)
+#define PIO_FLEVEL_RX0_LSB _u(4)
#define PIO_FLEVEL_RX0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FLEVEL_TX0
// Description : None
-#define PIO_FLEVEL_TX0_RESET _U(0x0)
-#define PIO_FLEVEL_TX0_BITS _U(0x0000000f)
-#define PIO_FLEVEL_TX0_MSB _U(3)
-#define PIO_FLEVEL_TX0_LSB _U(0)
+#define PIO_FLEVEL_TX0_RESET _u(0x0)
+#define PIO_FLEVEL_TX0_BITS _u(0x0000000f)
+#define PIO_FLEVEL_TX0_MSB _u(3)
+#define PIO_FLEVEL_TX0_LSB _u(0)
#define PIO_FLEVEL_TX0_ACCESS "RO"
// =============================================================================
// Register : PIO_TXF0
@@ -234,11 +234,11 @@
// write pushes one word to the FIFO. Attempting to write to a
// full FIFO has no effect on the FIFO state or contents, and sets
// the sticky FDEBUG_TXOVER error flag for this FIFO.
-#define PIO_TXF0_OFFSET _U(0x00000010)
-#define PIO_TXF0_BITS _U(0xffffffff)
-#define PIO_TXF0_RESET _U(0x00000000)
-#define PIO_TXF0_MSB _U(31)
-#define PIO_TXF0_LSB _U(0)
+#define PIO_TXF0_OFFSET _u(0x00000010)
+#define PIO_TXF0_BITS _u(0xffffffff)
+#define PIO_TXF0_RESET _u(0x00000000)
+#define PIO_TXF0_MSB _u(31)
+#define PIO_TXF0_LSB _u(0)
#define PIO_TXF0_ACCESS "WF"
// =============================================================================
// Register : PIO_TXF1
@@ -246,11 +246,11 @@
// write pushes one word to the FIFO. Attempting to write to a
// full FIFO has no effect on the FIFO state or contents, and sets
// the sticky FDEBUG_TXOVER error flag for this FIFO.
-#define PIO_TXF1_OFFSET _U(0x00000014)
-#define PIO_TXF1_BITS _U(0xffffffff)
-#define PIO_TXF1_RESET _U(0x00000000)
-#define PIO_TXF1_MSB _U(31)
-#define PIO_TXF1_LSB _U(0)
+#define PIO_TXF1_OFFSET _u(0x00000014)
+#define PIO_TXF1_BITS _u(0xffffffff)
+#define PIO_TXF1_RESET _u(0x00000000)
+#define PIO_TXF1_MSB _u(31)
+#define PIO_TXF1_LSB _u(0)
#define PIO_TXF1_ACCESS "WF"
// =============================================================================
// Register : PIO_TXF2
@@ -258,11 +258,11 @@
// write pushes one word to the FIFO. Attempting to write to a
// full FIFO has no effect on the FIFO state or contents, and sets
// the sticky FDEBUG_TXOVER error flag for this FIFO.
-#define PIO_TXF2_OFFSET _U(0x00000018)
-#define PIO_TXF2_BITS _U(0xffffffff)
-#define PIO_TXF2_RESET _U(0x00000000)
-#define PIO_TXF2_MSB _U(31)
-#define PIO_TXF2_LSB _U(0)
+#define PIO_TXF2_OFFSET _u(0x00000018)
+#define PIO_TXF2_BITS _u(0xffffffff)
+#define PIO_TXF2_RESET _u(0x00000000)
+#define PIO_TXF2_MSB _u(31)
+#define PIO_TXF2_LSB _u(0)
#define PIO_TXF2_ACCESS "WF"
// =============================================================================
// Register : PIO_TXF3
@@ -270,11 +270,11 @@
// write pushes one word to the FIFO. Attempting to write to a
// full FIFO has no effect on the FIFO state or contents, and sets
// the sticky FDEBUG_TXOVER error flag for this FIFO.
-#define PIO_TXF3_OFFSET _U(0x0000001c)
-#define PIO_TXF3_BITS _U(0xffffffff)
-#define PIO_TXF3_RESET _U(0x00000000)
-#define PIO_TXF3_MSB _U(31)
-#define PIO_TXF3_LSB _U(0)
+#define PIO_TXF3_OFFSET _u(0x0000001c)
+#define PIO_TXF3_BITS _u(0xffffffff)
+#define PIO_TXF3_RESET _u(0x00000000)
+#define PIO_TXF3_MSB _u(31)
+#define PIO_TXF3_LSB _u(0)
#define PIO_TXF3_ACCESS "WF"
// =============================================================================
// Register : PIO_RXF0
@@ -283,11 +283,11 @@
// empty FIFO has no effect on the FIFO state, and sets the sticky
// FDEBUG_RXUNDER error flag for this FIFO. The data returned to
// the system on a read from an empty FIFO is undefined.
-#define PIO_RXF0_OFFSET _U(0x00000020)
-#define PIO_RXF0_BITS _U(0xffffffff)
+#define PIO_RXF0_OFFSET _u(0x00000020)
+#define PIO_RXF0_BITS _u(0xffffffff)
#define PIO_RXF0_RESET "-"
-#define PIO_RXF0_MSB _U(31)
-#define PIO_RXF0_LSB _U(0)
+#define PIO_RXF0_MSB _u(31)
+#define PIO_RXF0_LSB _u(0)
#define PIO_RXF0_ACCESS "RF"
// =============================================================================
// Register : PIO_RXF1
@@ -296,11 +296,11 @@
// empty FIFO has no effect on the FIFO state, and sets the sticky
// FDEBUG_RXUNDER error flag for this FIFO. The data returned to
// the system on a read from an empty FIFO is undefined.
-#define PIO_RXF1_OFFSET _U(0x00000024)
-#define PIO_RXF1_BITS _U(0xffffffff)
+#define PIO_RXF1_OFFSET _u(0x00000024)
+#define PIO_RXF1_BITS _u(0xffffffff)
#define PIO_RXF1_RESET "-"
-#define PIO_RXF1_MSB _U(31)
-#define PIO_RXF1_LSB _U(0)
+#define PIO_RXF1_MSB _u(31)
+#define PIO_RXF1_LSB _u(0)
#define PIO_RXF1_ACCESS "RF"
// =============================================================================
// Register : PIO_RXF2
@@ -309,11 +309,11 @@
// empty FIFO has no effect on the FIFO state, and sets the sticky
// FDEBUG_RXUNDER error flag for this FIFO. The data returned to
// the system on a read from an empty FIFO is undefined.
-#define PIO_RXF2_OFFSET _U(0x00000028)
-#define PIO_RXF2_BITS _U(0xffffffff)
+#define PIO_RXF2_OFFSET _u(0x00000028)
+#define PIO_RXF2_BITS _u(0xffffffff)
#define PIO_RXF2_RESET "-"
-#define PIO_RXF2_MSB _U(31)
-#define PIO_RXF2_LSB _U(0)
+#define PIO_RXF2_MSB _u(31)
+#define PIO_RXF2_LSB _u(0)
#define PIO_RXF2_ACCESS "RF"
// =============================================================================
// Register : PIO_RXF3
@@ -322,11 +322,11 @@
// empty FIFO has no effect on the FIFO state, and sets the sticky
// FDEBUG_RXUNDER error flag for this FIFO. The data returned to
// the system on a read from an empty FIFO is undefined.
-#define PIO_RXF3_OFFSET _U(0x0000002c)
-#define PIO_RXF3_BITS _U(0xffffffff)
+#define PIO_RXF3_OFFSET _u(0x0000002c)
+#define PIO_RXF3_BITS _u(0xffffffff)
#define PIO_RXF3_RESET "-"
-#define PIO_RXF3_MSB _U(31)
-#define PIO_RXF3_LSB _U(0)
+#define PIO_RXF3_MSB _u(31)
+#define PIO_RXF3_LSB _u(0)
#define PIO_RXF3_ACCESS "RF"
// =============================================================================
// Register : PIO_IRQ
@@ -340,11 +340,11 @@
// lower four of these flags are also routed out to system-level
// interrupt requests, alongside FIFO status interrupts -- see
// e.g. IRQ0_INTE.
-#define PIO_IRQ_OFFSET _U(0x00000030)
-#define PIO_IRQ_BITS _U(0x000000ff)
-#define PIO_IRQ_RESET _U(0x00000000)
-#define PIO_IRQ_MSB _U(7)
-#define PIO_IRQ_LSB _U(0)
+#define PIO_IRQ_OFFSET _u(0x00000030)
+#define PIO_IRQ_BITS _u(0x000000ff)
+#define PIO_IRQ_RESET _u(0x00000000)
+#define PIO_IRQ_MSB _u(7)
+#define PIO_IRQ_LSB _u(0)
#define PIO_IRQ_ACCESS "WC"
// =============================================================================
// Register : PIO_IRQ_FORCE
@@ -353,11 +353,11 @@
// writing here affects PIO internal state. INTF just asserts the
// processor-facing IRQ signal for testing ISRs, and is not
// visible to the state machines.
-#define PIO_IRQ_FORCE_OFFSET _U(0x00000034)
-#define PIO_IRQ_FORCE_BITS _U(0x000000ff)
-#define PIO_IRQ_FORCE_RESET _U(0x00000000)
-#define PIO_IRQ_FORCE_MSB _U(7)
-#define PIO_IRQ_FORCE_LSB _U(0)
+#define PIO_IRQ_FORCE_OFFSET _u(0x00000034)
+#define PIO_IRQ_FORCE_BITS _u(0x000000ff)
+#define PIO_IRQ_FORCE_RESET _u(0x00000000)
+#define PIO_IRQ_FORCE_MSB _u(7)
+#define PIO_IRQ_FORCE_LSB _u(0)
#define PIO_IRQ_FORCE_ACCESS "WF"
// =============================================================================
// Register : PIO_INPUT_SYNC_BYPASS
@@ -369,31 +369,31 @@
// 0 -> input is synchronized (default)
// 1 -> synchronizer is bypassed
// If in doubt, leave this register as all zeroes.
-#define PIO_INPUT_SYNC_BYPASS_OFFSET _U(0x00000038)
-#define PIO_INPUT_SYNC_BYPASS_BITS _U(0xffffffff)
-#define PIO_INPUT_SYNC_BYPASS_RESET _U(0x00000000)
-#define PIO_INPUT_SYNC_BYPASS_MSB _U(31)
-#define PIO_INPUT_SYNC_BYPASS_LSB _U(0)
+#define PIO_INPUT_SYNC_BYPASS_OFFSET _u(0x00000038)
+#define PIO_INPUT_SYNC_BYPASS_BITS _u(0xffffffff)
+#define PIO_INPUT_SYNC_BYPASS_RESET _u(0x00000000)
+#define PIO_INPUT_SYNC_BYPASS_MSB _u(31)
+#define PIO_INPUT_SYNC_BYPASS_LSB _u(0)
#define PIO_INPUT_SYNC_BYPASS_ACCESS "RW"
// =============================================================================
// Register : PIO_DBG_PADOUT
// Description : Read to sample the pad output values PIO is currently driving
// to the GPIOs.
-#define PIO_DBG_PADOUT_OFFSET _U(0x0000003c)
-#define PIO_DBG_PADOUT_BITS _U(0xffffffff)
-#define PIO_DBG_PADOUT_RESET _U(0x00000000)
-#define PIO_DBG_PADOUT_MSB _U(31)
-#define PIO_DBG_PADOUT_LSB _U(0)
+#define PIO_DBG_PADOUT_OFFSET _u(0x0000003c)
+#define PIO_DBG_PADOUT_BITS _u(0xffffffff)
+#define PIO_DBG_PADOUT_RESET _u(0x00000000)
+#define PIO_DBG_PADOUT_MSB _u(31)
+#define PIO_DBG_PADOUT_LSB _u(0)
#define PIO_DBG_PADOUT_ACCESS "RO"
// =============================================================================
// Register : PIO_DBG_PADOE
// Description : Read to sample the pad output enables (direction) PIO is
// currently driving to the GPIOs.
-#define PIO_DBG_PADOE_OFFSET _U(0x00000040)
-#define PIO_DBG_PADOE_BITS _U(0xffffffff)
-#define PIO_DBG_PADOE_RESET _U(0x00000000)
-#define PIO_DBG_PADOE_MSB _U(31)
-#define PIO_DBG_PADOE_LSB _U(0)
+#define PIO_DBG_PADOE_OFFSET _u(0x00000040)
+#define PIO_DBG_PADOE_BITS _u(0xffffffff)
+#define PIO_DBG_PADOE_RESET _u(0x00000000)
+#define PIO_DBG_PADOE_MSB _u(31)
+#define PIO_DBG_PADOE_LSB _u(0)
#define PIO_DBG_PADOE_ACCESS "RO"
// =============================================================================
// Register : PIO_DBG_CFGINFO
@@ -401,26 +401,26 @@
// chip products.
// These should be provided in the chip datasheet, but are also
// exposed here.
-#define PIO_DBG_CFGINFO_OFFSET _U(0x00000044)
-#define PIO_DBG_CFGINFO_BITS _U(0x003f0f3f)
-#define PIO_DBG_CFGINFO_RESET _U(0x00000000)
+#define PIO_DBG_CFGINFO_OFFSET _u(0x00000044)
+#define PIO_DBG_CFGINFO_BITS _u(0x003f0f3f)
+#define PIO_DBG_CFGINFO_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_DBG_CFGINFO_IMEM_SIZE
// Description : The size of the instruction memory, measured in units of one
// instruction
#define PIO_DBG_CFGINFO_IMEM_SIZE_RESET "-"
-#define PIO_DBG_CFGINFO_IMEM_SIZE_BITS _U(0x003f0000)
-#define PIO_DBG_CFGINFO_IMEM_SIZE_MSB _U(21)
-#define PIO_DBG_CFGINFO_IMEM_SIZE_LSB _U(16)
+#define PIO_DBG_CFGINFO_IMEM_SIZE_BITS _u(0x003f0000)
+#define PIO_DBG_CFGINFO_IMEM_SIZE_MSB _u(21)
+#define PIO_DBG_CFGINFO_IMEM_SIZE_LSB _u(16)
#define PIO_DBG_CFGINFO_IMEM_SIZE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_DBG_CFGINFO_SM_COUNT
// Description : The number of state machines this PIO instance is equipped
// with.
#define PIO_DBG_CFGINFO_SM_COUNT_RESET "-"
-#define PIO_DBG_CFGINFO_SM_COUNT_BITS _U(0x00000f00)
-#define PIO_DBG_CFGINFO_SM_COUNT_MSB _U(11)
-#define PIO_DBG_CFGINFO_SM_COUNT_LSB _U(8)
+#define PIO_DBG_CFGINFO_SM_COUNT_BITS _u(0x00000f00)
+#define PIO_DBG_CFGINFO_SM_COUNT_MSB _u(11)
+#define PIO_DBG_CFGINFO_SM_COUNT_LSB _u(8)
#define PIO_DBG_CFGINFO_SM_COUNT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_DBG_CFGINFO_FIFO_DEPTH
@@ -428,338 +428,338 @@
// Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double
// this depth.
#define PIO_DBG_CFGINFO_FIFO_DEPTH_RESET "-"
-#define PIO_DBG_CFGINFO_FIFO_DEPTH_BITS _U(0x0000003f)
-#define PIO_DBG_CFGINFO_FIFO_DEPTH_MSB _U(5)
-#define PIO_DBG_CFGINFO_FIFO_DEPTH_LSB _U(0)
+#define PIO_DBG_CFGINFO_FIFO_DEPTH_BITS _u(0x0000003f)
+#define PIO_DBG_CFGINFO_FIFO_DEPTH_MSB _u(5)
+#define PIO_DBG_CFGINFO_FIFO_DEPTH_LSB _u(0)
#define PIO_DBG_CFGINFO_FIFO_DEPTH_ACCESS "RO"
// =============================================================================
// Register : PIO_INSTR_MEM0
// Description : Write-only access to instruction memory location 0
-#define PIO_INSTR_MEM0_OFFSET _U(0x00000048)
-#define PIO_INSTR_MEM0_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM0_RESET _U(0x00000000)
-#define PIO_INSTR_MEM0_MSB _U(15)
-#define PIO_INSTR_MEM0_LSB _U(0)
+#define PIO_INSTR_MEM0_OFFSET _u(0x00000048)
+#define PIO_INSTR_MEM0_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM0_RESET _u(0x00000000)
+#define PIO_INSTR_MEM0_MSB _u(15)
+#define PIO_INSTR_MEM0_LSB _u(0)
#define PIO_INSTR_MEM0_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM1
// Description : Write-only access to instruction memory location 1
-#define PIO_INSTR_MEM1_OFFSET _U(0x0000004c)
-#define PIO_INSTR_MEM1_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM1_RESET _U(0x00000000)
-#define PIO_INSTR_MEM1_MSB _U(15)
-#define PIO_INSTR_MEM1_LSB _U(0)
+#define PIO_INSTR_MEM1_OFFSET _u(0x0000004c)
+#define PIO_INSTR_MEM1_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM1_RESET _u(0x00000000)
+#define PIO_INSTR_MEM1_MSB _u(15)
+#define PIO_INSTR_MEM1_LSB _u(0)
#define PIO_INSTR_MEM1_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM2
// Description : Write-only access to instruction memory location 2
-#define PIO_INSTR_MEM2_OFFSET _U(0x00000050)
-#define PIO_INSTR_MEM2_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM2_RESET _U(0x00000000)
-#define PIO_INSTR_MEM2_MSB _U(15)
-#define PIO_INSTR_MEM2_LSB _U(0)
+#define PIO_INSTR_MEM2_OFFSET _u(0x00000050)
+#define PIO_INSTR_MEM2_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM2_RESET _u(0x00000000)
+#define PIO_INSTR_MEM2_MSB _u(15)
+#define PIO_INSTR_MEM2_LSB _u(0)
#define PIO_INSTR_MEM2_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM3
// Description : Write-only access to instruction memory location 3
-#define PIO_INSTR_MEM3_OFFSET _U(0x00000054)
-#define PIO_INSTR_MEM3_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM3_RESET _U(0x00000000)
-#define PIO_INSTR_MEM3_MSB _U(15)
-#define PIO_INSTR_MEM3_LSB _U(0)
+#define PIO_INSTR_MEM3_OFFSET _u(0x00000054)
+#define PIO_INSTR_MEM3_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM3_RESET _u(0x00000000)
+#define PIO_INSTR_MEM3_MSB _u(15)
+#define PIO_INSTR_MEM3_LSB _u(0)
#define PIO_INSTR_MEM3_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM4
// Description : Write-only access to instruction memory location 4
-#define PIO_INSTR_MEM4_OFFSET _U(0x00000058)
-#define PIO_INSTR_MEM4_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM4_RESET _U(0x00000000)
-#define PIO_INSTR_MEM4_MSB _U(15)
-#define PIO_INSTR_MEM4_LSB _U(0)
+#define PIO_INSTR_MEM4_OFFSET _u(0x00000058)
+#define PIO_INSTR_MEM4_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM4_RESET _u(0x00000000)
+#define PIO_INSTR_MEM4_MSB _u(15)
+#define PIO_INSTR_MEM4_LSB _u(0)
#define PIO_INSTR_MEM4_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM5
// Description : Write-only access to instruction memory location 5
-#define PIO_INSTR_MEM5_OFFSET _U(0x0000005c)
-#define PIO_INSTR_MEM5_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM5_RESET _U(0x00000000)
-#define PIO_INSTR_MEM5_MSB _U(15)
-#define PIO_INSTR_MEM5_LSB _U(0)
+#define PIO_INSTR_MEM5_OFFSET _u(0x0000005c)
+#define PIO_INSTR_MEM5_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM5_RESET _u(0x00000000)
+#define PIO_INSTR_MEM5_MSB _u(15)
+#define PIO_INSTR_MEM5_LSB _u(0)
#define PIO_INSTR_MEM5_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM6
// Description : Write-only access to instruction memory location 6
-#define PIO_INSTR_MEM6_OFFSET _U(0x00000060)
-#define PIO_INSTR_MEM6_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM6_RESET _U(0x00000000)
-#define PIO_INSTR_MEM6_MSB _U(15)
-#define PIO_INSTR_MEM6_LSB _U(0)
+#define PIO_INSTR_MEM6_OFFSET _u(0x00000060)
+#define PIO_INSTR_MEM6_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM6_RESET _u(0x00000000)
+#define PIO_INSTR_MEM6_MSB _u(15)
+#define PIO_INSTR_MEM6_LSB _u(0)
#define PIO_INSTR_MEM6_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM7
// Description : Write-only access to instruction memory location 7
-#define PIO_INSTR_MEM7_OFFSET _U(0x00000064)
-#define PIO_INSTR_MEM7_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM7_RESET _U(0x00000000)
-#define PIO_INSTR_MEM7_MSB _U(15)
-#define PIO_INSTR_MEM7_LSB _U(0)
+#define PIO_INSTR_MEM7_OFFSET _u(0x00000064)
+#define PIO_INSTR_MEM7_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM7_RESET _u(0x00000000)
+#define PIO_INSTR_MEM7_MSB _u(15)
+#define PIO_INSTR_MEM7_LSB _u(0)
#define PIO_INSTR_MEM7_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM8
// Description : Write-only access to instruction memory location 8
-#define PIO_INSTR_MEM8_OFFSET _U(0x00000068)
-#define PIO_INSTR_MEM8_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM8_RESET _U(0x00000000)
-#define PIO_INSTR_MEM8_MSB _U(15)
-#define PIO_INSTR_MEM8_LSB _U(0)
+#define PIO_INSTR_MEM8_OFFSET _u(0x00000068)
+#define PIO_INSTR_MEM8_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM8_RESET _u(0x00000000)
+#define PIO_INSTR_MEM8_MSB _u(15)
+#define PIO_INSTR_MEM8_LSB _u(0)
#define PIO_INSTR_MEM8_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM9
// Description : Write-only access to instruction memory location 9
-#define PIO_INSTR_MEM9_OFFSET _U(0x0000006c)
-#define PIO_INSTR_MEM9_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM9_RESET _U(0x00000000)
-#define PIO_INSTR_MEM9_MSB _U(15)
-#define PIO_INSTR_MEM9_LSB _U(0)
+#define PIO_INSTR_MEM9_OFFSET _u(0x0000006c)
+#define PIO_INSTR_MEM9_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM9_RESET _u(0x00000000)
+#define PIO_INSTR_MEM9_MSB _u(15)
+#define PIO_INSTR_MEM9_LSB _u(0)
#define PIO_INSTR_MEM9_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM10
// Description : Write-only access to instruction memory location 10
-#define PIO_INSTR_MEM10_OFFSET _U(0x00000070)
-#define PIO_INSTR_MEM10_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM10_RESET _U(0x00000000)
-#define PIO_INSTR_MEM10_MSB _U(15)
-#define PIO_INSTR_MEM10_LSB _U(0)
+#define PIO_INSTR_MEM10_OFFSET _u(0x00000070)
+#define PIO_INSTR_MEM10_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM10_RESET _u(0x00000000)
+#define PIO_INSTR_MEM10_MSB _u(15)
+#define PIO_INSTR_MEM10_LSB _u(0)
#define PIO_INSTR_MEM10_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM11
// Description : Write-only access to instruction memory location 11
-#define PIO_INSTR_MEM11_OFFSET _U(0x00000074)
-#define PIO_INSTR_MEM11_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM11_RESET _U(0x00000000)
-#define PIO_INSTR_MEM11_MSB _U(15)
-#define PIO_INSTR_MEM11_LSB _U(0)
+#define PIO_INSTR_MEM11_OFFSET _u(0x00000074)
+#define PIO_INSTR_MEM11_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM11_RESET _u(0x00000000)
+#define PIO_INSTR_MEM11_MSB _u(15)
+#define PIO_INSTR_MEM11_LSB _u(0)
#define PIO_INSTR_MEM11_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM12
// Description : Write-only access to instruction memory location 12
-#define PIO_INSTR_MEM12_OFFSET _U(0x00000078)
-#define PIO_INSTR_MEM12_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM12_RESET _U(0x00000000)
-#define PIO_INSTR_MEM12_MSB _U(15)
-#define PIO_INSTR_MEM12_LSB _U(0)
+#define PIO_INSTR_MEM12_OFFSET _u(0x00000078)
+#define PIO_INSTR_MEM12_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM12_RESET _u(0x00000000)
+#define PIO_INSTR_MEM12_MSB _u(15)
+#define PIO_INSTR_MEM12_LSB _u(0)
#define PIO_INSTR_MEM12_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM13
// Description : Write-only access to instruction memory location 13
-#define PIO_INSTR_MEM13_OFFSET _U(0x0000007c)
-#define PIO_INSTR_MEM13_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM13_RESET _U(0x00000000)
-#define PIO_INSTR_MEM13_MSB _U(15)
-#define PIO_INSTR_MEM13_LSB _U(0)
+#define PIO_INSTR_MEM13_OFFSET _u(0x0000007c)
+#define PIO_INSTR_MEM13_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM13_RESET _u(0x00000000)
+#define PIO_INSTR_MEM13_MSB _u(15)
+#define PIO_INSTR_MEM13_LSB _u(0)
#define PIO_INSTR_MEM13_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM14
// Description : Write-only access to instruction memory location 14
-#define PIO_INSTR_MEM14_OFFSET _U(0x00000080)
-#define PIO_INSTR_MEM14_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM14_RESET _U(0x00000000)
-#define PIO_INSTR_MEM14_MSB _U(15)
-#define PIO_INSTR_MEM14_LSB _U(0)
+#define PIO_INSTR_MEM14_OFFSET _u(0x00000080)
+#define PIO_INSTR_MEM14_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM14_RESET _u(0x00000000)
+#define PIO_INSTR_MEM14_MSB _u(15)
+#define PIO_INSTR_MEM14_LSB _u(0)
#define PIO_INSTR_MEM14_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM15
// Description : Write-only access to instruction memory location 15
-#define PIO_INSTR_MEM15_OFFSET _U(0x00000084)
-#define PIO_INSTR_MEM15_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM15_RESET _U(0x00000000)
-#define PIO_INSTR_MEM15_MSB _U(15)
-#define PIO_INSTR_MEM15_LSB _U(0)
+#define PIO_INSTR_MEM15_OFFSET _u(0x00000084)
+#define PIO_INSTR_MEM15_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM15_RESET _u(0x00000000)
+#define PIO_INSTR_MEM15_MSB _u(15)
+#define PIO_INSTR_MEM15_LSB _u(0)
#define PIO_INSTR_MEM15_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM16
// Description : Write-only access to instruction memory location 16
-#define PIO_INSTR_MEM16_OFFSET _U(0x00000088)
-#define PIO_INSTR_MEM16_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM16_RESET _U(0x00000000)
-#define PIO_INSTR_MEM16_MSB _U(15)
-#define PIO_INSTR_MEM16_LSB _U(0)
+#define PIO_INSTR_MEM16_OFFSET _u(0x00000088)
+#define PIO_INSTR_MEM16_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM16_RESET _u(0x00000000)
+#define PIO_INSTR_MEM16_MSB _u(15)
+#define PIO_INSTR_MEM16_LSB _u(0)
#define PIO_INSTR_MEM16_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM17
// Description : Write-only access to instruction memory location 17
-#define PIO_INSTR_MEM17_OFFSET _U(0x0000008c)
-#define PIO_INSTR_MEM17_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM17_RESET _U(0x00000000)
-#define PIO_INSTR_MEM17_MSB _U(15)
-#define PIO_INSTR_MEM17_LSB _U(0)
+#define PIO_INSTR_MEM17_OFFSET _u(0x0000008c)
+#define PIO_INSTR_MEM17_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM17_RESET _u(0x00000000)
+#define PIO_INSTR_MEM17_MSB _u(15)
+#define PIO_INSTR_MEM17_LSB _u(0)
#define PIO_INSTR_MEM17_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM18
// Description : Write-only access to instruction memory location 18
-#define PIO_INSTR_MEM18_OFFSET _U(0x00000090)
-#define PIO_INSTR_MEM18_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM18_RESET _U(0x00000000)
-#define PIO_INSTR_MEM18_MSB _U(15)
-#define PIO_INSTR_MEM18_LSB _U(0)
+#define PIO_INSTR_MEM18_OFFSET _u(0x00000090)
+#define PIO_INSTR_MEM18_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM18_RESET _u(0x00000000)
+#define PIO_INSTR_MEM18_MSB _u(15)
+#define PIO_INSTR_MEM18_LSB _u(0)
#define PIO_INSTR_MEM18_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM19
// Description : Write-only access to instruction memory location 19
-#define PIO_INSTR_MEM19_OFFSET _U(0x00000094)
-#define PIO_INSTR_MEM19_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM19_RESET _U(0x00000000)
-#define PIO_INSTR_MEM19_MSB _U(15)
-#define PIO_INSTR_MEM19_LSB _U(0)
+#define PIO_INSTR_MEM19_OFFSET _u(0x00000094)
+#define PIO_INSTR_MEM19_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM19_RESET _u(0x00000000)
+#define PIO_INSTR_MEM19_MSB _u(15)
+#define PIO_INSTR_MEM19_LSB _u(0)
#define PIO_INSTR_MEM19_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM20
// Description : Write-only access to instruction memory location 20
-#define PIO_INSTR_MEM20_OFFSET _U(0x00000098)
-#define PIO_INSTR_MEM20_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM20_RESET _U(0x00000000)
-#define PIO_INSTR_MEM20_MSB _U(15)
-#define PIO_INSTR_MEM20_LSB _U(0)
+#define PIO_INSTR_MEM20_OFFSET _u(0x00000098)
+#define PIO_INSTR_MEM20_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM20_RESET _u(0x00000000)
+#define PIO_INSTR_MEM20_MSB _u(15)
+#define PIO_INSTR_MEM20_LSB _u(0)
#define PIO_INSTR_MEM20_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM21
// Description : Write-only access to instruction memory location 21
-#define PIO_INSTR_MEM21_OFFSET _U(0x0000009c)
-#define PIO_INSTR_MEM21_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM21_RESET _U(0x00000000)
-#define PIO_INSTR_MEM21_MSB _U(15)
-#define PIO_INSTR_MEM21_LSB _U(0)
+#define PIO_INSTR_MEM21_OFFSET _u(0x0000009c)
+#define PIO_INSTR_MEM21_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM21_RESET _u(0x00000000)
+#define PIO_INSTR_MEM21_MSB _u(15)
+#define PIO_INSTR_MEM21_LSB _u(0)
#define PIO_INSTR_MEM21_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM22
// Description : Write-only access to instruction memory location 22
-#define PIO_INSTR_MEM22_OFFSET _U(0x000000a0)
-#define PIO_INSTR_MEM22_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM22_RESET _U(0x00000000)
-#define PIO_INSTR_MEM22_MSB _U(15)
-#define PIO_INSTR_MEM22_LSB _U(0)
+#define PIO_INSTR_MEM22_OFFSET _u(0x000000a0)
+#define PIO_INSTR_MEM22_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM22_RESET _u(0x00000000)
+#define PIO_INSTR_MEM22_MSB _u(15)
+#define PIO_INSTR_MEM22_LSB _u(0)
#define PIO_INSTR_MEM22_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM23
// Description : Write-only access to instruction memory location 23
-#define PIO_INSTR_MEM23_OFFSET _U(0x000000a4)
-#define PIO_INSTR_MEM23_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM23_RESET _U(0x00000000)
-#define PIO_INSTR_MEM23_MSB _U(15)
-#define PIO_INSTR_MEM23_LSB _U(0)
+#define PIO_INSTR_MEM23_OFFSET _u(0x000000a4)
+#define PIO_INSTR_MEM23_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM23_RESET _u(0x00000000)
+#define PIO_INSTR_MEM23_MSB _u(15)
+#define PIO_INSTR_MEM23_LSB _u(0)
#define PIO_INSTR_MEM23_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM24
// Description : Write-only access to instruction memory location 24
-#define PIO_INSTR_MEM24_OFFSET _U(0x000000a8)
-#define PIO_INSTR_MEM24_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM24_RESET _U(0x00000000)
-#define PIO_INSTR_MEM24_MSB _U(15)
-#define PIO_INSTR_MEM24_LSB _U(0)
+#define PIO_INSTR_MEM24_OFFSET _u(0x000000a8)
+#define PIO_INSTR_MEM24_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM24_RESET _u(0x00000000)
+#define PIO_INSTR_MEM24_MSB _u(15)
+#define PIO_INSTR_MEM24_LSB _u(0)
#define PIO_INSTR_MEM24_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM25
// Description : Write-only access to instruction memory location 25
-#define PIO_INSTR_MEM25_OFFSET _U(0x000000ac)
-#define PIO_INSTR_MEM25_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM25_RESET _U(0x00000000)
-#define PIO_INSTR_MEM25_MSB _U(15)
-#define PIO_INSTR_MEM25_LSB _U(0)
+#define PIO_INSTR_MEM25_OFFSET _u(0x000000ac)
+#define PIO_INSTR_MEM25_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM25_RESET _u(0x00000000)
+#define PIO_INSTR_MEM25_MSB _u(15)
+#define PIO_INSTR_MEM25_LSB _u(0)
#define PIO_INSTR_MEM25_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM26
// Description : Write-only access to instruction memory location 26
-#define PIO_INSTR_MEM26_OFFSET _U(0x000000b0)
-#define PIO_INSTR_MEM26_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM26_RESET _U(0x00000000)
-#define PIO_INSTR_MEM26_MSB _U(15)
-#define PIO_INSTR_MEM26_LSB _U(0)
+#define PIO_INSTR_MEM26_OFFSET _u(0x000000b0)
+#define PIO_INSTR_MEM26_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM26_RESET _u(0x00000000)
+#define PIO_INSTR_MEM26_MSB _u(15)
+#define PIO_INSTR_MEM26_LSB _u(0)
#define PIO_INSTR_MEM26_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM27
// Description : Write-only access to instruction memory location 27
-#define PIO_INSTR_MEM27_OFFSET _U(0x000000b4)
-#define PIO_INSTR_MEM27_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM27_RESET _U(0x00000000)
-#define PIO_INSTR_MEM27_MSB _U(15)
-#define PIO_INSTR_MEM27_LSB _U(0)
+#define PIO_INSTR_MEM27_OFFSET _u(0x000000b4)
+#define PIO_INSTR_MEM27_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM27_RESET _u(0x00000000)
+#define PIO_INSTR_MEM27_MSB _u(15)
+#define PIO_INSTR_MEM27_LSB _u(0)
#define PIO_INSTR_MEM27_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM28
// Description : Write-only access to instruction memory location 28
-#define PIO_INSTR_MEM28_OFFSET _U(0x000000b8)
-#define PIO_INSTR_MEM28_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM28_RESET _U(0x00000000)
-#define PIO_INSTR_MEM28_MSB _U(15)
-#define PIO_INSTR_MEM28_LSB _U(0)
+#define PIO_INSTR_MEM28_OFFSET _u(0x000000b8)
+#define PIO_INSTR_MEM28_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM28_RESET _u(0x00000000)
+#define PIO_INSTR_MEM28_MSB _u(15)
+#define PIO_INSTR_MEM28_LSB _u(0)
#define PIO_INSTR_MEM28_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM29
// Description : Write-only access to instruction memory location 29
-#define PIO_INSTR_MEM29_OFFSET _U(0x000000bc)
-#define PIO_INSTR_MEM29_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM29_RESET _U(0x00000000)
-#define PIO_INSTR_MEM29_MSB _U(15)
-#define PIO_INSTR_MEM29_LSB _U(0)
+#define PIO_INSTR_MEM29_OFFSET _u(0x000000bc)
+#define PIO_INSTR_MEM29_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM29_RESET _u(0x00000000)
+#define PIO_INSTR_MEM29_MSB _u(15)
+#define PIO_INSTR_MEM29_LSB _u(0)
#define PIO_INSTR_MEM29_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM30
// Description : Write-only access to instruction memory location 30
-#define PIO_INSTR_MEM30_OFFSET _U(0x000000c0)
-#define PIO_INSTR_MEM30_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM30_RESET _U(0x00000000)
-#define PIO_INSTR_MEM30_MSB _U(15)
-#define PIO_INSTR_MEM30_LSB _U(0)
+#define PIO_INSTR_MEM30_OFFSET _u(0x000000c0)
+#define PIO_INSTR_MEM30_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM30_RESET _u(0x00000000)
+#define PIO_INSTR_MEM30_MSB _u(15)
+#define PIO_INSTR_MEM30_LSB _u(0)
#define PIO_INSTR_MEM30_ACCESS "WO"
// =============================================================================
// Register : PIO_INSTR_MEM31
// Description : Write-only access to instruction memory location 31
-#define PIO_INSTR_MEM31_OFFSET _U(0x000000c4)
-#define PIO_INSTR_MEM31_BITS _U(0x0000ffff)
-#define PIO_INSTR_MEM31_RESET _U(0x00000000)
-#define PIO_INSTR_MEM31_MSB _U(15)
-#define PIO_INSTR_MEM31_LSB _U(0)
+#define PIO_INSTR_MEM31_OFFSET _u(0x000000c4)
+#define PIO_INSTR_MEM31_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM31_RESET _u(0x00000000)
+#define PIO_INSTR_MEM31_MSB _u(15)
+#define PIO_INSTR_MEM31_LSB _u(0)
#define PIO_INSTR_MEM31_ACCESS "WO"
// =============================================================================
// Register : PIO_SM0_CLKDIV
// Description : Clock divisor register for state machine 0
// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
-#define PIO_SM0_CLKDIV_OFFSET _U(0x000000c8)
-#define PIO_SM0_CLKDIV_BITS _U(0xffffff00)
-#define PIO_SM0_CLKDIV_RESET _U(0x00010000)
+#define PIO_SM0_CLKDIV_OFFSET _u(0x000000c8)
+#define PIO_SM0_CLKDIV_BITS _u(0xffffff00)
+#define PIO_SM0_CLKDIV_RESET _u(0x00010000)
// -----------------------------------------------------------------------------
// Field : PIO_SM0_CLKDIV_INT
// Description : Effective frequency is sysclk/(int + frac/256).
// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also
// be 0.
-#define PIO_SM0_CLKDIV_INT_RESET _U(0x0001)
-#define PIO_SM0_CLKDIV_INT_BITS _U(0xffff0000)
-#define PIO_SM0_CLKDIV_INT_MSB _U(31)
-#define PIO_SM0_CLKDIV_INT_LSB _U(16)
+#define PIO_SM0_CLKDIV_INT_RESET _u(0x0001)
+#define PIO_SM0_CLKDIV_INT_BITS _u(0xffff0000)
+#define PIO_SM0_CLKDIV_INT_MSB _u(31)
+#define PIO_SM0_CLKDIV_INT_LSB _u(16)
#define PIO_SM0_CLKDIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_CLKDIV_FRAC
// Description : Fractional part of clock divisor
-#define PIO_SM0_CLKDIV_FRAC_RESET _U(0x00)
-#define PIO_SM0_CLKDIV_FRAC_BITS _U(0x0000ff00)
-#define PIO_SM0_CLKDIV_FRAC_MSB _U(15)
-#define PIO_SM0_CLKDIV_FRAC_LSB _U(8)
+#define PIO_SM0_CLKDIV_FRAC_RESET _u(0x00)
+#define PIO_SM0_CLKDIV_FRAC_BITS _u(0x0000ff00)
+#define PIO_SM0_CLKDIV_FRAC_MSB _u(15)
+#define PIO_SM0_CLKDIV_FRAC_LSB _u(8)
#define PIO_SM0_CLKDIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : PIO_SM0_EXECCTRL
// Description : Execution/behavioural settings for state machine 0
-#define PIO_SM0_EXECCTRL_OFFSET _U(0x000000cc)
-#define PIO_SM0_EXECCTRL_BITS _U(0xffffff9f)
-#define PIO_SM0_EXECCTRL_RESET _U(0x0001f000)
+#define PIO_SM0_EXECCTRL_OFFSET _u(0x000000cc)
+#define PIO_SM0_EXECCTRL_BITS _u(0xffffff9f)
+#define PIO_SM0_EXECCTRL_RESET _u(0x0001f000)
// -----------------------------------------------------------------------------
// Field : PIO_SM0_EXECCTRL_EXEC_STALLED
// Description : If 1, an instruction written to SMx_INSTR is stalled, and
// latched by the state machine. Will clear to 0 once this
// instruction completes.
-#define PIO_SM0_EXECCTRL_EXEC_STALLED_RESET _U(0x0)
-#define PIO_SM0_EXECCTRL_EXEC_STALLED_BITS _U(0x80000000)
-#define PIO_SM0_EXECCTRL_EXEC_STALLED_MSB _U(31)
-#define PIO_SM0_EXECCTRL_EXEC_STALLED_LSB _U(31)
+#define PIO_SM0_EXECCTRL_EXEC_STALLED_RESET _u(0x0)
+#define PIO_SM0_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000)
+#define PIO_SM0_EXECCTRL_EXEC_STALLED_MSB _u(31)
+#define PIO_SM0_EXECCTRL_EXEC_STALLED_LSB _u(31)
#define PIO_SM0_EXECCTRL_EXEC_STALLED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_EXECCTRL_SIDE_EN
@@ -769,36 +769,36 @@
// on every instruction, but the maximum possible side-set width
// is reduced from 5 to 4. Note that the value of
// PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
-#define PIO_SM0_EXECCTRL_SIDE_EN_RESET _U(0x0)
-#define PIO_SM0_EXECCTRL_SIDE_EN_BITS _U(0x40000000)
-#define PIO_SM0_EXECCTRL_SIDE_EN_MSB _U(30)
-#define PIO_SM0_EXECCTRL_SIDE_EN_LSB _U(30)
+#define PIO_SM0_EXECCTRL_SIDE_EN_RESET _u(0x0)
+#define PIO_SM0_EXECCTRL_SIDE_EN_BITS _u(0x40000000)
+#define PIO_SM0_EXECCTRL_SIDE_EN_MSB _u(30)
+#define PIO_SM0_EXECCTRL_SIDE_EN_LSB _u(30)
#define PIO_SM0_EXECCTRL_SIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_EXECCTRL_SIDE_PINDIR
// Description : If 1, side-set data is asserted to pin directions, instead of
// pin values
-#define PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET _U(0x0)
-#define PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS _U(0x20000000)
-#define PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB _U(29)
-#define PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB _U(29)
+#define PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET _u(0x0)
+#define PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000)
+#define PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB _u(29)
+#define PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB _u(29)
#define PIO_SM0_EXECCTRL_SIDE_PINDIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_EXECCTRL_JMP_PIN
// Description : The GPIO number to use as condition for JMP PIN. Unaffected by
// input mapping.
-#define PIO_SM0_EXECCTRL_JMP_PIN_RESET _U(0x00)
-#define PIO_SM0_EXECCTRL_JMP_PIN_BITS _U(0x1f000000)
-#define PIO_SM0_EXECCTRL_JMP_PIN_MSB _U(28)
-#define PIO_SM0_EXECCTRL_JMP_PIN_LSB _U(24)
+#define PIO_SM0_EXECCTRL_JMP_PIN_RESET _u(0x00)
+#define PIO_SM0_EXECCTRL_JMP_PIN_BITS _u(0x1f000000)
+#define PIO_SM0_EXECCTRL_JMP_PIN_MSB _u(28)
+#define PIO_SM0_EXECCTRL_JMP_PIN_LSB _u(24)
#define PIO_SM0_EXECCTRL_JMP_PIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_EXECCTRL_OUT_EN_SEL
// Description : Which data bit to use for inline OUT enable
-#define PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET _U(0x00)
-#define PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS _U(0x00f80000)
-#define PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB _U(23)
-#define PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB _U(19)
+#define PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET _u(0x00)
+#define PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000)
+#define PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB _u(23)
+#define PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB _u(19)
#define PIO_SM0_EXECCTRL_OUT_EN_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_EXECCTRL_INLINE_OUT_EN
@@ -809,18 +809,18 @@
// masking/override behaviour
// due to the priority ordering of state machine pin writes (SM0 <
// SM1 < ...)
-#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET _U(0x0)
-#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS _U(0x00040000)
-#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB _U(18)
-#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB _U(18)
+#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0)
+#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000)
+#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB _u(18)
+#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB _u(18)
#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_EXECCTRL_OUT_STICKY
// Description : Continuously assert the most recent OUT/SET to the pins
-#define PIO_SM0_EXECCTRL_OUT_STICKY_RESET _U(0x0)
-#define PIO_SM0_EXECCTRL_OUT_STICKY_BITS _U(0x00020000)
-#define PIO_SM0_EXECCTRL_OUT_STICKY_MSB _U(17)
-#define PIO_SM0_EXECCTRL_OUT_STICKY_LSB _U(17)
+#define PIO_SM0_EXECCTRL_OUT_STICKY_RESET _u(0x0)
+#define PIO_SM0_EXECCTRL_OUT_STICKY_BITS _u(0x00020000)
+#define PIO_SM0_EXECCTRL_OUT_STICKY_MSB _u(17)
+#define PIO_SM0_EXECCTRL_OUT_STICKY_LSB _u(17)
#define PIO_SM0_EXECCTRL_OUT_STICKY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_EXECCTRL_WRAP_TOP
@@ -828,46 +828,46 @@
// wrap_bottom.
// If the instruction is a jump, and the jump condition is true,
// the jump takes priority.
-#define PIO_SM0_EXECCTRL_WRAP_TOP_RESET _U(0x1f)
-#define PIO_SM0_EXECCTRL_WRAP_TOP_BITS _U(0x0001f000)
-#define PIO_SM0_EXECCTRL_WRAP_TOP_MSB _U(16)
-#define PIO_SM0_EXECCTRL_WRAP_TOP_LSB _U(12)
+#define PIO_SM0_EXECCTRL_WRAP_TOP_RESET _u(0x1f)
+#define PIO_SM0_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000)
+#define PIO_SM0_EXECCTRL_WRAP_TOP_MSB _u(16)
+#define PIO_SM0_EXECCTRL_WRAP_TOP_LSB _u(12)
#define PIO_SM0_EXECCTRL_WRAP_TOP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_EXECCTRL_WRAP_BOTTOM
// Description : After reaching wrap_top, execution is wrapped to this address.
-#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET _U(0x00)
-#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS _U(0x00000f80)
-#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB _U(11)
-#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB _U(7)
+#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00)
+#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80)
+#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB _u(11)
+#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB _u(7)
#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_EXECCTRL_STATUS_SEL
// Description : Comparison used for the MOV x, STATUS instruction.
// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
-#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET _U(0x0)
-#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS _U(0x00000010)
-#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB _U(4)
-#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB _U(4)
+#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET _u(0x0)
+#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS _u(0x00000010)
+#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB _u(4)
+#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB _u(4)
#define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW"
-#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _U(0x0)
-#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _U(0x1)
+#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0)
+#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1)
// -----------------------------------------------------------------------------
// Field : PIO_SM0_EXECCTRL_STATUS_N
// Description : Comparison level for the MOV x, STATUS instruction
-#define PIO_SM0_EXECCTRL_STATUS_N_RESET _U(0x0)
-#define PIO_SM0_EXECCTRL_STATUS_N_BITS _U(0x0000000f)
-#define PIO_SM0_EXECCTRL_STATUS_N_MSB _U(3)
-#define PIO_SM0_EXECCTRL_STATUS_N_LSB _U(0)
+#define PIO_SM0_EXECCTRL_STATUS_N_RESET _u(0x0)
+#define PIO_SM0_EXECCTRL_STATUS_N_BITS _u(0x0000000f)
+#define PIO_SM0_EXECCTRL_STATUS_N_MSB _u(3)
+#define PIO_SM0_EXECCTRL_STATUS_N_LSB _u(0)
#define PIO_SM0_EXECCTRL_STATUS_N_ACCESS "RW"
// =============================================================================
// Register : PIO_SM0_SHIFTCTRL
// Description : Control behaviour of the input/output shift registers for state
// machine 0
-#define PIO_SM0_SHIFTCTRL_OFFSET _U(0x000000d0)
-#define PIO_SM0_SHIFTCTRL_BITS _U(0xffff0000)
-#define PIO_SM0_SHIFTCTRL_RESET _U(0x000c0000)
+#define PIO_SM0_SHIFTCTRL_OFFSET _u(0x000000d0)
+#define PIO_SM0_SHIFTCTRL_BITS _u(0xffff0000)
+#define PIO_SM0_SHIFTCTRL_RESET _u(0x000c0000)
// -----------------------------------------------------------------------------
// Field : PIO_SM0_SHIFTCTRL_FJOIN_RX
// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice
@@ -875,10 +875,10 @@
// TX FIFO is disabled as a result (always reads as both full and
// empty).
// FIFOs are flushed when this bit is changed.
-#define PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET _U(0x0)
-#define PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS _U(0x80000000)
-#define PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB _U(31)
-#define PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB _U(31)
+#define PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET _u(0x0)
+#define PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000)
+#define PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB _u(31)
+#define PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB _u(31)
#define PIO_SM0_SHIFTCTRL_FJOIN_RX_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_SHIFTCTRL_FJOIN_TX
@@ -887,76 +887,76 @@
// RX FIFO is disabled as a result (always reads as both full and
// empty).
// FIFOs are flushed when this bit is changed.
-#define PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET _U(0x0)
-#define PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS _U(0x40000000)
-#define PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB _U(30)
-#define PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB _U(30)
+#define PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET _u(0x0)
+#define PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000)
+#define PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB _u(30)
+#define PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB _u(30)
#define PIO_SM0_SHIFTCTRL_FJOIN_TX_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_SHIFTCTRL_PULL_THRESH
// Description : Number of bits shifted out of OSR before autopull, or
// conditional pull (PULL IFEMPTY), will take place.
// Write 0 for value of 32.
-#define PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET _U(0x00)
-#define PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS _U(0x3e000000)
-#define PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB _U(29)
-#define PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB _U(25)
+#define PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET _u(0x00)
+#define PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000)
+#define PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB _u(29)
+#define PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB _u(25)
#define PIO_SM0_SHIFTCTRL_PULL_THRESH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_SHIFTCTRL_PUSH_THRESH
// Description : Number of bits shifted into ISR before autopush, or conditional
// push (PUSH IFFULL), will take place.
// Write 0 for value of 32.
-#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET _U(0x00)
-#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS _U(0x01f00000)
-#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB _U(24)
-#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB _U(20)
+#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00)
+#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000)
+#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB _u(24)
+#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB _u(20)
#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR
// Description : 1 = shift out of output shift register to right. 0 = to left.
-#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET _U(0x1)
-#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS _U(0x00080000)
-#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB _U(19)
-#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB _U(19)
+#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1)
+#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000)
+#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19)
+#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19)
#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_SHIFTCTRL_IN_SHIFTDIR
// Description : 1 = shift input shift register to right (data enters from
// left). 0 = to left.
-#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET _U(0x1)
-#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS _U(0x00040000)
-#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB _U(18)
-#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB _U(18)
+#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1)
+#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000)
+#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18)
+#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18)
#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_SHIFTCTRL_AUTOPULL
// Description : Pull automatically when the output shift register is emptied,
// i.e. on or following an OUT instruction which causes the output
// shift counter to reach or exceed PULL_THRESH.
-#define PIO_SM0_SHIFTCTRL_AUTOPULL_RESET _U(0x0)
-#define PIO_SM0_SHIFTCTRL_AUTOPULL_BITS _U(0x00020000)
-#define PIO_SM0_SHIFTCTRL_AUTOPULL_MSB _U(17)
-#define PIO_SM0_SHIFTCTRL_AUTOPULL_LSB _U(17)
+#define PIO_SM0_SHIFTCTRL_AUTOPULL_RESET _u(0x0)
+#define PIO_SM0_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000)
+#define PIO_SM0_SHIFTCTRL_AUTOPULL_MSB _u(17)
+#define PIO_SM0_SHIFTCTRL_AUTOPULL_LSB _u(17)
#define PIO_SM0_SHIFTCTRL_AUTOPULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_SHIFTCTRL_AUTOPUSH
// Description : Push automatically when the input shift register is filled,
// i.e. on an IN instruction which causes the input shift counter
// to reach or exceed PUSH_THRESH.
-#define PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET _U(0x0)
-#define PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS _U(0x00010000)
-#define PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB _U(16)
-#define PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB _U(16)
+#define PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET _u(0x0)
+#define PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000)
+#define PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB _u(16)
+#define PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB _u(16)
#define PIO_SM0_SHIFTCTRL_AUTOPUSH_ACCESS "RW"
// =============================================================================
// Register : PIO_SM0_ADDR
// Description : Current instruction address of state machine 0
-#define PIO_SM0_ADDR_OFFSET _U(0x000000d4)
-#define PIO_SM0_ADDR_BITS _U(0x0000001f)
-#define PIO_SM0_ADDR_RESET _U(0x00000000)
-#define PIO_SM0_ADDR_MSB _U(4)
-#define PIO_SM0_ADDR_LSB _U(0)
+#define PIO_SM0_ADDR_OFFSET _u(0x000000d4)
+#define PIO_SM0_ADDR_BITS _u(0x0000001f)
+#define PIO_SM0_ADDR_RESET _u(0x00000000)
+#define PIO_SM0_ADDR_MSB _u(4)
+#define PIO_SM0_ADDR_LSB _u(0)
#define PIO_SM0_ADDR_ACCESS "RO"
// =============================================================================
// Register : PIO_SM0_INSTR
@@ -964,46 +964,46 @@
// machine 0's program counter
// Write to execute an instruction immediately (including jumps)
// and then resume execution.
-#define PIO_SM0_INSTR_OFFSET _U(0x000000d8)
-#define PIO_SM0_INSTR_BITS _U(0x0000ffff)
+#define PIO_SM0_INSTR_OFFSET _u(0x000000d8)
+#define PIO_SM0_INSTR_BITS _u(0x0000ffff)
#define PIO_SM0_INSTR_RESET "-"
-#define PIO_SM0_INSTR_MSB _U(15)
-#define PIO_SM0_INSTR_LSB _U(0)
+#define PIO_SM0_INSTR_MSB _u(15)
+#define PIO_SM0_INSTR_LSB _u(0)
#define PIO_SM0_INSTR_ACCESS "RW"
// =============================================================================
// Register : PIO_SM0_PINCTRL
// Description : State machine pin control
-#define PIO_SM0_PINCTRL_OFFSET _U(0x000000dc)
-#define PIO_SM0_PINCTRL_BITS _U(0xffffffff)
-#define PIO_SM0_PINCTRL_RESET _U(0x14000000)
+#define PIO_SM0_PINCTRL_OFFSET _u(0x000000dc)
+#define PIO_SM0_PINCTRL_BITS _u(0xffffffff)
+#define PIO_SM0_PINCTRL_RESET _u(0x14000000)
// -----------------------------------------------------------------------------
// Field : PIO_SM0_PINCTRL_SIDESET_COUNT
// Description : The number of MSBs of the Delay/Side-set instruction field
// which are used for side-set. Inclusive of the enable bit, if
// present. Minimum of 0 (all delay bits, no side-set) and maximum
// of 5 (all side-set, no delay).
-#define PIO_SM0_PINCTRL_SIDESET_COUNT_RESET _U(0x0)
-#define PIO_SM0_PINCTRL_SIDESET_COUNT_BITS _U(0xe0000000)
-#define PIO_SM0_PINCTRL_SIDESET_COUNT_MSB _U(31)
-#define PIO_SM0_PINCTRL_SIDESET_COUNT_LSB _U(29)
+#define PIO_SM0_PINCTRL_SIDESET_COUNT_RESET _u(0x0)
+#define PIO_SM0_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000)
+#define PIO_SM0_PINCTRL_SIDESET_COUNT_MSB _u(31)
+#define PIO_SM0_PINCTRL_SIDESET_COUNT_LSB _u(29)
#define PIO_SM0_PINCTRL_SIDESET_COUNT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_PINCTRL_SET_COUNT
// Description : The number of pins asserted by a SET. In the range 0 to 5
// inclusive.
-#define PIO_SM0_PINCTRL_SET_COUNT_RESET _U(0x5)
-#define PIO_SM0_PINCTRL_SET_COUNT_BITS _U(0x1c000000)
-#define PIO_SM0_PINCTRL_SET_COUNT_MSB _U(28)
-#define PIO_SM0_PINCTRL_SET_COUNT_LSB _U(26)
+#define PIO_SM0_PINCTRL_SET_COUNT_RESET _u(0x5)
+#define PIO_SM0_PINCTRL_SET_COUNT_BITS _u(0x1c000000)
+#define PIO_SM0_PINCTRL_SET_COUNT_MSB _u(28)
+#define PIO_SM0_PINCTRL_SET_COUNT_LSB _u(26)
#define PIO_SM0_PINCTRL_SET_COUNT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_PINCTRL_OUT_COUNT
// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV
// PINS instruction. In the range 0 to 32 inclusive.
-#define PIO_SM0_PINCTRL_OUT_COUNT_RESET _U(0x00)
-#define PIO_SM0_PINCTRL_OUT_COUNT_BITS _U(0x03f00000)
-#define PIO_SM0_PINCTRL_OUT_COUNT_MSB _U(25)
-#define PIO_SM0_PINCTRL_OUT_COUNT_LSB _U(20)
+#define PIO_SM0_PINCTRL_OUT_COUNT_RESET _u(0x00)
+#define PIO_SM0_PINCTRL_OUT_COUNT_BITS _u(0x03f00000)
+#define PIO_SM0_PINCTRL_OUT_COUNT_MSB _u(25)
+#define PIO_SM0_PINCTRL_OUT_COUNT_LSB _u(20)
#define PIO_SM0_PINCTRL_OUT_COUNT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_PINCTRL_IN_BASE
@@ -1011,10 +1011,10 @@
// machine's IN data bus. Higher-numbered pins are mapped to
// consecutively more-significant data bits, with a modulo of 32
// applied to pin number.
-#define PIO_SM0_PINCTRL_IN_BASE_RESET _U(0x00)
-#define PIO_SM0_PINCTRL_IN_BASE_BITS _U(0x000f8000)
-#define PIO_SM0_PINCTRL_IN_BASE_MSB _U(19)
-#define PIO_SM0_PINCTRL_IN_BASE_LSB _U(15)
+#define PIO_SM0_PINCTRL_IN_BASE_RESET _u(0x00)
+#define PIO_SM0_PINCTRL_IN_BASE_BITS _u(0x000f8000)
+#define PIO_SM0_PINCTRL_IN_BASE_MSB _u(19)
+#define PIO_SM0_PINCTRL_IN_BASE_LSB _u(15)
#define PIO_SM0_PINCTRL_IN_BASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_PINCTRL_SIDESET_BASE
@@ -1025,20 +1025,20 @@
// least-significant bit of the side-set portion is the bit
// written to this pin, with more-significant bits written to
// higher-numbered pins.
-#define PIO_SM0_PINCTRL_SIDESET_BASE_RESET _U(0x00)
-#define PIO_SM0_PINCTRL_SIDESET_BASE_BITS _U(0x00007c00)
-#define PIO_SM0_PINCTRL_SIDESET_BASE_MSB _U(14)
-#define PIO_SM0_PINCTRL_SIDESET_BASE_LSB _U(10)
+#define PIO_SM0_PINCTRL_SIDESET_BASE_RESET _u(0x00)
+#define PIO_SM0_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00)
+#define PIO_SM0_PINCTRL_SIDESET_BASE_MSB _u(14)
+#define PIO_SM0_PINCTRL_SIDESET_BASE_LSB _u(10)
#define PIO_SM0_PINCTRL_SIDESET_BASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_PINCTRL_SET_BASE
// Description : The lowest-numbered pin that will be affected by a SET PINS or
// SET PINDIRS instruction. The data written to this pin is the
// least-significant bit of the SET data.
-#define PIO_SM0_PINCTRL_SET_BASE_RESET _U(0x00)
-#define PIO_SM0_PINCTRL_SET_BASE_BITS _U(0x000003e0)
-#define PIO_SM0_PINCTRL_SET_BASE_MSB _U(9)
-#define PIO_SM0_PINCTRL_SET_BASE_LSB _U(5)
+#define PIO_SM0_PINCTRL_SET_BASE_RESET _u(0x00)
+#define PIO_SM0_PINCTRL_SET_BASE_BITS _u(0x000003e0)
+#define PIO_SM0_PINCTRL_SET_BASE_MSB _u(9)
+#define PIO_SM0_PINCTRL_SET_BASE_LSB _u(5)
#define PIO_SM0_PINCTRL_SET_BASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM0_PINCTRL_OUT_BASE
@@ -1046,51 +1046,51 @@
// OUT PINDIRS or MOV PINS instruction. The data written to this
// pin will always be the least-significant bit of the OUT or MOV
// data.
-#define PIO_SM0_PINCTRL_OUT_BASE_RESET _U(0x00)
-#define PIO_SM0_PINCTRL_OUT_BASE_BITS _U(0x0000001f)
-#define PIO_SM0_PINCTRL_OUT_BASE_MSB _U(4)
-#define PIO_SM0_PINCTRL_OUT_BASE_LSB _U(0)
+#define PIO_SM0_PINCTRL_OUT_BASE_RESET _u(0x00)
+#define PIO_SM0_PINCTRL_OUT_BASE_BITS _u(0x0000001f)
+#define PIO_SM0_PINCTRL_OUT_BASE_MSB _u(4)
+#define PIO_SM0_PINCTRL_OUT_BASE_LSB _u(0)
#define PIO_SM0_PINCTRL_OUT_BASE_ACCESS "RW"
// =============================================================================
// Register : PIO_SM1_CLKDIV
// Description : Clock divisor register for state machine 1
// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
-#define PIO_SM1_CLKDIV_OFFSET _U(0x000000e0)
-#define PIO_SM1_CLKDIV_BITS _U(0xffffff00)
-#define PIO_SM1_CLKDIV_RESET _U(0x00010000)
+#define PIO_SM1_CLKDIV_OFFSET _u(0x000000e0)
+#define PIO_SM1_CLKDIV_BITS _u(0xffffff00)
+#define PIO_SM1_CLKDIV_RESET _u(0x00010000)
// -----------------------------------------------------------------------------
// Field : PIO_SM1_CLKDIV_INT
// Description : Effective frequency is sysclk/(int + frac/256).
// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also
// be 0.
-#define PIO_SM1_CLKDIV_INT_RESET _U(0x0001)
-#define PIO_SM1_CLKDIV_INT_BITS _U(0xffff0000)
-#define PIO_SM1_CLKDIV_INT_MSB _U(31)
-#define PIO_SM1_CLKDIV_INT_LSB _U(16)
+#define PIO_SM1_CLKDIV_INT_RESET _u(0x0001)
+#define PIO_SM1_CLKDIV_INT_BITS _u(0xffff0000)
+#define PIO_SM1_CLKDIV_INT_MSB _u(31)
+#define PIO_SM1_CLKDIV_INT_LSB _u(16)
#define PIO_SM1_CLKDIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_CLKDIV_FRAC
// Description : Fractional part of clock divisor
-#define PIO_SM1_CLKDIV_FRAC_RESET _U(0x00)
-#define PIO_SM1_CLKDIV_FRAC_BITS _U(0x0000ff00)
-#define PIO_SM1_CLKDIV_FRAC_MSB _U(15)
-#define PIO_SM1_CLKDIV_FRAC_LSB _U(8)
+#define PIO_SM1_CLKDIV_FRAC_RESET _u(0x00)
+#define PIO_SM1_CLKDIV_FRAC_BITS _u(0x0000ff00)
+#define PIO_SM1_CLKDIV_FRAC_MSB _u(15)
+#define PIO_SM1_CLKDIV_FRAC_LSB _u(8)
#define PIO_SM1_CLKDIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : PIO_SM1_EXECCTRL
// Description : Execution/behavioural settings for state machine 1
-#define PIO_SM1_EXECCTRL_OFFSET _U(0x000000e4)
-#define PIO_SM1_EXECCTRL_BITS _U(0xffffff9f)
-#define PIO_SM1_EXECCTRL_RESET _U(0x0001f000)
+#define PIO_SM1_EXECCTRL_OFFSET _u(0x000000e4)
+#define PIO_SM1_EXECCTRL_BITS _u(0xffffff9f)
+#define PIO_SM1_EXECCTRL_RESET _u(0x0001f000)
// -----------------------------------------------------------------------------
// Field : PIO_SM1_EXECCTRL_EXEC_STALLED
// Description : If 1, an instruction written to SMx_INSTR is stalled, and
// latched by the state machine. Will clear to 0 once this
// instruction completes.
-#define PIO_SM1_EXECCTRL_EXEC_STALLED_RESET _U(0x0)
-#define PIO_SM1_EXECCTRL_EXEC_STALLED_BITS _U(0x80000000)
-#define PIO_SM1_EXECCTRL_EXEC_STALLED_MSB _U(31)
-#define PIO_SM1_EXECCTRL_EXEC_STALLED_LSB _U(31)
+#define PIO_SM1_EXECCTRL_EXEC_STALLED_RESET _u(0x0)
+#define PIO_SM1_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000)
+#define PIO_SM1_EXECCTRL_EXEC_STALLED_MSB _u(31)
+#define PIO_SM1_EXECCTRL_EXEC_STALLED_LSB _u(31)
#define PIO_SM1_EXECCTRL_EXEC_STALLED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_EXECCTRL_SIDE_EN
@@ -1100,36 +1100,36 @@
// on every instruction, but the maximum possible side-set width
// is reduced from 5 to 4. Note that the value of
// PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
-#define PIO_SM1_EXECCTRL_SIDE_EN_RESET _U(0x0)
-#define PIO_SM1_EXECCTRL_SIDE_EN_BITS _U(0x40000000)
-#define PIO_SM1_EXECCTRL_SIDE_EN_MSB _U(30)
-#define PIO_SM1_EXECCTRL_SIDE_EN_LSB _U(30)
+#define PIO_SM1_EXECCTRL_SIDE_EN_RESET _u(0x0)
+#define PIO_SM1_EXECCTRL_SIDE_EN_BITS _u(0x40000000)
+#define PIO_SM1_EXECCTRL_SIDE_EN_MSB _u(30)
+#define PIO_SM1_EXECCTRL_SIDE_EN_LSB _u(30)
#define PIO_SM1_EXECCTRL_SIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_EXECCTRL_SIDE_PINDIR
// Description : If 1, side-set data is asserted to pin directions, instead of
// pin values
-#define PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET _U(0x0)
-#define PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS _U(0x20000000)
-#define PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB _U(29)
-#define PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB _U(29)
+#define PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET _u(0x0)
+#define PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000)
+#define PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB _u(29)
+#define PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB _u(29)
#define PIO_SM1_EXECCTRL_SIDE_PINDIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_EXECCTRL_JMP_PIN
// Description : The GPIO number to use as condition for JMP PIN. Unaffected by
// input mapping.
-#define PIO_SM1_EXECCTRL_JMP_PIN_RESET _U(0x00)
-#define PIO_SM1_EXECCTRL_JMP_PIN_BITS _U(0x1f000000)
-#define PIO_SM1_EXECCTRL_JMP_PIN_MSB _U(28)
-#define PIO_SM1_EXECCTRL_JMP_PIN_LSB _U(24)
+#define PIO_SM1_EXECCTRL_JMP_PIN_RESET _u(0x00)
+#define PIO_SM1_EXECCTRL_JMP_PIN_BITS _u(0x1f000000)
+#define PIO_SM1_EXECCTRL_JMP_PIN_MSB _u(28)
+#define PIO_SM1_EXECCTRL_JMP_PIN_LSB _u(24)
#define PIO_SM1_EXECCTRL_JMP_PIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_EXECCTRL_OUT_EN_SEL
// Description : Which data bit to use for inline OUT enable
-#define PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET _U(0x00)
-#define PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS _U(0x00f80000)
-#define PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB _U(23)
-#define PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB _U(19)
+#define PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET _u(0x00)
+#define PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000)
+#define PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB _u(23)
+#define PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB _u(19)
#define PIO_SM1_EXECCTRL_OUT_EN_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_EXECCTRL_INLINE_OUT_EN
@@ -1140,18 +1140,18 @@
// masking/override behaviour
// due to the priority ordering of state machine pin writes (SM0 <
// SM1 < ...)
-#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET _U(0x0)
-#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS _U(0x00040000)
-#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB _U(18)
-#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB _U(18)
+#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0)
+#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000)
+#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB _u(18)
+#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB _u(18)
#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_EXECCTRL_OUT_STICKY
// Description : Continuously assert the most recent OUT/SET to the pins
-#define PIO_SM1_EXECCTRL_OUT_STICKY_RESET _U(0x0)
-#define PIO_SM1_EXECCTRL_OUT_STICKY_BITS _U(0x00020000)
-#define PIO_SM1_EXECCTRL_OUT_STICKY_MSB _U(17)
-#define PIO_SM1_EXECCTRL_OUT_STICKY_LSB _U(17)
+#define PIO_SM1_EXECCTRL_OUT_STICKY_RESET _u(0x0)
+#define PIO_SM1_EXECCTRL_OUT_STICKY_BITS _u(0x00020000)
+#define PIO_SM1_EXECCTRL_OUT_STICKY_MSB _u(17)
+#define PIO_SM1_EXECCTRL_OUT_STICKY_LSB _u(17)
#define PIO_SM1_EXECCTRL_OUT_STICKY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_EXECCTRL_WRAP_TOP
@@ -1159,46 +1159,46 @@
// wrap_bottom.
// If the instruction is a jump, and the jump condition is true,
// the jump takes priority.
-#define PIO_SM1_EXECCTRL_WRAP_TOP_RESET _U(0x1f)
-#define PIO_SM1_EXECCTRL_WRAP_TOP_BITS _U(0x0001f000)
-#define PIO_SM1_EXECCTRL_WRAP_TOP_MSB _U(16)
-#define PIO_SM1_EXECCTRL_WRAP_TOP_LSB _U(12)
+#define PIO_SM1_EXECCTRL_WRAP_TOP_RESET _u(0x1f)
+#define PIO_SM1_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000)
+#define PIO_SM1_EXECCTRL_WRAP_TOP_MSB _u(16)
+#define PIO_SM1_EXECCTRL_WRAP_TOP_LSB _u(12)
#define PIO_SM1_EXECCTRL_WRAP_TOP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_EXECCTRL_WRAP_BOTTOM
// Description : After reaching wrap_top, execution is wrapped to this address.
-#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET _U(0x00)
-#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS _U(0x00000f80)
-#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB _U(11)
-#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB _U(7)
+#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00)
+#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80)
+#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB _u(11)
+#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB _u(7)
#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_EXECCTRL_STATUS_SEL
// Description : Comparison used for the MOV x, STATUS instruction.
// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
-#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET _U(0x0)
-#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS _U(0x00000010)
-#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB _U(4)
-#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB _U(4)
+#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET _u(0x0)
+#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS _u(0x00000010)
+#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB _u(4)
+#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB _u(4)
#define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW"
-#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _U(0x0)
-#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _U(0x1)
+#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0)
+#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1)
// -----------------------------------------------------------------------------
// Field : PIO_SM1_EXECCTRL_STATUS_N
// Description : Comparison level for the MOV x, STATUS instruction
-#define PIO_SM1_EXECCTRL_STATUS_N_RESET _U(0x0)
-#define PIO_SM1_EXECCTRL_STATUS_N_BITS _U(0x0000000f)
-#define PIO_SM1_EXECCTRL_STATUS_N_MSB _U(3)
-#define PIO_SM1_EXECCTRL_STATUS_N_LSB _U(0)
+#define PIO_SM1_EXECCTRL_STATUS_N_RESET _u(0x0)
+#define PIO_SM1_EXECCTRL_STATUS_N_BITS _u(0x0000000f)
+#define PIO_SM1_EXECCTRL_STATUS_N_MSB _u(3)
+#define PIO_SM1_EXECCTRL_STATUS_N_LSB _u(0)
#define PIO_SM1_EXECCTRL_STATUS_N_ACCESS "RW"
// =============================================================================
// Register : PIO_SM1_SHIFTCTRL
// Description : Control behaviour of the input/output shift registers for state
// machine 1
-#define PIO_SM1_SHIFTCTRL_OFFSET _U(0x000000e8)
-#define PIO_SM1_SHIFTCTRL_BITS _U(0xffff0000)
-#define PIO_SM1_SHIFTCTRL_RESET _U(0x000c0000)
+#define PIO_SM1_SHIFTCTRL_OFFSET _u(0x000000e8)
+#define PIO_SM1_SHIFTCTRL_BITS _u(0xffff0000)
+#define PIO_SM1_SHIFTCTRL_RESET _u(0x000c0000)
// -----------------------------------------------------------------------------
// Field : PIO_SM1_SHIFTCTRL_FJOIN_RX
// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice
@@ -1206,10 +1206,10 @@
// TX FIFO is disabled as a result (always reads as both full and
// empty).
// FIFOs are flushed when this bit is changed.
-#define PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET _U(0x0)
-#define PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS _U(0x80000000)
-#define PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB _U(31)
-#define PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB _U(31)
+#define PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET _u(0x0)
+#define PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000)
+#define PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB _u(31)
+#define PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB _u(31)
#define PIO_SM1_SHIFTCTRL_FJOIN_RX_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_SHIFTCTRL_FJOIN_TX
@@ -1218,76 +1218,76 @@
// RX FIFO is disabled as a result (always reads as both full and
// empty).
// FIFOs are flushed when this bit is changed.
-#define PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET _U(0x0)
-#define PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS _U(0x40000000)
-#define PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB _U(30)
-#define PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB _U(30)
+#define PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET _u(0x0)
+#define PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000)
+#define PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB _u(30)
+#define PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB _u(30)
#define PIO_SM1_SHIFTCTRL_FJOIN_TX_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_SHIFTCTRL_PULL_THRESH
// Description : Number of bits shifted out of OSR before autopull, or
// conditional pull (PULL IFEMPTY), will take place.
// Write 0 for value of 32.
-#define PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET _U(0x00)
-#define PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS _U(0x3e000000)
-#define PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB _U(29)
-#define PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB _U(25)
+#define PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET _u(0x00)
+#define PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000)
+#define PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB _u(29)
+#define PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB _u(25)
#define PIO_SM1_SHIFTCTRL_PULL_THRESH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_SHIFTCTRL_PUSH_THRESH
// Description : Number of bits shifted into ISR before autopush, or conditional
// push (PUSH IFFULL), will take place.
// Write 0 for value of 32.
-#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET _U(0x00)
-#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS _U(0x01f00000)
-#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB _U(24)
-#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB _U(20)
+#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00)
+#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000)
+#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB _u(24)
+#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB _u(20)
#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR
// Description : 1 = shift out of output shift register to right. 0 = to left.
-#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET _U(0x1)
-#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS _U(0x00080000)
-#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB _U(19)
-#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB _U(19)
+#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1)
+#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000)
+#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19)
+#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19)
#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_SHIFTCTRL_IN_SHIFTDIR
// Description : 1 = shift input shift register to right (data enters from
// left). 0 = to left.
-#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET _U(0x1)
-#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS _U(0x00040000)
-#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB _U(18)
-#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB _U(18)
+#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1)
+#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000)
+#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18)
+#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18)
#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_SHIFTCTRL_AUTOPULL
// Description : Pull automatically when the output shift register is emptied,
// i.e. on or following an OUT instruction which causes the output
// shift counter to reach or exceed PULL_THRESH.
-#define PIO_SM1_SHIFTCTRL_AUTOPULL_RESET _U(0x0)
-#define PIO_SM1_SHIFTCTRL_AUTOPULL_BITS _U(0x00020000)
-#define PIO_SM1_SHIFTCTRL_AUTOPULL_MSB _U(17)
-#define PIO_SM1_SHIFTCTRL_AUTOPULL_LSB _U(17)
+#define PIO_SM1_SHIFTCTRL_AUTOPULL_RESET _u(0x0)
+#define PIO_SM1_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000)
+#define PIO_SM1_SHIFTCTRL_AUTOPULL_MSB _u(17)
+#define PIO_SM1_SHIFTCTRL_AUTOPULL_LSB _u(17)
#define PIO_SM1_SHIFTCTRL_AUTOPULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_SHIFTCTRL_AUTOPUSH
// Description : Push automatically when the input shift register is filled,
// i.e. on an IN instruction which causes the input shift counter
// to reach or exceed PUSH_THRESH.
-#define PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET _U(0x0)
-#define PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS _U(0x00010000)
-#define PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB _U(16)
-#define PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB _U(16)
+#define PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET _u(0x0)
+#define PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000)
+#define PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB _u(16)
+#define PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB _u(16)
#define PIO_SM1_SHIFTCTRL_AUTOPUSH_ACCESS "RW"
// =============================================================================
// Register : PIO_SM1_ADDR
// Description : Current instruction address of state machine 1
-#define PIO_SM1_ADDR_OFFSET _U(0x000000ec)
-#define PIO_SM1_ADDR_BITS _U(0x0000001f)
-#define PIO_SM1_ADDR_RESET _U(0x00000000)
-#define PIO_SM1_ADDR_MSB _U(4)
-#define PIO_SM1_ADDR_LSB _U(0)
+#define PIO_SM1_ADDR_OFFSET _u(0x000000ec)
+#define PIO_SM1_ADDR_BITS _u(0x0000001f)
+#define PIO_SM1_ADDR_RESET _u(0x00000000)
+#define PIO_SM1_ADDR_MSB _u(4)
+#define PIO_SM1_ADDR_LSB _u(0)
#define PIO_SM1_ADDR_ACCESS "RO"
// =============================================================================
// Register : PIO_SM1_INSTR
@@ -1295,46 +1295,46 @@
// machine 1's program counter
// Write to execute an instruction immediately (including jumps)
// and then resume execution.
-#define PIO_SM1_INSTR_OFFSET _U(0x000000f0)
-#define PIO_SM1_INSTR_BITS _U(0x0000ffff)
+#define PIO_SM1_INSTR_OFFSET _u(0x000000f0)
+#define PIO_SM1_INSTR_BITS _u(0x0000ffff)
#define PIO_SM1_INSTR_RESET "-"
-#define PIO_SM1_INSTR_MSB _U(15)
-#define PIO_SM1_INSTR_LSB _U(0)
+#define PIO_SM1_INSTR_MSB _u(15)
+#define PIO_SM1_INSTR_LSB _u(0)
#define PIO_SM1_INSTR_ACCESS "RW"
// =============================================================================
// Register : PIO_SM1_PINCTRL
// Description : State machine pin control
-#define PIO_SM1_PINCTRL_OFFSET _U(0x000000f4)
-#define PIO_SM1_PINCTRL_BITS _U(0xffffffff)
-#define PIO_SM1_PINCTRL_RESET _U(0x14000000)
+#define PIO_SM1_PINCTRL_OFFSET _u(0x000000f4)
+#define PIO_SM1_PINCTRL_BITS _u(0xffffffff)
+#define PIO_SM1_PINCTRL_RESET _u(0x14000000)
// -----------------------------------------------------------------------------
// Field : PIO_SM1_PINCTRL_SIDESET_COUNT
// Description : The number of MSBs of the Delay/Side-set instruction field
// which are used for side-set. Inclusive of the enable bit, if
// present. Minimum of 0 (all delay bits, no side-set) and maximum
// of 5 (all side-set, no delay).
-#define PIO_SM1_PINCTRL_SIDESET_COUNT_RESET _U(0x0)
-#define PIO_SM1_PINCTRL_SIDESET_COUNT_BITS _U(0xe0000000)
-#define PIO_SM1_PINCTRL_SIDESET_COUNT_MSB _U(31)
-#define PIO_SM1_PINCTRL_SIDESET_COUNT_LSB _U(29)
+#define PIO_SM1_PINCTRL_SIDESET_COUNT_RESET _u(0x0)
+#define PIO_SM1_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000)
+#define PIO_SM1_PINCTRL_SIDESET_COUNT_MSB _u(31)
+#define PIO_SM1_PINCTRL_SIDESET_COUNT_LSB _u(29)
#define PIO_SM1_PINCTRL_SIDESET_COUNT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_PINCTRL_SET_COUNT
// Description : The number of pins asserted by a SET. In the range 0 to 5
// inclusive.
-#define PIO_SM1_PINCTRL_SET_COUNT_RESET _U(0x5)
-#define PIO_SM1_PINCTRL_SET_COUNT_BITS _U(0x1c000000)
-#define PIO_SM1_PINCTRL_SET_COUNT_MSB _U(28)
-#define PIO_SM1_PINCTRL_SET_COUNT_LSB _U(26)
+#define PIO_SM1_PINCTRL_SET_COUNT_RESET _u(0x5)
+#define PIO_SM1_PINCTRL_SET_COUNT_BITS _u(0x1c000000)
+#define PIO_SM1_PINCTRL_SET_COUNT_MSB _u(28)
+#define PIO_SM1_PINCTRL_SET_COUNT_LSB _u(26)
#define PIO_SM1_PINCTRL_SET_COUNT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_PINCTRL_OUT_COUNT
// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV
// PINS instruction. In the range 0 to 32 inclusive.
-#define PIO_SM1_PINCTRL_OUT_COUNT_RESET _U(0x00)
-#define PIO_SM1_PINCTRL_OUT_COUNT_BITS _U(0x03f00000)
-#define PIO_SM1_PINCTRL_OUT_COUNT_MSB _U(25)
-#define PIO_SM1_PINCTRL_OUT_COUNT_LSB _U(20)
+#define PIO_SM1_PINCTRL_OUT_COUNT_RESET _u(0x00)
+#define PIO_SM1_PINCTRL_OUT_COUNT_BITS _u(0x03f00000)
+#define PIO_SM1_PINCTRL_OUT_COUNT_MSB _u(25)
+#define PIO_SM1_PINCTRL_OUT_COUNT_LSB _u(20)
#define PIO_SM1_PINCTRL_OUT_COUNT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_PINCTRL_IN_BASE
@@ -1342,10 +1342,10 @@
// machine's IN data bus. Higher-numbered pins are mapped to
// consecutively more-significant data bits, with a modulo of 32
// applied to pin number.
-#define PIO_SM1_PINCTRL_IN_BASE_RESET _U(0x00)
-#define PIO_SM1_PINCTRL_IN_BASE_BITS _U(0x000f8000)
-#define PIO_SM1_PINCTRL_IN_BASE_MSB _U(19)
-#define PIO_SM1_PINCTRL_IN_BASE_LSB _U(15)
+#define PIO_SM1_PINCTRL_IN_BASE_RESET _u(0x00)
+#define PIO_SM1_PINCTRL_IN_BASE_BITS _u(0x000f8000)
+#define PIO_SM1_PINCTRL_IN_BASE_MSB _u(19)
+#define PIO_SM1_PINCTRL_IN_BASE_LSB _u(15)
#define PIO_SM1_PINCTRL_IN_BASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_PINCTRL_SIDESET_BASE
@@ -1356,20 +1356,20 @@
// least-significant bit of the side-set portion is the bit
// written to this pin, with more-significant bits written to
// higher-numbered pins.
-#define PIO_SM1_PINCTRL_SIDESET_BASE_RESET _U(0x00)
-#define PIO_SM1_PINCTRL_SIDESET_BASE_BITS _U(0x00007c00)
-#define PIO_SM1_PINCTRL_SIDESET_BASE_MSB _U(14)
-#define PIO_SM1_PINCTRL_SIDESET_BASE_LSB _U(10)
+#define PIO_SM1_PINCTRL_SIDESET_BASE_RESET _u(0x00)
+#define PIO_SM1_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00)
+#define PIO_SM1_PINCTRL_SIDESET_BASE_MSB _u(14)
+#define PIO_SM1_PINCTRL_SIDESET_BASE_LSB _u(10)
#define PIO_SM1_PINCTRL_SIDESET_BASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_PINCTRL_SET_BASE
// Description : The lowest-numbered pin that will be affected by a SET PINS or
// SET PINDIRS instruction. The data written to this pin is the
// least-significant bit of the SET data.
-#define PIO_SM1_PINCTRL_SET_BASE_RESET _U(0x00)
-#define PIO_SM1_PINCTRL_SET_BASE_BITS _U(0x000003e0)
-#define PIO_SM1_PINCTRL_SET_BASE_MSB _U(9)
-#define PIO_SM1_PINCTRL_SET_BASE_LSB _U(5)
+#define PIO_SM1_PINCTRL_SET_BASE_RESET _u(0x00)
+#define PIO_SM1_PINCTRL_SET_BASE_BITS _u(0x000003e0)
+#define PIO_SM1_PINCTRL_SET_BASE_MSB _u(9)
+#define PIO_SM1_PINCTRL_SET_BASE_LSB _u(5)
#define PIO_SM1_PINCTRL_SET_BASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM1_PINCTRL_OUT_BASE
@@ -1377,51 +1377,51 @@
// OUT PINDIRS or MOV PINS instruction. The data written to this
// pin will always be the least-significant bit of the OUT or MOV
// data.
-#define PIO_SM1_PINCTRL_OUT_BASE_RESET _U(0x00)
-#define PIO_SM1_PINCTRL_OUT_BASE_BITS _U(0x0000001f)
-#define PIO_SM1_PINCTRL_OUT_BASE_MSB _U(4)
-#define PIO_SM1_PINCTRL_OUT_BASE_LSB _U(0)
+#define PIO_SM1_PINCTRL_OUT_BASE_RESET _u(0x00)
+#define PIO_SM1_PINCTRL_OUT_BASE_BITS _u(0x0000001f)
+#define PIO_SM1_PINCTRL_OUT_BASE_MSB _u(4)
+#define PIO_SM1_PINCTRL_OUT_BASE_LSB _u(0)
#define PIO_SM1_PINCTRL_OUT_BASE_ACCESS "RW"
// =============================================================================
// Register : PIO_SM2_CLKDIV
// Description : Clock divisor register for state machine 2
// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
-#define PIO_SM2_CLKDIV_OFFSET _U(0x000000f8)
-#define PIO_SM2_CLKDIV_BITS _U(0xffffff00)
-#define PIO_SM2_CLKDIV_RESET _U(0x00010000)
+#define PIO_SM2_CLKDIV_OFFSET _u(0x000000f8)
+#define PIO_SM2_CLKDIV_BITS _u(0xffffff00)
+#define PIO_SM2_CLKDIV_RESET _u(0x00010000)
// -----------------------------------------------------------------------------
// Field : PIO_SM2_CLKDIV_INT
// Description : Effective frequency is sysclk/(int + frac/256).
// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also
// be 0.
-#define PIO_SM2_CLKDIV_INT_RESET _U(0x0001)
-#define PIO_SM2_CLKDIV_INT_BITS _U(0xffff0000)
-#define PIO_SM2_CLKDIV_INT_MSB _U(31)
-#define PIO_SM2_CLKDIV_INT_LSB _U(16)
+#define PIO_SM2_CLKDIV_INT_RESET _u(0x0001)
+#define PIO_SM2_CLKDIV_INT_BITS _u(0xffff0000)
+#define PIO_SM2_CLKDIV_INT_MSB _u(31)
+#define PIO_SM2_CLKDIV_INT_LSB _u(16)
#define PIO_SM2_CLKDIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_CLKDIV_FRAC
// Description : Fractional part of clock divisor
-#define PIO_SM2_CLKDIV_FRAC_RESET _U(0x00)
-#define PIO_SM2_CLKDIV_FRAC_BITS _U(0x0000ff00)
-#define PIO_SM2_CLKDIV_FRAC_MSB _U(15)
-#define PIO_SM2_CLKDIV_FRAC_LSB _U(8)
+#define PIO_SM2_CLKDIV_FRAC_RESET _u(0x00)
+#define PIO_SM2_CLKDIV_FRAC_BITS _u(0x0000ff00)
+#define PIO_SM2_CLKDIV_FRAC_MSB _u(15)
+#define PIO_SM2_CLKDIV_FRAC_LSB _u(8)
#define PIO_SM2_CLKDIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : PIO_SM2_EXECCTRL
// Description : Execution/behavioural settings for state machine 2
-#define PIO_SM2_EXECCTRL_OFFSET _U(0x000000fc)
-#define PIO_SM2_EXECCTRL_BITS _U(0xffffff9f)
-#define PIO_SM2_EXECCTRL_RESET _U(0x0001f000)
+#define PIO_SM2_EXECCTRL_OFFSET _u(0x000000fc)
+#define PIO_SM2_EXECCTRL_BITS _u(0xffffff9f)
+#define PIO_SM2_EXECCTRL_RESET _u(0x0001f000)
// -----------------------------------------------------------------------------
// Field : PIO_SM2_EXECCTRL_EXEC_STALLED
// Description : If 1, an instruction written to SMx_INSTR is stalled, and
// latched by the state machine. Will clear to 0 once this
// instruction completes.
-#define PIO_SM2_EXECCTRL_EXEC_STALLED_RESET _U(0x0)
-#define PIO_SM2_EXECCTRL_EXEC_STALLED_BITS _U(0x80000000)
-#define PIO_SM2_EXECCTRL_EXEC_STALLED_MSB _U(31)
-#define PIO_SM2_EXECCTRL_EXEC_STALLED_LSB _U(31)
+#define PIO_SM2_EXECCTRL_EXEC_STALLED_RESET _u(0x0)
+#define PIO_SM2_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000)
+#define PIO_SM2_EXECCTRL_EXEC_STALLED_MSB _u(31)
+#define PIO_SM2_EXECCTRL_EXEC_STALLED_LSB _u(31)
#define PIO_SM2_EXECCTRL_EXEC_STALLED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_EXECCTRL_SIDE_EN
@@ -1431,36 +1431,36 @@
// on every instruction, but the maximum possible side-set width
// is reduced from 5 to 4. Note that the value of
// PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
-#define PIO_SM2_EXECCTRL_SIDE_EN_RESET _U(0x0)
-#define PIO_SM2_EXECCTRL_SIDE_EN_BITS _U(0x40000000)
-#define PIO_SM2_EXECCTRL_SIDE_EN_MSB _U(30)
-#define PIO_SM2_EXECCTRL_SIDE_EN_LSB _U(30)
+#define PIO_SM2_EXECCTRL_SIDE_EN_RESET _u(0x0)
+#define PIO_SM2_EXECCTRL_SIDE_EN_BITS _u(0x40000000)
+#define PIO_SM2_EXECCTRL_SIDE_EN_MSB _u(30)
+#define PIO_SM2_EXECCTRL_SIDE_EN_LSB _u(30)
#define PIO_SM2_EXECCTRL_SIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_EXECCTRL_SIDE_PINDIR
// Description : If 1, side-set data is asserted to pin directions, instead of
// pin values
-#define PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET _U(0x0)
-#define PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS _U(0x20000000)
-#define PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB _U(29)
-#define PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB _U(29)
+#define PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET _u(0x0)
+#define PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000)
+#define PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB _u(29)
+#define PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB _u(29)
#define PIO_SM2_EXECCTRL_SIDE_PINDIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_EXECCTRL_JMP_PIN
// Description : The GPIO number to use as condition for JMP PIN. Unaffected by
// input mapping.
-#define PIO_SM2_EXECCTRL_JMP_PIN_RESET _U(0x00)
-#define PIO_SM2_EXECCTRL_JMP_PIN_BITS _U(0x1f000000)
-#define PIO_SM2_EXECCTRL_JMP_PIN_MSB _U(28)
-#define PIO_SM2_EXECCTRL_JMP_PIN_LSB _U(24)
+#define PIO_SM2_EXECCTRL_JMP_PIN_RESET _u(0x00)
+#define PIO_SM2_EXECCTRL_JMP_PIN_BITS _u(0x1f000000)
+#define PIO_SM2_EXECCTRL_JMP_PIN_MSB _u(28)
+#define PIO_SM2_EXECCTRL_JMP_PIN_LSB _u(24)
#define PIO_SM2_EXECCTRL_JMP_PIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_EXECCTRL_OUT_EN_SEL
// Description : Which data bit to use for inline OUT enable
-#define PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET _U(0x00)
-#define PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS _U(0x00f80000)
-#define PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB _U(23)
-#define PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB _U(19)
+#define PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET _u(0x00)
+#define PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000)
+#define PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB _u(23)
+#define PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB _u(19)
#define PIO_SM2_EXECCTRL_OUT_EN_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_EXECCTRL_INLINE_OUT_EN
@@ -1471,18 +1471,18 @@
// masking/override behaviour
// due to the priority ordering of state machine pin writes (SM0 <
// SM1 < ...)
-#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET _U(0x0)
-#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS _U(0x00040000)
-#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB _U(18)
-#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB _U(18)
+#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0)
+#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000)
+#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB _u(18)
+#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB _u(18)
#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_EXECCTRL_OUT_STICKY
// Description : Continuously assert the most recent OUT/SET to the pins
-#define PIO_SM2_EXECCTRL_OUT_STICKY_RESET _U(0x0)
-#define PIO_SM2_EXECCTRL_OUT_STICKY_BITS _U(0x00020000)
-#define PIO_SM2_EXECCTRL_OUT_STICKY_MSB _U(17)
-#define PIO_SM2_EXECCTRL_OUT_STICKY_LSB _U(17)
+#define PIO_SM2_EXECCTRL_OUT_STICKY_RESET _u(0x0)
+#define PIO_SM2_EXECCTRL_OUT_STICKY_BITS _u(0x00020000)
+#define PIO_SM2_EXECCTRL_OUT_STICKY_MSB _u(17)
+#define PIO_SM2_EXECCTRL_OUT_STICKY_LSB _u(17)
#define PIO_SM2_EXECCTRL_OUT_STICKY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_EXECCTRL_WRAP_TOP
@@ -1490,46 +1490,46 @@
// wrap_bottom.
// If the instruction is a jump, and the jump condition is true,
// the jump takes priority.
-#define PIO_SM2_EXECCTRL_WRAP_TOP_RESET _U(0x1f)
-#define PIO_SM2_EXECCTRL_WRAP_TOP_BITS _U(0x0001f000)
-#define PIO_SM2_EXECCTRL_WRAP_TOP_MSB _U(16)
-#define PIO_SM2_EXECCTRL_WRAP_TOP_LSB _U(12)
+#define PIO_SM2_EXECCTRL_WRAP_TOP_RESET _u(0x1f)
+#define PIO_SM2_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000)
+#define PIO_SM2_EXECCTRL_WRAP_TOP_MSB _u(16)
+#define PIO_SM2_EXECCTRL_WRAP_TOP_LSB _u(12)
#define PIO_SM2_EXECCTRL_WRAP_TOP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_EXECCTRL_WRAP_BOTTOM
// Description : After reaching wrap_top, execution is wrapped to this address.
-#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET _U(0x00)
-#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS _U(0x00000f80)
-#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB _U(11)
-#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB _U(7)
+#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00)
+#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80)
+#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB _u(11)
+#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB _u(7)
#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_EXECCTRL_STATUS_SEL
// Description : Comparison used for the MOV x, STATUS instruction.
// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
-#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET _U(0x0)
-#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS _U(0x00000010)
-#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB _U(4)
-#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB _U(4)
+#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET _u(0x0)
+#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS _u(0x00000010)
+#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB _u(4)
+#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB _u(4)
#define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW"
-#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _U(0x0)
-#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _U(0x1)
+#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0)
+#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1)
// -----------------------------------------------------------------------------
// Field : PIO_SM2_EXECCTRL_STATUS_N
// Description : Comparison level for the MOV x, STATUS instruction
-#define PIO_SM2_EXECCTRL_STATUS_N_RESET _U(0x0)
-#define PIO_SM2_EXECCTRL_STATUS_N_BITS _U(0x0000000f)
-#define PIO_SM2_EXECCTRL_STATUS_N_MSB _U(3)
-#define PIO_SM2_EXECCTRL_STATUS_N_LSB _U(0)
+#define PIO_SM2_EXECCTRL_STATUS_N_RESET _u(0x0)
+#define PIO_SM2_EXECCTRL_STATUS_N_BITS _u(0x0000000f)
+#define PIO_SM2_EXECCTRL_STATUS_N_MSB _u(3)
+#define PIO_SM2_EXECCTRL_STATUS_N_LSB _u(0)
#define PIO_SM2_EXECCTRL_STATUS_N_ACCESS "RW"
// =============================================================================
// Register : PIO_SM2_SHIFTCTRL
// Description : Control behaviour of the input/output shift registers for state
// machine 2
-#define PIO_SM2_SHIFTCTRL_OFFSET _U(0x00000100)
-#define PIO_SM2_SHIFTCTRL_BITS _U(0xffff0000)
-#define PIO_SM2_SHIFTCTRL_RESET _U(0x000c0000)
+#define PIO_SM2_SHIFTCTRL_OFFSET _u(0x00000100)
+#define PIO_SM2_SHIFTCTRL_BITS _u(0xffff0000)
+#define PIO_SM2_SHIFTCTRL_RESET _u(0x000c0000)
// -----------------------------------------------------------------------------
// Field : PIO_SM2_SHIFTCTRL_FJOIN_RX
// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice
@@ -1537,10 +1537,10 @@
// TX FIFO is disabled as a result (always reads as both full and
// empty).
// FIFOs are flushed when this bit is changed.
-#define PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET _U(0x0)
-#define PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS _U(0x80000000)
-#define PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB _U(31)
-#define PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB _U(31)
+#define PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET _u(0x0)
+#define PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000)
+#define PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB _u(31)
+#define PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB _u(31)
#define PIO_SM2_SHIFTCTRL_FJOIN_RX_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_SHIFTCTRL_FJOIN_TX
@@ -1549,76 +1549,76 @@
// RX FIFO is disabled as a result (always reads as both full and
// empty).
// FIFOs are flushed when this bit is changed.
-#define PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET _U(0x0)
-#define PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS _U(0x40000000)
-#define PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB _U(30)
-#define PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB _U(30)
+#define PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET _u(0x0)
+#define PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000)
+#define PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB _u(30)
+#define PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB _u(30)
#define PIO_SM2_SHIFTCTRL_FJOIN_TX_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_SHIFTCTRL_PULL_THRESH
// Description : Number of bits shifted out of OSR before autopull, or
// conditional pull (PULL IFEMPTY), will take place.
// Write 0 for value of 32.
-#define PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET _U(0x00)
-#define PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS _U(0x3e000000)
-#define PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB _U(29)
-#define PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB _U(25)
+#define PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET _u(0x00)
+#define PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000)
+#define PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB _u(29)
+#define PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB _u(25)
#define PIO_SM2_SHIFTCTRL_PULL_THRESH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_SHIFTCTRL_PUSH_THRESH
// Description : Number of bits shifted into ISR before autopush, or conditional
// push (PUSH IFFULL), will take place.
// Write 0 for value of 32.
-#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET _U(0x00)
-#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS _U(0x01f00000)
-#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB _U(24)
-#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB _U(20)
+#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00)
+#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000)
+#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB _u(24)
+#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB _u(20)
#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR
// Description : 1 = shift out of output shift register to right. 0 = to left.
-#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET _U(0x1)
-#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS _U(0x00080000)
-#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB _U(19)
-#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB _U(19)
+#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1)
+#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000)
+#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19)
+#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19)
#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_SHIFTCTRL_IN_SHIFTDIR
// Description : 1 = shift input shift register to right (data enters from
// left). 0 = to left.
-#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET _U(0x1)
-#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS _U(0x00040000)
-#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB _U(18)
-#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB _U(18)
+#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1)
+#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000)
+#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18)
+#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18)
#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_SHIFTCTRL_AUTOPULL
// Description : Pull automatically when the output shift register is emptied,
// i.e. on or following an OUT instruction which causes the output
// shift counter to reach or exceed PULL_THRESH.
-#define PIO_SM2_SHIFTCTRL_AUTOPULL_RESET _U(0x0)
-#define PIO_SM2_SHIFTCTRL_AUTOPULL_BITS _U(0x00020000)
-#define PIO_SM2_SHIFTCTRL_AUTOPULL_MSB _U(17)
-#define PIO_SM2_SHIFTCTRL_AUTOPULL_LSB _U(17)
+#define PIO_SM2_SHIFTCTRL_AUTOPULL_RESET _u(0x0)
+#define PIO_SM2_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000)
+#define PIO_SM2_SHIFTCTRL_AUTOPULL_MSB _u(17)
+#define PIO_SM2_SHIFTCTRL_AUTOPULL_LSB _u(17)
#define PIO_SM2_SHIFTCTRL_AUTOPULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_SHIFTCTRL_AUTOPUSH
// Description : Push automatically when the input shift register is filled,
// i.e. on an IN instruction which causes the input shift counter
// to reach or exceed PUSH_THRESH.
-#define PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET _U(0x0)
-#define PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS _U(0x00010000)
-#define PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB _U(16)
-#define PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB _U(16)
+#define PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET _u(0x0)
+#define PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000)
+#define PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB _u(16)
+#define PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB _u(16)
#define PIO_SM2_SHIFTCTRL_AUTOPUSH_ACCESS "RW"
// =============================================================================
// Register : PIO_SM2_ADDR
// Description : Current instruction address of state machine 2
-#define PIO_SM2_ADDR_OFFSET _U(0x00000104)
-#define PIO_SM2_ADDR_BITS _U(0x0000001f)
-#define PIO_SM2_ADDR_RESET _U(0x00000000)
-#define PIO_SM2_ADDR_MSB _U(4)
-#define PIO_SM2_ADDR_LSB _U(0)
+#define PIO_SM2_ADDR_OFFSET _u(0x00000104)
+#define PIO_SM2_ADDR_BITS _u(0x0000001f)
+#define PIO_SM2_ADDR_RESET _u(0x00000000)
+#define PIO_SM2_ADDR_MSB _u(4)
+#define PIO_SM2_ADDR_LSB _u(0)
#define PIO_SM2_ADDR_ACCESS "RO"
// =============================================================================
// Register : PIO_SM2_INSTR
@@ -1626,46 +1626,46 @@
// machine 2's program counter
// Write to execute an instruction immediately (including jumps)
// and then resume execution.
-#define PIO_SM2_INSTR_OFFSET _U(0x00000108)
-#define PIO_SM2_INSTR_BITS _U(0x0000ffff)
+#define PIO_SM2_INSTR_OFFSET _u(0x00000108)
+#define PIO_SM2_INSTR_BITS _u(0x0000ffff)
#define PIO_SM2_INSTR_RESET "-"
-#define PIO_SM2_INSTR_MSB _U(15)
-#define PIO_SM2_INSTR_LSB _U(0)
+#define PIO_SM2_INSTR_MSB _u(15)
+#define PIO_SM2_INSTR_LSB _u(0)
#define PIO_SM2_INSTR_ACCESS "RW"
// =============================================================================
// Register : PIO_SM2_PINCTRL
// Description : State machine pin control
-#define PIO_SM2_PINCTRL_OFFSET _U(0x0000010c)
-#define PIO_SM2_PINCTRL_BITS _U(0xffffffff)
-#define PIO_SM2_PINCTRL_RESET _U(0x14000000)
+#define PIO_SM2_PINCTRL_OFFSET _u(0x0000010c)
+#define PIO_SM2_PINCTRL_BITS _u(0xffffffff)
+#define PIO_SM2_PINCTRL_RESET _u(0x14000000)
// -----------------------------------------------------------------------------
// Field : PIO_SM2_PINCTRL_SIDESET_COUNT
// Description : The number of MSBs of the Delay/Side-set instruction field
// which are used for side-set. Inclusive of the enable bit, if
// present. Minimum of 0 (all delay bits, no side-set) and maximum
// of 5 (all side-set, no delay).
-#define PIO_SM2_PINCTRL_SIDESET_COUNT_RESET _U(0x0)
-#define PIO_SM2_PINCTRL_SIDESET_COUNT_BITS _U(0xe0000000)
-#define PIO_SM2_PINCTRL_SIDESET_COUNT_MSB _U(31)
-#define PIO_SM2_PINCTRL_SIDESET_COUNT_LSB _U(29)
+#define PIO_SM2_PINCTRL_SIDESET_COUNT_RESET _u(0x0)
+#define PIO_SM2_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000)
+#define PIO_SM2_PINCTRL_SIDESET_COUNT_MSB _u(31)
+#define PIO_SM2_PINCTRL_SIDESET_COUNT_LSB _u(29)
#define PIO_SM2_PINCTRL_SIDESET_COUNT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_PINCTRL_SET_COUNT
// Description : The number of pins asserted by a SET. In the range 0 to 5
// inclusive.
-#define PIO_SM2_PINCTRL_SET_COUNT_RESET _U(0x5)
-#define PIO_SM2_PINCTRL_SET_COUNT_BITS _U(0x1c000000)
-#define PIO_SM2_PINCTRL_SET_COUNT_MSB _U(28)
-#define PIO_SM2_PINCTRL_SET_COUNT_LSB _U(26)
+#define PIO_SM2_PINCTRL_SET_COUNT_RESET _u(0x5)
+#define PIO_SM2_PINCTRL_SET_COUNT_BITS _u(0x1c000000)
+#define PIO_SM2_PINCTRL_SET_COUNT_MSB _u(28)
+#define PIO_SM2_PINCTRL_SET_COUNT_LSB _u(26)
#define PIO_SM2_PINCTRL_SET_COUNT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_PINCTRL_OUT_COUNT
// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV
// PINS instruction. In the range 0 to 32 inclusive.
-#define PIO_SM2_PINCTRL_OUT_COUNT_RESET _U(0x00)
-#define PIO_SM2_PINCTRL_OUT_COUNT_BITS _U(0x03f00000)
-#define PIO_SM2_PINCTRL_OUT_COUNT_MSB _U(25)
-#define PIO_SM2_PINCTRL_OUT_COUNT_LSB _U(20)
+#define PIO_SM2_PINCTRL_OUT_COUNT_RESET _u(0x00)
+#define PIO_SM2_PINCTRL_OUT_COUNT_BITS _u(0x03f00000)
+#define PIO_SM2_PINCTRL_OUT_COUNT_MSB _u(25)
+#define PIO_SM2_PINCTRL_OUT_COUNT_LSB _u(20)
#define PIO_SM2_PINCTRL_OUT_COUNT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_PINCTRL_IN_BASE
@@ -1673,10 +1673,10 @@
// machine's IN data bus. Higher-numbered pins are mapped to
// consecutively more-significant data bits, with a modulo of 32
// applied to pin number.
-#define PIO_SM2_PINCTRL_IN_BASE_RESET _U(0x00)
-#define PIO_SM2_PINCTRL_IN_BASE_BITS _U(0x000f8000)
-#define PIO_SM2_PINCTRL_IN_BASE_MSB _U(19)
-#define PIO_SM2_PINCTRL_IN_BASE_LSB _U(15)
+#define PIO_SM2_PINCTRL_IN_BASE_RESET _u(0x00)
+#define PIO_SM2_PINCTRL_IN_BASE_BITS _u(0x000f8000)
+#define PIO_SM2_PINCTRL_IN_BASE_MSB _u(19)
+#define PIO_SM2_PINCTRL_IN_BASE_LSB _u(15)
#define PIO_SM2_PINCTRL_IN_BASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_PINCTRL_SIDESET_BASE
@@ -1687,20 +1687,20 @@
// least-significant bit of the side-set portion is the bit
// written to this pin, with more-significant bits written to
// higher-numbered pins.
-#define PIO_SM2_PINCTRL_SIDESET_BASE_RESET _U(0x00)
-#define PIO_SM2_PINCTRL_SIDESET_BASE_BITS _U(0x00007c00)
-#define PIO_SM2_PINCTRL_SIDESET_BASE_MSB _U(14)
-#define PIO_SM2_PINCTRL_SIDESET_BASE_LSB _U(10)
+#define PIO_SM2_PINCTRL_SIDESET_BASE_RESET _u(0x00)
+#define PIO_SM2_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00)
+#define PIO_SM2_PINCTRL_SIDESET_BASE_MSB _u(14)
+#define PIO_SM2_PINCTRL_SIDESET_BASE_LSB _u(10)
#define PIO_SM2_PINCTRL_SIDESET_BASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_PINCTRL_SET_BASE
// Description : The lowest-numbered pin that will be affected by a SET PINS or
// SET PINDIRS instruction. The data written to this pin is the
// least-significant bit of the SET data.
-#define PIO_SM2_PINCTRL_SET_BASE_RESET _U(0x00)
-#define PIO_SM2_PINCTRL_SET_BASE_BITS _U(0x000003e0)
-#define PIO_SM2_PINCTRL_SET_BASE_MSB _U(9)
-#define PIO_SM2_PINCTRL_SET_BASE_LSB _U(5)
+#define PIO_SM2_PINCTRL_SET_BASE_RESET _u(0x00)
+#define PIO_SM2_PINCTRL_SET_BASE_BITS _u(0x000003e0)
+#define PIO_SM2_PINCTRL_SET_BASE_MSB _u(9)
+#define PIO_SM2_PINCTRL_SET_BASE_LSB _u(5)
#define PIO_SM2_PINCTRL_SET_BASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM2_PINCTRL_OUT_BASE
@@ -1708,51 +1708,51 @@
// OUT PINDIRS or MOV PINS instruction. The data written to this
// pin will always be the least-significant bit of the OUT or MOV
// data.
-#define PIO_SM2_PINCTRL_OUT_BASE_RESET _U(0x00)
-#define PIO_SM2_PINCTRL_OUT_BASE_BITS _U(0x0000001f)
-#define PIO_SM2_PINCTRL_OUT_BASE_MSB _U(4)
-#define PIO_SM2_PINCTRL_OUT_BASE_LSB _U(0)
+#define PIO_SM2_PINCTRL_OUT_BASE_RESET _u(0x00)
+#define PIO_SM2_PINCTRL_OUT_BASE_BITS _u(0x0000001f)
+#define PIO_SM2_PINCTRL_OUT_BASE_MSB _u(4)
+#define PIO_SM2_PINCTRL_OUT_BASE_LSB _u(0)
#define PIO_SM2_PINCTRL_OUT_BASE_ACCESS "RW"
// =============================================================================
// Register : PIO_SM3_CLKDIV
// Description : Clock divisor register for state machine 3
// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
-#define PIO_SM3_CLKDIV_OFFSET _U(0x00000110)
-#define PIO_SM3_CLKDIV_BITS _U(0xffffff00)
-#define PIO_SM3_CLKDIV_RESET _U(0x00010000)
+#define PIO_SM3_CLKDIV_OFFSET _u(0x00000110)
+#define PIO_SM3_CLKDIV_BITS _u(0xffffff00)
+#define PIO_SM3_CLKDIV_RESET _u(0x00010000)
// -----------------------------------------------------------------------------
// Field : PIO_SM3_CLKDIV_INT
// Description : Effective frequency is sysclk/(int + frac/256).
// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also
// be 0.
-#define PIO_SM3_CLKDIV_INT_RESET _U(0x0001)
-#define PIO_SM3_CLKDIV_INT_BITS _U(0xffff0000)
-#define PIO_SM3_CLKDIV_INT_MSB _U(31)
-#define PIO_SM3_CLKDIV_INT_LSB _U(16)
+#define PIO_SM3_CLKDIV_INT_RESET _u(0x0001)
+#define PIO_SM3_CLKDIV_INT_BITS _u(0xffff0000)
+#define PIO_SM3_CLKDIV_INT_MSB _u(31)
+#define PIO_SM3_CLKDIV_INT_LSB _u(16)
#define PIO_SM3_CLKDIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_CLKDIV_FRAC
// Description : Fractional part of clock divisor
-#define PIO_SM3_CLKDIV_FRAC_RESET _U(0x00)
-#define PIO_SM3_CLKDIV_FRAC_BITS _U(0x0000ff00)
-#define PIO_SM3_CLKDIV_FRAC_MSB _U(15)
-#define PIO_SM3_CLKDIV_FRAC_LSB _U(8)
+#define PIO_SM3_CLKDIV_FRAC_RESET _u(0x00)
+#define PIO_SM3_CLKDIV_FRAC_BITS _u(0x0000ff00)
+#define PIO_SM3_CLKDIV_FRAC_MSB _u(15)
+#define PIO_SM3_CLKDIV_FRAC_LSB _u(8)
#define PIO_SM3_CLKDIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : PIO_SM3_EXECCTRL
// Description : Execution/behavioural settings for state machine 3
-#define PIO_SM3_EXECCTRL_OFFSET _U(0x00000114)
-#define PIO_SM3_EXECCTRL_BITS _U(0xffffff9f)
-#define PIO_SM3_EXECCTRL_RESET _U(0x0001f000)
+#define PIO_SM3_EXECCTRL_OFFSET _u(0x00000114)
+#define PIO_SM3_EXECCTRL_BITS _u(0xffffff9f)
+#define PIO_SM3_EXECCTRL_RESET _u(0x0001f000)
// -----------------------------------------------------------------------------
// Field : PIO_SM3_EXECCTRL_EXEC_STALLED
// Description : If 1, an instruction written to SMx_INSTR is stalled, and
// latched by the state machine. Will clear to 0 once this
// instruction completes.
-#define PIO_SM3_EXECCTRL_EXEC_STALLED_RESET _U(0x0)
-#define PIO_SM3_EXECCTRL_EXEC_STALLED_BITS _U(0x80000000)
-#define PIO_SM3_EXECCTRL_EXEC_STALLED_MSB _U(31)
-#define PIO_SM3_EXECCTRL_EXEC_STALLED_LSB _U(31)
+#define PIO_SM3_EXECCTRL_EXEC_STALLED_RESET _u(0x0)
+#define PIO_SM3_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000)
+#define PIO_SM3_EXECCTRL_EXEC_STALLED_MSB _u(31)
+#define PIO_SM3_EXECCTRL_EXEC_STALLED_LSB _u(31)
#define PIO_SM3_EXECCTRL_EXEC_STALLED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_EXECCTRL_SIDE_EN
@@ -1762,36 +1762,36 @@
// on every instruction, but the maximum possible side-set width
// is reduced from 5 to 4. Note that the value of
// PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
-#define PIO_SM3_EXECCTRL_SIDE_EN_RESET _U(0x0)
-#define PIO_SM3_EXECCTRL_SIDE_EN_BITS _U(0x40000000)
-#define PIO_SM3_EXECCTRL_SIDE_EN_MSB _U(30)
-#define PIO_SM3_EXECCTRL_SIDE_EN_LSB _U(30)
+#define PIO_SM3_EXECCTRL_SIDE_EN_RESET _u(0x0)
+#define PIO_SM3_EXECCTRL_SIDE_EN_BITS _u(0x40000000)
+#define PIO_SM3_EXECCTRL_SIDE_EN_MSB _u(30)
+#define PIO_SM3_EXECCTRL_SIDE_EN_LSB _u(30)
#define PIO_SM3_EXECCTRL_SIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_EXECCTRL_SIDE_PINDIR
// Description : If 1, side-set data is asserted to pin directions, instead of
// pin values
-#define PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET _U(0x0)
-#define PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS _U(0x20000000)
-#define PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB _U(29)
-#define PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB _U(29)
+#define PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET _u(0x0)
+#define PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000)
+#define PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB _u(29)
+#define PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB _u(29)
#define PIO_SM3_EXECCTRL_SIDE_PINDIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_EXECCTRL_JMP_PIN
// Description : The GPIO number to use as condition for JMP PIN. Unaffected by
// input mapping.
-#define PIO_SM3_EXECCTRL_JMP_PIN_RESET _U(0x00)
-#define PIO_SM3_EXECCTRL_JMP_PIN_BITS _U(0x1f000000)
-#define PIO_SM3_EXECCTRL_JMP_PIN_MSB _U(28)
-#define PIO_SM3_EXECCTRL_JMP_PIN_LSB _U(24)
+#define PIO_SM3_EXECCTRL_JMP_PIN_RESET _u(0x00)
+#define PIO_SM3_EXECCTRL_JMP_PIN_BITS _u(0x1f000000)
+#define PIO_SM3_EXECCTRL_JMP_PIN_MSB _u(28)
+#define PIO_SM3_EXECCTRL_JMP_PIN_LSB _u(24)
#define PIO_SM3_EXECCTRL_JMP_PIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_EXECCTRL_OUT_EN_SEL
// Description : Which data bit to use for inline OUT enable
-#define PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET _U(0x00)
-#define PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS _U(0x00f80000)
-#define PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB _U(23)
-#define PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB _U(19)
+#define PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET _u(0x00)
+#define PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000)
+#define PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB _u(23)
+#define PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB _u(19)
#define PIO_SM3_EXECCTRL_OUT_EN_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_EXECCTRL_INLINE_OUT_EN
@@ -1802,18 +1802,18 @@
// masking/override behaviour
// due to the priority ordering of state machine pin writes (SM0 <
// SM1 < ...)
-#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET _U(0x0)
-#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS _U(0x00040000)
-#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB _U(18)
-#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB _U(18)
+#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0)
+#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000)
+#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB _u(18)
+#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB _u(18)
#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_EXECCTRL_OUT_STICKY
// Description : Continuously assert the most recent OUT/SET to the pins
-#define PIO_SM3_EXECCTRL_OUT_STICKY_RESET _U(0x0)
-#define PIO_SM3_EXECCTRL_OUT_STICKY_BITS _U(0x00020000)
-#define PIO_SM3_EXECCTRL_OUT_STICKY_MSB _U(17)
-#define PIO_SM3_EXECCTRL_OUT_STICKY_LSB _U(17)
+#define PIO_SM3_EXECCTRL_OUT_STICKY_RESET _u(0x0)
+#define PIO_SM3_EXECCTRL_OUT_STICKY_BITS _u(0x00020000)
+#define PIO_SM3_EXECCTRL_OUT_STICKY_MSB _u(17)
+#define PIO_SM3_EXECCTRL_OUT_STICKY_LSB _u(17)
#define PIO_SM3_EXECCTRL_OUT_STICKY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_EXECCTRL_WRAP_TOP
@@ -1821,46 +1821,46 @@
// wrap_bottom.
// If the instruction is a jump, and the jump condition is true,
// the jump takes priority.
-#define PIO_SM3_EXECCTRL_WRAP_TOP_RESET _U(0x1f)
-#define PIO_SM3_EXECCTRL_WRAP_TOP_BITS _U(0x0001f000)
-#define PIO_SM3_EXECCTRL_WRAP_TOP_MSB _U(16)
-#define PIO_SM3_EXECCTRL_WRAP_TOP_LSB _U(12)
+#define PIO_SM3_EXECCTRL_WRAP_TOP_RESET _u(0x1f)
+#define PIO_SM3_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000)
+#define PIO_SM3_EXECCTRL_WRAP_TOP_MSB _u(16)
+#define PIO_SM3_EXECCTRL_WRAP_TOP_LSB _u(12)
#define PIO_SM3_EXECCTRL_WRAP_TOP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_EXECCTRL_WRAP_BOTTOM
// Description : After reaching wrap_top, execution is wrapped to this address.
-#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET _U(0x00)
-#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS _U(0x00000f80)
-#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB _U(11)
-#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB _U(7)
+#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00)
+#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80)
+#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB _u(11)
+#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB _u(7)
#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_EXECCTRL_STATUS_SEL
// Description : Comparison used for the MOV x, STATUS instruction.
// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
-#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET _U(0x0)
-#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS _U(0x00000010)
-#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB _U(4)
-#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB _U(4)
+#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET _u(0x0)
+#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS _u(0x00000010)
+#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB _u(4)
+#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB _u(4)
#define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW"
-#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _U(0x0)
-#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _U(0x1)
+#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0)
+#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1)
// -----------------------------------------------------------------------------
// Field : PIO_SM3_EXECCTRL_STATUS_N
// Description : Comparison level for the MOV x, STATUS instruction
-#define PIO_SM3_EXECCTRL_STATUS_N_RESET _U(0x0)
-#define PIO_SM3_EXECCTRL_STATUS_N_BITS _U(0x0000000f)
-#define PIO_SM3_EXECCTRL_STATUS_N_MSB _U(3)
-#define PIO_SM3_EXECCTRL_STATUS_N_LSB _U(0)
+#define PIO_SM3_EXECCTRL_STATUS_N_RESET _u(0x0)
+#define PIO_SM3_EXECCTRL_STATUS_N_BITS _u(0x0000000f)
+#define PIO_SM3_EXECCTRL_STATUS_N_MSB _u(3)
+#define PIO_SM3_EXECCTRL_STATUS_N_LSB _u(0)
#define PIO_SM3_EXECCTRL_STATUS_N_ACCESS "RW"
// =============================================================================
// Register : PIO_SM3_SHIFTCTRL
// Description : Control behaviour of the input/output shift registers for state
// machine 3
-#define PIO_SM3_SHIFTCTRL_OFFSET _U(0x00000118)
-#define PIO_SM3_SHIFTCTRL_BITS _U(0xffff0000)
-#define PIO_SM3_SHIFTCTRL_RESET _U(0x000c0000)
+#define PIO_SM3_SHIFTCTRL_OFFSET _u(0x00000118)
+#define PIO_SM3_SHIFTCTRL_BITS _u(0xffff0000)
+#define PIO_SM3_SHIFTCTRL_RESET _u(0x000c0000)
// -----------------------------------------------------------------------------
// Field : PIO_SM3_SHIFTCTRL_FJOIN_RX
// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice
@@ -1868,10 +1868,10 @@
// TX FIFO is disabled as a result (always reads as both full and
// empty).
// FIFOs are flushed when this bit is changed.
-#define PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET _U(0x0)
-#define PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS _U(0x80000000)
-#define PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB _U(31)
-#define PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB _U(31)
+#define PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET _u(0x0)
+#define PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000)
+#define PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB _u(31)
+#define PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB _u(31)
#define PIO_SM3_SHIFTCTRL_FJOIN_RX_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_SHIFTCTRL_FJOIN_TX
@@ -1880,76 +1880,76 @@
// RX FIFO is disabled as a result (always reads as both full and
// empty).
// FIFOs are flushed when this bit is changed.
-#define PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET _U(0x0)
-#define PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS _U(0x40000000)
-#define PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB _U(30)
-#define PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB _U(30)
+#define PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET _u(0x0)
+#define PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000)
+#define PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB _u(30)
+#define PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB _u(30)
#define PIO_SM3_SHIFTCTRL_FJOIN_TX_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_SHIFTCTRL_PULL_THRESH
// Description : Number of bits shifted out of OSR before autopull, or
// conditional pull (PULL IFEMPTY), will take place.
// Write 0 for value of 32.
-#define PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET _U(0x00)
-#define PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS _U(0x3e000000)
-#define PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB _U(29)
-#define PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB _U(25)
+#define PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET _u(0x00)
+#define PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000)
+#define PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB _u(29)
+#define PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB _u(25)
#define PIO_SM3_SHIFTCTRL_PULL_THRESH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_SHIFTCTRL_PUSH_THRESH
// Description : Number of bits shifted into ISR before autopush, or conditional
// push (PUSH IFFULL), will take place.
// Write 0 for value of 32.
-#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET _U(0x00)
-#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS _U(0x01f00000)
-#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB _U(24)
-#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB _U(20)
+#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00)
+#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000)
+#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB _u(24)
+#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB _u(20)
#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR
// Description : 1 = shift out of output shift register to right. 0 = to left.
-#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET _U(0x1)
-#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS _U(0x00080000)
-#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB _U(19)
-#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB _U(19)
+#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1)
+#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000)
+#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19)
+#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19)
#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_SHIFTCTRL_IN_SHIFTDIR
// Description : 1 = shift input shift register to right (data enters from
// left). 0 = to left.
-#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET _U(0x1)
-#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS _U(0x00040000)
-#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB _U(18)
-#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB _U(18)
+#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1)
+#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000)
+#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18)
+#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18)
#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_SHIFTCTRL_AUTOPULL
// Description : Pull automatically when the output shift register is emptied,
// i.e. on or following an OUT instruction which causes the output
// shift counter to reach or exceed PULL_THRESH.
-#define PIO_SM3_SHIFTCTRL_AUTOPULL_RESET _U(0x0)
-#define PIO_SM3_SHIFTCTRL_AUTOPULL_BITS _U(0x00020000)
-#define PIO_SM3_SHIFTCTRL_AUTOPULL_MSB _U(17)
-#define PIO_SM3_SHIFTCTRL_AUTOPULL_LSB _U(17)
+#define PIO_SM3_SHIFTCTRL_AUTOPULL_RESET _u(0x0)
+#define PIO_SM3_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000)
+#define PIO_SM3_SHIFTCTRL_AUTOPULL_MSB _u(17)
+#define PIO_SM3_SHIFTCTRL_AUTOPULL_LSB _u(17)
#define PIO_SM3_SHIFTCTRL_AUTOPULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_SHIFTCTRL_AUTOPUSH
// Description : Push automatically when the input shift register is filled,
// i.e. on an IN instruction which causes the input shift counter
// to reach or exceed PUSH_THRESH.
-#define PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET _U(0x0)
-#define PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS _U(0x00010000)
-#define PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB _U(16)
-#define PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB _U(16)
+#define PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET _u(0x0)
+#define PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000)
+#define PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB _u(16)
+#define PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB _u(16)
#define PIO_SM3_SHIFTCTRL_AUTOPUSH_ACCESS "RW"
// =============================================================================
// Register : PIO_SM3_ADDR
// Description : Current instruction address of state machine 3
-#define PIO_SM3_ADDR_OFFSET _U(0x0000011c)
-#define PIO_SM3_ADDR_BITS _U(0x0000001f)
-#define PIO_SM3_ADDR_RESET _U(0x00000000)
-#define PIO_SM3_ADDR_MSB _U(4)
-#define PIO_SM3_ADDR_LSB _U(0)
+#define PIO_SM3_ADDR_OFFSET _u(0x0000011c)
+#define PIO_SM3_ADDR_BITS _u(0x0000001f)
+#define PIO_SM3_ADDR_RESET _u(0x00000000)
+#define PIO_SM3_ADDR_MSB _u(4)
+#define PIO_SM3_ADDR_LSB _u(0)
#define PIO_SM3_ADDR_ACCESS "RO"
// =============================================================================
// Register : PIO_SM3_INSTR
@@ -1957,46 +1957,46 @@
// machine 3's program counter
// Write to execute an instruction immediately (including jumps)
// and then resume execution.
-#define PIO_SM3_INSTR_OFFSET _U(0x00000120)
-#define PIO_SM3_INSTR_BITS _U(0x0000ffff)
+#define PIO_SM3_INSTR_OFFSET _u(0x00000120)
+#define PIO_SM3_INSTR_BITS _u(0x0000ffff)
#define PIO_SM3_INSTR_RESET "-"
-#define PIO_SM3_INSTR_MSB _U(15)
-#define PIO_SM3_INSTR_LSB _U(0)
+#define PIO_SM3_INSTR_MSB _u(15)
+#define PIO_SM3_INSTR_LSB _u(0)
#define PIO_SM3_INSTR_ACCESS "RW"
// =============================================================================
// Register : PIO_SM3_PINCTRL
// Description : State machine pin control
-#define PIO_SM3_PINCTRL_OFFSET _U(0x00000124)
-#define PIO_SM3_PINCTRL_BITS _U(0xffffffff)
-#define PIO_SM3_PINCTRL_RESET _U(0x14000000)
+#define PIO_SM3_PINCTRL_OFFSET _u(0x00000124)
+#define PIO_SM3_PINCTRL_BITS _u(0xffffffff)
+#define PIO_SM3_PINCTRL_RESET _u(0x14000000)
// -----------------------------------------------------------------------------
// Field : PIO_SM3_PINCTRL_SIDESET_COUNT
// Description : The number of MSBs of the Delay/Side-set instruction field
// which are used for side-set. Inclusive of the enable bit, if
// present. Minimum of 0 (all delay bits, no side-set) and maximum
// of 5 (all side-set, no delay).
-#define PIO_SM3_PINCTRL_SIDESET_COUNT_RESET _U(0x0)
-#define PIO_SM3_PINCTRL_SIDESET_COUNT_BITS _U(0xe0000000)
-#define PIO_SM3_PINCTRL_SIDESET_COUNT_MSB _U(31)
-#define PIO_SM3_PINCTRL_SIDESET_COUNT_LSB _U(29)
+#define PIO_SM3_PINCTRL_SIDESET_COUNT_RESET _u(0x0)
+#define PIO_SM3_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000)
+#define PIO_SM3_PINCTRL_SIDESET_COUNT_MSB _u(31)
+#define PIO_SM3_PINCTRL_SIDESET_COUNT_LSB _u(29)
#define PIO_SM3_PINCTRL_SIDESET_COUNT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_PINCTRL_SET_COUNT
// Description : The number of pins asserted by a SET. In the range 0 to 5
// inclusive.
-#define PIO_SM3_PINCTRL_SET_COUNT_RESET _U(0x5)
-#define PIO_SM3_PINCTRL_SET_COUNT_BITS _U(0x1c000000)
-#define PIO_SM3_PINCTRL_SET_COUNT_MSB _U(28)
-#define PIO_SM3_PINCTRL_SET_COUNT_LSB _U(26)
+#define PIO_SM3_PINCTRL_SET_COUNT_RESET _u(0x5)
+#define PIO_SM3_PINCTRL_SET_COUNT_BITS _u(0x1c000000)
+#define PIO_SM3_PINCTRL_SET_COUNT_MSB _u(28)
+#define PIO_SM3_PINCTRL_SET_COUNT_LSB _u(26)
#define PIO_SM3_PINCTRL_SET_COUNT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_PINCTRL_OUT_COUNT
// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV
// PINS instruction. In the range 0 to 32 inclusive.
-#define PIO_SM3_PINCTRL_OUT_COUNT_RESET _U(0x00)
-#define PIO_SM3_PINCTRL_OUT_COUNT_BITS _U(0x03f00000)
-#define PIO_SM3_PINCTRL_OUT_COUNT_MSB _U(25)
-#define PIO_SM3_PINCTRL_OUT_COUNT_LSB _U(20)
+#define PIO_SM3_PINCTRL_OUT_COUNT_RESET _u(0x00)
+#define PIO_SM3_PINCTRL_OUT_COUNT_BITS _u(0x03f00000)
+#define PIO_SM3_PINCTRL_OUT_COUNT_MSB _u(25)
+#define PIO_SM3_PINCTRL_OUT_COUNT_LSB _u(20)
#define PIO_SM3_PINCTRL_OUT_COUNT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_PINCTRL_IN_BASE
@@ -2004,10 +2004,10 @@
// machine's IN data bus. Higher-numbered pins are mapped to
// consecutively more-significant data bits, with a modulo of 32
// applied to pin number.
-#define PIO_SM3_PINCTRL_IN_BASE_RESET _U(0x00)
-#define PIO_SM3_PINCTRL_IN_BASE_BITS _U(0x000f8000)
-#define PIO_SM3_PINCTRL_IN_BASE_MSB _U(19)
-#define PIO_SM3_PINCTRL_IN_BASE_LSB _U(15)
+#define PIO_SM3_PINCTRL_IN_BASE_RESET _u(0x00)
+#define PIO_SM3_PINCTRL_IN_BASE_BITS _u(0x000f8000)
+#define PIO_SM3_PINCTRL_IN_BASE_MSB _u(19)
+#define PIO_SM3_PINCTRL_IN_BASE_LSB _u(15)
#define PIO_SM3_PINCTRL_IN_BASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_PINCTRL_SIDESET_BASE
@@ -2018,20 +2018,20 @@
// least-significant bit of the side-set portion is the bit
// written to this pin, with more-significant bits written to
// higher-numbered pins.
-#define PIO_SM3_PINCTRL_SIDESET_BASE_RESET _U(0x00)
-#define PIO_SM3_PINCTRL_SIDESET_BASE_BITS _U(0x00007c00)
-#define PIO_SM3_PINCTRL_SIDESET_BASE_MSB _U(14)
-#define PIO_SM3_PINCTRL_SIDESET_BASE_LSB _U(10)
+#define PIO_SM3_PINCTRL_SIDESET_BASE_RESET _u(0x00)
+#define PIO_SM3_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00)
+#define PIO_SM3_PINCTRL_SIDESET_BASE_MSB _u(14)
+#define PIO_SM3_PINCTRL_SIDESET_BASE_LSB _u(10)
#define PIO_SM3_PINCTRL_SIDESET_BASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_PINCTRL_SET_BASE
// Description : The lowest-numbered pin that will be affected by a SET PINS or
// SET PINDIRS instruction. The data written to this pin is the
// least-significant bit of the SET data.
-#define PIO_SM3_PINCTRL_SET_BASE_RESET _U(0x00)
-#define PIO_SM3_PINCTRL_SET_BASE_BITS _U(0x000003e0)
-#define PIO_SM3_PINCTRL_SET_BASE_MSB _U(9)
-#define PIO_SM3_PINCTRL_SET_BASE_LSB _U(5)
+#define PIO_SM3_PINCTRL_SET_BASE_RESET _u(0x00)
+#define PIO_SM3_PINCTRL_SET_BASE_BITS _u(0x000003e0)
+#define PIO_SM3_PINCTRL_SET_BASE_MSB _u(9)
+#define PIO_SM3_PINCTRL_SET_BASE_LSB _u(5)
#define PIO_SM3_PINCTRL_SET_BASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_SM3_PINCTRL_OUT_BASE
@@ -2039,724 +2039,724 @@
// OUT PINDIRS or MOV PINS instruction. The data written to this
// pin will always be the least-significant bit of the OUT or MOV
// data.
-#define PIO_SM3_PINCTRL_OUT_BASE_RESET _U(0x00)
-#define PIO_SM3_PINCTRL_OUT_BASE_BITS _U(0x0000001f)
-#define PIO_SM3_PINCTRL_OUT_BASE_MSB _U(4)
-#define PIO_SM3_PINCTRL_OUT_BASE_LSB _U(0)
+#define PIO_SM3_PINCTRL_OUT_BASE_RESET _u(0x00)
+#define PIO_SM3_PINCTRL_OUT_BASE_BITS _u(0x0000001f)
+#define PIO_SM3_PINCTRL_OUT_BASE_MSB _u(4)
+#define PIO_SM3_PINCTRL_OUT_BASE_LSB _u(0)
#define PIO_SM3_PINCTRL_OUT_BASE_ACCESS "RW"
// =============================================================================
// Register : PIO_INTR
// Description : Raw Interrupts
-#define PIO_INTR_OFFSET _U(0x00000128)
-#define PIO_INTR_BITS _U(0x00000fff)
-#define PIO_INTR_RESET _U(0x00000000)
+#define PIO_INTR_OFFSET _u(0x00000128)
+#define PIO_INTR_BITS _u(0x00000fff)
+#define PIO_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM3
// Description : None
-#define PIO_INTR_SM3_RESET _U(0x0)
-#define PIO_INTR_SM3_BITS _U(0x00000800)
-#define PIO_INTR_SM3_MSB _U(11)
-#define PIO_INTR_SM3_LSB _U(11)
+#define PIO_INTR_SM3_RESET _u(0x0)
+#define PIO_INTR_SM3_BITS _u(0x00000800)
+#define PIO_INTR_SM3_MSB _u(11)
+#define PIO_INTR_SM3_LSB _u(11)
#define PIO_INTR_SM3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM2
// Description : None
-#define PIO_INTR_SM2_RESET _U(0x0)
-#define PIO_INTR_SM2_BITS _U(0x00000400)
-#define PIO_INTR_SM2_MSB _U(10)
-#define PIO_INTR_SM2_LSB _U(10)
+#define PIO_INTR_SM2_RESET _u(0x0)
+#define PIO_INTR_SM2_BITS _u(0x00000400)
+#define PIO_INTR_SM2_MSB _u(10)
+#define PIO_INTR_SM2_LSB _u(10)
#define PIO_INTR_SM2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM1
// Description : None
-#define PIO_INTR_SM1_RESET _U(0x0)
-#define PIO_INTR_SM1_BITS _U(0x00000200)
-#define PIO_INTR_SM1_MSB _U(9)
-#define PIO_INTR_SM1_LSB _U(9)
+#define PIO_INTR_SM1_RESET _u(0x0)
+#define PIO_INTR_SM1_BITS _u(0x00000200)
+#define PIO_INTR_SM1_MSB _u(9)
+#define PIO_INTR_SM1_LSB _u(9)
#define PIO_INTR_SM1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM0
// Description : None
-#define PIO_INTR_SM0_RESET _U(0x0)
-#define PIO_INTR_SM0_BITS _U(0x00000100)
-#define PIO_INTR_SM0_MSB _U(8)
-#define PIO_INTR_SM0_LSB _U(8)
+#define PIO_INTR_SM0_RESET _u(0x0)
+#define PIO_INTR_SM0_BITS _u(0x00000100)
+#define PIO_INTR_SM0_MSB _u(8)
+#define PIO_INTR_SM0_LSB _u(8)
#define PIO_INTR_SM0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM3_TXNFULL
// Description : None
-#define PIO_INTR_SM3_TXNFULL_RESET _U(0x0)
-#define PIO_INTR_SM3_TXNFULL_BITS _U(0x00000080)
-#define PIO_INTR_SM3_TXNFULL_MSB _U(7)
-#define PIO_INTR_SM3_TXNFULL_LSB _U(7)
+#define PIO_INTR_SM3_TXNFULL_RESET _u(0x0)
+#define PIO_INTR_SM3_TXNFULL_BITS _u(0x00000080)
+#define PIO_INTR_SM3_TXNFULL_MSB _u(7)
+#define PIO_INTR_SM3_TXNFULL_LSB _u(7)
#define PIO_INTR_SM3_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM2_TXNFULL
// Description : None
-#define PIO_INTR_SM2_TXNFULL_RESET _U(0x0)
-#define PIO_INTR_SM2_TXNFULL_BITS _U(0x00000040)
-#define PIO_INTR_SM2_TXNFULL_MSB _U(6)
-#define PIO_INTR_SM2_TXNFULL_LSB _U(6)
+#define PIO_INTR_SM2_TXNFULL_RESET _u(0x0)
+#define PIO_INTR_SM2_TXNFULL_BITS _u(0x00000040)
+#define PIO_INTR_SM2_TXNFULL_MSB _u(6)
+#define PIO_INTR_SM2_TXNFULL_LSB _u(6)
#define PIO_INTR_SM2_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM1_TXNFULL
// Description : None
-#define PIO_INTR_SM1_TXNFULL_RESET _U(0x0)
-#define PIO_INTR_SM1_TXNFULL_BITS _U(0x00000020)
-#define PIO_INTR_SM1_TXNFULL_MSB _U(5)
-#define PIO_INTR_SM1_TXNFULL_LSB _U(5)
+#define PIO_INTR_SM1_TXNFULL_RESET _u(0x0)
+#define PIO_INTR_SM1_TXNFULL_BITS _u(0x00000020)
+#define PIO_INTR_SM1_TXNFULL_MSB _u(5)
+#define PIO_INTR_SM1_TXNFULL_LSB _u(5)
#define PIO_INTR_SM1_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM0_TXNFULL
// Description : None
-#define PIO_INTR_SM0_TXNFULL_RESET _U(0x0)
-#define PIO_INTR_SM0_TXNFULL_BITS _U(0x00000010)
-#define PIO_INTR_SM0_TXNFULL_MSB _U(4)
-#define PIO_INTR_SM0_TXNFULL_LSB _U(4)
+#define PIO_INTR_SM0_TXNFULL_RESET _u(0x0)
+#define PIO_INTR_SM0_TXNFULL_BITS _u(0x00000010)
+#define PIO_INTR_SM0_TXNFULL_MSB _u(4)
+#define PIO_INTR_SM0_TXNFULL_LSB _u(4)
#define PIO_INTR_SM0_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM3_RXNEMPTY
// Description : None
-#define PIO_INTR_SM3_RXNEMPTY_RESET _U(0x0)
-#define PIO_INTR_SM3_RXNEMPTY_BITS _U(0x00000008)
-#define PIO_INTR_SM3_RXNEMPTY_MSB _U(3)
-#define PIO_INTR_SM3_RXNEMPTY_LSB _U(3)
+#define PIO_INTR_SM3_RXNEMPTY_RESET _u(0x0)
+#define PIO_INTR_SM3_RXNEMPTY_BITS _u(0x00000008)
+#define PIO_INTR_SM3_RXNEMPTY_MSB _u(3)
+#define PIO_INTR_SM3_RXNEMPTY_LSB _u(3)
#define PIO_INTR_SM3_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM2_RXNEMPTY
// Description : None
-#define PIO_INTR_SM2_RXNEMPTY_RESET _U(0x0)
-#define PIO_INTR_SM2_RXNEMPTY_BITS _U(0x00000004)
-#define PIO_INTR_SM2_RXNEMPTY_MSB _U(2)
-#define PIO_INTR_SM2_RXNEMPTY_LSB _U(2)
+#define PIO_INTR_SM2_RXNEMPTY_RESET _u(0x0)
+#define PIO_INTR_SM2_RXNEMPTY_BITS _u(0x00000004)
+#define PIO_INTR_SM2_RXNEMPTY_MSB _u(2)
+#define PIO_INTR_SM2_RXNEMPTY_LSB _u(2)
#define PIO_INTR_SM2_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM1_RXNEMPTY
// Description : None
-#define PIO_INTR_SM1_RXNEMPTY_RESET _U(0x0)
-#define PIO_INTR_SM1_RXNEMPTY_BITS _U(0x00000002)
-#define PIO_INTR_SM1_RXNEMPTY_MSB _U(1)
-#define PIO_INTR_SM1_RXNEMPTY_LSB _U(1)
+#define PIO_INTR_SM1_RXNEMPTY_RESET _u(0x0)
+#define PIO_INTR_SM1_RXNEMPTY_BITS _u(0x00000002)
+#define PIO_INTR_SM1_RXNEMPTY_MSB _u(1)
+#define PIO_INTR_SM1_RXNEMPTY_LSB _u(1)
#define PIO_INTR_SM1_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM0_RXNEMPTY
// Description : None
-#define PIO_INTR_SM0_RXNEMPTY_RESET _U(0x0)
-#define PIO_INTR_SM0_RXNEMPTY_BITS _U(0x00000001)
-#define PIO_INTR_SM0_RXNEMPTY_MSB _U(0)
-#define PIO_INTR_SM0_RXNEMPTY_LSB _U(0)
+#define PIO_INTR_SM0_RXNEMPTY_RESET _u(0x0)
+#define PIO_INTR_SM0_RXNEMPTY_BITS _u(0x00000001)
+#define PIO_INTR_SM0_RXNEMPTY_MSB _u(0)
+#define PIO_INTR_SM0_RXNEMPTY_LSB _u(0)
#define PIO_INTR_SM0_RXNEMPTY_ACCESS "RO"
// =============================================================================
// Register : PIO_IRQ0_INTE
// Description : Interrupt Enable for irq0
-#define PIO_IRQ0_INTE_OFFSET _U(0x0000012c)
-#define PIO_IRQ0_INTE_BITS _U(0x00000fff)
-#define PIO_IRQ0_INTE_RESET _U(0x00000000)
+#define PIO_IRQ0_INTE_OFFSET _u(0x0000012c)
+#define PIO_IRQ0_INTE_BITS _u(0x00000fff)
+#define PIO_IRQ0_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM3
// Description : None
-#define PIO_IRQ0_INTE_SM3_RESET _U(0x0)
-#define PIO_IRQ0_INTE_SM3_BITS _U(0x00000800)
-#define PIO_IRQ0_INTE_SM3_MSB _U(11)
-#define PIO_IRQ0_INTE_SM3_LSB _U(11)
+#define PIO_IRQ0_INTE_SM3_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM3_BITS _u(0x00000800)
+#define PIO_IRQ0_INTE_SM3_MSB _u(11)
+#define PIO_IRQ0_INTE_SM3_LSB _u(11)
#define PIO_IRQ0_INTE_SM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM2
// Description : None
-#define PIO_IRQ0_INTE_SM2_RESET _U(0x0)
-#define PIO_IRQ0_INTE_SM2_BITS _U(0x00000400)
-#define PIO_IRQ0_INTE_SM2_MSB _U(10)
-#define PIO_IRQ0_INTE_SM2_LSB _U(10)
+#define PIO_IRQ0_INTE_SM2_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM2_BITS _u(0x00000400)
+#define PIO_IRQ0_INTE_SM2_MSB _u(10)
+#define PIO_IRQ0_INTE_SM2_LSB _u(10)
#define PIO_IRQ0_INTE_SM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM1
// Description : None
-#define PIO_IRQ0_INTE_SM1_RESET _U(0x0)
-#define PIO_IRQ0_INTE_SM1_BITS _U(0x00000200)
-#define PIO_IRQ0_INTE_SM1_MSB _U(9)
-#define PIO_IRQ0_INTE_SM1_LSB _U(9)
+#define PIO_IRQ0_INTE_SM1_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM1_BITS _u(0x00000200)
+#define PIO_IRQ0_INTE_SM1_MSB _u(9)
+#define PIO_IRQ0_INTE_SM1_LSB _u(9)
#define PIO_IRQ0_INTE_SM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM0
// Description : None
-#define PIO_IRQ0_INTE_SM0_RESET _U(0x0)
-#define PIO_IRQ0_INTE_SM0_BITS _U(0x00000100)
-#define PIO_IRQ0_INTE_SM0_MSB _U(8)
-#define PIO_IRQ0_INTE_SM0_LSB _U(8)
+#define PIO_IRQ0_INTE_SM0_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM0_BITS _u(0x00000100)
+#define PIO_IRQ0_INTE_SM0_MSB _u(8)
+#define PIO_IRQ0_INTE_SM0_LSB _u(8)
#define PIO_IRQ0_INTE_SM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM3_TXNFULL
// Description : None
-#define PIO_IRQ0_INTE_SM3_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ0_INTE_SM3_TXNFULL_BITS _U(0x00000080)
-#define PIO_IRQ0_INTE_SM3_TXNFULL_MSB _U(7)
-#define PIO_IRQ0_INTE_SM3_TXNFULL_LSB _U(7)
+#define PIO_IRQ0_INTE_SM3_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM3_TXNFULL_BITS _u(0x00000080)
+#define PIO_IRQ0_INTE_SM3_TXNFULL_MSB _u(7)
+#define PIO_IRQ0_INTE_SM3_TXNFULL_LSB _u(7)
#define PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM2_TXNFULL
// Description : None
-#define PIO_IRQ0_INTE_SM2_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ0_INTE_SM2_TXNFULL_BITS _U(0x00000040)
-#define PIO_IRQ0_INTE_SM2_TXNFULL_MSB _U(6)
-#define PIO_IRQ0_INTE_SM2_TXNFULL_LSB _U(6)
+#define PIO_IRQ0_INTE_SM2_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM2_TXNFULL_BITS _u(0x00000040)
+#define PIO_IRQ0_INTE_SM2_TXNFULL_MSB _u(6)
+#define PIO_IRQ0_INTE_SM2_TXNFULL_LSB _u(6)
#define PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM1_TXNFULL
// Description : None
-#define PIO_IRQ0_INTE_SM1_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ0_INTE_SM1_TXNFULL_BITS _U(0x00000020)
-#define PIO_IRQ0_INTE_SM1_TXNFULL_MSB _U(5)
-#define PIO_IRQ0_INTE_SM1_TXNFULL_LSB _U(5)
+#define PIO_IRQ0_INTE_SM1_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM1_TXNFULL_BITS _u(0x00000020)
+#define PIO_IRQ0_INTE_SM1_TXNFULL_MSB _u(5)
+#define PIO_IRQ0_INTE_SM1_TXNFULL_LSB _u(5)
#define PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM0_TXNFULL
// Description : None
-#define PIO_IRQ0_INTE_SM0_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ0_INTE_SM0_TXNFULL_BITS _U(0x00000010)
-#define PIO_IRQ0_INTE_SM0_TXNFULL_MSB _U(4)
-#define PIO_IRQ0_INTE_SM0_TXNFULL_LSB _U(4)
+#define PIO_IRQ0_INTE_SM0_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM0_TXNFULL_BITS _u(0x00000010)
+#define PIO_IRQ0_INTE_SM0_TXNFULL_MSB _u(4)
+#define PIO_IRQ0_INTE_SM0_TXNFULL_LSB _u(4)
#define PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM3_RXNEMPTY
// Description : None
-#define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS _U(0x00000008)
-#define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB _U(3)
-#define PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB _U(3)
+#define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS _u(0x00000008)
+#define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB _u(3)
+#define PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB _u(3)
#define PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM2_RXNEMPTY
// Description : None
-#define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS _U(0x00000004)
-#define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB _U(2)
-#define PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB _U(2)
+#define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS _u(0x00000004)
+#define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB _u(2)
+#define PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB _u(2)
#define PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM1_RXNEMPTY
// Description : None
-#define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS _U(0x00000002)
-#define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB _U(1)
-#define PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB _U(1)
+#define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS _u(0x00000002)
+#define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB _u(1)
+#define PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB _u(1)
#define PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM0_RXNEMPTY
// Description : None
-#define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS _U(0x00000001)
-#define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB _U(0)
-#define PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB _U(0)
+#define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS _u(0x00000001)
+#define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB _u(0)
+#define PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB _u(0)
#define PIO_IRQ0_INTE_SM0_RXNEMPTY_ACCESS "RW"
// =============================================================================
// Register : PIO_IRQ0_INTF
// Description : Interrupt Force for irq0
-#define PIO_IRQ0_INTF_OFFSET _U(0x00000130)
-#define PIO_IRQ0_INTF_BITS _U(0x00000fff)
-#define PIO_IRQ0_INTF_RESET _U(0x00000000)
+#define PIO_IRQ0_INTF_OFFSET _u(0x00000130)
+#define PIO_IRQ0_INTF_BITS _u(0x00000fff)
+#define PIO_IRQ0_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM3
// Description : None
-#define PIO_IRQ0_INTF_SM3_RESET _U(0x0)
-#define PIO_IRQ0_INTF_SM3_BITS _U(0x00000800)
-#define PIO_IRQ0_INTF_SM3_MSB _U(11)
-#define PIO_IRQ0_INTF_SM3_LSB _U(11)
+#define PIO_IRQ0_INTF_SM3_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM3_BITS _u(0x00000800)
+#define PIO_IRQ0_INTF_SM3_MSB _u(11)
+#define PIO_IRQ0_INTF_SM3_LSB _u(11)
#define PIO_IRQ0_INTF_SM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM2
// Description : None
-#define PIO_IRQ0_INTF_SM2_RESET _U(0x0)
-#define PIO_IRQ0_INTF_SM2_BITS _U(0x00000400)
-#define PIO_IRQ0_INTF_SM2_MSB _U(10)
-#define PIO_IRQ0_INTF_SM2_LSB _U(10)
+#define PIO_IRQ0_INTF_SM2_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM2_BITS _u(0x00000400)
+#define PIO_IRQ0_INTF_SM2_MSB _u(10)
+#define PIO_IRQ0_INTF_SM2_LSB _u(10)
#define PIO_IRQ0_INTF_SM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM1
// Description : None
-#define PIO_IRQ0_INTF_SM1_RESET _U(0x0)
-#define PIO_IRQ0_INTF_SM1_BITS _U(0x00000200)
-#define PIO_IRQ0_INTF_SM1_MSB _U(9)
-#define PIO_IRQ0_INTF_SM1_LSB _U(9)
+#define PIO_IRQ0_INTF_SM1_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM1_BITS _u(0x00000200)
+#define PIO_IRQ0_INTF_SM1_MSB _u(9)
+#define PIO_IRQ0_INTF_SM1_LSB _u(9)
#define PIO_IRQ0_INTF_SM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM0
// Description : None
-#define PIO_IRQ0_INTF_SM0_RESET _U(0x0)
-#define PIO_IRQ0_INTF_SM0_BITS _U(0x00000100)
-#define PIO_IRQ0_INTF_SM0_MSB _U(8)
-#define PIO_IRQ0_INTF_SM0_LSB _U(8)
+#define PIO_IRQ0_INTF_SM0_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM0_BITS _u(0x00000100)
+#define PIO_IRQ0_INTF_SM0_MSB _u(8)
+#define PIO_IRQ0_INTF_SM0_LSB _u(8)
#define PIO_IRQ0_INTF_SM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM3_TXNFULL
// Description : None
-#define PIO_IRQ0_INTF_SM3_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ0_INTF_SM3_TXNFULL_BITS _U(0x00000080)
-#define PIO_IRQ0_INTF_SM3_TXNFULL_MSB _U(7)
-#define PIO_IRQ0_INTF_SM3_TXNFULL_LSB _U(7)
+#define PIO_IRQ0_INTF_SM3_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM3_TXNFULL_BITS _u(0x00000080)
+#define PIO_IRQ0_INTF_SM3_TXNFULL_MSB _u(7)
+#define PIO_IRQ0_INTF_SM3_TXNFULL_LSB _u(7)
#define PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM2_TXNFULL
// Description : None
-#define PIO_IRQ0_INTF_SM2_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ0_INTF_SM2_TXNFULL_BITS _U(0x00000040)
-#define PIO_IRQ0_INTF_SM2_TXNFULL_MSB _U(6)
-#define PIO_IRQ0_INTF_SM2_TXNFULL_LSB _U(6)
+#define PIO_IRQ0_INTF_SM2_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM2_TXNFULL_BITS _u(0x00000040)
+#define PIO_IRQ0_INTF_SM2_TXNFULL_MSB _u(6)
+#define PIO_IRQ0_INTF_SM2_TXNFULL_LSB _u(6)
#define PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM1_TXNFULL
// Description : None
-#define PIO_IRQ0_INTF_SM1_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ0_INTF_SM1_TXNFULL_BITS _U(0x00000020)
-#define PIO_IRQ0_INTF_SM1_TXNFULL_MSB _U(5)
-#define PIO_IRQ0_INTF_SM1_TXNFULL_LSB _U(5)
+#define PIO_IRQ0_INTF_SM1_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM1_TXNFULL_BITS _u(0x00000020)
+#define PIO_IRQ0_INTF_SM1_TXNFULL_MSB _u(5)
+#define PIO_IRQ0_INTF_SM1_TXNFULL_LSB _u(5)
#define PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM0_TXNFULL
// Description : None
-#define PIO_IRQ0_INTF_SM0_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ0_INTF_SM0_TXNFULL_BITS _U(0x00000010)
-#define PIO_IRQ0_INTF_SM0_TXNFULL_MSB _U(4)
-#define PIO_IRQ0_INTF_SM0_TXNFULL_LSB _U(4)
+#define PIO_IRQ0_INTF_SM0_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM0_TXNFULL_BITS _u(0x00000010)
+#define PIO_IRQ0_INTF_SM0_TXNFULL_MSB _u(4)
+#define PIO_IRQ0_INTF_SM0_TXNFULL_LSB _u(4)
#define PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM3_RXNEMPTY
// Description : None
-#define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS _U(0x00000008)
-#define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB _U(3)
-#define PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB _U(3)
+#define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS _u(0x00000008)
+#define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB _u(3)
+#define PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB _u(3)
#define PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM2_RXNEMPTY
// Description : None
-#define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS _U(0x00000004)
-#define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB _U(2)
-#define PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB _U(2)
+#define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS _u(0x00000004)
+#define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB _u(2)
+#define PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB _u(2)
#define PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM1_RXNEMPTY
// Description : None
-#define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS _U(0x00000002)
-#define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB _U(1)
-#define PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB _U(1)
+#define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS _u(0x00000002)
+#define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB _u(1)
+#define PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB _u(1)
#define PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM0_RXNEMPTY
// Description : None
-#define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS _U(0x00000001)
-#define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB _U(0)
-#define PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB _U(0)
+#define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS _u(0x00000001)
+#define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB _u(0)
+#define PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB _u(0)
#define PIO_IRQ0_INTF_SM0_RXNEMPTY_ACCESS "RW"
// =============================================================================
// Register : PIO_IRQ0_INTS
// Description : Interrupt status after masking & forcing for irq0
-#define PIO_IRQ0_INTS_OFFSET _U(0x00000134)
-#define PIO_IRQ0_INTS_BITS _U(0x00000fff)
-#define PIO_IRQ0_INTS_RESET _U(0x00000000)
+#define PIO_IRQ0_INTS_OFFSET _u(0x00000134)
+#define PIO_IRQ0_INTS_BITS _u(0x00000fff)
+#define PIO_IRQ0_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM3
// Description : None
-#define PIO_IRQ0_INTS_SM3_RESET _U(0x0)
-#define PIO_IRQ0_INTS_SM3_BITS _U(0x00000800)
-#define PIO_IRQ0_INTS_SM3_MSB _U(11)
-#define PIO_IRQ0_INTS_SM3_LSB _U(11)
+#define PIO_IRQ0_INTS_SM3_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM3_BITS _u(0x00000800)
+#define PIO_IRQ0_INTS_SM3_MSB _u(11)
+#define PIO_IRQ0_INTS_SM3_LSB _u(11)
#define PIO_IRQ0_INTS_SM3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM2
// Description : None
-#define PIO_IRQ0_INTS_SM2_RESET _U(0x0)
-#define PIO_IRQ0_INTS_SM2_BITS _U(0x00000400)
-#define PIO_IRQ0_INTS_SM2_MSB _U(10)
-#define PIO_IRQ0_INTS_SM2_LSB _U(10)
+#define PIO_IRQ0_INTS_SM2_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM2_BITS _u(0x00000400)
+#define PIO_IRQ0_INTS_SM2_MSB _u(10)
+#define PIO_IRQ0_INTS_SM2_LSB _u(10)
#define PIO_IRQ0_INTS_SM2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM1
// Description : None
-#define PIO_IRQ0_INTS_SM1_RESET _U(0x0)
-#define PIO_IRQ0_INTS_SM1_BITS _U(0x00000200)
-#define PIO_IRQ0_INTS_SM1_MSB _U(9)
-#define PIO_IRQ0_INTS_SM1_LSB _U(9)
+#define PIO_IRQ0_INTS_SM1_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM1_BITS _u(0x00000200)
+#define PIO_IRQ0_INTS_SM1_MSB _u(9)
+#define PIO_IRQ0_INTS_SM1_LSB _u(9)
#define PIO_IRQ0_INTS_SM1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM0
// Description : None
-#define PIO_IRQ0_INTS_SM0_RESET _U(0x0)
-#define PIO_IRQ0_INTS_SM0_BITS _U(0x00000100)
-#define PIO_IRQ0_INTS_SM0_MSB _U(8)
-#define PIO_IRQ0_INTS_SM0_LSB _U(8)
+#define PIO_IRQ0_INTS_SM0_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM0_BITS _u(0x00000100)
+#define PIO_IRQ0_INTS_SM0_MSB _u(8)
+#define PIO_IRQ0_INTS_SM0_LSB _u(8)
#define PIO_IRQ0_INTS_SM0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM3_TXNFULL
// Description : None
-#define PIO_IRQ0_INTS_SM3_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ0_INTS_SM3_TXNFULL_BITS _U(0x00000080)
-#define PIO_IRQ0_INTS_SM3_TXNFULL_MSB _U(7)
-#define PIO_IRQ0_INTS_SM3_TXNFULL_LSB _U(7)
+#define PIO_IRQ0_INTS_SM3_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM3_TXNFULL_BITS _u(0x00000080)
+#define PIO_IRQ0_INTS_SM3_TXNFULL_MSB _u(7)
+#define PIO_IRQ0_INTS_SM3_TXNFULL_LSB _u(7)
#define PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM2_TXNFULL
// Description : None
-#define PIO_IRQ0_INTS_SM2_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ0_INTS_SM2_TXNFULL_BITS _U(0x00000040)
-#define PIO_IRQ0_INTS_SM2_TXNFULL_MSB _U(6)
-#define PIO_IRQ0_INTS_SM2_TXNFULL_LSB _U(6)
+#define PIO_IRQ0_INTS_SM2_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM2_TXNFULL_BITS _u(0x00000040)
+#define PIO_IRQ0_INTS_SM2_TXNFULL_MSB _u(6)
+#define PIO_IRQ0_INTS_SM2_TXNFULL_LSB _u(6)
#define PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM1_TXNFULL
// Description : None
-#define PIO_IRQ0_INTS_SM1_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ0_INTS_SM1_TXNFULL_BITS _U(0x00000020)
-#define PIO_IRQ0_INTS_SM1_TXNFULL_MSB _U(5)
-#define PIO_IRQ0_INTS_SM1_TXNFULL_LSB _U(5)
+#define PIO_IRQ0_INTS_SM1_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM1_TXNFULL_BITS _u(0x00000020)
+#define PIO_IRQ0_INTS_SM1_TXNFULL_MSB _u(5)
+#define PIO_IRQ0_INTS_SM1_TXNFULL_LSB _u(5)
#define PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM0_TXNFULL
// Description : None
-#define PIO_IRQ0_INTS_SM0_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ0_INTS_SM0_TXNFULL_BITS _U(0x00000010)
-#define PIO_IRQ0_INTS_SM0_TXNFULL_MSB _U(4)
-#define PIO_IRQ0_INTS_SM0_TXNFULL_LSB _U(4)
+#define PIO_IRQ0_INTS_SM0_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM0_TXNFULL_BITS _u(0x00000010)
+#define PIO_IRQ0_INTS_SM0_TXNFULL_MSB _u(4)
+#define PIO_IRQ0_INTS_SM0_TXNFULL_LSB _u(4)
#define PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM3_RXNEMPTY
// Description : None
-#define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS _U(0x00000008)
-#define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB _U(3)
-#define PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB _U(3)
+#define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS _u(0x00000008)
+#define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB _u(3)
+#define PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB _u(3)
#define PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM2_RXNEMPTY
// Description : None
-#define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS _U(0x00000004)
-#define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB _U(2)
-#define PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB _U(2)
+#define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS _u(0x00000004)
+#define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB _u(2)
+#define PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB _u(2)
#define PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM1_RXNEMPTY
// Description : None
-#define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS _U(0x00000002)
-#define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB _U(1)
-#define PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB _U(1)
+#define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS _u(0x00000002)
+#define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB _u(1)
+#define PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB _u(1)
#define PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM0_RXNEMPTY
// Description : None
-#define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS _U(0x00000001)
-#define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB _U(0)
-#define PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB _U(0)
+#define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS _u(0x00000001)
+#define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB _u(0)
+#define PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB _u(0)
#define PIO_IRQ0_INTS_SM0_RXNEMPTY_ACCESS "RO"
// =============================================================================
// Register : PIO_IRQ1_INTE
// Description : Interrupt Enable for irq1
-#define PIO_IRQ1_INTE_OFFSET _U(0x00000138)
-#define PIO_IRQ1_INTE_BITS _U(0x00000fff)
-#define PIO_IRQ1_INTE_RESET _U(0x00000000)
+#define PIO_IRQ1_INTE_OFFSET _u(0x00000138)
+#define PIO_IRQ1_INTE_BITS _u(0x00000fff)
+#define PIO_IRQ1_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM3
// Description : None
-#define PIO_IRQ1_INTE_SM3_RESET _U(0x0)
-#define PIO_IRQ1_INTE_SM3_BITS _U(0x00000800)
-#define PIO_IRQ1_INTE_SM3_MSB _U(11)
-#define PIO_IRQ1_INTE_SM3_LSB _U(11)
+#define PIO_IRQ1_INTE_SM3_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM3_BITS _u(0x00000800)
+#define PIO_IRQ1_INTE_SM3_MSB _u(11)
+#define PIO_IRQ1_INTE_SM3_LSB _u(11)
#define PIO_IRQ1_INTE_SM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM2
// Description : None
-#define PIO_IRQ1_INTE_SM2_RESET _U(0x0)
-#define PIO_IRQ1_INTE_SM2_BITS _U(0x00000400)
-#define PIO_IRQ1_INTE_SM2_MSB _U(10)
-#define PIO_IRQ1_INTE_SM2_LSB _U(10)
+#define PIO_IRQ1_INTE_SM2_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM2_BITS _u(0x00000400)
+#define PIO_IRQ1_INTE_SM2_MSB _u(10)
+#define PIO_IRQ1_INTE_SM2_LSB _u(10)
#define PIO_IRQ1_INTE_SM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM1
// Description : None
-#define PIO_IRQ1_INTE_SM1_RESET _U(0x0)
-#define PIO_IRQ1_INTE_SM1_BITS _U(0x00000200)
-#define PIO_IRQ1_INTE_SM1_MSB _U(9)
-#define PIO_IRQ1_INTE_SM1_LSB _U(9)
+#define PIO_IRQ1_INTE_SM1_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM1_BITS _u(0x00000200)
+#define PIO_IRQ1_INTE_SM1_MSB _u(9)
+#define PIO_IRQ1_INTE_SM1_LSB _u(9)
#define PIO_IRQ1_INTE_SM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM0
// Description : None
-#define PIO_IRQ1_INTE_SM0_RESET _U(0x0)
-#define PIO_IRQ1_INTE_SM0_BITS _U(0x00000100)
-#define PIO_IRQ1_INTE_SM0_MSB _U(8)
-#define PIO_IRQ1_INTE_SM0_LSB _U(8)
+#define PIO_IRQ1_INTE_SM0_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM0_BITS _u(0x00000100)
+#define PIO_IRQ1_INTE_SM0_MSB _u(8)
+#define PIO_IRQ1_INTE_SM0_LSB _u(8)
#define PIO_IRQ1_INTE_SM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM3_TXNFULL
// Description : None
-#define PIO_IRQ1_INTE_SM3_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ1_INTE_SM3_TXNFULL_BITS _U(0x00000080)
-#define PIO_IRQ1_INTE_SM3_TXNFULL_MSB _U(7)
-#define PIO_IRQ1_INTE_SM3_TXNFULL_LSB _U(7)
+#define PIO_IRQ1_INTE_SM3_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM3_TXNFULL_BITS _u(0x00000080)
+#define PIO_IRQ1_INTE_SM3_TXNFULL_MSB _u(7)
+#define PIO_IRQ1_INTE_SM3_TXNFULL_LSB _u(7)
#define PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM2_TXNFULL
// Description : None
-#define PIO_IRQ1_INTE_SM2_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ1_INTE_SM2_TXNFULL_BITS _U(0x00000040)
-#define PIO_IRQ1_INTE_SM2_TXNFULL_MSB _U(6)
-#define PIO_IRQ1_INTE_SM2_TXNFULL_LSB _U(6)
+#define PIO_IRQ1_INTE_SM2_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM2_TXNFULL_BITS _u(0x00000040)
+#define PIO_IRQ1_INTE_SM2_TXNFULL_MSB _u(6)
+#define PIO_IRQ1_INTE_SM2_TXNFULL_LSB _u(6)
#define PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM1_TXNFULL
// Description : None
-#define PIO_IRQ1_INTE_SM1_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ1_INTE_SM1_TXNFULL_BITS _U(0x00000020)
-#define PIO_IRQ1_INTE_SM1_TXNFULL_MSB _U(5)
-#define PIO_IRQ1_INTE_SM1_TXNFULL_LSB _U(5)
+#define PIO_IRQ1_INTE_SM1_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM1_TXNFULL_BITS _u(0x00000020)
+#define PIO_IRQ1_INTE_SM1_TXNFULL_MSB _u(5)
+#define PIO_IRQ1_INTE_SM1_TXNFULL_LSB _u(5)
#define PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM0_TXNFULL
// Description : None
-#define PIO_IRQ1_INTE_SM0_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ1_INTE_SM0_TXNFULL_BITS _U(0x00000010)
-#define PIO_IRQ1_INTE_SM0_TXNFULL_MSB _U(4)
-#define PIO_IRQ1_INTE_SM0_TXNFULL_LSB _U(4)
+#define PIO_IRQ1_INTE_SM0_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM0_TXNFULL_BITS _u(0x00000010)
+#define PIO_IRQ1_INTE_SM0_TXNFULL_MSB _u(4)
+#define PIO_IRQ1_INTE_SM0_TXNFULL_LSB _u(4)
#define PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM3_RXNEMPTY
// Description : None
-#define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS _U(0x00000008)
-#define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB _U(3)
-#define PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB _U(3)
+#define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS _u(0x00000008)
+#define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB _u(3)
+#define PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB _u(3)
#define PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM2_RXNEMPTY
// Description : None
-#define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS _U(0x00000004)
-#define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB _U(2)
-#define PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB _U(2)
+#define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS _u(0x00000004)
+#define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB _u(2)
+#define PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB _u(2)
#define PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM1_RXNEMPTY
// Description : None
-#define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS _U(0x00000002)
-#define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB _U(1)
-#define PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB _U(1)
+#define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS _u(0x00000002)
+#define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB _u(1)
+#define PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB _u(1)
#define PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM0_RXNEMPTY
// Description : None
-#define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS _U(0x00000001)
-#define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB _U(0)
-#define PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB _U(0)
+#define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS _u(0x00000001)
+#define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB _u(0)
+#define PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB _u(0)
#define PIO_IRQ1_INTE_SM0_RXNEMPTY_ACCESS "RW"
// =============================================================================
// Register : PIO_IRQ1_INTF
// Description : Interrupt Force for irq1
-#define PIO_IRQ1_INTF_OFFSET _U(0x0000013c)
-#define PIO_IRQ1_INTF_BITS _U(0x00000fff)
-#define PIO_IRQ1_INTF_RESET _U(0x00000000)
+#define PIO_IRQ1_INTF_OFFSET _u(0x0000013c)
+#define PIO_IRQ1_INTF_BITS _u(0x00000fff)
+#define PIO_IRQ1_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM3
// Description : None
-#define PIO_IRQ1_INTF_SM3_RESET _U(0x0)
-#define PIO_IRQ1_INTF_SM3_BITS _U(0x00000800)
-#define PIO_IRQ1_INTF_SM3_MSB _U(11)
-#define PIO_IRQ1_INTF_SM3_LSB _U(11)
+#define PIO_IRQ1_INTF_SM3_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM3_BITS _u(0x00000800)
+#define PIO_IRQ1_INTF_SM3_MSB _u(11)
+#define PIO_IRQ1_INTF_SM3_LSB _u(11)
#define PIO_IRQ1_INTF_SM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM2
// Description : None
-#define PIO_IRQ1_INTF_SM2_RESET _U(0x0)
-#define PIO_IRQ1_INTF_SM2_BITS _U(0x00000400)
-#define PIO_IRQ1_INTF_SM2_MSB _U(10)
-#define PIO_IRQ1_INTF_SM2_LSB _U(10)
+#define PIO_IRQ1_INTF_SM2_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM2_BITS _u(0x00000400)
+#define PIO_IRQ1_INTF_SM2_MSB _u(10)
+#define PIO_IRQ1_INTF_SM2_LSB _u(10)
#define PIO_IRQ1_INTF_SM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM1
// Description : None
-#define PIO_IRQ1_INTF_SM1_RESET _U(0x0)
-#define PIO_IRQ1_INTF_SM1_BITS _U(0x00000200)
-#define PIO_IRQ1_INTF_SM1_MSB _U(9)
-#define PIO_IRQ1_INTF_SM1_LSB _U(9)
+#define PIO_IRQ1_INTF_SM1_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM1_BITS _u(0x00000200)
+#define PIO_IRQ1_INTF_SM1_MSB _u(9)
+#define PIO_IRQ1_INTF_SM1_LSB _u(9)
#define PIO_IRQ1_INTF_SM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM0
// Description : None
-#define PIO_IRQ1_INTF_SM0_RESET _U(0x0)
-#define PIO_IRQ1_INTF_SM0_BITS _U(0x00000100)
-#define PIO_IRQ1_INTF_SM0_MSB _U(8)
-#define PIO_IRQ1_INTF_SM0_LSB _U(8)
+#define PIO_IRQ1_INTF_SM0_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM0_BITS _u(0x00000100)
+#define PIO_IRQ1_INTF_SM0_MSB _u(8)
+#define PIO_IRQ1_INTF_SM0_LSB _u(8)
#define PIO_IRQ1_INTF_SM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM3_TXNFULL
// Description : None
-#define PIO_IRQ1_INTF_SM3_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ1_INTF_SM3_TXNFULL_BITS _U(0x00000080)
-#define PIO_IRQ1_INTF_SM3_TXNFULL_MSB _U(7)
-#define PIO_IRQ1_INTF_SM3_TXNFULL_LSB _U(7)
+#define PIO_IRQ1_INTF_SM3_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM3_TXNFULL_BITS _u(0x00000080)
+#define PIO_IRQ1_INTF_SM3_TXNFULL_MSB _u(7)
+#define PIO_IRQ1_INTF_SM3_TXNFULL_LSB _u(7)
#define PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM2_TXNFULL
// Description : None
-#define PIO_IRQ1_INTF_SM2_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ1_INTF_SM2_TXNFULL_BITS _U(0x00000040)
-#define PIO_IRQ1_INTF_SM2_TXNFULL_MSB _U(6)
-#define PIO_IRQ1_INTF_SM2_TXNFULL_LSB _U(6)
+#define PIO_IRQ1_INTF_SM2_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM2_TXNFULL_BITS _u(0x00000040)
+#define PIO_IRQ1_INTF_SM2_TXNFULL_MSB _u(6)
+#define PIO_IRQ1_INTF_SM2_TXNFULL_LSB _u(6)
#define PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM1_TXNFULL
// Description : None
-#define PIO_IRQ1_INTF_SM1_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ1_INTF_SM1_TXNFULL_BITS _U(0x00000020)
-#define PIO_IRQ1_INTF_SM1_TXNFULL_MSB _U(5)
-#define PIO_IRQ1_INTF_SM1_TXNFULL_LSB _U(5)
+#define PIO_IRQ1_INTF_SM1_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM1_TXNFULL_BITS _u(0x00000020)
+#define PIO_IRQ1_INTF_SM1_TXNFULL_MSB _u(5)
+#define PIO_IRQ1_INTF_SM1_TXNFULL_LSB _u(5)
#define PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM0_TXNFULL
// Description : None
-#define PIO_IRQ1_INTF_SM0_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ1_INTF_SM0_TXNFULL_BITS _U(0x00000010)
-#define PIO_IRQ1_INTF_SM0_TXNFULL_MSB _U(4)
-#define PIO_IRQ1_INTF_SM0_TXNFULL_LSB _U(4)
+#define PIO_IRQ1_INTF_SM0_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM0_TXNFULL_BITS _u(0x00000010)
+#define PIO_IRQ1_INTF_SM0_TXNFULL_MSB _u(4)
+#define PIO_IRQ1_INTF_SM0_TXNFULL_LSB _u(4)
#define PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM3_RXNEMPTY
// Description : None
-#define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS _U(0x00000008)
-#define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB _U(3)
-#define PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB _U(3)
+#define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS _u(0x00000008)
+#define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB _u(3)
+#define PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB _u(3)
#define PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM2_RXNEMPTY
// Description : None
-#define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS _U(0x00000004)
-#define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB _U(2)
-#define PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB _U(2)
+#define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS _u(0x00000004)
+#define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB _u(2)
+#define PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB _u(2)
#define PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM1_RXNEMPTY
// Description : None
-#define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS _U(0x00000002)
-#define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB _U(1)
-#define PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB _U(1)
+#define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS _u(0x00000002)
+#define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB _u(1)
+#define PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB _u(1)
#define PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM0_RXNEMPTY
// Description : None
-#define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS _U(0x00000001)
-#define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB _U(0)
-#define PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB _U(0)
+#define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS _u(0x00000001)
+#define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB _u(0)
+#define PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB _u(0)
#define PIO_IRQ1_INTF_SM0_RXNEMPTY_ACCESS "RW"
// =============================================================================
// Register : PIO_IRQ1_INTS
// Description : Interrupt status after masking & forcing for irq1
-#define PIO_IRQ1_INTS_OFFSET _U(0x00000140)
-#define PIO_IRQ1_INTS_BITS _U(0x00000fff)
-#define PIO_IRQ1_INTS_RESET _U(0x00000000)
+#define PIO_IRQ1_INTS_OFFSET _u(0x00000140)
+#define PIO_IRQ1_INTS_BITS _u(0x00000fff)
+#define PIO_IRQ1_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM3
// Description : None
-#define PIO_IRQ1_INTS_SM3_RESET _U(0x0)
-#define PIO_IRQ1_INTS_SM3_BITS _U(0x00000800)
-#define PIO_IRQ1_INTS_SM3_MSB _U(11)
-#define PIO_IRQ1_INTS_SM3_LSB _U(11)
+#define PIO_IRQ1_INTS_SM3_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM3_BITS _u(0x00000800)
+#define PIO_IRQ1_INTS_SM3_MSB _u(11)
+#define PIO_IRQ1_INTS_SM3_LSB _u(11)
#define PIO_IRQ1_INTS_SM3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM2
// Description : None
-#define PIO_IRQ1_INTS_SM2_RESET _U(0x0)
-#define PIO_IRQ1_INTS_SM2_BITS _U(0x00000400)
-#define PIO_IRQ1_INTS_SM2_MSB _U(10)
-#define PIO_IRQ1_INTS_SM2_LSB _U(10)
+#define PIO_IRQ1_INTS_SM2_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM2_BITS _u(0x00000400)
+#define PIO_IRQ1_INTS_SM2_MSB _u(10)
+#define PIO_IRQ1_INTS_SM2_LSB _u(10)
#define PIO_IRQ1_INTS_SM2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM1
// Description : None
-#define PIO_IRQ1_INTS_SM1_RESET _U(0x0)
-#define PIO_IRQ1_INTS_SM1_BITS _U(0x00000200)
-#define PIO_IRQ1_INTS_SM1_MSB _U(9)
-#define PIO_IRQ1_INTS_SM1_LSB _U(9)
+#define PIO_IRQ1_INTS_SM1_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM1_BITS _u(0x00000200)
+#define PIO_IRQ1_INTS_SM1_MSB _u(9)
+#define PIO_IRQ1_INTS_SM1_LSB _u(9)
#define PIO_IRQ1_INTS_SM1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM0
// Description : None
-#define PIO_IRQ1_INTS_SM0_RESET _U(0x0)
-#define PIO_IRQ1_INTS_SM0_BITS _U(0x00000100)
-#define PIO_IRQ1_INTS_SM0_MSB _U(8)
-#define PIO_IRQ1_INTS_SM0_LSB _U(8)
+#define PIO_IRQ1_INTS_SM0_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM0_BITS _u(0x00000100)
+#define PIO_IRQ1_INTS_SM0_MSB _u(8)
+#define PIO_IRQ1_INTS_SM0_LSB _u(8)
#define PIO_IRQ1_INTS_SM0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM3_TXNFULL
// Description : None
-#define PIO_IRQ1_INTS_SM3_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ1_INTS_SM3_TXNFULL_BITS _U(0x00000080)
-#define PIO_IRQ1_INTS_SM3_TXNFULL_MSB _U(7)
-#define PIO_IRQ1_INTS_SM3_TXNFULL_LSB _U(7)
+#define PIO_IRQ1_INTS_SM3_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM3_TXNFULL_BITS _u(0x00000080)
+#define PIO_IRQ1_INTS_SM3_TXNFULL_MSB _u(7)
+#define PIO_IRQ1_INTS_SM3_TXNFULL_LSB _u(7)
#define PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM2_TXNFULL
// Description : None
-#define PIO_IRQ1_INTS_SM2_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ1_INTS_SM2_TXNFULL_BITS _U(0x00000040)
-#define PIO_IRQ1_INTS_SM2_TXNFULL_MSB _U(6)
-#define PIO_IRQ1_INTS_SM2_TXNFULL_LSB _U(6)
+#define PIO_IRQ1_INTS_SM2_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM2_TXNFULL_BITS _u(0x00000040)
+#define PIO_IRQ1_INTS_SM2_TXNFULL_MSB _u(6)
+#define PIO_IRQ1_INTS_SM2_TXNFULL_LSB _u(6)
#define PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM1_TXNFULL
// Description : None
-#define PIO_IRQ1_INTS_SM1_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ1_INTS_SM1_TXNFULL_BITS _U(0x00000020)
-#define PIO_IRQ1_INTS_SM1_TXNFULL_MSB _U(5)
-#define PIO_IRQ1_INTS_SM1_TXNFULL_LSB _U(5)
+#define PIO_IRQ1_INTS_SM1_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM1_TXNFULL_BITS _u(0x00000020)
+#define PIO_IRQ1_INTS_SM1_TXNFULL_MSB _u(5)
+#define PIO_IRQ1_INTS_SM1_TXNFULL_LSB _u(5)
#define PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM0_TXNFULL
// Description : None
-#define PIO_IRQ1_INTS_SM0_TXNFULL_RESET _U(0x0)
-#define PIO_IRQ1_INTS_SM0_TXNFULL_BITS _U(0x00000010)
-#define PIO_IRQ1_INTS_SM0_TXNFULL_MSB _U(4)
-#define PIO_IRQ1_INTS_SM0_TXNFULL_LSB _U(4)
+#define PIO_IRQ1_INTS_SM0_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM0_TXNFULL_BITS _u(0x00000010)
+#define PIO_IRQ1_INTS_SM0_TXNFULL_MSB _u(4)
+#define PIO_IRQ1_INTS_SM0_TXNFULL_LSB _u(4)
#define PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM3_RXNEMPTY
// Description : None
-#define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS _U(0x00000008)
-#define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB _U(3)
-#define PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB _U(3)
+#define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS _u(0x00000008)
+#define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB _u(3)
+#define PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB _u(3)
#define PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM2_RXNEMPTY
// Description : None
-#define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS _U(0x00000004)
-#define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB _U(2)
-#define PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB _U(2)
+#define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS _u(0x00000004)
+#define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB _u(2)
+#define PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB _u(2)
#define PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM1_RXNEMPTY
// Description : None
-#define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS _U(0x00000002)
-#define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB _U(1)
-#define PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB _U(1)
+#define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS _u(0x00000002)
+#define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB _u(1)
+#define PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB _u(1)
#define PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM0_RXNEMPTY
// Description : None
-#define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET _U(0x0)
-#define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS _U(0x00000001)
-#define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB _U(0)
-#define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB _U(0)
+#define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS _u(0x00000001)
+#define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB _u(0)
+#define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB _u(0)
#define PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_PIO_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pll.h b/src/rp2040/hardware_regs/include/hardware/regs/pll.h
index d12aedc..a0f5ad0 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/pll.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/pll.h
@@ -18,16 +18,16 @@
// Reference clock frequency min=5MHz, max=800MHz
// Feedback divider min=16, max=320
// VCO frequency min=400MHz, max=1600MHz
-#define PLL_CS_OFFSET _U(0x00000000)
-#define PLL_CS_BITS _U(0x8000013f)
-#define PLL_CS_RESET _U(0x00000001)
+#define PLL_CS_OFFSET _u(0x00000000)
+#define PLL_CS_BITS _u(0x8000013f)
+#define PLL_CS_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : PLL_CS_LOCK
// Description : PLL is locked
-#define PLL_CS_LOCK_RESET _U(0x0)
-#define PLL_CS_LOCK_BITS _U(0x80000000)
-#define PLL_CS_LOCK_MSB _U(31)
-#define PLL_CS_LOCK_LSB _U(31)
+#define PLL_CS_LOCK_RESET _u(0x0)
+#define PLL_CS_LOCK_BITS _u(0x80000000)
+#define PLL_CS_LOCK_MSB _u(31)
+#define PLL_CS_LOCK_LSB _u(31)
#define PLL_CS_LOCK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PLL_CS_BYPASS
@@ -35,10 +35,10 @@
// VCO. The VCO continues to run so the user can switch between
// the reference clock and the divided VCO but the output will
// glitch when doing so.
-#define PLL_CS_BYPASS_RESET _U(0x0)
-#define PLL_CS_BYPASS_BITS _U(0x00000100)
-#define PLL_CS_BYPASS_MSB _U(8)
-#define PLL_CS_BYPASS_LSB _U(8)
+#define PLL_CS_BYPASS_RESET _u(0x0)
+#define PLL_CS_BYPASS_BITS _u(0x00000100)
+#define PLL_CS_BYPASS_MSB _u(8)
+#define PLL_CS_BYPASS_LSB _u(8)
#define PLL_CS_BYPASS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_CS_REFDIV
@@ -46,65 +46,65 @@
// Behaviour is undefined for div=0.
// PLL output will be unpredictable during refdiv changes, wait
// for lock=1 before using it.
-#define PLL_CS_REFDIV_RESET _U(0x01)
-#define PLL_CS_REFDIV_BITS _U(0x0000003f)
-#define PLL_CS_REFDIV_MSB _U(5)
-#define PLL_CS_REFDIV_LSB _U(0)
+#define PLL_CS_REFDIV_RESET _u(0x01)
+#define PLL_CS_REFDIV_BITS _u(0x0000003f)
+#define PLL_CS_REFDIV_MSB _u(5)
+#define PLL_CS_REFDIV_LSB _u(0)
#define PLL_CS_REFDIV_ACCESS "RW"
// =============================================================================
// Register : PLL_PWR
// Description : Controls the PLL power modes.
-#define PLL_PWR_OFFSET _U(0x00000004)
-#define PLL_PWR_BITS _U(0x0000002d)
-#define PLL_PWR_RESET _U(0x0000002d)
+#define PLL_PWR_OFFSET _u(0x00000004)
+#define PLL_PWR_BITS _u(0x0000002d)
+#define PLL_PWR_RESET _u(0x0000002d)
// -----------------------------------------------------------------------------
// Field : PLL_PWR_VCOPD
// Description : PLL VCO powerdown
// To save power set high when PLL output not required or
// bypass=1.
-#define PLL_PWR_VCOPD_RESET _U(0x1)
-#define PLL_PWR_VCOPD_BITS _U(0x00000020)
-#define PLL_PWR_VCOPD_MSB _U(5)
-#define PLL_PWR_VCOPD_LSB _U(5)
+#define PLL_PWR_VCOPD_RESET _u(0x1)
+#define PLL_PWR_VCOPD_BITS _u(0x00000020)
+#define PLL_PWR_VCOPD_MSB _u(5)
+#define PLL_PWR_VCOPD_LSB _u(5)
#define PLL_PWR_VCOPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_POSTDIVPD
// Description : PLL post divider powerdown
// To save power set high when PLL output not required or
// bypass=1.
-#define PLL_PWR_POSTDIVPD_RESET _U(0x1)
-#define PLL_PWR_POSTDIVPD_BITS _U(0x00000008)
-#define PLL_PWR_POSTDIVPD_MSB _U(3)
-#define PLL_PWR_POSTDIVPD_LSB _U(3)
+#define PLL_PWR_POSTDIVPD_RESET _u(0x1)
+#define PLL_PWR_POSTDIVPD_BITS _u(0x00000008)
+#define PLL_PWR_POSTDIVPD_MSB _u(3)
+#define PLL_PWR_POSTDIVPD_LSB _u(3)
#define PLL_PWR_POSTDIVPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_DSMPD
// Description : PLL DSM powerdown
// Nothing is achieved by setting this low.
-#define PLL_PWR_DSMPD_RESET _U(0x1)
-#define PLL_PWR_DSMPD_BITS _U(0x00000004)
-#define PLL_PWR_DSMPD_MSB _U(2)
-#define PLL_PWR_DSMPD_LSB _U(2)
+#define PLL_PWR_DSMPD_RESET _u(0x1)
+#define PLL_PWR_DSMPD_BITS _u(0x00000004)
+#define PLL_PWR_DSMPD_MSB _u(2)
+#define PLL_PWR_DSMPD_LSB _u(2)
#define PLL_PWR_DSMPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_PD
// Description : PLL powerdown
// To save power set high when PLL output not required.
-#define PLL_PWR_PD_RESET _U(0x1)
-#define PLL_PWR_PD_BITS _U(0x00000001)
-#define PLL_PWR_PD_MSB _U(0)
-#define PLL_PWR_PD_LSB _U(0)
+#define PLL_PWR_PD_RESET _u(0x1)
+#define PLL_PWR_PD_BITS _u(0x00000001)
+#define PLL_PWR_PD_MSB _u(0)
+#define PLL_PWR_PD_LSB _u(0)
#define PLL_PWR_PD_ACCESS "RW"
// =============================================================================
// Register : PLL_FBDIV_INT
// Description : Feedback divisor
// (note: this PLL does not support fractional division)
// see ctrl reg description for constraints
-#define PLL_FBDIV_INT_OFFSET _U(0x00000008)
-#define PLL_FBDIV_INT_BITS _U(0x00000fff)
-#define PLL_FBDIV_INT_RESET _U(0x00000000)
-#define PLL_FBDIV_INT_MSB _U(11)
-#define PLL_FBDIV_INT_LSB _U(0)
+#define PLL_FBDIV_INT_OFFSET _u(0x00000008)
+#define PLL_FBDIV_INT_BITS _u(0x00000fff)
+#define PLL_FBDIV_INT_RESET _u(0x00000000)
+#define PLL_FBDIV_INT_MSB _u(11)
+#define PLL_FBDIV_INT_LSB _u(0)
#define PLL_FBDIV_INT_ACCESS "RW"
// =============================================================================
// Register : PLL_PRIM
@@ -112,24 +112,24 @@
// (note: this PLL does not have a secondary output)
// the primary output is driven from VCO divided by
// postdiv1*postdiv2
-#define PLL_PRIM_OFFSET _U(0x0000000c)
-#define PLL_PRIM_BITS _U(0x00077000)
-#define PLL_PRIM_RESET _U(0x00077000)
+#define PLL_PRIM_OFFSET _u(0x0000000c)
+#define PLL_PRIM_BITS _u(0x00077000)
+#define PLL_PRIM_RESET _u(0x00077000)
// -----------------------------------------------------------------------------
// Field : PLL_PRIM_POSTDIV1
// Description : divide by 1-7
-#define PLL_PRIM_POSTDIV1_RESET _U(0x7)
-#define PLL_PRIM_POSTDIV1_BITS _U(0x00070000)
-#define PLL_PRIM_POSTDIV1_MSB _U(18)
-#define PLL_PRIM_POSTDIV1_LSB _U(16)
+#define PLL_PRIM_POSTDIV1_RESET _u(0x7)
+#define PLL_PRIM_POSTDIV1_BITS _u(0x00070000)
+#define PLL_PRIM_POSTDIV1_MSB _u(18)
+#define PLL_PRIM_POSTDIV1_LSB _u(16)
#define PLL_PRIM_POSTDIV1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PRIM_POSTDIV2
// Description : divide by 1-7
-#define PLL_PRIM_POSTDIV2_RESET _U(0x7)
-#define PLL_PRIM_POSTDIV2_BITS _U(0x00007000)
-#define PLL_PRIM_POSTDIV2_MSB _U(14)
-#define PLL_PRIM_POSTDIV2_LSB _U(12)
+#define PLL_PRIM_POSTDIV2_RESET _u(0x7)
+#define PLL_PRIM_POSTDIV2_BITS _u(0x00007000)
+#define PLL_PRIM_POSTDIV2_MSB _u(14)
+#define PLL_PRIM_POSTDIV2_LSB _u(12)
#define PLL_PRIM_POSTDIV2_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_PLL_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/psm.h b/src/rp2040/hardware_regs/include/hardware/regs/psm.h
index d4aa51b..8810ae8 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/psm.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/psm.h
@@ -14,571 +14,571 @@
// =============================================================================
// Register : PSM_FRCE_ON
// Description : Force block out of reset (i.e. power it on)
-#define PSM_FRCE_ON_OFFSET _U(0x00000000)
-#define PSM_FRCE_ON_BITS _U(0x0001ffff)
-#define PSM_FRCE_ON_RESET _U(0x00000000)
+#define PSM_FRCE_ON_OFFSET _u(0x00000000)
+#define PSM_FRCE_ON_BITS _u(0x0001ffff)
+#define PSM_FRCE_ON_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC1
// Description : None
-#define PSM_FRCE_ON_PROC1_RESET _U(0x0)
-#define PSM_FRCE_ON_PROC1_BITS _U(0x00010000)
-#define PSM_FRCE_ON_PROC1_MSB _U(16)
-#define PSM_FRCE_ON_PROC1_LSB _U(16)
+#define PSM_FRCE_ON_PROC1_RESET _u(0x0)
+#define PSM_FRCE_ON_PROC1_BITS _u(0x00010000)
+#define PSM_FRCE_ON_PROC1_MSB _u(16)
+#define PSM_FRCE_ON_PROC1_LSB _u(16)
#define PSM_FRCE_ON_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC0
// Description : None
-#define PSM_FRCE_ON_PROC0_RESET _U(0x0)
-#define PSM_FRCE_ON_PROC0_BITS _U(0x00008000)
-#define PSM_FRCE_ON_PROC0_MSB _U(15)
-#define PSM_FRCE_ON_PROC0_LSB _U(15)
+#define PSM_FRCE_ON_PROC0_RESET _u(0x0)
+#define PSM_FRCE_ON_PROC0_BITS _u(0x00008000)
+#define PSM_FRCE_ON_PROC0_MSB _u(15)
+#define PSM_FRCE_ON_PROC0_LSB _u(15)
#define PSM_FRCE_ON_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SIO
// Description : None
-#define PSM_FRCE_ON_SIO_RESET _U(0x0)
-#define PSM_FRCE_ON_SIO_BITS _U(0x00004000)
-#define PSM_FRCE_ON_SIO_MSB _U(14)
-#define PSM_FRCE_ON_SIO_LSB _U(14)
+#define PSM_FRCE_ON_SIO_RESET _u(0x0)
+#define PSM_FRCE_ON_SIO_BITS _u(0x00004000)
+#define PSM_FRCE_ON_SIO_MSB _u(14)
+#define PSM_FRCE_ON_SIO_LSB _u(14)
#define PSM_FRCE_ON_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET
// Description : None
-#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET _U(0x0)
-#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS _U(0x00002000)
-#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB _U(13)
-#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB _U(13)
+#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET _u(0x0)
+#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
+#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB _u(13)
+#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB _u(13)
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XIP
// Description : None
-#define PSM_FRCE_ON_XIP_RESET _U(0x0)
-#define PSM_FRCE_ON_XIP_BITS _U(0x00001000)
-#define PSM_FRCE_ON_XIP_MSB _U(12)
-#define PSM_FRCE_ON_XIP_LSB _U(12)
+#define PSM_FRCE_ON_XIP_RESET _u(0x0)
+#define PSM_FRCE_ON_XIP_BITS _u(0x00001000)
+#define PSM_FRCE_ON_XIP_MSB _u(12)
+#define PSM_FRCE_ON_XIP_LSB _u(12)
#define PSM_FRCE_ON_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM5
// Description : None
-#define PSM_FRCE_ON_SRAM5_RESET _U(0x0)
-#define PSM_FRCE_ON_SRAM5_BITS _U(0x00000800)
-#define PSM_FRCE_ON_SRAM5_MSB _U(11)
-#define PSM_FRCE_ON_SRAM5_LSB _U(11)
+#define PSM_FRCE_ON_SRAM5_RESET _u(0x0)
+#define PSM_FRCE_ON_SRAM5_BITS _u(0x00000800)
+#define PSM_FRCE_ON_SRAM5_MSB _u(11)
+#define PSM_FRCE_ON_SRAM5_LSB _u(11)
#define PSM_FRCE_ON_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM4
// Description : None
-#define PSM_FRCE_ON_SRAM4_RESET _U(0x0)
-#define PSM_FRCE_ON_SRAM4_BITS _U(0x00000400)
-#define PSM_FRCE_ON_SRAM4_MSB _U(10)
-#define PSM_FRCE_ON_SRAM4_LSB _U(10)
+#define PSM_FRCE_ON_SRAM4_RESET _u(0x0)
+#define PSM_FRCE_ON_SRAM4_BITS _u(0x00000400)
+#define PSM_FRCE_ON_SRAM4_MSB _u(10)
+#define PSM_FRCE_ON_SRAM4_LSB _u(10)
#define PSM_FRCE_ON_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM3
// Description : None
-#define PSM_FRCE_ON_SRAM3_RESET _U(0x0)
-#define PSM_FRCE_ON_SRAM3_BITS _U(0x00000200)
-#define PSM_FRCE_ON_SRAM3_MSB _U(9)
-#define PSM_FRCE_ON_SRAM3_LSB _U(9)
+#define PSM_FRCE_ON_SRAM3_RESET _u(0x0)
+#define PSM_FRCE_ON_SRAM3_BITS _u(0x00000200)
+#define PSM_FRCE_ON_SRAM3_MSB _u(9)
+#define PSM_FRCE_ON_SRAM3_LSB _u(9)
#define PSM_FRCE_ON_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM2
// Description : None
-#define PSM_FRCE_ON_SRAM2_RESET _U(0x0)
-#define PSM_FRCE_ON_SRAM2_BITS _U(0x00000100)
-#define PSM_FRCE_ON_SRAM2_MSB _U(8)
-#define PSM_FRCE_ON_SRAM2_LSB _U(8)
+#define PSM_FRCE_ON_SRAM2_RESET _u(0x0)
+#define PSM_FRCE_ON_SRAM2_BITS _u(0x00000100)
+#define PSM_FRCE_ON_SRAM2_MSB _u(8)
+#define PSM_FRCE_ON_SRAM2_LSB _u(8)
#define PSM_FRCE_ON_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM1
// Description : None
-#define PSM_FRCE_ON_SRAM1_RESET _U(0x0)
-#define PSM_FRCE_ON_SRAM1_BITS _U(0x00000080)
-#define PSM_FRCE_ON_SRAM1_MSB _U(7)
-#define PSM_FRCE_ON_SRAM1_LSB _U(7)
+#define PSM_FRCE_ON_SRAM1_RESET _u(0x0)
+#define PSM_FRCE_ON_SRAM1_BITS _u(0x00000080)
+#define PSM_FRCE_ON_SRAM1_MSB _u(7)
+#define PSM_FRCE_ON_SRAM1_LSB _u(7)
#define PSM_FRCE_ON_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM0
// Description : None
-#define PSM_FRCE_ON_SRAM0_RESET _U(0x0)
-#define PSM_FRCE_ON_SRAM0_BITS _U(0x00000040)
-#define PSM_FRCE_ON_SRAM0_MSB _U(6)
-#define PSM_FRCE_ON_SRAM0_LSB _U(6)
+#define PSM_FRCE_ON_SRAM0_RESET _u(0x0)
+#define PSM_FRCE_ON_SRAM0_BITS _u(0x00000040)
+#define PSM_FRCE_ON_SRAM0_MSB _u(6)
+#define PSM_FRCE_ON_SRAM0_LSB _u(6)
#define PSM_FRCE_ON_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROM
// Description : None
-#define PSM_FRCE_ON_ROM_RESET _U(0x0)
-#define PSM_FRCE_ON_ROM_BITS _U(0x00000020)
-#define PSM_FRCE_ON_ROM_MSB _U(5)
-#define PSM_FRCE_ON_ROM_LSB _U(5)
+#define PSM_FRCE_ON_ROM_RESET _u(0x0)
+#define PSM_FRCE_ON_ROM_BITS _u(0x00000020)
+#define PSM_FRCE_ON_ROM_MSB _u(5)
+#define PSM_FRCE_ON_ROM_LSB _u(5)
#define PSM_FRCE_ON_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_BUSFABRIC
// Description : None
-#define PSM_FRCE_ON_BUSFABRIC_RESET _U(0x0)
-#define PSM_FRCE_ON_BUSFABRIC_BITS _U(0x00000010)
-#define PSM_FRCE_ON_BUSFABRIC_MSB _U(4)
-#define PSM_FRCE_ON_BUSFABRIC_LSB _U(4)
+#define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0)
+#define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000010)
+#define PSM_FRCE_ON_BUSFABRIC_MSB _u(4)
+#define PSM_FRCE_ON_BUSFABRIC_LSB _u(4)
#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_RESETS
// Description : None
-#define PSM_FRCE_ON_RESETS_RESET _U(0x0)
-#define PSM_FRCE_ON_RESETS_BITS _U(0x00000008)
-#define PSM_FRCE_ON_RESETS_MSB _U(3)
-#define PSM_FRCE_ON_RESETS_LSB _U(3)
+#define PSM_FRCE_ON_RESETS_RESET _u(0x0)
+#define PSM_FRCE_ON_RESETS_BITS _u(0x00000008)
+#define PSM_FRCE_ON_RESETS_MSB _u(3)
+#define PSM_FRCE_ON_RESETS_LSB _u(3)
#define PSM_FRCE_ON_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_CLOCKS
// Description : None
-#define PSM_FRCE_ON_CLOCKS_RESET _U(0x0)
-#define PSM_FRCE_ON_CLOCKS_BITS _U(0x00000004)
-#define PSM_FRCE_ON_CLOCKS_MSB _U(2)
-#define PSM_FRCE_ON_CLOCKS_LSB _U(2)
+#define PSM_FRCE_ON_CLOCKS_RESET _u(0x0)
+#define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000004)
+#define PSM_FRCE_ON_CLOCKS_MSB _u(2)
+#define PSM_FRCE_ON_CLOCKS_LSB _u(2)
#define PSM_FRCE_ON_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XOSC
// Description : None
-#define PSM_FRCE_ON_XOSC_RESET _U(0x0)
-#define PSM_FRCE_ON_XOSC_BITS _U(0x00000002)
-#define PSM_FRCE_ON_XOSC_MSB _U(1)
-#define PSM_FRCE_ON_XOSC_LSB _U(1)
+#define PSM_FRCE_ON_XOSC_RESET _u(0x0)
+#define PSM_FRCE_ON_XOSC_BITS _u(0x00000002)
+#define PSM_FRCE_ON_XOSC_MSB _u(1)
+#define PSM_FRCE_ON_XOSC_LSB _u(1)
#define PSM_FRCE_ON_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROSC
// Description : None
-#define PSM_FRCE_ON_ROSC_RESET _U(0x0)
-#define PSM_FRCE_ON_ROSC_BITS _U(0x00000001)
-#define PSM_FRCE_ON_ROSC_MSB _U(0)
-#define PSM_FRCE_ON_ROSC_LSB _U(0)
+#define PSM_FRCE_ON_ROSC_RESET _u(0x0)
+#define PSM_FRCE_ON_ROSC_BITS _u(0x00000001)
+#define PSM_FRCE_ON_ROSC_MSB _u(0)
+#define PSM_FRCE_ON_ROSC_LSB _u(0)
#define PSM_FRCE_ON_ROSC_ACCESS "RW"
// =============================================================================
// Register : PSM_FRCE_OFF
// Description : Force into reset (i.e. power it off)
-#define PSM_FRCE_OFF_OFFSET _U(0x00000004)
-#define PSM_FRCE_OFF_BITS _U(0x0001ffff)
-#define PSM_FRCE_OFF_RESET _U(0x00000000)
+#define PSM_FRCE_OFF_OFFSET _u(0x00000004)
+#define PSM_FRCE_OFF_BITS _u(0x0001ffff)
+#define PSM_FRCE_OFF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC1
// Description : None
-#define PSM_FRCE_OFF_PROC1_RESET _U(0x0)
-#define PSM_FRCE_OFF_PROC1_BITS _U(0x00010000)
-#define PSM_FRCE_OFF_PROC1_MSB _U(16)
-#define PSM_FRCE_OFF_PROC1_LSB _U(16)
+#define PSM_FRCE_OFF_PROC1_RESET _u(0x0)
+#define PSM_FRCE_OFF_PROC1_BITS _u(0x00010000)
+#define PSM_FRCE_OFF_PROC1_MSB _u(16)
+#define PSM_FRCE_OFF_PROC1_LSB _u(16)
#define PSM_FRCE_OFF_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC0
// Description : None
-#define PSM_FRCE_OFF_PROC0_RESET _U(0x0)
-#define PSM_FRCE_OFF_PROC0_BITS _U(0x00008000)
-#define PSM_FRCE_OFF_PROC0_MSB _U(15)
-#define PSM_FRCE_OFF_PROC0_LSB _U(15)
+#define PSM_FRCE_OFF_PROC0_RESET _u(0x0)
+#define PSM_FRCE_OFF_PROC0_BITS _u(0x00008000)
+#define PSM_FRCE_OFF_PROC0_MSB _u(15)
+#define PSM_FRCE_OFF_PROC0_LSB _u(15)
#define PSM_FRCE_OFF_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SIO
// Description : None
-#define PSM_FRCE_OFF_SIO_RESET _U(0x0)
-#define PSM_FRCE_OFF_SIO_BITS _U(0x00004000)
-#define PSM_FRCE_OFF_SIO_MSB _U(14)
-#define PSM_FRCE_OFF_SIO_LSB _U(14)
+#define PSM_FRCE_OFF_SIO_RESET _u(0x0)
+#define PSM_FRCE_OFF_SIO_BITS _u(0x00004000)
+#define PSM_FRCE_OFF_SIO_MSB _u(14)
+#define PSM_FRCE_OFF_SIO_LSB _u(14)
#define PSM_FRCE_OFF_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET
// Description : None
-#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET _U(0x0)
-#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS _U(0x00002000)
-#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB _U(13)
-#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB _U(13)
+#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET _u(0x0)
+#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
+#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB _u(13)
+#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB _u(13)
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XIP
// Description : None
-#define PSM_FRCE_OFF_XIP_RESET _U(0x0)
-#define PSM_FRCE_OFF_XIP_BITS _U(0x00001000)
-#define PSM_FRCE_OFF_XIP_MSB _U(12)
-#define PSM_FRCE_OFF_XIP_LSB _U(12)
+#define PSM_FRCE_OFF_XIP_RESET _u(0x0)
+#define PSM_FRCE_OFF_XIP_BITS _u(0x00001000)
+#define PSM_FRCE_OFF_XIP_MSB _u(12)
+#define PSM_FRCE_OFF_XIP_LSB _u(12)
#define PSM_FRCE_OFF_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM5
// Description : None
-#define PSM_FRCE_OFF_SRAM5_RESET _U(0x0)
-#define PSM_FRCE_OFF_SRAM5_BITS _U(0x00000800)
-#define PSM_FRCE_OFF_SRAM5_MSB _U(11)
-#define PSM_FRCE_OFF_SRAM5_LSB _U(11)
+#define PSM_FRCE_OFF_SRAM5_RESET _u(0x0)
+#define PSM_FRCE_OFF_SRAM5_BITS _u(0x00000800)
+#define PSM_FRCE_OFF_SRAM5_MSB _u(11)
+#define PSM_FRCE_OFF_SRAM5_LSB _u(11)
#define PSM_FRCE_OFF_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM4
// Description : None
-#define PSM_FRCE_OFF_SRAM4_RESET _U(0x0)
-#define PSM_FRCE_OFF_SRAM4_BITS _U(0x00000400)
-#define PSM_FRCE_OFF_SRAM4_MSB _U(10)
-#define PSM_FRCE_OFF_SRAM4_LSB _U(10)
+#define PSM_FRCE_OFF_SRAM4_RESET _u(0x0)
+#define PSM_FRCE_OFF_SRAM4_BITS _u(0x00000400)
+#define PSM_FRCE_OFF_SRAM4_MSB _u(10)
+#define PSM_FRCE_OFF_SRAM4_LSB _u(10)
#define PSM_FRCE_OFF_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM3
// Description : None
-#define PSM_FRCE_OFF_SRAM3_RESET _U(0x0)
-#define PSM_FRCE_OFF_SRAM3_BITS _U(0x00000200)
-#define PSM_FRCE_OFF_SRAM3_MSB _U(9)
-#define PSM_FRCE_OFF_SRAM3_LSB _U(9)
+#define PSM_FRCE_OFF_SRAM3_RESET _u(0x0)
+#define PSM_FRCE_OFF_SRAM3_BITS _u(0x00000200)
+#define PSM_FRCE_OFF_SRAM3_MSB _u(9)
+#define PSM_FRCE_OFF_SRAM3_LSB _u(9)
#define PSM_FRCE_OFF_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM2
// Description : None
-#define PSM_FRCE_OFF_SRAM2_RESET _U(0x0)
-#define PSM_FRCE_OFF_SRAM2_BITS _U(0x00000100)
-#define PSM_FRCE_OFF_SRAM2_MSB _U(8)
-#define PSM_FRCE_OFF_SRAM2_LSB _U(8)
+#define PSM_FRCE_OFF_SRAM2_RESET _u(0x0)
+#define PSM_FRCE_OFF_SRAM2_BITS _u(0x00000100)
+#define PSM_FRCE_OFF_SRAM2_MSB _u(8)
+#define PSM_FRCE_OFF_SRAM2_LSB _u(8)
#define PSM_FRCE_OFF_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM1
// Description : None
-#define PSM_FRCE_OFF_SRAM1_RESET _U(0x0)
-#define PSM_FRCE_OFF_SRAM1_BITS _U(0x00000080)
-#define PSM_FRCE_OFF_SRAM1_MSB _U(7)
-#define PSM_FRCE_OFF_SRAM1_LSB _U(7)
+#define PSM_FRCE_OFF_SRAM1_RESET _u(0x0)
+#define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000080)
+#define PSM_FRCE_OFF_SRAM1_MSB _u(7)
+#define PSM_FRCE_OFF_SRAM1_LSB _u(7)
#define PSM_FRCE_OFF_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM0
// Description : None
-#define PSM_FRCE_OFF_SRAM0_RESET _U(0x0)
-#define PSM_FRCE_OFF_SRAM0_BITS _U(0x00000040)
-#define PSM_FRCE_OFF_SRAM0_MSB _U(6)
-#define PSM_FRCE_OFF_SRAM0_LSB _U(6)
+#define PSM_FRCE_OFF_SRAM0_RESET _u(0x0)
+#define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000040)
+#define PSM_FRCE_OFF_SRAM0_MSB _u(6)
+#define PSM_FRCE_OFF_SRAM0_LSB _u(6)
#define PSM_FRCE_OFF_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROM
// Description : None
-#define PSM_FRCE_OFF_ROM_RESET _U(0x0)
-#define PSM_FRCE_OFF_ROM_BITS _U(0x00000020)
-#define PSM_FRCE_OFF_ROM_MSB _U(5)
-#define PSM_FRCE_OFF_ROM_LSB _U(5)
+#define PSM_FRCE_OFF_ROM_RESET _u(0x0)
+#define PSM_FRCE_OFF_ROM_BITS _u(0x00000020)
+#define PSM_FRCE_OFF_ROM_MSB _u(5)
+#define PSM_FRCE_OFF_ROM_LSB _u(5)
#define PSM_FRCE_OFF_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_BUSFABRIC
// Description : None
-#define PSM_FRCE_OFF_BUSFABRIC_RESET _U(0x0)
-#define PSM_FRCE_OFF_BUSFABRIC_BITS _U(0x00000010)
-#define PSM_FRCE_OFF_BUSFABRIC_MSB _U(4)
-#define PSM_FRCE_OFF_BUSFABRIC_LSB _U(4)
+#define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0)
+#define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000010)
+#define PSM_FRCE_OFF_BUSFABRIC_MSB _u(4)
+#define PSM_FRCE_OFF_BUSFABRIC_LSB _u(4)
#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_RESETS
// Description : None
-#define PSM_FRCE_OFF_RESETS_RESET _U(0x0)
-#define PSM_FRCE_OFF_RESETS_BITS _U(0x00000008)
-#define PSM_FRCE_OFF_RESETS_MSB _U(3)
-#define PSM_FRCE_OFF_RESETS_LSB _U(3)
+#define PSM_FRCE_OFF_RESETS_RESET _u(0x0)
+#define PSM_FRCE_OFF_RESETS_BITS _u(0x00000008)
+#define PSM_FRCE_OFF_RESETS_MSB _u(3)
+#define PSM_FRCE_OFF_RESETS_LSB _u(3)
#define PSM_FRCE_OFF_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_CLOCKS
// Description : None
-#define PSM_FRCE_OFF_CLOCKS_RESET _U(0x0)
-#define PSM_FRCE_OFF_CLOCKS_BITS _U(0x00000004)
-#define PSM_FRCE_OFF_CLOCKS_MSB _U(2)
-#define PSM_FRCE_OFF_CLOCKS_LSB _U(2)
+#define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0)
+#define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000004)
+#define PSM_FRCE_OFF_CLOCKS_MSB _u(2)
+#define PSM_FRCE_OFF_CLOCKS_LSB _u(2)
#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XOSC
// Description : None
-#define PSM_FRCE_OFF_XOSC_RESET _U(0x0)
-#define PSM_FRCE_OFF_XOSC_BITS _U(0x00000002)
-#define PSM_FRCE_OFF_XOSC_MSB _U(1)
-#define PSM_FRCE_OFF_XOSC_LSB _U(1)
+#define PSM_FRCE_OFF_XOSC_RESET _u(0x0)
+#define PSM_FRCE_OFF_XOSC_BITS _u(0x00000002)
+#define PSM_FRCE_OFF_XOSC_MSB _u(1)
+#define PSM_FRCE_OFF_XOSC_LSB _u(1)
#define PSM_FRCE_OFF_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROSC
// Description : None
-#define PSM_FRCE_OFF_ROSC_RESET _U(0x0)
-#define PSM_FRCE_OFF_ROSC_BITS _U(0x00000001)
-#define PSM_FRCE_OFF_ROSC_MSB _U(0)
-#define PSM_FRCE_OFF_ROSC_LSB _U(0)
+#define PSM_FRCE_OFF_ROSC_RESET _u(0x0)
+#define PSM_FRCE_OFF_ROSC_BITS _u(0x00000001)
+#define PSM_FRCE_OFF_ROSC_MSB _u(0)
+#define PSM_FRCE_OFF_ROSC_LSB _u(0)
#define PSM_FRCE_OFF_ROSC_ACCESS "RW"
// =============================================================================
// Register : PSM_WDSEL
// Description : Set to 1 if this peripheral should be reset when the watchdog
// fires.
-#define PSM_WDSEL_OFFSET _U(0x00000008)
-#define PSM_WDSEL_BITS _U(0x0001ffff)
-#define PSM_WDSEL_RESET _U(0x00000000)
+#define PSM_WDSEL_OFFSET _u(0x00000008)
+#define PSM_WDSEL_BITS _u(0x0001ffff)
+#define PSM_WDSEL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC1
// Description : None
-#define PSM_WDSEL_PROC1_RESET _U(0x0)
-#define PSM_WDSEL_PROC1_BITS _U(0x00010000)
-#define PSM_WDSEL_PROC1_MSB _U(16)
-#define PSM_WDSEL_PROC1_LSB _U(16)
+#define PSM_WDSEL_PROC1_RESET _u(0x0)
+#define PSM_WDSEL_PROC1_BITS _u(0x00010000)
+#define PSM_WDSEL_PROC1_MSB _u(16)
+#define PSM_WDSEL_PROC1_LSB _u(16)
#define PSM_WDSEL_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC0
// Description : None
-#define PSM_WDSEL_PROC0_RESET _U(0x0)
-#define PSM_WDSEL_PROC0_BITS _U(0x00008000)
-#define PSM_WDSEL_PROC0_MSB _U(15)
-#define PSM_WDSEL_PROC0_LSB _U(15)
+#define PSM_WDSEL_PROC0_RESET _u(0x0)
+#define PSM_WDSEL_PROC0_BITS _u(0x00008000)
+#define PSM_WDSEL_PROC0_MSB _u(15)
+#define PSM_WDSEL_PROC0_LSB _u(15)
#define PSM_WDSEL_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SIO
// Description : None
-#define PSM_WDSEL_SIO_RESET _U(0x0)
-#define PSM_WDSEL_SIO_BITS _U(0x00004000)
-#define PSM_WDSEL_SIO_MSB _U(14)
-#define PSM_WDSEL_SIO_LSB _U(14)
+#define PSM_WDSEL_SIO_RESET _u(0x0)
+#define PSM_WDSEL_SIO_BITS _u(0x00004000)
+#define PSM_WDSEL_SIO_MSB _u(14)
+#define PSM_WDSEL_SIO_LSB _u(14)
#define PSM_WDSEL_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_VREG_AND_CHIP_RESET
// Description : None
-#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET _U(0x0)
-#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS _U(0x00002000)
-#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB _U(13)
-#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB _U(13)
+#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET _u(0x0)
+#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
+#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB _u(13)
+#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB _u(13)
#define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XIP
// Description : None
-#define PSM_WDSEL_XIP_RESET _U(0x0)
-#define PSM_WDSEL_XIP_BITS _U(0x00001000)
-#define PSM_WDSEL_XIP_MSB _U(12)
-#define PSM_WDSEL_XIP_LSB _U(12)
+#define PSM_WDSEL_XIP_RESET _u(0x0)
+#define PSM_WDSEL_XIP_BITS _u(0x00001000)
+#define PSM_WDSEL_XIP_MSB _u(12)
+#define PSM_WDSEL_XIP_LSB _u(12)
#define PSM_WDSEL_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM5
// Description : None
-#define PSM_WDSEL_SRAM5_RESET _U(0x0)
-#define PSM_WDSEL_SRAM5_BITS _U(0x00000800)
-#define PSM_WDSEL_SRAM5_MSB _U(11)
-#define PSM_WDSEL_SRAM5_LSB _U(11)
+#define PSM_WDSEL_SRAM5_RESET _u(0x0)
+#define PSM_WDSEL_SRAM5_BITS _u(0x00000800)
+#define PSM_WDSEL_SRAM5_MSB _u(11)
+#define PSM_WDSEL_SRAM5_LSB _u(11)
#define PSM_WDSEL_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM4
// Description : None
-#define PSM_WDSEL_SRAM4_RESET _U(0x0)
-#define PSM_WDSEL_SRAM4_BITS _U(0x00000400)
-#define PSM_WDSEL_SRAM4_MSB _U(10)
-#define PSM_WDSEL_SRAM4_LSB _U(10)
+#define PSM_WDSEL_SRAM4_RESET _u(0x0)
+#define PSM_WDSEL_SRAM4_BITS _u(0x00000400)
+#define PSM_WDSEL_SRAM4_MSB _u(10)
+#define PSM_WDSEL_SRAM4_LSB _u(10)
#define PSM_WDSEL_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM3
// Description : None
-#define PSM_WDSEL_SRAM3_RESET _U(0x0)
-#define PSM_WDSEL_SRAM3_BITS _U(0x00000200)
-#define PSM_WDSEL_SRAM3_MSB _U(9)
-#define PSM_WDSEL_SRAM3_LSB _U(9)
+#define PSM_WDSEL_SRAM3_RESET _u(0x0)
+#define PSM_WDSEL_SRAM3_BITS _u(0x00000200)
+#define PSM_WDSEL_SRAM3_MSB _u(9)
+#define PSM_WDSEL_SRAM3_LSB _u(9)
#define PSM_WDSEL_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM2
// Description : None
-#define PSM_WDSEL_SRAM2_RESET _U(0x0)
-#define PSM_WDSEL_SRAM2_BITS _U(0x00000100)
-#define PSM_WDSEL_SRAM2_MSB _U(8)
-#define PSM_WDSEL_SRAM2_LSB _U(8)
+#define PSM_WDSEL_SRAM2_RESET _u(0x0)
+#define PSM_WDSEL_SRAM2_BITS _u(0x00000100)
+#define PSM_WDSEL_SRAM2_MSB _u(8)
+#define PSM_WDSEL_SRAM2_LSB _u(8)
#define PSM_WDSEL_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM1
// Description : None
-#define PSM_WDSEL_SRAM1_RESET _U(0x0)
-#define PSM_WDSEL_SRAM1_BITS _U(0x00000080)
-#define PSM_WDSEL_SRAM1_MSB _U(7)
-#define PSM_WDSEL_SRAM1_LSB _U(7)
+#define PSM_WDSEL_SRAM1_RESET _u(0x0)
+#define PSM_WDSEL_SRAM1_BITS _u(0x00000080)
+#define PSM_WDSEL_SRAM1_MSB _u(7)
+#define PSM_WDSEL_SRAM1_LSB _u(7)
#define PSM_WDSEL_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM0
// Description : None
-#define PSM_WDSEL_SRAM0_RESET _U(0x0)
-#define PSM_WDSEL_SRAM0_BITS _U(0x00000040)
-#define PSM_WDSEL_SRAM0_MSB _U(6)
-#define PSM_WDSEL_SRAM0_LSB _U(6)
+#define PSM_WDSEL_SRAM0_RESET _u(0x0)
+#define PSM_WDSEL_SRAM0_BITS _u(0x00000040)
+#define PSM_WDSEL_SRAM0_MSB _u(6)
+#define PSM_WDSEL_SRAM0_LSB _u(6)
#define PSM_WDSEL_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROM
// Description : None
-#define PSM_WDSEL_ROM_RESET _U(0x0)
-#define PSM_WDSEL_ROM_BITS _U(0x00000020)
-#define PSM_WDSEL_ROM_MSB _U(5)
-#define PSM_WDSEL_ROM_LSB _U(5)
+#define PSM_WDSEL_ROM_RESET _u(0x0)
+#define PSM_WDSEL_ROM_BITS _u(0x00000020)
+#define PSM_WDSEL_ROM_MSB _u(5)
+#define PSM_WDSEL_ROM_LSB _u(5)
#define PSM_WDSEL_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_BUSFABRIC
// Description : None
-#define PSM_WDSEL_BUSFABRIC_RESET _U(0x0)
-#define PSM_WDSEL_BUSFABRIC_BITS _U(0x00000010)
-#define PSM_WDSEL_BUSFABRIC_MSB _U(4)
-#define PSM_WDSEL_BUSFABRIC_LSB _U(4)
+#define PSM_WDSEL_BUSFABRIC_RESET _u(0x0)
+#define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000010)
+#define PSM_WDSEL_BUSFABRIC_MSB _u(4)
+#define PSM_WDSEL_BUSFABRIC_LSB _u(4)
#define PSM_WDSEL_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_RESETS
// Description : None
-#define PSM_WDSEL_RESETS_RESET _U(0x0)
-#define PSM_WDSEL_RESETS_BITS _U(0x00000008)
-#define PSM_WDSEL_RESETS_MSB _U(3)
-#define PSM_WDSEL_RESETS_LSB _U(3)
+#define PSM_WDSEL_RESETS_RESET _u(0x0)
+#define PSM_WDSEL_RESETS_BITS _u(0x00000008)
+#define PSM_WDSEL_RESETS_MSB _u(3)
+#define PSM_WDSEL_RESETS_LSB _u(3)
#define PSM_WDSEL_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_CLOCKS
// Description : None
-#define PSM_WDSEL_CLOCKS_RESET _U(0x0)
-#define PSM_WDSEL_CLOCKS_BITS _U(0x00000004)
-#define PSM_WDSEL_CLOCKS_MSB _U(2)
-#define PSM_WDSEL_CLOCKS_LSB _U(2)
+#define PSM_WDSEL_CLOCKS_RESET _u(0x0)
+#define PSM_WDSEL_CLOCKS_BITS _u(0x00000004)
+#define PSM_WDSEL_CLOCKS_MSB _u(2)
+#define PSM_WDSEL_CLOCKS_LSB _u(2)
#define PSM_WDSEL_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XOSC
// Description : None
-#define PSM_WDSEL_XOSC_RESET _U(0x0)
-#define PSM_WDSEL_XOSC_BITS _U(0x00000002)
-#define PSM_WDSEL_XOSC_MSB _U(1)
-#define PSM_WDSEL_XOSC_LSB _U(1)
+#define PSM_WDSEL_XOSC_RESET _u(0x0)
+#define PSM_WDSEL_XOSC_BITS _u(0x00000002)
+#define PSM_WDSEL_XOSC_MSB _u(1)
+#define PSM_WDSEL_XOSC_LSB _u(1)
#define PSM_WDSEL_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROSC
// Description : None
-#define PSM_WDSEL_ROSC_RESET _U(0x0)
-#define PSM_WDSEL_ROSC_BITS _U(0x00000001)
-#define PSM_WDSEL_ROSC_MSB _U(0)
-#define PSM_WDSEL_ROSC_LSB _U(0)
+#define PSM_WDSEL_ROSC_RESET _u(0x0)
+#define PSM_WDSEL_ROSC_BITS _u(0x00000001)
+#define PSM_WDSEL_ROSC_MSB _u(0)
+#define PSM_WDSEL_ROSC_LSB _u(0)
#define PSM_WDSEL_ROSC_ACCESS "RW"
// =============================================================================
// Register : PSM_DONE
// Description : Indicates the peripheral's registers are ready to access.
-#define PSM_DONE_OFFSET _U(0x0000000c)
-#define PSM_DONE_BITS _U(0x0001ffff)
-#define PSM_DONE_RESET _U(0x00000000)
+#define PSM_DONE_OFFSET _u(0x0000000c)
+#define PSM_DONE_BITS _u(0x0001ffff)
+#define PSM_DONE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC1
// Description : None
-#define PSM_DONE_PROC1_RESET _U(0x0)
-#define PSM_DONE_PROC1_BITS _U(0x00010000)
-#define PSM_DONE_PROC1_MSB _U(16)
-#define PSM_DONE_PROC1_LSB _U(16)
+#define PSM_DONE_PROC1_RESET _u(0x0)
+#define PSM_DONE_PROC1_BITS _u(0x00010000)
+#define PSM_DONE_PROC1_MSB _u(16)
+#define PSM_DONE_PROC1_LSB _u(16)
#define PSM_DONE_PROC1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC0
// Description : None
-#define PSM_DONE_PROC0_RESET _U(0x0)
-#define PSM_DONE_PROC0_BITS _U(0x00008000)
-#define PSM_DONE_PROC0_MSB _U(15)
-#define PSM_DONE_PROC0_LSB _U(15)
+#define PSM_DONE_PROC0_RESET _u(0x0)
+#define PSM_DONE_PROC0_BITS _u(0x00008000)
+#define PSM_DONE_PROC0_MSB _u(15)
+#define PSM_DONE_PROC0_LSB _u(15)
#define PSM_DONE_PROC0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SIO
// Description : None
-#define PSM_DONE_SIO_RESET _U(0x0)
-#define PSM_DONE_SIO_BITS _U(0x00004000)
-#define PSM_DONE_SIO_MSB _U(14)
-#define PSM_DONE_SIO_LSB _U(14)
+#define PSM_DONE_SIO_RESET _u(0x0)
+#define PSM_DONE_SIO_BITS _u(0x00004000)
+#define PSM_DONE_SIO_MSB _u(14)
+#define PSM_DONE_SIO_LSB _u(14)
#define PSM_DONE_SIO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_VREG_AND_CHIP_RESET
// Description : None
-#define PSM_DONE_VREG_AND_CHIP_RESET_RESET _U(0x0)
-#define PSM_DONE_VREG_AND_CHIP_RESET_BITS _U(0x00002000)
-#define PSM_DONE_VREG_AND_CHIP_RESET_MSB _U(13)
-#define PSM_DONE_VREG_AND_CHIP_RESET_LSB _U(13)
+#define PSM_DONE_VREG_AND_CHIP_RESET_RESET _u(0x0)
+#define PSM_DONE_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
+#define PSM_DONE_VREG_AND_CHIP_RESET_MSB _u(13)
+#define PSM_DONE_VREG_AND_CHIP_RESET_LSB _u(13)
#define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XIP
// Description : None
-#define PSM_DONE_XIP_RESET _U(0x0)
-#define PSM_DONE_XIP_BITS _U(0x00001000)
-#define PSM_DONE_XIP_MSB _U(12)
-#define PSM_DONE_XIP_LSB _U(12)
+#define PSM_DONE_XIP_RESET _u(0x0)
+#define PSM_DONE_XIP_BITS _u(0x00001000)
+#define PSM_DONE_XIP_MSB _u(12)
+#define PSM_DONE_XIP_LSB _u(12)
#define PSM_DONE_XIP_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM5
// Description : None
-#define PSM_DONE_SRAM5_RESET _U(0x0)
-#define PSM_DONE_SRAM5_BITS _U(0x00000800)
-#define PSM_DONE_SRAM5_MSB _U(11)
-#define PSM_DONE_SRAM5_LSB _U(11)
+#define PSM_DONE_SRAM5_RESET _u(0x0)
+#define PSM_DONE_SRAM5_BITS _u(0x00000800)
+#define PSM_DONE_SRAM5_MSB _u(11)
+#define PSM_DONE_SRAM5_LSB _u(11)
#define PSM_DONE_SRAM5_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM4
// Description : None
-#define PSM_DONE_SRAM4_RESET _U(0x0)
-#define PSM_DONE_SRAM4_BITS _U(0x00000400)
-#define PSM_DONE_SRAM4_MSB _U(10)
-#define PSM_DONE_SRAM4_LSB _U(10)
+#define PSM_DONE_SRAM4_RESET _u(0x0)
+#define PSM_DONE_SRAM4_BITS _u(0x00000400)
+#define PSM_DONE_SRAM4_MSB _u(10)
+#define PSM_DONE_SRAM4_LSB _u(10)
#define PSM_DONE_SRAM4_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM3
// Description : None
-#define PSM_DONE_SRAM3_RESET _U(0x0)
-#define PSM_DONE_SRAM3_BITS _U(0x00000200)
-#define PSM_DONE_SRAM3_MSB _U(9)
-#define PSM_DONE_SRAM3_LSB _U(9)
+#define PSM_DONE_SRAM3_RESET _u(0x0)
+#define PSM_DONE_SRAM3_BITS _u(0x00000200)
+#define PSM_DONE_SRAM3_MSB _u(9)
+#define PSM_DONE_SRAM3_LSB _u(9)
#define PSM_DONE_SRAM3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM2
// Description : None
-#define PSM_DONE_SRAM2_RESET _U(0x0)
-#define PSM_DONE_SRAM2_BITS _U(0x00000100)
-#define PSM_DONE_SRAM2_MSB _U(8)
-#define PSM_DONE_SRAM2_LSB _U(8)
+#define PSM_DONE_SRAM2_RESET _u(0x0)
+#define PSM_DONE_SRAM2_BITS _u(0x00000100)
+#define PSM_DONE_SRAM2_MSB _u(8)
+#define PSM_DONE_SRAM2_LSB _u(8)
#define PSM_DONE_SRAM2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM1
// Description : None
-#define PSM_DONE_SRAM1_RESET _U(0x0)
-#define PSM_DONE_SRAM1_BITS _U(0x00000080)
-#define PSM_DONE_SRAM1_MSB _U(7)
-#define PSM_DONE_SRAM1_LSB _U(7)
+#define PSM_DONE_SRAM1_RESET _u(0x0)
+#define PSM_DONE_SRAM1_BITS _u(0x00000080)
+#define PSM_DONE_SRAM1_MSB _u(7)
+#define PSM_DONE_SRAM1_LSB _u(7)
#define PSM_DONE_SRAM1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM0
// Description : None
-#define PSM_DONE_SRAM0_RESET _U(0x0)
-#define PSM_DONE_SRAM0_BITS _U(0x00000040)
-#define PSM_DONE_SRAM0_MSB _U(6)
-#define PSM_DONE_SRAM0_LSB _U(6)
+#define PSM_DONE_SRAM0_RESET _u(0x0)
+#define PSM_DONE_SRAM0_BITS _u(0x00000040)
+#define PSM_DONE_SRAM0_MSB _u(6)
+#define PSM_DONE_SRAM0_LSB _u(6)
#define PSM_DONE_SRAM0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROM
// Description : None
-#define PSM_DONE_ROM_RESET _U(0x0)
-#define PSM_DONE_ROM_BITS _U(0x00000020)
-#define PSM_DONE_ROM_MSB _U(5)
-#define PSM_DONE_ROM_LSB _U(5)
+#define PSM_DONE_ROM_RESET _u(0x0)
+#define PSM_DONE_ROM_BITS _u(0x00000020)
+#define PSM_DONE_ROM_MSB _u(5)
+#define PSM_DONE_ROM_LSB _u(5)
#define PSM_DONE_ROM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_BUSFABRIC
// Description : None
-#define PSM_DONE_BUSFABRIC_RESET _U(0x0)
-#define PSM_DONE_BUSFABRIC_BITS _U(0x00000010)
-#define PSM_DONE_BUSFABRIC_MSB _U(4)
-#define PSM_DONE_BUSFABRIC_LSB _U(4)
+#define PSM_DONE_BUSFABRIC_RESET _u(0x0)
+#define PSM_DONE_BUSFABRIC_BITS _u(0x00000010)
+#define PSM_DONE_BUSFABRIC_MSB _u(4)
+#define PSM_DONE_BUSFABRIC_LSB _u(4)
#define PSM_DONE_BUSFABRIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_RESETS
// Description : None
-#define PSM_DONE_RESETS_RESET _U(0x0)
-#define PSM_DONE_RESETS_BITS _U(0x00000008)
-#define PSM_DONE_RESETS_MSB _U(3)
-#define PSM_DONE_RESETS_LSB _U(3)
+#define PSM_DONE_RESETS_RESET _u(0x0)
+#define PSM_DONE_RESETS_BITS _u(0x00000008)
+#define PSM_DONE_RESETS_MSB _u(3)
+#define PSM_DONE_RESETS_LSB _u(3)
#define PSM_DONE_RESETS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_CLOCKS
// Description : None
-#define PSM_DONE_CLOCKS_RESET _U(0x0)
-#define PSM_DONE_CLOCKS_BITS _U(0x00000004)
-#define PSM_DONE_CLOCKS_MSB _U(2)
-#define PSM_DONE_CLOCKS_LSB _U(2)
+#define PSM_DONE_CLOCKS_RESET _u(0x0)
+#define PSM_DONE_CLOCKS_BITS _u(0x00000004)
+#define PSM_DONE_CLOCKS_MSB _u(2)
+#define PSM_DONE_CLOCKS_LSB _u(2)
#define PSM_DONE_CLOCKS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XOSC
// Description : None
-#define PSM_DONE_XOSC_RESET _U(0x0)
-#define PSM_DONE_XOSC_BITS _U(0x00000002)
-#define PSM_DONE_XOSC_MSB _U(1)
-#define PSM_DONE_XOSC_LSB _U(1)
+#define PSM_DONE_XOSC_RESET _u(0x0)
+#define PSM_DONE_XOSC_BITS _u(0x00000002)
+#define PSM_DONE_XOSC_MSB _u(1)
+#define PSM_DONE_XOSC_LSB _u(1)
#define PSM_DONE_XOSC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROSC
// Description : None
-#define PSM_DONE_ROSC_RESET _U(0x0)
-#define PSM_DONE_ROSC_BITS _U(0x00000001)
-#define PSM_DONE_ROSC_MSB _U(0)
-#define PSM_DONE_ROSC_LSB _U(0)
+#define PSM_DONE_ROSC_RESET _u(0x0)
+#define PSM_DONE_ROSC_BITS _u(0x00000001)
+#define PSM_DONE_ROSC_MSB _u(0)
+#define PSM_DONE_ROSC_LSB _u(0)
#define PSM_DONE_ROSC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_PSM_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pwm.h b/src/rp2040/hardware_regs/include/hardware/regs/pwm.h
index 988cfdc..a853597 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/pwm.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/pwm.h
@@ -14,9 +14,9 @@
// =============================================================================
// Register : PWM_CH0_CSR
// Description : Control and status register
-#define PWM_CH0_CSR_OFFSET _U(0x00000000)
-#define PWM_CH0_CSR_BITS _U(0x000000ff)
-#define PWM_CH0_CSR_RESET _U(0x00000000)
+#define PWM_CH0_CSR_OFFSET _u(0x00000000)
+#define PWM_CH0_CSR_BITS _u(0x000000ff)
+#define PWM_CH0_CSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH0_CSR_PH_ADV
// Description : Advance the phase of the counter by 1 count, while it is
@@ -24,10 +24,10 @@
// Self-clearing. Write a 1, and poll until low. Counter must be
// running
// at less than full speed (div_int + div_frac / 16 > 1)
-#define PWM_CH0_CSR_PH_ADV_RESET _U(0x0)
-#define PWM_CH0_CSR_PH_ADV_BITS _U(0x00000080)
-#define PWM_CH0_CSR_PH_ADV_MSB _U(7)
-#define PWM_CH0_CSR_PH_ADV_LSB _U(7)
+#define PWM_CH0_CSR_PH_ADV_RESET _u(0x0)
+#define PWM_CH0_CSR_PH_ADV_BITS _u(0x00000080)
+#define PWM_CH0_CSR_PH_ADV_MSB _u(7)
+#define PWM_CH0_CSR_PH_ADV_LSB _u(7)
#define PWM_CH0_CSR_PH_ADV_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH0_CSR_PH_RET
@@ -35,10 +35,10 @@
// running.
// Self-clearing. Write a 1, and poll until low. Counter must be
// running.
-#define PWM_CH0_CSR_PH_RET_RESET _U(0x0)
-#define PWM_CH0_CSR_PH_RET_BITS _U(0x00000040)
-#define PWM_CH0_CSR_PH_RET_MSB _U(6)
-#define PWM_CH0_CSR_PH_RET_LSB _U(6)
+#define PWM_CH0_CSR_PH_RET_RESET _u(0x0)
+#define PWM_CH0_CSR_PH_RET_BITS _u(0x00000040)
+#define PWM_CH0_CSR_PH_RET_MSB _u(6)
+#define PWM_CH0_CSR_PH_RET_LSB _u(6)
#define PWM_CH0_CSR_PH_RET_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH0_CSR_DIVMODE
@@ -48,117 +48,117 @@
// 0x2 -> Counter advances with each rising edge of the PWM B pin.
// 0x3 -> Counter advances with each falling edge of the PWM B
// pin.
-#define PWM_CH0_CSR_DIVMODE_RESET _U(0x0)
-#define PWM_CH0_CSR_DIVMODE_BITS _U(0x00000030)
-#define PWM_CH0_CSR_DIVMODE_MSB _U(5)
-#define PWM_CH0_CSR_DIVMODE_LSB _U(4)
+#define PWM_CH0_CSR_DIVMODE_RESET _u(0x0)
+#define PWM_CH0_CSR_DIVMODE_BITS _u(0x00000030)
+#define PWM_CH0_CSR_DIVMODE_MSB _u(5)
+#define PWM_CH0_CSR_DIVMODE_LSB _u(4)
#define PWM_CH0_CSR_DIVMODE_ACCESS "RW"
-#define PWM_CH0_CSR_DIVMODE_VALUE_DIV _U(0x0)
-#define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL _U(0x1)
-#define PWM_CH0_CSR_DIVMODE_VALUE_RISE _U(0x2)
-#define PWM_CH0_CSR_DIVMODE_VALUE_FALL _U(0x3)
+#define PWM_CH0_CSR_DIVMODE_VALUE_DIV _u(0x0)
+#define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH0_CSR_DIVMODE_VALUE_RISE _u(0x2)
+#define PWM_CH0_CSR_DIVMODE_VALUE_FALL _u(0x3)
// -----------------------------------------------------------------------------
// Field : PWM_CH0_CSR_B_INV
// Description : Invert output B
-#define PWM_CH0_CSR_B_INV_RESET _U(0x0)
-#define PWM_CH0_CSR_B_INV_BITS _U(0x00000008)
-#define PWM_CH0_CSR_B_INV_MSB _U(3)
-#define PWM_CH0_CSR_B_INV_LSB _U(3)
+#define PWM_CH0_CSR_B_INV_RESET _u(0x0)
+#define PWM_CH0_CSR_B_INV_BITS _u(0x00000008)
+#define PWM_CH0_CSR_B_INV_MSB _u(3)
+#define PWM_CH0_CSR_B_INV_LSB _u(3)
#define PWM_CH0_CSR_B_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH0_CSR_A_INV
// Description : Invert output A
-#define PWM_CH0_CSR_A_INV_RESET _U(0x0)
-#define PWM_CH0_CSR_A_INV_BITS _U(0x00000004)
-#define PWM_CH0_CSR_A_INV_MSB _U(2)
-#define PWM_CH0_CSR_A_INV_LSB _U(2)
+#define PWM_CH0_CSR_A_INV_RESET _u(0x0)
+#define PWM_CH0_CSR_A_INV_BITS _u(0x00000004)
+#define PWM_CH0_CSR_A_INV_MSB _u(2)
+#define PWM_CH0_CSR_A_INV_LSB _u(2)
#define PWM_CH0_CSR_A_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH0_CSR_PH_CORRECT
// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
-#define PWM_CH0_CSR_PH_CORRECT_RESET _U(0x0)
-#define PWM_CH0_CSR_PH_CORRECT_BITS _U(0x00000002)
-#define PWM_CH0_CSR_PH_CORRECT_MSB _U(1)
-#define PWM_CH0_CSR_PH_CORRECT_LSB _U(1)
+#define PWM_CH0_CSR_PH_CORRECT_RESET _u(0x0)
+#define PWM_CH0_CSR_PH_CORRECT_BITS _u(0x00000002)
+#define PWM_CH0_CSR_PH_CORRECT_MSB _u(1)
+#define PWM_CH0_CSR_PH_CORRECT_LSB _u(1)
#define PWM_CH0_CSR_PH_CORRECT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH0_CSR_EN
// Description : Enable the PWM channel.
-#define PWM_CH0_CSR_EN_RESET _U(0x0)
-#define PWM_CH0_CSR_EN_BITS _U(0x00000001)
-#define PWM_CH0_CSR_EN_MSB _U(0)
-#define PWM_CH0_CSR_EN_LSB _U(0)
+#define PWM_CH0_CSR_EN_RESET _u(0x0)
+#define PWM_CH0_CSR_EN_BITS _u(0x00000001)
+#define PWM_CH0_CSR_EN_MSB _u(0)
+#define PWM_CH0_CSR_EN_LSB _u(0)
#define PWM_CH0_CSR_EN_ACCESS "RW"
// =============================================================================
// Register : PWM_CH0_DIV
// Description : INT and FRAC form a fixed-point fractional number.
// Counting rate is system clock frequency divided by this number.
// Fractional division uses simple 1st-order sigma-delta.
-#define PWM_CH0_DIV_OFFSET _U(0x00000004)
-#define PWM_CH0_DIV_BITS _U(0x00000fff)
-#define PWM_CH0_DIV_RESET _U(0x00000010)
+#define PWM_CH0_DIV_OFFSET _u(0x00000004)
+#define PWM_CH0_DIV_BITS _u(0x00000fff)
+#define PWM_CH0_DIV_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : PWM_CH0_DIV_INT
// Description : None
-#define PWM_CH0_DIV_INT_RESET _U(0x01)
-#define PWM_CH0_DIV_INT_BITS _U(0x00000ff0)
-#define PWM_CH0_DIV_INT_MSB _U(11)
-#define PWM_CH0_DIV_INT_LSB _U(4)
+#define PWM_CH0_DIV_INT_RESET _u(0x01)
+#define PWM_CH0_DIV_INT_BITS _u(0x00000ff0)
+#define PWM_CH0_DIV_INT_MSB _u(11)
+#define PWM_CH0_DIV_INT_LSB _u(4)
#define PWM_CH0_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH0_DIV_FRAC
// Description : None
-#define PWM_CH0_DIV_FRAC_RESET _U(0x0)
-#define PWM_CH0_DIV_FRAC_BITS _U(0x0000000f)
-#define PWM_CH0_DIV_FRAC_MSB _U(3)
-#define PWM_CH0_DIV_FRAC_LSB _U(0)
+#define PWM_CH0_DIV_FRAC_RESET _u(0x0)
+#define PWM_CH0_DIV_FRAC_BITS _u(0x0000000f)
+#define PWM_CH0_DIV_FRAC_MSB _u(3)
+#define PWM_CH0_DIV_FRAC_LSB _u(0)
#define PWM_CH0_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : PWM_CH0_CTR
// Description : Direct access to the PWM counter
-#define PWM_CH0_CTR_OFFSET _U(0x00000008)
-#define PWM_CH0_CTR_BITS _U(0x0000ffff)
-#define PWM_CH0_CTR_RESET _U(0x00000000)
-#define PWM_CH0_CTR_MSB _U(15)
-#define PWM_CH0_CTR_LSB _U(0)
+#define PWM_CH0_CTR_OFFSET _u(0x00000008)
+#define PWM_CH0_CTR_BITS _u(0x0000ffff)
+#define PWM_CH0_CTR_RESET _u(0x00000000)
+#define PWM_CH0_CTR_MSB _u(15)
+#define PWM_CH0_CTR_LSB _u(0)
#define PWM_CH0_CTR_ACCESS "RW"
// =============================================================================
// Register : PWM_CH0_CC
// Description : Counter compare values
-#define PWM_CH0_CC_OFFSET _U(0x0000000c)
-#define PWM_CH0_CC_BITS _U(0xffffffff)
-#define PWM_CH0_CC_RESET _U(0x00000000)
+#define PWM_CH0_CC_OFFSET _u(0x0000000c)
+#define PWM_CH0_CC_BITS _u(0xffffffff)
+#define PWM_CH0_CC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH0_CC_B
// Description : None
-#define PWM_CH0_CC_B_RESET _U(0x0000)
-#define PWM_CH0_CC_B_BITS _U(0xffff0000)
-#define PWM_CH0_CC_B_MSB _U(31)
-#define PWM_CH0_CC_B_LSB _U(16)
+#define PWM_CH0_CC_B_RESET _u(0x0000)
+#define PWM_CH0_CC_B_BITS _u(0xffff0000)
+#define PWM_CH0_CC_B_MSB _u(31)
+#define PWM_CH0_CC_B_LSB _u(16)
#define PWM_CH0_CC_B_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH0_CC_A
// Description : None
-#define PWM_CH0_CC_A_RESET _U(0x0000)
-#define PWM_CH0_CC_A_BITS _U(0x0000ffff)
-#define PWM_CH0_CC_A_MSB _U(15)
-#define PWM_CH0_CC_A_LSB _U(0)
+#define PWM_CH0_CC_A_RESET _u(0x0000)
+#define PWM_CH0_CC_A_BITS _u(0x0000ffff)
+#define PWM_CH0_CC_A_MSB _u(15)
+#define PWM_CH0_CC_A_LSB _u(0)
#define PWM_CH0_CC_A_ACCESS "RW"
// =============================================================================
// Register : PWM_CH0_TOP
// Description : Counter wrap value
-#define PWM_CH0_TOP_OFFSET _U(0x00000010)
-#define PWM_CH0_TOP_BITS _U(0x0000ffff)
-#define PWM_CH0_TOP_RESET _U(0x0000ffff)
-#define PWM_CH0_TOP_MSB _U(15)
-#define PWM_CH0_TOP_LSB _U(0)
+#define PWM_CH0_TOP_OFFSET _u(0x00000010)
+#define PWM_CH0_TOP_BITS _u(0x0000ffff)
+#define PWM_CH0_TOP_RESET _u(0x0000ffff)
+#define PWM_CH0_TOP_MSB _u(15)
+#define PWM_CH0_TOP_LSB _u(0)
#define PWM_CH0_TOP_ACCESS "RW"
// =============================================================================
// Register : PWM_CH1_CSR
// Description : Control and status register
-#define PWM_CH1_CSR_OFFSET _U(0x00000014)
-#define PWM_CH1_CSR_BITS _U(0x000000ff)
-#define PWM_CH1_CSR_RESET _U(0x00000000)
+#define PWM_CH1_CSR_OFFSET _u(0x00000014)
+#define PWM_CH1_CSR_BITS _u(0x000000ff)
+#define PWM_CH1_CSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH1_CSR_PH_ADV
// Description : Advance the phase of the counter by 1 count, while it is
@@ -166,10 +166,10 @@
// Self-clearing. Write a 1, and poll until low. Counter must be
// running
// at less than full speed (div_int + div_frac / 16 > 1)
-#define PWM_CH1_CSR_PH_ADV_RESET _U(0x0)
-#define PWM_CH1_CSR_PH_ADV_BITS _U(0x00000080)
-#define PWM_CH1_CSR_PH_ADV_MSB _U(7)
-#define PWM_CH1_CSR_PH_ADV_LSB _U(7)
+#define PWM_CH1_CSR_PH_ADV_RESET _u(0x0)
+#define PWM_CH1_CSR_PH_ADV_BITS _u(0x00000080)
+#define PWM_CH1_CSR_PH_ADV_MSB _u(7)
+#define PWM_CH1_CSR_PH_ADV_LSB _u(7)
#define PWM_CH1_CSR_PH_ADV_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH1_CSR_PH_RET
@@ -177,10 +177,10 @@
// running.
// Self-clearing. Write a 1, and poll until low. Counter must be
// running.
-#define PWM_CH1_CSR_PH_RET_RESET _U(0x0)
-#define PWM_CH1_CSR_PH_RET_BITS _U(0x00000040)
-#define PWM_CH1_CSR_PH_RET_MSB _U(6)
-#define PWM_CH1_CSR_PH_RET_LSB _U(6)
+#define PWM_CH1_CSR_PH_RET_RESET _u(0x0)
+#define PWM_CH1_CSR_PH_RET_BITS _u(0x00000040)
+#define PWM_CH1_CSR_PH_RET_MSB _u(6)
+#define PWM_CH1_CSR_PH_RET_LSB _u(6)
#define PWM_CH1_CSR_PH_RET_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH1_CSR_DIVMODE
@@ -190,117 +190,117 @@
// 0x2 -> Counter advances with each rising edge of the PWM B pin.
// 0x3 -> Counter advances with each falling edge of the PWM B
// pin.
-#define PWM_CH1_CSR_DIVMODE_RESET _U(0x0)
-#define PWM_CH1_CSR_DIVMODE_BITS _U(0x00000030)
-#define PWM_CH1_CSR_DIVMODE_MSB _U(5)
-#define PWM_CH1_CSR_DIVMODE_LSB _U(4)
+#define PWM_CH1_CSR_DIVMODE_RESET _u(0x0)
+#define PWM_CH1_CSR_DIVMODE_BITS _u(0x00000030)
+#define PWM_CH1_CSR_DIVMODE_MSB _u(5)
+#define PWM_CH1_CSR_DIVMODE_LSB _u(4)
#define PWM_CH1_CSR_DIVMODE_ACCESS "RW"
-#define PWM_CH1_CSR_DIVMODE_VALUE_DIV _U(0x0)
-#define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL _U(0x1)
-#define PWM_CH1_CSR_DIVMODE_VALUE_RISE _U(0x2)
-#define PWM_CH1_CSR_DIVMODE_VALUE_FALL _U(0x3)
+#define PWM_CH1_CSR_DIVMODE_VALUE_DIV _u(0x0)
+#define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH1_CSR_DIVMODE_VALUE_RISE _u(0x2)
+#define PWM_CH1_CSR_DIVMODE_VALUE_FALL _u(0x3)
// -----------------------------------------------------------------------------
// Field : PWM_CH1_CSR_B_INV
// Description : Invert output B
-#define PWM_CH1_CSR_B_INV_RESET _U(0x0)
-#define PWM_CH1_CSR_B_INV_BITS _U(0x00000008)
-#define PWM_CH1_CSR_B_INV_MSB _U(3)
-#define PWM_CH1_CSR_B_INV_LSB _U(3)
+#define PWM_CH1_CSR_B_INV_RESET _u(0x0)
+#define PWM_CH1_CSR_B_INV_BITS _u(0x00000008)
+#define PWM_CH1_CSR_B_INV_MSB _u(3)
+#define PWM_CH1_CSR_B_INV_LSB _u(3)
#define PWM_CH1_CSR_B_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH1_CSR_A_INV
// Description : Invert output A
-#define PWM_CH1_CSR_A_INV_RESET _U(0x0)
-#define PWM_CH1_CSR_A_INV_BITS _U(0x00000004)
-#define PWM_CH1_CSR_A_INV_MSB _U(2)
-#define PWM_CH1_CSR_A_INV_LSB _U(2)
+#define PWM_CH1_CSR_A_INV_RESET _u(0x0)
+#define PWM_CH1_CSR_A_INV_BITS _u(0x00000004)
+#define PWM_CH1_CSR_A_INV_MSB _u(2)
+#define PWM_CH1_CSR_A_INV_LSB _u(2)
#define PWM_CH1_CSR_A_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH1_CSR_PH_CORRECT
// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
-#define PWM_CH1_CSR_PH_CORRECT_RESET _U(0x0)
-#define PWM_CH1_CSR_PH_CORRECT_BITS _U(0x00000002)
-#define PWM_CH1_CSR_PH_CORRECT_MSB _U(1)
-#define PWM_CH1_CSR_PH_CORRECT_LSB _U(1)
+#define PWM_CH1_CSR_PH_CORRECT_RESET _u(0x0)
+#define PWM_CH1_CSR_PH_CORRECT_BITS _u(0x00000002)
+#define PWM_CH1_CSR_PH_CORRECT_MSB _u(1)
+#define PWM_CH1_CSR_PH_CORRECT_LSB _u(1)
#define PWM_CH1_CSR_PH_CORRECT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH1_CSR_EN
// Description : Enable the PWM channel.
-#define PWM_CH1_CSR_EN_RESET _U(0x0)
-#define PWM_CH1_CSR_EN_BITS _U(0x00000001)
-#define PWM_CH1_CSR_EN_MSB _U(0)
-#define PWM_CH1_CSR_EN_LSB _U(0)
+#define PWM_CH1_CSR_EN_RESET _u(0x0)
+#define PWM_CH1_CSR_EN_BITS _u(0x00000001)
+#define PWM_CH1_CSR_EN_MSB _u(0)
+#define PWM_CH1_CSR_EN_LSB _u(0)
#define PWM_CH1_CSR_EN_ACCESS "RW"
// =============================================================================
// Register : PWM_CH1_DIV
// Description : INT and FRAC form a fixed-point fractional number.
// Counting rate is system clock frequency divided by this number.
// Fractional division uses simple 1st-order sigma-delta.
-#define PWM_CH1_DIV_OFFSET _U(0x00000018)
-#define PWM_CH1_DIV_BITS _U(0x00000fff)
-#define PWM_CH1_DIV_RESET _U(0x00000010)
+#define PWM_CH1_DIV_OFFSET _u(0x00000018)
+#define PWM_CH1_DIV_BITS _u(0x00000fff)
+#define PWM_CH1_DIV_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : PWM_CH1_DIV_INT
// Description : None
-#define PWM_CH1_DIV_INT_RESET _U(0x01)
-#define PWM_CH1_DIV_INT_BITS _U(0x00000ff0)
-#define PWM_CH1_DIV_INT_MSB _U(11)
-#define PWM_CH1_DIV_INT_LSB _U(4)
+#define PWM_CH1_DIV_INT_RESET _u(0x01)
+#define PWM_CH1_DIV_INT_BITS _u(0x00000ff0)
+#define PWM_CH1_DIV_INT_MSB _u(11)
+#define PWM_CH1_DIV_INT_LSB _u(4)
#define PWM_CH1_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH1_DIV_FRAC
// Description : None
-#define PWM_CH1_DIV_FRAC_RESET _U(0x0)
-#define PWM_CH1_DIV_FRAC_BITS _U(0x0000000f)
-#define PWM_CH1_DIV_FRAC_MSB _U(3)
-#define PWM_CH1_DIV_FRAC_LSB _U(0)
+#define PWM_CH1_DIV_FRAC_RESET _u(0x0)
+#define PWM_CH1_DIV_FRAC_BITS _u(0x0000000f)
+#define PWM_CH1_DIV_FRAC_MSB _u(3)
+#define PWM_CH1_DIV_FRAC_LSB _u(0)
#define PWM_CH1_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : PWM_CH1_CTR
// Description : Direct access to the PWM counter
-#define PWM_CH1_CTR_OFFSET _U(0x0000001c)
-#define PWM_CH1_CTR_BITS _U(0x0000ffff)
-#define PWM_CH1_CTR_RESET _U(0x00000000)
-#define PWM_CH1_CTR_MSB _U(15)
-#define PWM_CH1_CTR_LSB _U(0)
+#define PWM_CH1_CTR_OFFSET _u(0x0000001c)
+#define PWM_CH1_CTR_BITS _u(0x0000ffff)
+#define PWM_CH1_CTR_RESET _u(0x00000000)
+#define PWM_CH1_CTR_MSB _u(15)
+#define PWM_CH1_CTR_LSB _u(0)
#define PWM_CH1_CTR_ACCESS "RW"
// =============================================================================
// Register : PWM_CH1_CC
// Description : Counter compare values
-#define PWM_CH1_CC_OFFSET _U(0x00000020)
-#define PWM_CH1_CC_BITS _U(0xffffffff)
-#define PWM_CH1_CC_RESET _U(0x00000000)
+#define PWM_CH1_CC_OFFSET _u(0x00000020)
+#define PWM_CH1_CC_BITS _u(0xffffffff)
+#define PWM_CH1_CC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH1_CC_B
// Description : None
-#define PWM_CH1_CC_B_RESET _U(0x0000)
-#define PWM_CH1_CC_B_BITS _U(0xffff0000)
-#define PWM_CH1_CC_B_MSB _U(31)
-#define PWM_CH1_CC_B_LSB _U(16)
+#define PWM_CH1_CC_B_RESET _u(0x0000)
+#define PWM_CH1_CC_B_BITS _u(0xffff0000)
+#define PWM_CH1_CC_B_MSB _u(31)
+#define PWM_CH1_CC_B_LSB _u(16)
#define PWM_CH1_CC_B_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH1_CC_A
// Description : None
-#define PWM_CH1_CC_A_RESET _U(0x0000)
-#define PWM_CH1_CC_A_BITS _U(0x0000ffff)
-#define PWM_CH1_CC_A_MSB _U(15)
-#define PWM_CH1_CC_A_LSB _U(0)
+#define PWM_CH1_CC_A_RESET _u(0x0000)
+#define PWM_CH1_CC_A_BITS _u(0x0000ffff)
+#define PWM_CH1_CC_A_MSB _u(15)
+#define PWM_CH1_CC_A_LSB _u(0)
#define PWM_CH1_CC_A_ACCESS "RW"
// =============================================================================
// Register : PWM_CH1_TOP
// Description : Counter wrap value
-#define PWM_CH1_TOP_OFFSET _U(0x00000024)
-#define PWM_CH1_TOP_BITS _U(0x0000ffff)
-#define PWM_CH1_TOP_RESET _U(0x0000ffff)
-#define PWM_CH1_TOP_MSB _U(15)
-#define PWM_CH1_TOP_LSB _U(0)
+#define PWM_CH1_TOP_OFFSET _u(0x00000024)
+#define PWM_CH1_TOP_BITS _u(0x0000ffff)
+#define PWM_CH1_TOP_RESET _u(0x0000ffff)
+#define PWM_CH1_TOP_MSB _u(15)
+#define PWM_CH1_TOP_LSB _u(0)
#define PWM_CH1_TOP_ACCESS "RW"
// =============================================================================
// Register : PWM_CH2_CSR
// Description : Control and status register
-#define PWM_CH2_CSR_OFFSET _U(0x00000028)
-#define PWM_CH2_CSR_BITS _U(0x000000ff)
-#define PWM_CH2_CSR_RESET _U(0x00000000)
+#define PWM_CH2_CSR_OFFSET _u(0x00000028)
+#define PWM_CH2_CSR_BITS _u(0x000000ff)
+#define PWM_CH2_CSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH2_CSR_PH_ADV
// Description : Advance the phase of the counter by 1 count, while it is
@@ -308,10 +308,10 @@
// Self-clearing. Write a 1, and poll until low. Counter must be
// running
// at less than full speed (div_int + div_frac / 16 > 1)
-#define PWM_CH2_CSR_PH_ADV_RESET _U(0x0)
-#define PWM_CH2_CSR_PH_ADV_BITS _U(0x00000080)
-#define PWM_CH2_CSR_PH_ADV_MSB _U(7)
-#define PWM_CH2_CSR_PH_ADV_LSB _U(7)
+#define PWM_CH2_CSR_PH_ADV_RESET _u(0x0)
+#define PWM_CH2_CSR_PH_ADV_BITS _u(0x00000080)
+#define PWM_CH2_CSR_PH_ADV_MSB _u(7)
+#define PWM_CH2_CSR_PH_ADV_LSB _u(7)
#define PWM_CH2_CSR_PH_ADV_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH2_CSR_PH_RET
@@ -319,10 +319,10 @@
// running.
// Self-clearing. Write a 1, and poll until low. Counter must be
// running.
-#define PWM_CH2_CSR_PH_RET_RESET _U(0x0)
-#define PWM_CH2_CSR_PH_RET_BITS _U(0x00000040)
-#define PWM_CH2_CSR_PH_RET_MSB _U(6)
-#define PWM_CH2_CSR_PH_RET_LSB _U(6)
+#define PWM_CH2_CSR_PH_RET_RESET _u(0x0)
+#define PWM_CH2_CSR_PH_RET_BITS _u(0x00000040)
+#define PWM_CH2_CSR_PH_RET_MSB _u(6)
+#define PWM_CH2_CSR_PH_RET_LSB _u(6)
#define PWM_CH2_CSR_PH_RET_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH2_CSR_DIVMODE
@@ -332,117 +332,117 @@
// 0x2 -> Counter advances with each rising edge of the PWM B pin.
// 0x3 -> Counter advances with each falling edge of the PWM B
// pin.
-#define PWM_CH2_CSR_DIVMODE_RESET _U(0x0)
-#define PWM_CH2_CSR_DIVMODE_BITS _U(0x00000030)
-#define PWM_CH2_CSR_DIVMODE_MSB _U(5)
-#define PWM_CH2_CSR_DIVMODE_LSB _U(4)
+#define PWM_CH2_CSR_DIVMODE_RESET _u(0x0)
+#define PWM_CH2_CSR_DIVMODE_BITS _u(0x00000030)
+#define PWM_CH2_CSR_DIVMODE_MSB _u(5)
+#define PWM_CH2_CSR_DIVMODE_LSB _u(4)
#define PWM_CH2_CSR_DIVMODE_ACCESS "RW"
-#define PWM_CH2_CSR_DIVMODE_VALUE_DIV _U(0x0)
-#define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL _U(0x1)
-#define PWM_CH2_CSR_DIVMODE_VALUE_RISE _U(0x2)
-#define PWM_CH2_CSR_DIVMODE_VALUE_FALL _U(0x3)
+#define PWM_CH2_CSR_DIVMODE_VALUE_DIV _u(0x0)
+#define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH2_CSR_DIVMODE_VALUE_RISE _u(0x2)
+#define PWM_CH2_CSR_DIVMODE_VALUE_FALL _u(0x3)
// -----------------------------------------------------------------------------
// Field : PWM_CH2_CSR_B_INV
// Description : Invert output B
-#define PWM_CH2_CSR_B_INV_RESET _U(0x0)
-#define PWM_CH2_CSR_B_INV_BITS _U(0x00000008)
-#define PWM_CH2_CSR_B_INV_MSB _U(3)
-#define PWM_CH2_CSR_B_INV_LSB _U(3)
+#define PWM_CH2_CSR_B_INV_RESET _u(0x0)
+#define PWM_CH2_CSR_B_INV_BITS _u(0x00000008)
+#define PWM_CH2_CSR_B_INV_MSB _u(3)
+#define PWM_CH2_CSR_B_INV_LSB _u(3)
#define PWM_CH2_CSR_B_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH2_CSR_A_INV
// Description : Invert output A
-#define PWM_CH2_CSR_A_INV_RESET _U(0x0)
-#define PWM_CH2_CSR_A_INV_BITS _U(0x00000004)
-#define PWM_CH2_CSR_A_INV_MSB _U(2)
-#define PWM_CH2_CSR_A_INV_LSB _U(2)
+#define PWM_CH2_CSR_A_INV_RESET _u(0x0)
+#define PWM_CH2_CSR_A_INV_BITS _u(0x00000004)
+#define PWM_CH2_CSR_A_INV_MSB _u(2)
+#define PWM_CH2_CSR_A_INV_LSB _u(2)
#define PWM_CH2_CSR_A_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH2_CSR_PH_CORRECT
// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
-#define PWM_CH2_CSR_PH_CORRECT_RESET _U(0x0)
-#define PWM_CH2_CSR_PH_CORRECT_BITS _U(0x00000002)
-#define PWM_CH2_CSR_PH_CORRECT_MSB _U(1)
-#define PWM_CH2_CSR_PH_CORRECT_LSB _U(1)
+#define PWM_CH2_CSR_PH_CORRECT_RESET _u(0x0)
+#define PWM_CH2_CSR_PH_CORRECT_BITS _u(0x00000002)
+#define PWM_CH2_CSR_PH_CORRECT_MSB _u(1)
+#define PWM_CH2_CSR_PH_CORRECT_LSB _u(1)
#define PWM_CH2_CSR_PH_CORRECT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH2_CSR_EN
// Description : Enable the PWM channel.
-#define PWM_CH2_CSR_EN_RESET _U(0x0)
-#define PWM_CH2_CSR_EN_BITS _U(0x00000001)
-#define PWM_CH2_CSR_EN_MSB _U(0)
-#define PWM_CH2_CSR_EN_LSB _U(0)
+#define PWM_CH2_CSR_EN_RESET _u(0x0)
+#define PWM_CH2_CSR_EN_BITS _u(0x00000001)
+#define PWM_CH2_CSR_EN_MSB _u(0)
+#define PWM_CH2_CSR_EN_LSB _u(0)
#define PWM_CH2_CSR_EN_ACCESS "RW"
// =============================================================================
// Register : PWM_CH2_DIV
// Description : INT and FRAC form a fixed-point fractional number.
// Counting rate is system clock frequency divided by this number.
// Fractional division uses simple 1st-order sigma-delta.
-#define PWM_CH2_DIV_OFFSET _U(0x0000002c)
-#define PWM_CH2_DIV_BITS _U(0x00000fff)
-#define PWM_CH2_DIV_RESET _U(0x00000010)
+#define PWM_CH2_DIV_OFFSET _u(0x0000002c)
+#define PWM_CH2_DIV_BITS _u(0x00000fff)
+#define PWM_CH2_DIV_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : PWM_CH2_DIV_INT
// Description : None
-#define PWM_CH2_DIV_INT_RESET _U(0x01)
-#define PWM_CH2_DIV_INT_BITS _U(0x00000ff0)
-#define PWM_CH2_DIV_INT_MSB _U(11)
-#define PWM_CH2_DIV_INT_LSB _U(4)
+#define PWM_CH2_DIV_INT_RESET _u(0x01)
+#define PWM_CH2_DIV_INT_BITS _u(0x00000ff0)
+#define PWM_CH2_DIV_INT_MSB _u(11)
+#define PWM_CH2_DIV_INT_LSB _u(4)
#define PWM_CH2_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH2_DIV_FRAC
// Description : None
-#define PWM_CH2_DIV_FRAC_RESET _U(0x0)
-#define PWM_CH2_DIV_FRAC_BITS _U(0x0000000f)
-#define PWM_CH2_DIV_FRAC_MSB _U(3)
-#define PWM_CH2_DIV_FRAC_LSB _U(0)
+#define PWM_CH2_DIV_FRAC_RESET _u(0x0)
+#define PWM_CH2_DIV_FRAC_BITS _u(0x0000000f)
+#define PWM_CH2_DIV_FRAC_MSB _u(3)
+#define PWM_CH2_DIV_FRAC_LSB _u(0)
#define PWM_CH2_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : PWM_CH2_CTR
// Description : Direct access to the PWM counter
-#define PWM_CH2_CTR_OFFSET _U(0x00000030)
-#define PWM_CH2_CTR_BITS _U(0x0000ffff)
-#define PWM_CH2_CTR_RESET _U(0x00000000)
-#define PWM_CH2_CTR_MSB _U(15)
-#define PWM_CH2_CTR_LSB _U(0)
+#define PWM_CH2_CTR_OFFSET _u(0x00000030)
+#define PWM_CH2_CTR_BITS _u(0x0000ffff)
+#define PWM_CH2_CTR_RESET _u(0x00000000)
+#define PWM_CH2_CTR_MSB _u(15)
+#define PWM_CH2_CTR_LSB _u(0)
#define PWM_CH2_CTR_ACCESS "RW"
// =============================================================================
// Register : PWM_CH2_CC
// Description : Counter compare values
-#define PWM_CH2_CC_OFFSET _U(0x00000034)
-#define PWM_CH2_CC_BITS _U(0xffffffff)
-#define PWM_CH2_CC_RESET _U(0x00000000)
+#define PWM_CH2_CC_OFFSET _u(0x00000034)
+#define PWM_CH2_CC_BITS _u(0xffffffff)
+#define PWM_CH2_CC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH2_CC_B
// Description : None
-#define PWM_CH2_CC_B_RESET _U(0x0000)
-#define PWM_CH2_CC_B_BITS _U(0xffff0000)
-#define PWM_CH2_CC_B_MSB _U(31)
-#define PWM_CH2_CC_B_LSB _U(16)
+#define PWM_CH2_CC_B_RESET _u(0x0000)
+#define PWM_CH2_CC_B_BITS _u(0xffff0000)
+#define PWM_CH2_CC_B_MSB _u(31)
+#define PWM_CH2_CC_B_LSB _u(16)
#define PWM_CH2_CC_B_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH2_CC_A
// Description : None
-#define PWM_CH2_CC_A_RESET _U(0x0000)
-#define PWM_CH2_CC_A_BITS _U(0x0000ffff)
-#define PWM_CH2_CC_A_MSB _U(15)
-#define PWM_CH2_CC_A_LSB _U(0)
+#define PWM_CH2_CC_A_RESET _u(0x0000)
+#define PWM_CH2_CC_A_BITS _u(0x0000ffff)
+#define PWM_CH2_CC_A_MSB _u(15)
+#define PWM_CH2_CC_A_LSB _u(0)
#define PWM_CH2_CC_A_ACCESS "RW"
// =============================================================================
// Register : PWM_CH2_TOP
// Description : Counter wrap value
-#define PWM_CH2_TOP_OFFSET _U(0x00000038)
-#define PWM_CH2_TOP_BITS _U(0x0000ffff)
-#define PWM_CH2_TOP_RESET _U(0x0000ffff)
-#define PWM_CH2_TOP_MSB _U(15)
-#define PWM_CH2_TOP_LSB _U(0)
+#define PWM_CH2_TOP_OFFSET _u(0x00000038)
+#define PWM_CH2_TOP_BITS _u(0x0000ffff)
+#define PWM_CH2_TOP_RESET _u(0x0000ffff)
+#define PWM_CH2_TOP_MSB _u(15)
+#define PWM_CH2_TOP_LSB _u(0)
#define PWM_CH2_TOP_ACCESS "RW"
// =============================================================================
// Register : PWM_CH3_CSR
// Description : Control and status register
-#define PWM_CH3_CSR_OFFSET _U(0x0000003c)
-#define PWM_CH3_CSR_BITS _U(0x000000ff)
-#define PWM_CH3_CSR_RESET _U(0x00000000)
+#define PWM_CH3_CSR_OFFSET _u(0x0000003c)
+#define PWM_CH3_CSR_BITS _u(0x000000ff)
+#define PWM_CH3_CSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH3_CSR_PH_ADV
// Description : Advance the phase of the counter by 1 count, while it is
@@ -450,10 +450,10 @@
// Self-clearing. Write a 1, and poll until low. Counter must be
// running
// at less than full speed (div_int + div_frac / 16 > 1)
-#define PWM_CH3_CSR_PH_ADV_RESET _U(0x0)
-#define PWM_CH3_CSR_PH_ADV_BITS _U(0x00000080)
-#define PWM_CH3_CSR_PH_ADV_MSB _U(7)
-#define PWM_CH3_CSR_PH_ADV_LSB _U(7)
+#define PWM_CH3_CSR_PH_ADV_RESET _u(0x0)
+#define PWM_CH3_CSR_PH_ADV_BITS _u(0x00000080)
+#define PWM_CH3_CSR_PH_ADV_MSB _u(7)
+#define PWM_CH3_CSR_PH_ADV_LSB _u(7)
#define PWM_CH3_CSR_PH_ADV_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH3_CSR_PH_RET
@@ -461,10 +461,10 @@
// running.
// Self-clearing. Write a 1, and poll until low. Counter must be
// running.
-#define PWM_CH3_CSR_PH_RET_RESET _U(0x0)
-#define PWM_CH3_CSR_PH_RET_BITS _U(0x00000040)
-#define PWM_CH3_CSR_PH_RET_MSB _U(6)
-#define PWM_CH3_CSR_PH_RET_LSB _U(6)
+#define PWM_CH3_CSR_PH_RET_RESET _u(0x0)
+#define PWM_CH3_CSR_PH_RET_BITS _u(0x00000040)
+#define PWM_CH3_CSR_PH_RET_MSB _u(6)
+#define PWM_CH3_CSR_PH_RET_LSB _u(6)
#define PWM_CH3_CSR_PH_RET_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH3_CSR_DIVMODE
@@ -474,117 +474,117 @@
// 0x2 -> Counter advances with each rising edge of the PWM B pin.
// 0x3 -> Counter advances with each falling edge of the PWM B
// pin.
-#define PWM_CH3_CSR_DIVMODE_RESET _U(0x0)
-#define PWM_CH3_CSR_DIVMODE_BITS _U(0x00000030)
-#define PWM_CH3_CSR_DIVMODE_MSB _U(5)
-#define PWM_CH3_CSR_DIVMODE_LSB _U(4)
+#define PWM_CH3_CSR_DIVMODE_RESET _u(0x0)
+#define PWM_CH3_CSR_DIVMODE_BITS _u(0x00000030)
+#define PWM_CH3_CSR_DIVMODE_MSB _u(5)
+#define PWM_CH3_CSR_DIVMODE_LSB _u(4)
#define PWM_CH3_CSR_DIVMODE_ACCESS "RW"
-#define PWM_CH3_CSR_DIVMODE_VALUE_DIV _U(0x0)
-#define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL _U(0x1)
-#define PWM_CH3_CSR_DIVMODE_VALUE_RISE _U(0x2)
-#define PWM_CH3_CSR_DIVMODE_VALUE_FALL _U(0x3)
+#define PWM_CH3_CSR_DIVMODE_VALUE_DIV _u(0x0)
+#define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH3_CSR_DIVMODE_VALUE_RISE _u(0x2)
+#define PWM_CH3_CSR_DIVMODE_VALUE_FALL _u(0x3)
// -----------------------------------------------------------------------------
// Field : PWM_CH3_CSR_B_INV
// Description : Invert output B
-#define PWM_CH3_CSR_B_INV_RESET _U(0x0)
-#define PWM_CH3_CSR_B_INV_BITS _U(0x00000008)
-#define PWM_CH3_CSR_B_INV_MSB _U(3)
-#define PWM_CH3_CSR_B_INV_LSB _U(3)
+#define PWM_CH3_CSR_B_INV_RESET _u(0x0)
+#define PWM_CH3_CSR_B_INV_BITS _u(0x00000008)
+#define PWM_CH3_CSR_B_INV_MSB _u(3)
+#define PWM_CH3_CSR_B_INV_LSB _u(3)
#define PWM_CH3_CSR_B_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH3_CSR_A_INV
// Description : Invert output A
-#define PWM_CH3_CSR_A_INV_RESET _U(0x0)
-#define PWM_CH3_CSR_A_INV_BITS _U(0x00000004)
-#define PWM_CH3_CSR_A_INV_MSB _U(2)
-#define PWM_CH3_CSR_A_INV_LSB _U(2)
+#define PWM_CH3_CSR_A_INV_RESET _u(0x0)
+#define PWM_CH3_CSR_A_INV_BITS _u(0x00000004)
+#define PWM_CH3_CSR_A_INV_MSB _u(2)
+#define PWM_CH3_CSR_A_INV_LSB _u(2)
#define PWM_CH3_CSR_A_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH3_CSR_PH_CORRECT
// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
-#define PWM_CH3_CSR_PH_CORRECT_RESET _U(0x0)
-#define PWM_CH3_CSR_PH_CORRECT_BITS _U(0x00000002)
-#define PWM_CH3_CSR_PH_CORRECT_MSB _U(1)
-#define PWM_CH3_CSR_PH_CORRECT_LSB _U(1)
+#define PWM_CH3_CSR_PH_CORRECT_RESET _u(0x0)
+#define PWM_CH3_CSR_PH_CORRECT_BITS _u(0x00000002)
+#define PWM_CH3_CSR_PH_CORRECT_MSB _u(1)
+#define PWM_CH3_CSR_PH_CORRECT_LSB _u(1)
#define PWM_CH3_CSR_PH_CORRECT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH3_CSR_EN
// Description : Enable the PWM channel.
-#define PWM_CH3_CSR_EN_RESET _U(0x0)
-#define PWM_CH3_CSR_EN_BITS _U(0x00000001)
-#define PWM_CH3_CSR_EN_MSB _U(0)
-#define PWM_CH3_CSR_EN_LSB _U(0)
+#define PWM_CH3_CSR_EN_RESET _u(0x0)
+#define PWM_CH3_CSR_EN_BITS _u(0x00000001)
+#define PWM_CH3_CSR_EN_MSB _u(0)
+#define PWM_CH3_CSR_EN_LSB _u(0)
#define PWM_CH3_CSR_EN_ACCESS "RW"
// =============================================================================
// Register : PWM_CH3_DIV
// Description : INT and FRAC form a fixed-point fractional number.
// Counting rate is system clock frequency divided by this number.
// Fractional division uses simple 1st-order sigma-delta.
-#define PWM_CH3_DIV_OFFSET _U(0x00000040)
-#define PWM_CH3_DIV_BITS _U(0x00000fff)
-#define PWM_CH3_DIV_RESET _U(0x00000010)
+#define PWM_CH3_DIV_OFFSET _u(0x00000040)
+#define PWM_CH3_DIV_BITS _u(0x00000fff)
+#define PWM_CH3_DIV_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : PWM_CH3_DIV_INT
// Description : None
-#define PWM_CH3_DIV_INT_RESET _U(0x01)
-#define PWM_CH3_DIV_INT_BITS _U(0x00000ff0)
-#define PWM_CH3_DIV_INT_MSB _U(11)
-#define PWM_CH3_DIV_INT_LSB _U(4)
+#define PWM_CH3_DIV_INT_RESET _u(0x01)
+#define PWM_CH3_DIV_INT_BITS _u(0x00000ff0)
+#define PWM_CH3_DIV_INT_MSB _u(11)
+#define PWM_CH3_DIV_INT_LSB _u(4)
#define PWM_CH3_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH3_DIV_FRAC
// Description : None
-#define PWM_CH3_DIV_FRAC_RESET _U(0x0)
-#define PWM_CH3_DIV_FRAC_BITS _U(0x0000000f)
-#define PWM_CH3_DIV_FRAC_MSB _U(3)
-#define PWM_CH3_DIV_FRAC_LSB _U(0)
+#define PWM_CH3_DIV_FRAC_RESET _u(0x0)
+#define PWM_CH3_DIV_FRAC_BITS _u(0x0000000f)
+#define PWM_CH3_DIV_FRAC_MSB _u(3)
+#define PWM_CH3_DIV_FRAC_LSB _u(0)
#define PWM_CH3_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : PWM_CH3_CTR
// Description : Direct access to the PWM counter
-#define PWM_CH3_CTR_OFFSET _U(0x00000044)
-#define PWM_CH3_CTR_BITS _U(0x0000ffff)
-#define PWM_CH3_CTR_RESET _U(0x00000000)
-#define PWM_CH3_CTR_MSB _U(15)
-#define PWM_CH3_CTR_LSB _U(0)
+#define PWM_CH3_CTR_OFFSET _u(0x00000044)
+#define PWM_CH3_CTR_BITS _u(0x0000ffff)
+#define PWM_CH3_CTR_RESET _u(0x00000000)
+#define PWM_CH3_CTR_MSB _u(15)
+#define PWM_CH3_CTR_LSB _u(0)
#define PWM_CH3_CTR_ACCESS "RW"
// =============================================================================
// Register : PWM_CH3_CC
// Description : Counter compare values
-#define PWM_CH3_CC_OFFSET _U(0x00000048)
-#define PWM_CH3_CC_BITS _U(0xffffffff)
-#define PWM_CH3_CC_RESET _U(0x00000000)
+#define PWM_CH3_CC_OFFSET _u(0x00000048)
+#define PWM_CH3_CC_BITS _u(0xffffffff)
+#define PWM_CH3_CC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH3_CC_B
// Description : None
-#define PWM_CH3_CC_B_RESET _U(0x0000)
-#define PWM_CH3_CC_B_BITS _U(0xffff0000)
-#define PWM_CH3_CC_B_MSB _U(31)
-#define PWM_CH3_CC_B_LSB _U(16)
+#define PWM_CH3_CC_B_RESET _u(0x0000)
+#define PWM_CH3_CC_B_BITS _u(0xffff0000)
+#define PWM_CH3_CC_B_MSB _u(31)
+#define PWM_CH3_CC_B_LSB _u(16)
#define PWM_CH3_CC_B_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH3_CC_A
// Description : None
-#define PWM_CH3_CC_A_RESET _U(0x0000)
-#define PWM_CH3_CC_A_BITS _U(0x0000ffff)
-#define PWM_CH3_CC_A_MSB _U(15)
-#define PWM_CH3_CC_A_LSB _U(0)
+#define PWM_CH3_CC_A_RESET _u(0x0000)
+#define PWM_CH3_CC_A_BITS _u(0x0000ffff)
+#define PWM_CH3_CC_A_MSB _u(15)
+#define PWM_CH3_CC_A_LSB _u(0)
#define PWM_CH3_CC_A_ACCESS "RW"
// =============================================================================
// Register : PWM_CH3_TOP
// Description : Counter wrap value
-#define PWM_CH3_TOP_OFFSET _U(0x0000004c)
-#define PWM_CH3_TOP_BITS _U(0x0000ffff)
-#define PWM_CH3_TOP_RESET _U(0x0000ffff)
-#define PWM_CH3_TOP_MSB _U(15)
-#define PWM_CH3_TOP_LSB _U(0)
+#define PWM_CH3_TOP_OFFSET _u(0x0000004c)
+#define PWM_CH3_TOP_BITS _u(0x0000ffff)
+#define PWM_CH3_TOP_RESET _u(0x0000ffff)
+#define PWM_CH3_TOP_MSB _u(15)
+#define PWM_CH3_TOP_LSB _u(0)
#define PWM_CH3_TOP_ACCESS "RW"
// =============================================================================
// Register : PWM_CH4_CSR
// Description : Control and status register
-#define PWM_CH4_CSR_OFFSET _U(0x00000050)
-#define PWM_CH4_CSR_BITS _U(0x000000ff)
-#define PWM_CH4_CSR_RESET _U(0x00000000)
+#define PWM_CH4_CSR_OFFSET _u(0x00000050)
+#define PWM_CH4_CSR_BITS _u(0x000000ff)
+#define PWM_CH4_CSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH4_CSR_PH_ADV
// Description : Advance the phase of the counter by 1 count, while it is
@@ -592,10 +592,10 @@
// Self-clearing. Write a 1, and poll until low. Counter must be
// running
// at less than full speed (div_int + div_frac / 16 > 1)
-#define PWM_CH4_CSR_PH_ADV_RESET _U(0x0)
-#define PWM_CH4_CSR_PH_ADV_BITS _U(0x00000080)
-#define PWM_CH4_CSR_PH_ADV_MSB _U(7)
-#define PWM_CH4_CSR_PH_ADV_LSB _U(7)
+#define PWM_CH4_CSR_PH_ADV_RESET _u(0x0)
+#define PWM_CH4_CSR_PH_ADV_BITS _u(0x00000080)
+#define PWM_CH4_CSR_PH_ADV_MSB _u(7)
+#define PWM_CH4_CSR_PH_ADV_LSB _u(7)
#define PWM_CH4_CSR_PH_ADV_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH4_CSR_PH_RET
@@ -603,10 +603,10 @@
// running.
// Self-clearing. Write a 1, and poll until low. Counter must be
// running.
-#define PWM_CH4_CSR_PH_RET_RESET _U(0x0)
-#define PWM_CH4_CSR_PH_RET_BITS _U(0x00000040)
-#define PWM_CH4_CSR_PH_RET_MSB _U(6)
-#define PWM_CH4_CSR_PH_RET_LSB _U(6)
+#define PWM_CH4_CSR_PH_RET_RESET _u(0x0)
+#define PWM_CH4_CSR_PH_RET_BITS _u(0x00000040)
+#define PWM_CH4_CSR_PH_RET_MSB _u(6)
+#define PWM_CH4_CSR_PH_RET_LSB _u(6)
#define PWM_CH4_CSR_PH_RET_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH4_CSR_DIVMODE
@@ -616,117 +616,117 @@
// 0x2 -> Counter advances with each rising edge of the PWM B pin.
// 0x3 -> Counter advances with each falling edge of the PWM B
// pin.
-#define PWM_CH4_CSR_DIVMODE_RESET _U(0x0)
-#define PWM_CH4_CSR_DIVMODE_BITS _U(0x00000030)
-#define PWM_CH4_CSR_DIVMODE_MSB _U(5)
-#define PWM_CH4_CSR_DIVMODE_LSB _U(4)
+#define PWM_CH4_CSR_DIVMODE_RESET _u(0x0)
+#define PWM_CH4_CSR_DIVMODE_BITS _u(0x00000030)
+#define PWM_CH4_CSR_DIVMODE_MSB _u(5)
+#define PWM_CH4_CSR_DIVMODE_LSB _u(4)
#define PWM_CH4_CSR_DIVMODE_ACCESS "RW"
-#define PWM_CH4_CSR_DIVMODE_VALUE_DIV _U(0x0)
-#define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL _U(0x1)
-#define PWM_CH4_CSR_DIVMODE_VALUE_RISE _U(0x2)
-#define PWM_CH4_CSR_DIVMODE_VALUE_FALL _U(0x3)
+#define PWM_CH4_CSR_DIVMODE_VALUE_DIV _u(0x0)
+#define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH4_CSR_DIVMODE_VALUE_RISE _u(0x2)
+#define PWM_CH4_CSR_DIVMODE_VALUE_FALL _u(0x3)
// -----------------------------------------------------------------------------
// Field : PWM_CH4_CSR_B_INV
// Description : Invert output B
-#define PWM_CH4_CSR_B_INV_RESET _U(0x0)
-#define PWM_CH4_CSR_B_INV_BITS _U(0x00000008)
-#define PWM_CH4_CSR_B_INV_MSB _U(3)
-#define PWM_CH4_CSR_B_INV_LSB _U(3)
+#define PWM_CH4_CSR_B_INV_RESET _u(0x0)
+#define PWM_CH4_CSR_B_INV_BITS _u(0x00000008)
+#define PWM_CH4_CSR_B_INV_MSB _u(3)
+#define PWM_CH4_CSR_B_INV_LSB _u(3)
#define PWM_CH4_CSR_B_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH4_CSR_A_INV
// Description : Invert output A
-#define PWM_CH4_CSR_A_INV_RESET _U(0x0)
-#define PWM_CH4_CSR_A_INV_BITS _U(0x00000004)
-#define PWM_CH4_CSR_A_INV_MSB _U(2)
-#define PWM_CH4_CSR_A_INV_LSB _U(2)
+#define PWM_CH4_CSR_A_INV_RESET _u(0x0)
+#define PWM_CH4_CSR_A_INV_BITS _u(0x00000004)
+#define PWM_CH4_CSR_A_INV_MSB _u(2)
+#define PWM_CH4_CSR_A_INV_LSB _u(2)
#define PWM_CH4_CSR_A_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH4_CSR_PH_CORRECT
// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
-#define PWM_CH4_CSR_PH_CORRECT_RESET _U(0x0)
-#define PWM_CH4_CSR_PH_CORRECT_BITS _U(0x00000002)
-#define PWM_CH4_CSR_PH_CORRECT_MSB _U(1)
-#define PWM_CH4_CSR_PH_CORRECT_LSB _U(1)
+#define PWM_CH4_CSR_PH_CORRECT_RESET _u(0x0)
+#define PWM_CH4_CSR_PH_CORRECT_BITS _u(0x00000002)
+#define PWM_CH4_CSR_PH_CORRECT_MSB _u(1)
+#define PWM_CH4_CSR_PH_CORRECT_LSB _u(1)
#define PWM_CH4_CSR_PH_CORRECT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH4_CSR_EN
// Description : Enable the PWM channel.
-#define PWM_CH4_CSR_EN_RESET _U(0x0)
-#define PWM_CH4_CSR_EN_BITS _U(0x00000001)
-#define PWM_CH4_CSR_EN_MSB _U(0)
-#define PWM_CH4_CSR_EN_LSB _U(0)
+#define PWM_CH4_CSR_EN_RESET _u(0x0)
+#define PWM_CH4_CSR_EN_BITS _u(0x00000001)
+#define PWM_CH4_CSR_EN_MSB _u(0)
+#define PWM_CH4_CSR_EN_LSB _u(0)
#define PWM_CH4_CSR_EN_ACCESS "RW"
// =============================================================================
// Register : PWM_CH4_DIV
// Description : INT and FRAC form a fixed-point fractional number.
// Counting rate is system clock frequency divided by this number.
// Fractional division uses simple 1st-order sigma-delta.
-#define PWM_CH4_DIV_OFFSET _U(0x00000054)
-#define PWM_CH4_DIV_BITS _U(0x00000fff)
-#define PWM_CH4_DIV_RESET _U(0x00000010)
+#define PWM_CH4_DIV_OFFSET _u(0x00000054)
+#define PWM_CH4_DIV_BITS _u(0x00000fff)
+#define PWM_CH4_DIV_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : PWM_CH4_DIV_INT
// Description : None
-#define PWM_CH4_DIV_INT_RESET _U(0x01)
-#define PWM_CH4_DIV_INT_BITS _U(0x00000ff0)
-#define PWM_CH4_DIV_INT_MSB _U(11)
-#define PWM_CH4_DIV_INT_LSB _U(4)
+#define PWM_CH4_DIV_INT_RESET _u(0x01)
+#define PWM_CH4_DIV_INT_BITS _u(0x00000ff0)
+#define PWM_CH4_DIV_INT_MSB _u(11)
+#define PWM_CH4_DIV_INT_LSB _u(4)
#define PWM_CH4_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH4_DIV_FRAC
// Description : None
-#define PWM_CH4_DIV_FRAC_RESET _U(0x0)
-#define PWM_CH4_DIV_FRAC_BITS _U(0x0000000f)
-#define PWM_CH4_DIV_FRAC_MSB _U(3)
-#define PWM_CH4_DIV_FRAC_LSB _U(0)
+#define PWM_CH4_DIV_FRAC_RESET _u(0x0)
+#define PWM_CH4_DIV_FRAC_BITS _u(0x0000000f)
+#define PWM_CH4_DIV_FRAC_MSB _u(3)
+#define PWM_CH4_DIV_FRAC_LSB _u(0)
#define PWM_CH4_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : PWM_CH4_CTR
// Description : Direct access to the PWM counter
-#define PWM_CH4_CTR_OFFSET _U(0x00000058)
-#define PWM_CH4_CTR_BITS _U(0x0000ffff)
-#define PWM_CH4_CTR_RESET _U(0x00000000)
-#define PWM_CH4_CTR_MSB _U(15)
-#define PWM_CH4_CTR_LSB _U(0)
+#define PWM_CH4_CTR_OFFSET _u(0x00000058)
+#define PWM_CH4_CTR_BITS _u(0x0000ffff)
+#define PWM_CH4_CTR_RESET _u(0x00000000)
+#define PWM_CH4_CTR_MSB _u(15)
+#define PWM_CH4_CTR_LSB _u(0)
#define PWM_CH4_CTR_ACCESS "RW"
// =============================================================================
// Register : PWM_CH4_CC
// Description : Counter compare values
-#define PWM_CH4_CC_OFFSET _U(0x0000005c)
-#define PWM_CH4_CC_BITS _U(0xffffffff)
-#define PWM_CH4_CC_RESET _U(0x00000000)
+#define PWM_CH4_CC_OFFSET _u(0x0000005c)
+#define PWM_CH4_CC_BITS _u(0xffffffff)
+#define PWM_CH4_CC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH4_CC_B
// Description : None
-#define PWM_CH4_CC_B_RESET _U(0x0000)
-#define PWM_CH4_CC_B_BITS _U(0xffff0000)
-#define PWM_CH4_CC_B_MSB _U(31)
-#define PWM_CH4_CC_B_LSB _U(16)
+#define PWM_CH4_CC_B_RESET _u(0x0000)
+#define PWM_CH4_CC_B_BITS _u(0xffff0000)
+#define PWM_CH4_CC_B_MSB _u(31)
+#define PWM_CH4_CC_B_LSB _u(16)
#define PWM_CH4_CC_B_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH4_CC_A
// Description : None
-#define PWM_CH4_CC_A_RESET _U(0x0000)
-#define PWM_CH4_CC_A_BITS _U(0x0000ffff)
-#define PWM_CH4_CC_A_MSB _U(15)
-#define PWM_CH4_CC_A_LSB _U(0)
+#define PWM_CH4_CC_A_RESET _u(0x0000)
+#define PWM_CH4_CC_A_BITS _u(0x0000ffff)
+#define PWM_CH4_CC_A_MSB _u(15)
+#define PWM_CH4_CC_A_LSB _u(0)
#define PWM_CH4_CC_A_ACCESS "RW"
// =============================================================================
// Register : PWM_CH4_TOP
// Description : Counter wrap value
-#define PWM_CH4_TOP_OFFSET _U(0x00000060)
-#define PWM_CH4_TOP_BITS _U(0x0000ffff)
-#define PWM_CH4_TOP_RESET _U(0x0000ffff)
-#define PWM_CH4_TOP_MSB _U(15)
-#define PWM_CH4_TOP_LSB _U(0)
+#define PWM_CH4_TOP_OFFSET _u(0x00000060)
+#define PWM_CH4_TOP_BITS _u(0x0000ffff)
+#define PWM_CH4_TOP_RESET _u(0x0000ffff)
+#define PWM_CH4_TOP_MSB _u(15)
+#define PWM_CH4_TOP_LSB _u(0)
#define PWM_CH4_TOP_ACCESS "RW"
// =============================================================================
// Register : PWM_CH5_CSR
// Description : Control and status register
-#define PWM_CH5_CSR_OFFSET _U(0x00000064)
-#define PWM_CH5_CSR_BITS _U(0x000000ff)
-#define PWM_CH5_CSR_RESET _U(0x00000000)
+#define PWM_CH5_CSR_OFFSET _u(0x00000064)
+#define PWM_CH5_CSR_BITS _u(0x000000ff)
+#define PWM_CH5_CSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH5_CSR_PH_ADV
// Description : Advance the phase of the counter by 1 count, while it is
@@ -734,10 +734,10 @@
// Self-clearing. Write a 1, and poll until low. Counter must be
// running
// at less than full speed (div_int + div_frac / 16 > 1)
-#define PWM_CH5_CSR_PH_ADV_RESET _U(0x0)
-#define PWM_CH5_CSR_PH_ADV_BITS _U(0x00000080)
-#define PWM_CH5_CSR_PH_ADV_MSB _U(7)
-#define PWM_CH5_CSR_PH_ADV_LSB _U(7)
+#define PWM_CH5_CSR_PH_ADV_RESET _u(0x0)
+#define PWM_CH5_CSR_PH_ADV_BITS _u(0x00000080)
+#define PWM_CH5_CSR_PH_ADV_MSB _u(7)
+#define PWM_CH5_CSR_PH_ADV_LSB _u(7)
#define PWM_CH5_CSR_PH_ADV_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH5_CSR_PH_RET
@@ -745,10 +745,10 @@
// running.
// Self-clearing. Write a 1, and poll until low. Counter must be
// running.
-#define PWM_CH5_CSR_PH_RET_RESET _U(0x0)
-#define PWM_CH5_CSR_PH_RET_BITS _U(0x00000040)
-#define PWM_CH5_CSR_PH_RET_MSB _U(6)
-#define PWM_CH5_CSR_PH_RET_LSB _U(6)
+#define PWM_CH5_CSR_PH_RET_RESET _u(0x0)
+#define PWM_CH5_CSR_PH_RET_BITS _u(0x00000040)
+#define PWM_CH5_CSR_PH_RET_MSB _u(6)
+#define PWM_CH5_CSR_PH_RET_LSB _u(6)
#define PWM_CH5_CSR_PH_RET_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH5_CSR_DIVMODE
@@ -758,117 +758,117 @@
// 0x2 -> Counter advances with each rising edge of the PWM B pin.
// 0x3 -> Counter advances with each falling edge of the PWM B
// pin.
-#define PWM_CH5_CSR_DIVMODE_RESET _U(0x0)
-#define PWM_CH5_CSR_DIVMODE_BITS _U(0x00000030)
-#define PWM_CH5_CSR_DIVMODE_MSB _U(5)
-#define PWM_CH5_CSR_DIVMODE_LSB _U(4)
+#define PWM_CH5_CSR_DIVMODE_RESET _u(0x0)
+#define PWM_CH5_CSR_DIVMODE_BITS _u(0x00000030)
+#define PWM_CH5_CSR_DIVMODE_MSB _u(5)
+#define PWM_CH5_CSR_DIVMODE_LSB _u(4)
#define PWM_CH5_CSR_DIVMODE_ACCESS "RW"
-#define PWM_CH5_CSR_DIVMODE_VALUE_DIV _U(0x0)
-#define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL _U(0x1)
-#define PWM_CH5_CSR_DIVMODE_VALUE_RISE _U(0x2)
-#define PWM_CH5_CSR_DIVMODE_VALUE_FALL _U(0x3)
+#define PWM_CH5_CSR_DIVMODE_VALUE_DIV _u(0x0)
+#define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH5_CSR_DIVMODE_VALUE_RISE _u(0x2)
+#define PWM_CH5_CSR_DIVMODE_VALUE_FALL _u(0x3)
// -----------------------------------------------------------------------------
// Field : PWM_CH5_CSR_B_INV
// Description : Invert output B
-#define PWM_CH5_CSR_B_INV_RESET _U(0x0)
-#define PWM_CH5_CSR_B_INV_BITS _U(0x00000008)
-#define PWM_CH5_CSR_B_INV_MSB _U(3)
-#define PWM_CH5_CSR_B_INV_LSB _U(3)
+#define PWM_CH5_CSR_B_INV_RESET _u(0x0)
+#define PWM_CH5_CSR_B_INV_BITS _u(0x00000008)
+#define PWM_CH5_CSR_B_INV_MSB _u(3)
+#define PWM_CH5_CSR_B_INV_LSB _u(3)
#define PWM_CH5_CSR_B_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH5_CSR_A_INV
// Description : Invert output A
-#define PWM_CH5_CSR_A_INV_RESET _U(0x0)
-#define PWM_CH5_CSR_A_INV_BITS _U(0x00000004)
-#define PWM_CH5_CSR_A_INV_MSB _U(2)
-#define PWM_CH5_CSR_A_INV_LSB _U(2)
+#define PWM_CH5_CSR_A_INV_RESET _u(0x0)
+#define PWM_CH5_CSR_A_INV_BITS _u(0x00000004)
+#define PWM_CH5_CSR_A_INV_MSB _u(2)
+#define PWM_CH5_CSR_A_INV_LSB _u(2)
#define PWM_CH5_CSR_A_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH5_CSR_PH_CORRECT
// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
-#define PWM_CH5_CSR_PH_CORRECT_RESET _U(0x0)
-#define PWM_CH5_CSR_PH_CORRECT_BITS _U(0x00000002)
-#define PWM_CH5_CSR_PH_CORRECT_MSB _U(1)
-#define PWM_CH5_CSR_PH_CORRECT_LSB _U(1)
+#define PWM_CH5_CSR_PH_CORRECT_RESET _u(0x0)
+#define PWM_CH5_CSR_PH_CORRECT_BITS _u(0x00000002)
+#define PWM_CH5_CSR_PH_CORRECT_MSB _u(1)
+#define PWM_CH5_CSR_PH_CORRECT_LSB _u(1)
#define PWM_CH5_CSR_PH_CORRECT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH5_CSR_EN
// Description : Enable the PWM channel.
-#define PWM_CH5_CSR_EN_RESET _U(0x0)
-#define PWM_CH5_CSR_EN_BITS _U(0x00000001)
-#define PWM_CH5_CSR_EN_MSB _U(0)
-#define PWM_CH5_CSR_EN_LSB _U(0)
+#define PWM_CH5_CSR_EN_RESET _u(0x0)
+#define PWM_CH5_CSR_EN_BITS _u(0x00000001)
+#define PWM_CH5_CSR_EN_MSB _u(0)
+#define PWM_CH5_CSR_EN_LSB _u(0)
#define PWM_CH5_CSR_EN_ACCESS "RW"
// =============================================================================
// Register : PWM_CH5_DIV
// Description : INT and FRAC form a fixed-point fractional number.
// Counting rate is system clock frequency divided by this number.
// Fractional division uses simple 1st-order sigma-delta.
-#define PWM_CH5_DIV_OFFSET _U(0x00000068)
-#define PWM_CH5_DIV_BITS _U(0x00000fff)
-#define PWM_CH5_DIV_RESET _U(0x00000010)
+#define PWM_CH5_DIV_OFFSET _u(0x00000068)
+#define PWM_CH5_DIV_BITS _u(0x00000fff)
+#define PWM_CH5_DIV_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : PWM_CH5_DIV_INT
// Description : None
-#define PWM_CH5_DIV_INT_RESET _U(0x01)
-#define PWM_CH5_DIV_INT_BITS _U(0x00000ff0)
-#define PWM_CH5_DIV_INT_MSB _U(11)
-#define PWM_CH5_DIV_INT_LSB _U(4)
+#define PWM_CH5_DIV_INT_RESET _u(0x01)
+#define PWM_CH5_DIV_INT_BITS _u(0x00000ff0)
+#define PWM_CH5_DIV_INT_MSB _u(11)
+#define PWM_CH5_DIV_INT_LSB _u(4)
#define PWM_CH5_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH5_DIV_FRAC
// Description : None
-#define PWM_CH5_DIV_FRAC_RESET _U(0x0)
-#define PWM_CH5_DIV_FRAC_BITS _U(0x0000000f)
-#define PWM_CH5_DIV_FRAC_MSB _U(3)
-#define PWM_CH5_DIV_FRAC_LSB _U(0)
+#define PWM_CH5_DIV_FRAC_RESET _u(0x0)
+#define PWM_CH5_DIV_FRAC_BITS _u(0x0000000f)
+#define PWM_CH5_DIV_FRAC_MSB _u(3)
+#define PWM_CH5_DIV_FRAC_LSB _u(0)
#define PWM_CH5_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : PWM_CH5_CTR
// Description : Direct access to the PWM counter
-#define PWM_CH5_CTR_OFFSET _U(0x0000006c)
-#define PWM_CH5_CTR_BITS _U(0x0000ffff)
-#define PWM_CH5_CTR_RESET _U(0x00000000)
-#define PWM_CH5_CTR_MSB _U(15)
-#define PWM_CH5_CTR_LSB _U(0)
+#define PWM_CH5_CTR_OFFSET _u(0x0000006c)
+#define PWM_CH5_CTR_BITS _u(0x0000ffff)
+#define PWM_CH5_CTR_RESET _u(0x00000000)
+#define PWM_CH5_CTR_MSB _u(15)
+#define PWM_CH5_CTR_LSB _u(0)
#define PWM_CH5_CTR_ACCESS "RW"
// =============================================================================
// Register : PWM_CH5_CC
// Description : Counter compare values
-#define PWM_CH5_CC_OFFSET _U(0x00000070)
-#define PWM_CH5_CC_BITS _U(0xffffffff)
-#define PWM_CH5_CC_RESET _U(0x00000000)
+#define PWM_CH5_CC_OFFSET _u(0x00000070)
+#define PWM_CH5_CC_BITS _u(0xffffffff)
+#define PWM_CH5_CC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH5_CC_B
// Description : None
-#define PWM_CH5_CC_B_RESET _U(0x0000)
-#define PWM_CH5_CC_B_BITS _U(0xffff0000)
-#define PWM_CH5_CC_B_MSB _U(31)
-#define PWM_CH5_CC_B_LSB _U(16)
+#define PWM_CH5_CC_B_RESET _u(0x0000)
+#define PWM_CH5_CC_B_BITS _u(0xffff0000)
+#define PWM_CH5_CC_B_MSB _u(31)
+#define PWM_CH5_CC_B_LSB _u(16)
#define PWM_CH5_CC_B_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH5_CC_A
// Description : None
-#define PWM_CH5_CC_A_RESET _U(0x0000)
-#define PWM_CH5_CC_A_BITS _U(0x0000ffff)
-#define PWM_CH5_CC_A_MSB _U(15)
-#define PWM_CH5_CC_A_LSB _U(0)
+#define PWM_CH5_CC_A_RESET _u(0x0000)
+#define PWM_CH5_CC_A_BITS _u(0x0000ffff)
+#define PWM_CH5_CC_A_MSB _u(15)
+#define PWM_CH5_CC_A_LSB _u(0)
#define PWM_CH5_CC_A_ACCESS "RW"
// =============================================================================
// Register : PWM_CH5_TOP
// Description : Counter wrap value
-#define PWM_CH5_TOP_OFFSET _U(0x00000074)
-#define PWM_CH5_TOP_BITS _U(0x0000ffff)
-#define PWM_CH5_TOP_RESET _U(0x0000ffff)
-#define PWM_CH5_TOP_MSB _U(15)
-#define PWM_CH5_TOP_LSB _U(0)
+#define PWM_CH5_TOP_OFFSET _u(0x00000074)
+#define PWM_CH5_TOP_BITS _u(0x0000ffff)
+#define PWM_CH5_TOP_RESET _u(0x0000ffff)
+#define PWM_CH5_TOP_MSB _u(15)
+#define PWM_CH5_TOP_LSB _u(0)
#define PWM_CH5_TOP_ACCESS "RW"
// =============================================================================
// Register : PWM_CH6_CSR
// Description : Control and status register
-#define PWM_CH6_CSR_OFFSET _U(0x00000078)
-#define PWM_CH6_CSR_BITS _U(0x000000ff)
-#define PWM_CH6_CSR_RESET _U(0x00000000)
+#define PWM_CH6_CSR_OFFSET _u(0x00000078)
+#define PWM_CH6_CSR_BITS _u(0x000000ff)
+#define PWM_CH6_CSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH6_CSR_PH_ADV
// Description : Advance the phase of the counter by 1 count, while it is
@@ -876,10 +876,10 @@
// Self-clearing. Write a 1, and poll until low. Counter must be
// running
// at less than full speed (div_int + div_frac / 16 > 1)
-#define PWM_CH6_CSR_PH_ADV_RESET _U(0x0)
-#define PWM_CH6_CSR_PH_ADV_BITS _U(0x00000080)
-#define PWM_CH6_CSR_PH_ADV_MSB _U(7)
-#define PWM_CH6_CSR_PH_ADV_LSB _U(7)
+#define PWM_CH6_CSR_PH_ADV_RESET _u(0x0)
+#define PWM_CH6_CSR_PH_ADV_BITS _u(0x00000080)
+#define PWM_CH6_CSR_PH_ADV_MSB _u(7)
+#define PWM_CH6_CSR_PH_ADV_LSB _u(7)
#define PWM_CH6_CSR_PH_ADV_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH6_CSR_PH_RET
@@ -887,10 +887,10 @@
// running.
// Self-clearing. Write a 1, and poll until low. Counter must be
// running.
-#define PWM_CH6_CSR_PH_RET_RESET _U(0x0)
-#define PWM_CH6_CSR_PH_RET_BITS _U(0x00000040)
-#define PWM_CH6_CSR_PH_RET_MSB _U(6)
-#define PWM_CH6_CSR_PH_RET_LSB _U(6)
+#define PWM_CH6_CSR_PH_RET_RESET _u(0x0)
+#define PWM_CH6_CSR_PH_RET_BITS _u(0x00000040)
+#define PWM_CH6_CSR_PH_RET_MSB _u(6)
+#define PWM_CH6_CSR_PH_RET_LSB _u(6)
#define PWM_CH6_CSR_PH_RET_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH6_CSR_DIVMODE
@@ -900,117 +900,117 @@
// 0x2 -> Counter advances with each rising edge of the PWM B pin.
// 0x3 -> Counter advances with each falling edge of the PWM B
// pin.
-#define PWM_CH6_CSR_DIVMODE_RESET _U(0x0)
-#define PWM_CH6_CSR_DIVMODE_BITS _U(0x00000030)
-#define PWM_CH6_CSR_DIVMODE_MSB _U(5)
-#define PWM_CH6_CSR_DIVMODE_LSB _U(4)
+#define PWM_CH6_CSR_DIVMODE_RESET _u(0x0)
+#define PWM_CH6_CSR_DIVMODE_BITS _u(0x00000030)
+#define PWM_CH6_CSR_DIVMODE_MSB _u(5)
+#define PWM_CH6_CSR_DIVMODE_LSB _u(4)
#define PWM_CH6_CSR_DIVMODE_ACCESS "RW"
-#define PWM_CH6_CSR_DIVMODE_VALUE_DIV _U(0x0)
-#define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL _U(0x1)
-#define PWM_CH6_CSR_DIVMODE_VALUE_RISE _U(0x2)
-#define PWM_CH6_CSR_DIVMODE_VALUE_FALL _U(0x3)
+#define PWM_CH6_CSR_DIVMODE_VALUE_DIV _u(0x0)
+#define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH6_CSR_DIVMODE_VALUE_RISE _u(0x2)
+#define PWM_CH6_CSR_DIVMODE_VALUE_FALL _u(0x3)
// -----------------------------------------------------------------------------
// Field : PWM_CH6_CSR_B_INV
// Description : Invert output B
-#define PWM_CH6_CSR_B_INV_RESET _U(0x0)
-#define PWM_CH6_CSR_B_INV_BITS _U(0x00000008)
-#define PWM_CH6_CSR_B_INV_MSB _U(3)
-#define PWM_CH6_CSR_B_INV_LSB _U(3)
+#define PWM_CH6_CSR_B_INV_RESET _u(0x0)
+#define PWM_CH6_CSR_B_INV_BITS _u(0x00000008)
+#define PWM_CH6_CSR_B_INV_MSB _u(3)
+#define PWM_CH6_CSR_B_INV_LSB _u(3)
#define PWM_CH6_CSR_B_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH6_CSR_A_INV
// Description : Invert output A
-#define PWM_CH6_CSR_A_INV_RESET _U(0x0)
-#define PWM_CH6_CSR_A_INV_BITS _U(0x00000004)
-#define PWM_CH6_CSR_A_INV_MSB _U(2)
-#define PWM_CH6_CSR_A_INV_LSB _U(2)
+#define PWM_CH6_CSR_A_INV_RESET _u(0x0)
+#define PWM_CH6_CSR_A_INV_BITS _u(0x00000004)
+#define PWM_CH6_CSR_A_INV_MSB _u(2)
+#define PWM_CH6_CSR_A_INV_LSB _u(2)
#define PWM_CH6_CSR_A_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH6_CSR_PH_CORRECT
// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
-#define PWM_CH6_CSR_PH_CORRECT_RESET _U(0x0)
-#define PWM_CH6_CSR_PH_CORRECT_BITS _U(0x00000002)
-#define PWM_CH6_CSR_PH_CORRECT_MSB _U(1)
-#define PWM_CH6_CSR_PH_CORRECT_LSB _U(1)
+#define PWM_CH6_CSR_PH_CORRECT_RESET _u(0x0)
+#define PWM_CH6_CSR_PH_CORRECT_BITS _u(0x00000002)
+#define PWM_CH6_CSR_PH_CORRECT_MSB _u(1)
+#define PWM_CH6_CSR_PH_CORRECT_LSB _u(1)
#define PWM_CH6_CSR_PH_CORRECT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH6_CSR_EN
// Description : Enable the PWM channel.
-#define PWM_CH6_CSR_EN_RESET _U(0x0)
-#define PWM_CH6_CSR_EN_BITS _U(0x00000001)
-#define PWM_CH6_CSR_EN_MSB _U(0)
-#define PWM_CH6_CSR_EN_LSB _U(0)
+#define PWM_CH6_CSR_EN_RESET _u(0x0)
+#define PWM_CH6_CSR_EN_BITS _u(0x00000001)
+#define PWM_CH6_CSR_EN_MSB _u(0)
+#define PWM_CH6_CSR_EN_LSB _u(0)
#define PWM_CH6_CSR_EN_ACCESS "RW"
// =============================================================================
// Register : PWM_CH6_DIV
// Description : INT and FRAC form a fixed-point fractional number.
// Counting rate is system clock frequency divided by this number.
// Fractional division uses simple 1st-order sigma-delta.
-#define PWM_CH6_DIV_OFFSET _U(0x0000007c)
-#define PWM_CH6_DIV_BITS _U(0x00000fff)
-#define PWM_CH6_DIV_RESET _U(0x00000010)
+#define PWM_CH6_DIV_OFFSET _u(0x0000007c)
+#define PWM_CH6_DIV_BITS _u(0x00000fff)
+#define PWM_CH6_DIV_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : PWM_CH6_DIV_INT
// Description : None
-#define PWM_CH6_DIV_INT_RESET _U(0x01)
-#define PWM_CH6_DIV_INT_BITS _U(0x00000ff0)
-#define PWM_CH6_DIV_INT_MSB _U(11)
-#define PWM_CH6_DIV_INT_LSB _U(4)
+#define PWM_CH6_DIV_INT_RESET _u(0x01)
+#define PWM_CH6_DIV_INT_BITS _u(0x00000ff0)
+#define PWM_CH6_DIV_INT_MSB _u(11)
+#define PWM_CH6_DIV_INT_LSB _u(4)
#define PWM_CH6_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH6_DIV_FRAC
// Description : None
-#define PWM_CH6_DIV_FRAC_RESET _U(0x0)
-#define PWM_CH6_DIV_FRAC_BITS _U(0x0000000f)
-#define PWM_CH6_DIV_FRAC_MSB _U(3)
-#define PWM_CH6_DIV_FRAC_LSB _U(0)
+#define PWM_CH6_DIV_FRAC_RESET _u(0x0)
+#define PWM_CH6_DIV_FRAC_BITS _u(0x0000000f)
+#define PWM_CH6_DIV_FRAC_MSB _u(3)
+#define PWM_CH6_DIV_FRAC_LSB _u(0)
#define PWM_CH6_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : PWM_CH6_CTR
// Description : Direct access to the PWM counter
-#define PWM_CH6_CTR_OFFSET _U(0x00000080)
-#define PWM_CH6_CTR_BITS _U(0x0000ffff)
-#define PWM_CH6_CTR_RESET _U(0x00000000)
-#define PWM_CH6_CTR_MSB _U(15)
-#define PWM_CH6_CTR_LSB _U(0)
+#define PWM_CH6_CTR_OFFSET _u(0x00000080)
+#define PWM_CH6_CTR_BITS _u(0x0000ffff)
+#define PWM_CH6_CTR_RESET _u(0x00000000)
+#define PWM_CH6_CTR_MSB _u(15)
+#define PWM_CH6_CTR_LSB _u(0)
#define PWM_CH6_CTR_ACCESS "RW"
// =============================================================================
// Register : PWM_CH6_CC
// Description : Counter compare values
-#define PWM_CH6_CC_OFFSET _U(0x00000084)
-#define PWM_CH6_CC_BITS _U(0xffffffff)
-#define PWM_CH6_CC_RESET _U(0x00000000)
+#define PWM_CH6_CC_OFFSET _u(0x00000084)
+#define PWM_CH6_CC_BITS _u(0xffffffff)
+#define PWM_CH6_CC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH6_CC_B
// Description : None
-#define PWM_CH6_CC_B_RESET _U(0x0000)
-#define PWM_CH6_CC_B_BITS _U(0xffff0000)
-#define PWM_CH6_CC_B_MSB _U(31)
-#define PWM_CH6_CC_B_LSB _U(16)
+#define PWM_CH6_CC_B_RESET _u(0x0000)
+#define PWM_CH6_CC_B_BITS _u(0xffff0000)
+#define PWM_CH6_CC_B_MSB _u(31)
+#define PWM_CH6_CC_B_LSB _u(16)
#define PWM_CH6_CC_B_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH6_CC_A
// Description : None
-#define PWM_CH6_CC_A_RESET _U(0x0000)
-#define PWM_CH6_CC_A_BITS _U(0x0000ffff)
-#define PWM_CH6_CC_A_MSB _U(15)
-#define PWM_CH6_CC_A_LSB _U(0)
+#define PWM_CH6_CC_A_RESET _u(0x0000)
+#define PWM_CH6_CC_A_BITS _u(0x0000ffff)
+#define PWM_CH6_CC_A_MSB _u(15)
+#define PWM_CH6_CC_A_LSB _u(0)
#define PWM_CH6_CC_A_ACCESS "RW"
// =============================================================================
// Register : PWM_CH6_TOP
// Description : Counter wrap value
-#define PWM_CH6_TOP_OFFSET _U(0x00000088)
-#define PWM_CH6_TOP_BITS _U(0x0000ffff)
-#define PWM_CH6_TOP_RESET _U(0x0000ffff)
-#define PWM_CH6_TOP_MSB _U(15)
-#define PWM_CH6_TOP_LSB _U(0)
+#define PWM_CH6_TOP_OFFSET _u(0x00000088)
+#define PWM_CH6_TOP_BITS _u(0x0000ffff)
+#define PWM_CH6_TOP_RESET _u(0x0000ffff)
+#define PWM_CH6_TOP_MSB _u(15)
+#define PWM_CH6_TOP_LSB _u(0)
#define PWM_CH6_TOP_ACCESS "RW"
// =============================================================================
// Register : PWM_CH7_CSR
// Description : Control and status register
-#define PWM_CH7_CSR_OFFSET _U(0x0000008c)
-#define PWM_CH7_CSR_BITS _U(0x000000ff)
-#define PWM_CH7_CSR_RESET _U(0x00000000)
+#define PWM_CH7_CSR_OFFSET _u(0x0000008c)
+#define PWM_CH7_CSR_BITS _u(0x000000ff)
+#define PWM_CH7_CSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH7_CSR_PH_ADV
// Description : Advance the phase of the counter by 1 count, while it is
@@ -1018,10 +1018,10 @@
// Self-clearing. Write a 1, and poll until low. Counter must be
// running
// at less than full speed (div_int + div_frac / 16 > 1)
-#define PWM_CH7_CSR_PH_ADV_RESET _U(0x0)
-#define PWM_CH7_CSR_PH_ADV_BITS _U(0x00000080)
-#define PWM_CH7_CSR_PH_ADV_MSB _U(7)
-#define PWM_CH7_CSR_PH_ADV_LSB _U(7)
+#define PWM_CH7_CSR_PH_ADV_RESET _u(0x0)
+#define PWM_CH7_CSR_PH_ADV_BITS _u(0x00000080)
+#define PWM_CH7_CSR_PH_ADV_MSB _u(7)
+#define PWM_CH7_CSR_PH_ADV_LSB _u(7)
#define PWM_CH7_CSR_PH_ADV_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH7_CSR_PH_RET
@@ -1029,10 +1029,10 @@
// running.
// Self-clearing. Write a 1, and poll until low. Counter must be
// running.
-#define PWM_CH7_CSR_PH_RET_RESET _U(0x0)
-#define PWM_CH7_CSR_PH_RET_BITS _U(0x00000040)
-#define PWM_CH7_CSR_PH_RET_MSB _U(6)
-#define PWM_CH7_CSR_PH_RET_LSB _U(6)
+#define PWM_CH7_CSR_PH_RET_RESET _u(0x0)
+#define PWM_CH7_CSR_PH_RET_BITS _u(0x00000040)
+#define PWM_CH7_CSR_PH_RET_MSB _u(6)
+#define PWM_CH7_CSR_PH_RET_LSB _u(6)
#define PWM_CH7_CSR_PH_RET_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH7_CSR_DIVMODE
@@ -1042,110 +1042,110 @@
// 0x2 -> Counter advances with each rising edge of the PWM B pin.
// 0x3 -> Counter advances with each falling edge of the PWM B
// pin.
-#define PWM_CH7_CSR_DIVMODE_RESET _U(0x0)
-#define PWM_CH7_CSR_DIVMODE_BITS _U(0x00000030)
-#define PWM_CH7_CSR_DIVMODE_MSB _U(5)
-#define PWM_CH7_CSR_DIVMODE_LSB _U(4)
+#define PWM_CH7_CSR_DIVMODE_RESET _u(0x0)
+#define PWM_CH7_CSR_DIVMODE_BITS _u(0x00000030)
+#define PWM_CH7_CSR_DIVMODE_MSB _u(5)
+#define PWM_CH7_CSR_DIVMODE_LSB _u(4)
#define PWM_CH7_CSR_DIVMODE_ACCESS "RW"
-#define PWM_CH7_CSR_DIVMODE_VALUE_DIV _U(0x0)
-#define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL _U(0x1)
-#define PWM_CH7_CSR_DIVMODE_VALUE_RISE _U(0x2)
-#define PWM_CH7_CSR_DIVMODE_VALUE_FALL _U(0x3)
+#define PWM_CH7_CSR_DIVMODE_VALUE_DIV _u(0x0)
+#define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH7_CSR_DIVMODE_VALUE_RISE _u(0x2)
+#define PWM_CH7_CSR_DIVMODE_VALUE_FALL _u(0x3)
// -----------------------------------------------------------------------------
// Field : PWM_CH7_CSR_B_INV
// Description : Invert output B
-#define PWM_CH7_CSR_B_INV_RESET _U(0x0)
-#define PWM_CH7_CSR_B_INV_BITS _U(0x00000008)
-#define PWM_CH7_CSR_B_INV_MSB _U(3)
-#define PWM_CH7_CSR_B_INV_LSB _U(3)
+#define PWM_CH7_CSR_B_INV_RESET _u(0x0)
+#define PWM_CH7_CSR_B_INV_BITS _u(0x00000008)
+#define PWM_CH7_CSR_B_INV_MSB _u(3)
+#define PWM_CH7_CSR_B_INV_LSB _u(3)
#define PWM_CH7_CSR_B_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH7_CSR_A_INV
// Description : Invert output A
-#define PWM_CH7_CSR_A_INV_RESET _U(0x0)
-#define PWM_CH7_CSR_A_INV_BITS _U(0x00000004)
-#define PWM_CH7_CSR_A_INV_MSB _U(2)
-#define PWM_CH7_CSR_A_INV_LSB _U(2)
+#define PWM_CH7_CSR_A_INV_RESET _u(0x0)
+#define PWM_CH7_CSR_A_INV_BITS _u(0x00000004)
+#define PWM_CH7_CSR_A_INV_MSB _u(2)
+#define PWM_CH7_CSR_A_INV_LSB _u(2)
#define PWM_CH7_CSR_A_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH7_CSR_PH_CORRECT
// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
-#define PWM_CH7_CSR_PH_CORRECT_RESET _U(0x0)
-#define PWM_CH7_CSR_PH_CORRECT_BITS _U(0x00000002)
-#define PWM_CH7_CSR_PH_CORRECT_MSB _U(1)
-#define PWM_CH7_CSR_PH_CORRECT_LSB _U(1)
+#define PWM_CH7_CSR_PH_CORRECT_RESET _u(0x0)
+#define PWM_CH7_CSR_PH_CORRECT_BITS _u(0x00000002)
+#define PWM_CH7_CSR_PH_CORRECT_MSB _u(1)
+#define PWM_CH7_CSR_PH_CORRECT_LSB _u(1)
#define PWM_CH7_CSR_PH_CORRECT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH7_CSR_EN
// Description : Enable the PWM channel.
-#define PWM_CH7_CSR_EN_RESET _U(0x0)
-#define PWM_CH7_CSR_EN_BITS _U(0x00000001)
-#define PWM_CH7_CSR_EN_MSB _U(0)
-#define PWM_CH7_CSR_EN_LSB _U(0)
+#define PWM_CH7_CSR_EN_RESET _u(0x0)
+#define PWM_CH7_CSR_EN_BITS _u(0x00000001)
+#define PWM_CH7_CSR_EN_MSB _u(0)
+#define PWM_CH7_CSR_EN_LSB _u(0)
#define PWM_CH7_CSR_EN_ACCESS "RW"
// =============================================================================
// Register : PWM_CH7_DIV
// Description : INT and FRAC form a fixed-point fractional number.
// Counting rate is system clock frequency divided by this number.
// Fractional division uses simple 1st-order sigma-delta.
-#define PWM_CH7_DIV_OFFSET _U(0x00000090)
-#define PWM_CH7_DIV_BITS _U(0x00000fff)
-#define PWM_CH7_DIV_RESET _U(0x00000010)
+#define PWM_CH7_DIV_OFFSET _u(0x00000090)
+#define PWM_CH7_DIV_BITS _u(0x00000fff)
+#define PWM_CH7_DIV_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : PWM_CH7_DIV_INT
// Description : None
-#define PWM_CH7_DIV_INT_RESET _U(0x01)
-#define PWM_CH7_DIV_INT_BITS _U(0x00000ff0)
-#define PWM_CH7_DIV_INT_MSB _U(11)
-#define PWM_CH7_DIV_INT_LSB _U(4)
+#define PWM_CH7_DIV_INT_RESET _u(0x01)
+#define PWM_CH7_DIV_INT_BITS _u(0x00000ff0)
+#define PWM_CH7_DIV_INT_MSB _u(11)
+#define PWM_CH7_DIV_INT_LSB _u(4)
#define PWM_CH7_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH7_DIV_FRAC
// Description : None
-#define PWM_CH7_DIV_FRAC_RESET _U(0x0)
-#define PWM_CH7_DIV_FRAC_BITS _U(0x0000000f)
-#define PWM_CH7_DIV_FRAC_MSB _U(3)
-#define PWM_CH7_DIV_FRAC_LSB _U(0)
+#define PWM_CH7_DIV_FRAC_RESET _u(0x0)
+#define PWM_CH7_DIV_FRAC_BITS _u(0x0000000f)
+#define PWM_CH7_DIV_FRAC_MSB _u(3)
+#define PWM_CH7_DIV_FRAC_LSB _u(0)
#define PWM_CH7_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : PWM_CH7_CTR
// Description : Direct access to the PWM counter
-#define PWM_CH7_CTR_OFFSET _U(0x00000094)
-#define PWM_CH7_CTR_BITS _U(0x0000ffff)
-#define PWM_CH7_CTR_RESET _U(0x00000000)
-#define PWM_CH7_CTR_MSB _U(15)
-#define PWM_CH7_CTR_LSB _U(0)
+#define PWM_CH7_CTR_OFFSET _u(0x00000094)
+#define PWM_CH7_CTR_BITS _u(0x0000ffff)
+#define PWM_CH7_CTR_RESET _u(0x00000000)
+#define PWM_CH7_CTR_MSB _u(15)
+#define PWM_CH7_CTR_LSB _u(0)
#define PWM_CH7_CTR_ACCESS "RW"
// =============================================================================
// Register : PWM_CH7_CC
// Description : Counter compare values
-#define PWM_CH7_CC_OFFSET _U(0x00000098)
-#define PWM_CH7_CC_BITS _U(0xffffffff)
-#define PWM_CH7_CC_RESET _U(0x00000000)
+#define PWM_CH7_CC_OFFSET _u(0x00000098)
+#define PWM_CH7_CC_BITS _u(0xffffffff)
+#define PWM_CH7_CC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH7_CC_B
// Description : None
-#define PWM_CH7_CC_B_RESET _U(0x0000)
-#define PWM_CH7_CC_B_BITS _U(0xffff0000)
-#define PWM_CH7_CC_B_MSB _U(31)
-#define PWM_CH7_CC_B_LSB _U(16)
+#define PWM_CH7_CC_B_RESET _u(0x0000)
+#define PWM_CH7_CC_B_BITS _u(0xffff0000)
+#define PWM_CH7_CC_B_MSB _u(31)
+#define PWM_CH7_CC_B_LSB _u(16)
#define PWM_CH7_CC_B_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH7_CC_A
// Description : None
-#define PWM_CH7_CC_A_RESET _U(0x0000)
-#define PWM_CH7_CC_A_BITS _U(0x0000ffff)
-#define PWM_CH7_CC_A_MSB _U(15)
-#define PWM_CH7_CC_A_LSB _U(0)
+#define PWM_CH7_CC_A_RESET _u(0x0000)
+#define PWM_CH7_CC_A_BITS _u(0x0000ffff)
+#define PWM_CH7_CC_A_MSB _u(15)
+#define PWM_CH7_CC_A_LSB _u(0)
#define PWM_CH7_CC_A_ACCESS "RW"
// =============================================================================
// Register : PWM_CH7_TOP
// Description : Counter wrap value
-#define PWM_CH7_TOP_OFFSET _U(0x0000009c)
-#define PWM_CH7_TOP_BITS _U(0x0000ffff)
-#define PWM_CH7_TOP_RESET _U(0x0000ffff)
-#define PWM_CH7_TOP_MSB _U(15)
-#define PWM_CH7_TOP_LSB _U(0)
+#define PWM_CH7_TOP_OFFSET _u(0x0000009c)
+#define PWM_CH7_TOP_BITS _u(0x0000ffff)
+#define PWM_CH7_TOP_RESET _u(0x0000ffff)
+#define PWM_CH7_TOP_MSB _u(15)
+#define PWM_CH7_TOP_LSB _u(0)
#define PWM_CH7_TOP_ACCESS "RW"
// =============================================================================
// Register : PWM_EN
@@ -1154,352 +1154,352 @@
// or disabled simultaneously, so they can run in perfect sync.
// For each channel, there is only one physical EN register bit,
// which can be accessed through here or CHx_CSR.
-#define PWM_EN_OFFSET _U(0x000000a0)
-#define PWM_EN_BITS _U(0x000000ff)
-#define PWM_EN_RESET _U(0x00000000)
+#define PWM_EN_OFFSET _u(0x000000a0)
+#define PWM_EN_BITS _u(0x000000ff)
+#define PWM_EN_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_EN_CH7
// Description : None
-#define PWM_EN_CH7_RESET _U(0x0)
-#define PWM_EN_CH7_BITS _U(0x00000080)
-#define PWM_EN_CH7_MSB _U(7)
-#define PWM_EN_CH7_LSB _U(7)
+#define PWM_EN_CH7_RESET _u(0x0)
+#define PWM_EN_CH7_BITS _u(0x00000080)
+#define PWM_EN_CH7_MSB _u(7)
+#define PWM_EN_CH7_LSB _u(7)
#define PWM_EN_CH7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_EN_CH6
// Description : None
-#define PWM_EN_CH6_RESET _U(0x0)
-#define PWM_EN_CH6_BITS _U(0x00000040)
-#define PWM_EN_CH6_MSB _U(6)
-#define PWM_EN_CH6_LSB _U(6)
+#define PWM_EN_CH6_RESET _u(0x0)
+#define PWM_EN_CH6_BITS _u(0x00000040)
+#define PWM_EN_CH6_MSB _u(6)
+#define PWM_EN_CH6_LSB _u(6)
#define PWM_EN_CH6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_EN_CH5
// Description : None
-#define PWM_EN_CH5_RESET _U(0x0)
-#define PWM_EN_CH5_BITS _U(0x00000020)
-#define PWM_EN_CH5_MSB _U(5)
-#define PWM_EN_CH5_LSB _U(5)
+#define PWM_EN_CH5_RESET _u(0x0)
+#define PWM_EN_CH5_BITS _u(0x00000020)
+#define PWM_EN_CH5_MSB _u(5)
+#define PWM_EN_CH5_LSB _u(5)
#define PWM_EN_CH5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_EN_CH4
// Description : None
-#define PWM_EN_CH4_RESET _U(0x0)
-#define PWM_EN_CH4_BITS _U(0x00000010)
-#define PWM_EN_CH4_MSB _U(4)
-#define PWM_EN_CH4_LSB _U(4)
+#define PWM_EN_CH4_RESET _u(0x0)
+#define PWM_EN_CH4_BITS _u(0x00000010)
+#define PWM_EN_CH4_MSB _u(4)
+#define PWM_EN_CH4_LSB _u(4)
#define PWM_EN_CH4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_EN_CH3
// Description : None
-#define PWM_EN_CH3_RESET _U(0x0)
-#define PWM_EN_CH3_BITS _U(0x00000008)
-#define PWM_EN_CH3_MSB _U(3)
-#define PWM_EN_CH3_LSB _U(3)
+#define PWM_EN_CH3_RESET _u(0x0)
+#define PWM_EN_CH3_BITS _u(0x00000008)
+#define PWM_EN_CH3_MSB _u(3)
+#define PWM_EN_CH3_LSB _u(3)
#define PWM_EN_CH3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_EN_CH2
// Description : None
-#define PWM_EN_CH2_RESET _U(0x0)
-#define PWM_EN_CH2_BITS _U(0x00000004)
-#define PWM_EN_CH2_MSB _U(2)
-#define PWM_EN_CH2_LSB _U(2)
+#define PWM_EN_CH2_RESET _u(0x0)
+#define PWM_EN_CH2_BITS _u(0x00000004)
+#define PWM_EN_CH2_MSB _u(2)
+#define PWM_EN_CH2_LSB _u(2)
#define PWM_EN_CH2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_EN_CH1
// Description : None
-#define PWM_EN_CH1_RESET _U(0x0)
-#define PWM_EN_CH1_BITS _U(0x00000002)
-#define PWM_EN_CH1_MSB _U(1)
-#define PWM_EN_CH1_LSB _U(1)
+#define PWM_EN_CH1_RESET _u(0x0)
+#define PWM_EN_CH1_BITS _u(0x00000002)
+#define PWM_EN_CH1_MSB _u(1)
+#define PWM_EN_CH1_LSB _u(1)
#define PWM_EN_CH1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_EN_CH0
// Description : None
-#define PWM_EN_CH0_RESET _U(0x0)
-#define PWM_EN_CH0_BITS _U(0x00000001)
-#define PWM_EN_CH0_MSB _U(0)
-#define PWM_EN_CH0_LSB _U(0)
+#define PWM_EN_CH0_RESET _u(0x0)
+#define PWM_EN_CH0_BITS _u(0x00000001)
+#define PWM_EN_CH0_MSB _u(0)
+#define PWM_EN_CH0_LSB _u(0)
#define PWM_EN_CH0_ACCESS "RW"
// =============================================================================
// Register : PWM_INTR
// Description : Raw Interrupts
-#define PWM_INTR_OFFSET _U(0x000000a4)
-#define PWM_INTR_BITS _U(0x000000ff)
-#define PWM_INTR_RESET _U(0x00000000)
+#define PWM_INTR_OFFSET _u(0x000000a4)
+#define PWM_INTR_BITS _u(0x000000ff)
+#define PWM_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_INTR_CH7
// Description : None
-#define PWM_INTR_CH7_RESET _U(0x0)
-#define PWM_INTR_CH7_BITS _U(0x00000080)
-#define PWM_INTR_CH7_MSB _U(7)
-#define PWM_INTR_CH7_LSB _U(7)
+#define PWM_INTR_CH7_RESET _u(0x0)
+#define PWM_INTR_CH7_BITS _u(0x00000080)
+#define PWM_INTR_CH7_MSB _u(7)
+#define PWM_INTR_CH7_LSB _u(7)
#define PWM_INTR_CH7_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PWM_INTR_CH6
// Description : None
-#define PWM_INTR_CH6_RESET _U(0x0)
-#define PWM_INTR_CH6_BITS _U(0x00000040)
-#define PWM_INTR_CH6_MSB _U(6)
-#define PWM_INTR_CH6_LSB _U(6)
+#define PWM_INTR_CH6_RESET _u(0x0)
+#define PWM_INTR_CH6_BITS _u(0x00000040)
+#define PWM_INTR_CH6_MSB _u(6)
+#define PWM_INTR_CH6_LSB _u(6)
#define PWM_INTR_CH6_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PWM_INTR_CH5
// Description : None
-#define PWM_INTR_CH5_RESET _U(0x0)
-#define PWM_INTR_CH5_BITS _U(0x00000020)
-#define PWM_INTR_CH5_MSB _U(5)
-#define PWM_INTR_CH5_LSB _U(5)
+#define PWM_INTR_CH5_RESET _u(0x0)
+#define PWM_INTR_CH5_BITS _u(0x00000020)
+#define PWM_INTR_CH5_MSB _u(5)
+#define PWM_INTR_CH5_LSB _u(5)
#define PWM_INTR_CH5_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PWM_INTR_CH4
// Description : None
-#define PWM_INTR_CH4_RESET _U(0x0)
-#define PWM_INTR_CH4_BITS _U(0x00000010)
-#define PWM_INTR_CH4_MSB _U(4)
-#define PWM_INTR_CH4_LSB _U(4)
+#define PWM_INTR_CH4_RESET _u(0x0)
+#define PWM_INTR_CH4_BITS _u(0x00000010)
+#define PWM_INTR_CH4_MSB _u(4)
+#define PWM_INTR_CH4_LSB _u(4)
#define PWM_INTR_CH4_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PWM_INTR_CH3
// Description : None
-#define PWM_INTR_CH3_RESET _U(0x0)
-#define PWM_INTR_CH3_BITS _U(0x00000008)
-#define PWM_INTR_CH3_MSB _U(3)
-#define PWM_INTR_CH3_LSB _U(3)
+#define PWM_INTR_CH3_RESET _u(0x0)
+#define PWM_INTR_CH3_BITS _u(0x00000008)
+#define PWM_INTR_CH3_MSB _u(3)
+#define PWM_INTR_CH3_LSB _u(3)
#define PWM_INTR_CH3_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PWM_INTR_CH2
// Description : None
-#define PWM_INTR_CH2_RESET _U(0x0)
-#define PWM_INTR_CH2_BITS _U(0x00000004)
-#define PWM_INTR_CH2_MSB _U(2)
-#define PWM_INTR_CH2_LSB _U(2)
+#define PWM_INTR_CH2_RESET _u(0x0)
+#define PWM_INTR_CH2_BITS _u(0x00000004)
+#define PWM_INTR_CH2_MSB _u(2)
+#define PWM_INTR_CH2_LSB _u(2)
#define PWM_INTR_CH2_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PWM_INTR_CH1
// Description : None
-#define PWM_INTR_CH1_RESET _U(0x0)
-#define PWM_INTR_CH1_BITS _U(0x00000002)
-#define PWM_INTR_CH1_MSB _U(1)
-#define PWM_INTR_CH1_LSB _U(1)
+#define PWM_INTR_CH1_RESET _u(0x0)
+#define PWM_INTR_CH1_BITS _u(0x00000002)
+#define PWM_INTR_CH1_MSB _u(1)
+#define PWM_INTR_CH1_LSB _u(1)
#define PWM_INTR_CH1_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PWM_INTR_CH0
// Description : None
-#define PWM_INTR_CH0_RESET _U(0x0)
-#define PWM_INTR_CH0_BITS _U(0x00000001)
-#define PWM_INTR_CH0_MSB _U(0)
-#define PWM_INTR_CH0_LSB _U(0)
+#define PWM_INTR_CH0_RESET _u(0x0)
+#define PWM_INTR_CH0_BITS _u(0x00000001)
+#define PWM_INTR_CH0_MSB _u(0)
+#define PWM_INTR_CH0_LSB _u(0)
#define PWM_INTR_CH0_ACCESS "WC"
// =============================================================================
// Register : PWM_INTE
// Description : Interrupt Enable
-#define PWM_INTE_OFFSET _U(0x000000a8)
-#define PWM_INTE_BITS _U(0x000000ff)
-#define PWM_INTE_RESET _U(0x00000000)
+#define PWM_INTE_OFFSET _u(0x000000a8)
+#define PWM_INTE_BITS _u(0x000000ff)
+#define PWM_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_INTE_CH7
// Description : None
-#define PWM_INTE_CH7_RESET _U(0x0)
-#define PWM_INTE_CH7_BITS _U(0x00000080)
-#define PWM_INTE_CH7_MSB _U(7)
-#define PWM_INTE_CH7_LSB _U(7)
+#define PWM_INTE_CH7_RESET _u(0x0)
+#define PWM_INTE_CH7_BITS _u(0x00000080)
+#define PWM_INTE_CH7_MSB _u(7)
+#define PWM_INTE_CH7_LSB _u(7)
#define PWM_INTE_CH7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTE_CH6
// Description : None
-#define PWM_INTE_CH6_RESET _U(0x0)
-#define PWM_INTE_CH6_BITS _U(0x00000040)
-#define PWM_INTE_CH6_MSB _U(6)
-#define PWM_INTE_CH6_LSB _U(6)
+#define PWM_INTE_CH6_RESET _u(0x0)
+#define PWM_INTE_CH6_BITS _u(0x00000040)
+#define PWM_INTE_CH6_MSB _u(6)
+#define PWM_INTE_CH6_LSB _u(6)
#define PWM_INTE_CH6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTE_CH5
// Description : None
-#define PWM_INTE_CH5_RESET _U(0x0)
-#define PWM_INTE_CH5_BITS _U(0x00000020)
-#define PWM_INTE_CH5_MSB _U(5)
-#define PWM_INTE_CH5_LSB _U(5)
+#define PWM_INTE_CH5_RESET _u(0x0)
+#define PWM_INTE_CH5_BITS _u(0x00000020)
+#define PWM_INTE_CH5_MSB _u(5)
+#define PWM_INTE_CH5_LSB _u(5)
#define PWM_INTE_CH5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTE_CH4
// Description : None
-#define PWM_INTE_CH4_RESET _U(0x0)
-#define PWM_INTE_CH4_BITS _U(0x00000010)
-#define PWM_INTE_CH4_MSB _U(4)
-#define PWM_INTE_CH4_LSB _U(4)
+#define PWM_INTE_CH4_RESET _u(0x0)
+#define PWM_INTE_CH4_BITS _u(0x00000010)
+#define PWM_INTE_CH4_MSB _u(4)
+#define PWM_INTE_CH4_LSB _u(4)
#define PWM_INTE_CH4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTE_CH3
// Description : None
-#define PWM_INTE_CH3_RESET _U(0x0)
-#define PWM_INTE_CH3_BITS _U(0x00000008)
-#define PWM_INTE_CH3_MSB _U(3)
-#define PWM_INTE_CH3_LSB _U(3)
+#define PWM_INTE_CH3_RESET _u(0x0)
+#define PWM_INTE_CH3_BITS _u(0x00000008)
+#define PWM_INTE_CH3_MSB _u(3)
+#define PWM_INTE_CH3_LSB _u(3)
#define PWM_INTE_CH3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTE_CH2
// Description : None
-#define PWM_INTE_CH2_RESET _U(0x0)
-#define PWM_INTE_CH2_BITS _U(0x00000004)
-#define PWM_INTE_CH2_MSB _U(2)
-#define PWM_INTE_CH2_LSB _U(2)
+#define PWM_INTE_CH2_RESET _u(0x0)
+#define PWM_INTE_CH2_BITS _u(0x00000004)
+#define PWM_INTE_CH2_MSB _u(2)
+#define PWM_INTE_CH2_LSB _u(2)
#define PWM_INTE_CH2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTE_CH1
// Description : None
-#define PWM_INTE_CH1_RESET _U(0x0)
-#define PWM_INTE_CH1_BITS _U(0x00000002)
-#define PWM_INTE_CH1_MSB _U(1)
-#define PWM_INTE_CH1_LSB _U(1)
+#define PWM_INTE_CH1_RESET _u(0x0)
+#define PWM_INTE_CH1_BITS _u(0x00000002)
+#define PWM_INTE_CH1_MSB _u(1)
+#define PWM_INTE_CH1_LSB _u(1)
#define PWM_INTE_CH1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTE_CH0
// Description : None
-#define PWM_INTE_CH0_RESET _U(0x0)
-#define PWM_INTE_CH0_BITS _U(0x00000001)
-#define PWM_INTE_CH0_MSB _U(0)
-#define PWM_INTE_CH0_LSB _U(0)
+#define PWM_INTE_CH0_RESET _u(0x0)
+#define PWM_INTE_CH0_BITS _u(0x00000001)
+#define PWM_INTE_CH0_MSB _u(0)
+#define PWM_INTE_CH0_LSB _u(0)
#define PWM_INTE_CH0_ACCESS "RW"
// =============================================================================
// Register : PWM_INTF
// Description : Interrupt Force
-#define PWM_INTF_OFFSET _U(0x000000ac)
-#define PWM_INTF_BITS _U(0x000000ff)
-#define PWM_INTF_RESET _U(0x00000000)
+#define PWM_INTF_OFFSET _u(0x000000ac)
+#define PWM_INTF_BITS _u(0x000000ff)
+#define PWM_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_INTF_CH7
// Description : None
-#define PWM_INTF_CH7_RESET _U(0x0)
-#define PWM_INTF_CH7_BITS _U(0x00000080)
-#define PWM_INTF_CH7_MSB _U(7)
-#define PWM_INTF_CH7_LSB _U(7)
+#define PWM_INTF_CH7_RESET _u(0x0)
+#define PWM_INTF_CH7_BITS _u(0x00000080)
+#define PWM_INTF_CH7_MSB _u(7)
+#define PWM_INTF_CH7_LSB _u(7)
#define PWM_INTF_CH7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTF_CH6
// Description : None
-#define PWM_INTF_CH6_RESET _U(0x0)
-#define PWM_INTF_CH6_BITS _U(0x00000040)
-#define PWM_INTF_CH6_MSB _U(6)
-#define PWM_INTF_CH6_LSB _U(6)
+#define PWM_INTF_CH6_RESET _u(0x0)
+#define PWM_INTF_CH6_BITS _u(0x00000040)
+#define PWM_INTF_CH6_MSB _u(6)
+#define PWM_INTF_CH6_LSB _u(6)
#define PWM_INTF_CH6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTF_CH5
// Description : None
-#define PWM_INTF_CH5_RESET _U(0x0)
-#define PWM_INTF_CH5_BITS _U(0x00000020)
-#define PWM_INTF_CH5_MSB _U(5)
-#define PWM_INTF_CH5_LSB _U(5)
+#define PWM_INTF_CH5_RESET _u(0x0)
+#define PWM_INTF_CH5_BITS _u(0x00000020)
+#define PWM_INTF_CH5_MSB _u(5)
+#define PWM_INTF_CH5_LSB _u(5)
#define PWM_INTF_CH5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTF_CH4
// Description : None
-#define PWM_INTF_CH4_RESET _U(0x0)
-#define PWM_INTF_CH4_BITS _U(0x00000010)
-#define PWM_INTF_CH4_MSB _U(4)
-#define PWM_INTF_CH4_LSB _U(4)
+#define PWM_INTF_CH4_RESET _u(0x0)
+#define PWM_INTF_CH4_BITS _u(0x00000010)
+#define PWM_INTF_CH4_MSB _u(4)
+#define PWM_INTF_CH4_LSB _u(4)
#define PWM_INTF_CH4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTF_CH3
// Description : None
-#define PWM_INTF_CH3_RESET _U(0x0)
-#define PWM_INTF_CH3_BITS _U(0x00000008)
-#define PWM_INTF_CH3_MSB _U(3)
-#define PWM_INTF_CH3_LSB _U(3)
+#define PWM_INTF_CH3_RESET _u(0x0)
+#define PWM_INTF_CH3_BITS _u(0x00000008)
+#define PWM_INTF_CH3_MSB _u(3)
+#define PWM_INTF_CH3_LSB _u(3)
#define PWM_INTF_CH3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTF_CH2
// Description : None
-#define PWM_INTF_CH2_RESET _U(0x0)
-#define PWM_INTF_CH2_BITS _U(0x00000004)
-#define PWM_INTF_CH2_MSB _U(2)
-#define PWM_INTF_CH2_LSB _U(2)
+#define PWM_INTF_CH2_RESET _u(0x0)
+#define PWM_INTF_CH2_BITS _u(0x00000004)
+#define PWM_INTF_CH2_MSB _u(2)
+#define PWM_INTF_CH2_LSB _u(2)
#define PWM_INTF_CH2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTF_CH1
// Description : None
-#define PWM_INTF_CH1_RESET _U(0x0)
-#define PWM_INTF_CH1_BITS _U(0x00000002)
-#define PWM_INTF_CH1_MSB _U(1)
-#define PWM_INTF_CH1_LSB _U(1)
+#define PWM_INTF_CH1_RESET _u(0x0)
+#define PWM_INTF_CH1_BITS _u(0x00000002)
+#define PWM_INTF_CH1_MSB _u(1)
+#define PWM_INTF_CH1_LSB _u(1)
#define PWM_INTF_CH1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTF_CH0
// Description : None
-#define PWM_INTF_CH0_RESET _U(0x0)
-#define PWM_INTF_CH0_BITS _U(0x00000001)
-#define PWM_INTF_CH0_MSB _U(0)
-#define PWM_INTF_CH0_LSB _U(0)
+#define PWM_INTF_CH0_RESET _u(0x0)
+#define PWM_INTF_CH0_BITS _u(0x00000001)
+#define PWM_INTF_CH0_MSB _u(0)
+#define PWM_INTF_CH0_LSB _u(0)
#define PWM_INTF_CH0_ACCESS "RW"
// =============================================================================
// Register : PWM_INTS
// Description : Interrupt status after masking & forcing
-#define PWM_INTS_OFFSET _U(0x000000b0)
-#define PWM_INTS_BITS _U(0x000000ff)
-#define PWM_INTS_RESET _U(0x00000000)
+#define PWM_INTS_OFFSET _u(0x000000b0)
+#define PWM_INTS_BITS _u(0x000000ff)
+#define PWM_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_INTS_CH7
// Description : None
-#define PWM_INTS_CH7_RESET _U(0x0)
-#define PWM_INTS_CH7_BITS _U(0x00000080)
-#define PWM_INTS_CH7_MSB _U(7)
-#define PWM_INTS_CH7_LSB _U(7)
+#define PWM_INTS_CH7_RESET _u(0x0)
+#define PWM_INTS_CH7_BITS _u(0x00000080)
+#define PWM_INTS_CH7_MSB _u(7)
+#define PWM_INTS_CH7_LSB _u(7)
#define PWM_INTS_CH7_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PWM_INTS_CH6
// Description : None
-#define PWM_INTS_CH6_RESET _U(0x0)
-#define PWM_INTS_CH6_BITS _U(0x00000040)
-#define PWM_INTS_CH6_MSB _U(6)
-#define PWM_INTS_CH6_LSB _U(6)
+#define PWM_INTS_CH6_RESET _u(0x0)
+#define PWM_INTS_CH6_BITS _u(0x00000040)
+#define PWM_INTS_CH6_MSB _u(6)
+#define PWM_INTS_CH6_LSB _u(6)
#define PWM_INTS_CH6_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PWM_INTS_CH5
// Description : None
-#define PWM_INTS_CH5_RESET _U(0x0)
-#define PWM_INTS_CH5_BITS _U(0x00000020)
-#define PWM_INTS_CH5_MSB _U(5)
-#define PWM_INTS_CH5_LSB _U(5)
+#define PWM_INTS_CH5_RESET _u(0x0)
+#define PWM_INTS_CH5_BITS _u(0x00000020)
+#define PWM_INTS_CH5_MSB _u(5)
+#define PWM_INTS_CH5_LSB _u(5)
#define PWM_INTS_CH5_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PWM_INTS_CH4
// Description : None
-#define PWM_INTS_CH4_RESET _U(0x0)
-#define PWM_INTS_CH4_BITS _U(0x00000010)
-#define PWM_INTS_CH4_MSB _U(4)
-#define PWM_INTS_CH4_LSB _U(4)
+#define PWM_INTS_CH4_RESET _u(0x0)
+#define PWM_INTS_CH4_BITS _u(0x00000010)
+#define PWM_INTS_CH4_MSB _u(4)
+#define PWM_INTS_CH4_LSB _u(4)
#define PWM_INTS_CH4_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PWM_INTS_CH3
// Description : None
-#define PWM_INTS_CH3_RESET _U(0x0)
-#define PWM_INTS_CH3_BITS _U(0x00000008)
-#define PWM_INTS_CH3_MSB _U(3)
-#define PWM_INTS_CH3_LSB _U(3)
+#define PWM_INTS_CH3_RESET _u(0x0)
+#define PWM_INTS_CH3_BITS _u(0x00000008)
+#define PWM_INTS_CH3_MSB _u(3)
+#define PWM_INTS_CH3_LSB _u(3)
#define PWM_INTS_CH3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PWM_INTS_CH2
// Description : None
-#define PWM_INTS_CH2_RESET _U(0x0)
-#define PWM_INTS_CH2_BITS _U(0x00000004)
-#define PWM_INTS_CH2_MSB _U(2)
-#define PWM_INTS_CH2_LSB _U(2)
+#define PWM_INTS_CH2_RESET _u(0x0)
+#define PWM_INTS_CH2_BITS _u(0x00000004)
+#define PWM_INTS_CH2_MSB _u(2)
+#define PWM_INTS_CH2_LSB _u(2)
#define PWM_INTS_CH2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PWM_INTS_CH1
// Description : None
-#define PWM_INTS_CH1_RESET _U(0x0)
-#define PWM_INTS_CH1_BITS _U(0x00000002)
-#define PWM_INTS_CH1_MSB _U(1)
-#define PWM_INTS_CH1_LSB _U(1)
+#define PWM_INTS_CH1_RESET _u(0x0)
+#define PWM_INTS_CH1_BITS _u(0x00000002)
+#define PWM_INTS_CH1_MSB _u(1)
+#define PWM_INTS_CH1_LSB _u(1)
#define PWM_INTS_CH1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PWM_INTS_CH0
// Description : None
-#define PWM_INTS_CH0_RESET _U(0x0)
-#define PWM_INTS_CH0_BITS _U(0x00000001)
-#define PWM_INTS_CH0_MSB _U(0)
-#define PWM_INTS_CH0_LSB _U(0)
+#define PWM_INTS_CH0_RESET _u(0x0)
+#define PWM_INTS_CH0_BITS _u(0x00000001)
+#define PWM_INTS_CH0_MSB _u(0)
+#define PWM_INTS_CH0_LSB _u(0)
#define PWM_INTS_CH0_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_PWM_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/resets.h b/src/rp2040/hardware_regs/include/hardware/regs/resets.h
index ddbad96..689a358 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/resets.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/resets.h
@@ -15,623 +15,623 @@
// Register : RESETS_RESET
// Description : Reset control. If a bit is set it means the peripheral is in
// reset. 0 means the peripheral's reset is deasserted.
-#define RESETS_RESET_OFFSET _U(0x00000000)
-#define RESETS_RESET_BITS _U(0x01ffffff)
-#define RESETS_RESET_RESET _U(0x01ffffff)
+#define RESETS_RESET_OFFSET _u(0x00000000)
+#define RESETS_RESET_BITS _u(0x01ffffff)
+#define RESETS_RESET_RESET _u(0x01ffffff)
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_USBCTRL
// Description : None
-#define RESETS_RESET_USBCTRL_RESET _U(0x1)
-#define RESETS_RESET_USBCTRL_BITS _U(0x01000000)
-#define RESETS_RESET_USBCTRL_MSB _U(24)
-#define RESETS_RESET_USBCTRL_LSB _U(24)
+#define RESETS_RESET_USBCTRL_RESET _u(0x1)
+#define RESETS_RESET_USBCTRL_BITS _u(0x01000000)
+#define RESETS_RESET_USBCTRL_MSB _u(24)
+#define RESETS_RESET_USBCTRL_LSB _u(24)
#define RESETS_RESET_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_UART1
// Description : None
-#define RESETS_RESET_UART1_RESET _U(0x1)
-#define RESETS_RESET_UART1_BITS _U(0x00800000)
-#define RESETS_RESET_UART1_MSB _U(23)
-#define RESETS_RESET_UART1_LSB _U(23)
+#define RESETS_RESET_UART1_RESET _u(0x1)
+#define RESETS_RESET_UART1_BITS _u(0x00800000)
+#define RESETS_RESET_UART1_MSB _u(23)
+#define RESETS_RESET_UART1_LSB _u(23)
#define RESETS_RESET_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_UART0
// Description : None
-#define RESETS_RESET_UART0_RESET _U(0x1)
-#define RESETS_RESET_UART0_BITS _U(0x00400000)
-#define RESETS_RESET_UART0_MSB _U(22)
-#define RESETS_RESET_UART0_LSB _U(22)
+#define RESETS_RESET_UART0_RESET _u(0x1)
+#define RESETS_RESET_UART0_BITS _u(0x00400000)
+#define RESETS_RESET_UART0_MSB _u(22)
+#define RESETS_RESET_UART0_LSB _u(22)
#define RESETS_RESET_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TIMER
// Description : None
-#define RESETS_RESET_TIMER_RESET _U(0x1)
-#define RESETS_RESET_TIMER_BITS _U(0x00200000)
-#define RESETS_RESET_TIMER_MSB _U(21)
-#define RESETS_RESET_TIMER_LSB _U(21)
+#define RESETS_RESET_TIMER_RESET _u(0x1)
+#define RESETS_RESET_TIMER_BITS _u(0x00200000)
+#define RESETS_RESET_TIMER_MSB _u(21)
+#define RESETS_RESET_TIMER_LSB _u(21)
#define RESETS_RESET_TIMER_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TBMAN
// Description : None
-#define RESETS_RESET_TBMAN_RESET _U(0x1)
-#define RESETS_RESET_TBMAN_BITS _U(0x00100000)
-#define RESETS_RESET_TBMAN_MSB _U(20)
-#define RESETS_RESET_TBMAN_LSB _U(20)
+#define RESETS_RESET_TBMAN_RESET _u(0x1)
+#define RESETS_RESET_TBMAN_BITS _u(0x00100000)
+#define RESETS_RESET_TBMAN_MSB _u(20)
+#define RESETS_RESET_TBMAN_LSB _u(20)
#define RESETS_RESET_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SYSINFO
// Description : None
-#define RESETS_RESET_SYSINFO_RESET _U(0x1)
-#define RESETS_RESET_SYSINFO_BITS _U(0x00080000)
-#define RESETS_RESET_SYSINFO_MSB _U(19)
-#define RESETS_RESET_SYSINFO_LSB _U(19)
+#define RESETS_RESET_SYSINFO_RESET _u(0x1)
+#define RESETS_RESET_SYSINFO_BITS _u(0x00080000)
+#define RESETS_RESET_SYSINFO_MSB _u(19)
+#define RESETS_RESET_SYSINFO_LSB _u(19)
#define RESETS_RESET_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SYSCFG
// Description : None
-#define RESETS_RESET_SYSCFG_RESET _U(0x1)
-#define RESETS_RESET_SYSCFG_BITS _U(0x00040000)
-#define RESETS_RESET_SYSCFG_MSB _U(18)
-#define RESETS_RESET_SYSCFG_LSB _U(18)
+#define RESETS_RESET_SYSCFG_RESET _u(0x1)
+#define RESETS_RESET_SYSCFG_BITS _u(0x00040000)
+#define RESETS_RESET_SYSCFG_MSB _u(18)
+#define RESETS_RESET_SYSCFG_LSB _u(18)
#define RESETS_RESET_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SPI1
// Description : None
-#define RESETS_RESET_SPI1_RESET _U(0x1)
-#define RESETS_RESET_SPI1_BITS _U(0x00020000)
-#define RESETS_RESET_SPI1_MSB _U(17)
-#define RESETS_RESET_SPI1_LSB _U(17)
+#define RESETS_RESET_SPI1_RESET _u(0x1)
+#define RESETS_RESET_SPI1_BITS _u(0x00020000)
+#define RESETS_RESET_SPI1_MSB _u(17)
+#define RESETS_RESET_SPI1_LSB _u(17)
#define RESETS_RESET_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SPI0
// Description : None
-#define RESETS_RESET_SPI0_RESET _U(0x1)
-#define RESETS_RESET_SPI0_BITS _U(0x00010000)
-#define RESETS_RESET_SPI0_MSB _U(16)
-#define RESETS_RESET_SPI0_LSB _U(16)
+#define RESETS_RESET_SPI0_RESET _u(0x1)
+#define RESETS_RESET_SPI0_BITS _u(0x00010000)
+#define RESETS_RESET_SPI0_MSB _u(16)
+#define RESETS_RESET_SPI0_LSB _u(16)
#define RESETS_RESET_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_RTC
// Description : None
-#define RESETS_RESET_RTC_RESET _U(0x1)
-#define RESETS_RESET_RTC_BITS _U(0x00008000)
-#define RESETS_RESET_RTC_MSB _U(15)
-#define RESETS_RESET_RTC_LSB _U(15)
+#define RESETS_RESET_RTC_RESET _u(0x1)
+#define RESETS_RESET_RTC_BITS _u(0x00008000)
+#define RESETS_RESET_RTC_MSB _u(15)
+#define RESETS_RESET_RTC_LSB _u(15)
#define RESETS_RESET_RTC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PWM
// Description : None
-#define RESETS_RESET_PWM_RESET _U(0x1)
-#define RESETS_RESET_PWM_BITS _U(0x00004000)
-#define RESETS_RESET_PWM_MSB _U(14)
-#define RESETS_RESET_PWM_LSB _U(14)
+#define RESETS_RESET_PWM_RESET _u(0x1)
+#define RESETS_RESET_PWM_BITS _u(0x00004000)
+#define RESETS_RESET_PWM_MSB _u(14)
+#define RESETS_RESET_PWM_LSB _u(14)
#define RESETS_RESET_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PLL_USB
// Description : None
-#define RESETS_RESET_PLL_USB_RESET _U(0x1)
-#define RESETS_RESET_PLL_USB_BITS _U(0x00002000)
-#define RESETS_RESET_PLL_USB_MSB _U(13)
-#define RESETS_RESET_PLL_USB_LSB _U(13)
+#define RESETS_RESET_PLL_USB_RESET _u(0x1)
+#define RESETS_RESET_PLL_USB_BITS _u(0x00002000)
+#define RESETS_RESET_PLL_USB_MSB _u(13)
+#define RESETS_RESET_PLL_USB_LSB _u(13)
#define RESETS_RESET_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PLL_SYS
// Description : None
-#define RESETS_RESET_PLL_SYS_RESET _U(0x1)
-#define RESETS_RESET_PLL_SYS_BITS _U(0x00001000)
-#define RESETS_RESET_PLL_SYS_MSB _U(12)
-#define RESETS_RESET_PLL_SYS_LSB _U(12)
+#define RESETS_RESET_PLL_SYS_RESET _u(0x1)
+#define RESETS_RESET_PLL_SYS_BITS _u(0x00001000)
+#define RESETS_RESET_PLL_SYS_MSB _u(12)
+#define RESETS_RESET_PLL_SYS_LSB _u(12)
#define RESETS_RESET_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO1
// Description : None
-#define RESETS_RESET_PIO1_RESET _U(0x1)
-#define RESETS_RESET_PIO1_BITS _U(0x00000800)
-#define RESETS_RESET_PIO1_MSB _U(11)
-#define RESETS_RESET_PIO1_LSB _U(11)
+#define RESETS_RESET_PIO1_RESET _u(0x1)
+#define RESETS_RESET_PIO1_BITS _u(0x00000800)
+#define RESETS_RESET_PIO1_MSB _u(11)
+#define RESETS_RESET_PIO1_LSB _u(11)
#define RESETS_RESET_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO0
// Description : None
-#define RESETS_RESET_PIO0_RESET _U(0x1)
-#define RESETS_RESET_PIO0_BITS _U(0x00000400)
-#define RESETS_RESET_PIO0_MSB _U(10)
-#define RESETS_RESET_PIO0_LSB _U(10)
+#define RESETS_RESET_PIO0_RESET _u(0x1)
+#define RESETS_RESET_PIO0_BITS _u(0x00000400)
+#define RESETS_RESET_PIO0_MSB _u(10)
+#define RESETS_RESET_PIO0_LSB _u(10)
#define RESETS_RESET_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PADS_QSPI
// Description : None
-#define RESETS_RESET_PADS_QSPI_RESET _U(0x1)
-#define RESETS_RESET_PADS_QSPI_BITS _U(0x00000200)
-#define RESETS_RESET_PADS_QSPI_MSB _U(9)
-#define RESETS_RESET_PADS_QSPI_LSB _U(9)
+#define RESETS_RESET_PADS_QSPI_RESET _u(0x1)
+#define RESETS_RESET_PADS_QSPI_BITS _u(0x00000200)
+#define RESETS_RESET_PADS_QSPI_MSB _u(9)
+#define RESETS_RESET_PADS_QSPI_LSB _u(9)
#define RESETS_RESET_PADS_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PADS_BANK0
// Description : None
-#define RESETS_RESET_PADS_BANK0_RESET _U(0x1)
-#define RESETS_RESET_PADS_BANK0_BITS _U(0x00000100)
-#define RESETS_RESET_PADS_BANK0_MSB _U(8)
-#define RESETS_RESET_PADS_BANK0_LSB _U(8)
+#define RESETS_RESET_PADS_BANK0_RESET _u(0x1)
+#define RESETS_RESET_PADS_BANK0_BITS _u(0x00000100)
+#define RESETS_RESET_PADS_BANK0_MSB _u(8)
+#define RESETS_RESET_PADS_BANK0_LSB _u(8)
#define RESETS_RESET_PADS_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_JTAG
// Description : None
-#define RESETS_RESET_JTAG_RESET _U(0x1)
-#define RESETS_RESET_JTAG_BITS _U(0x00000080)
-#define RESETS_RESET_JTAG_MSB _U(7)
-#define RESETS_RESET_JTAG_LSB _U(7)
+#define RESETS_RESET_JTAG_RESET _u(0x1)
+#define RESETS_RESET_JTAG_BITS _u(0x00000080)
+#define RESETS_RESET_JTAG_MSB _u(7)
+#define RESETS_RESET_JTAG_LSB _u(7)
#define RESETS_RESET_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_IO_QSPI
// Description : None
-#define RESETS_RESET_IO_QSPI_RESET _U(0x1)
-#define RESETS_RESET_IO_QSPI_BITS _U(0x00000040)
-#define RESETS_RESET_IO_QSPI_MSB _U(6)
-#define RESETS_RESET_IO_QSPI_LSB _U(6)
+#define RESETS_RESET_IO_QSPI_RESET _u(0x1)
+#define RESETS_RESET_IO_QSPI_BITS _u(0x00000040)
+#define RESETS_RESET_IO_QSPI_MSB _u(6)
+#define RESETS_RESET_IO_QSPI_LSB _u(6)
#define RESETS_RESET_IO_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_IO_BANK0
// Description : None
-#define RESETS_RESET_IO_BANK0_RESET _U(0x1)
-#define RESETS_RESET_IO_BANK0_BITS _U(0x00000020)
-#define RESETS_RESET_IO_BANK0_MSB _U(5)
-#define RESETS_RESET_IO_BANK0_LSB _U(5)
+#define RESETS_RESET_IO_BANK0_RESET _u(0x1)
+#define RESETS_RESET_IO_BANK0_BITS _u(0x00000020)
+#define RESETS_RESET_IO_BANK0_MSB _u(5)
+#define RESETS_RESET_IO_BANK0_LSB _u(5)
#define RESETS_RESET_IO_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_I2C1
// Description : None
-#define RESETS_RESET_I2C1_RESET _U(0x1)
-#define RESETS_RESET_I2C1_BITS _U(0x00000010)
-#define RESETS_RESET_I2C1_MSB _U(4)
-#define RESETS_RESET_I2C1_LSB _U(4)
+#define RESETS_RESET_I2C1_RESET _u(0x1)
+#define RESETS_RESET_I2C1_BITS _u(0x00000010)
+#define RESETS_RESET_I2C1_MSB _u(4)
+#define RESETS_RESET_I2C1_LSB _u(4)
#define RESETS_RESET_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_I2C0
// Description : None
-#define RESETS_RESET_I2C0_RESET _U(0x1)
-#define RESETS_RESET_I2C0_BITS _U(0x00000008)
-#define RESETS_RESET_I2C0_MSB _U(3)
-#define RESETS_RESET_I2C0_LSB _U(3)
+#define RESETS_RESET_I2C0_RESET _u(0x1)
+#define RESETS_RESET_I2C0_BITS _u(0x00000008)
+#define RESETS_RESET_I2C0_MSB _u(3)
+#define RESETS_RESET_I2C0_LSB _u(3)
#define RESETS_RESET_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DMA
// Description : None
-#define RESETS_RESET_DMA_RESET _U(0x1)
-#define RESETS_RESET_DMA_BITS _U(0x00000004)
-#define RESETS_RESET_DMA_MSB _U(2)
-#define RESETS_RESET_DMA_LSB _U(2)
+#define RESETS_RESET_DMA_RESET _u(0x1)
+#define RESETS_RESET_DMA_BITS _u(0x00000004)
+#define RESETS_RESET_DMA_MSB _u(2)
+#define RESETS_RESET_DMA_LSB _u(2)
#define RESETS_RESET_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_BUSCTRL
// Description : None
-#define RESETS_RESET_BUSCTRL_RESET _U(0x1)
-#define RESETS_RESET_BUSCTRL_BITS _U(0x00000002)
-#define RESETS_RESET_BUSCTRL_MSB _U(1)
-#define RESETS_RESET_BUSCTRL_LSB _U(1)
+#define RESETS_RESET_BUSCTRL_RESET _u(0x1)
+#define RESETS_RESET_BUSCTRL_BITS _u(0x00000002)
+#define RESETS_RESET_BUSCTRL_MSB _u(1)
+#define RESETS_RESET_BUSCTRL_LSB _u(1)
#define RESETS_RESET_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_ADC
// Description : None
-#define RESETS_RESET_ADC_RESET _U(0x1)
-#define RESETS_RESET_ADC_BITS _U(0x00000001)
-#define RESETS_RESET_ADC_MSB _U(0)
-#define RESETS_RESET_ADC_LSB _U(0)
+#define RESETS_RESET_ADC_RESET _u(0x1)
+#define RESETS_RESET_ADC_BITS _u(0x00000001)
+#define RESETS_RESET_ADC_MSB _u(0)
+#define RESETS_RESET_ADC_LSB _u(0)
#define RESETS_RESET_ADC_ACCESS "RW"
// =============================================================================
// Register : RESETS_WDSEL
// Description : Watchdog select. If a bit is set then the watchdog will reset
// this peripheral when the watchdog fires.
-#define RESETS_WDSEL_OFFSET _U(0x00000004)
-#define RESETS_WDSEL_BITS _U(0x01ffffff)
-#define RESETS_WDSEL_RESET _U(0x00000000)
+#define RESETS_WDSEL_OFFSET _u(0x00000004)
+#define RESETS_WDSEL_BITS _u(0x01ffffff)
+#define RESETS_WDSEL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_USBCTRL
// Description : None
-#define RESETS_WDSEL_USBCTRL_RESET _U(0x0)
-#define RESETS_WDSEL_USBCTRL_BITS _U(0x01000000)
-#define RESETS_WDSEL_USBCTRL_MSB _U(24)
-#define RESETS_WDSEL_USBCTRL_LSB _U(24)
+#define RESETS_WDSEL_USBCTRL_RESET _u(0x0)
+#define RESETS_WDSEL_USBCTRL_BITS _u(0x01000000)
+#define RESETS_WDSEL_USBCTRL_MSB _u(24)
+#define RESETS_WDSEL_USBCTRL_LSB _u(24)
#define RESETS_WDSEL_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_UART1
// Description : None
-#define RESETS_WDSEL_UART1_RESET _U(0x0)
-#define RESETS_WDSEL_UART1_BITS _U(0x00800000)
-#define RESETS_WDSEL_UART1_MSB _U(23)
-#define RESETS_WDSEL_UART1_LSB _U(23)
+#define RESETS_WDSEL_UART1_RESET _u(0x0)
+#define RESETS_WDSEL_UART1_BITS _u(0x00800000)
+#define RESETS_WDSEL_UART1_MSB _u(23)
+#define RESETS_WDSEL_UART1_LSB _u(23)
#define RESETS_WDSEL_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_UART0
// Description : None
-#define RESETS_WDSEL_UART0_RESET _U(0x0)
-#define RESETS_WDSEL_UART0_BITS _U(0x00400000)
-#define RESETS_WDSEL_UART0_MSB _U(22)
-#define RESETS_WDSEL_UART0_LSB _U(22)
+#define RESETS_WDSEL_UART0_RESET _u(0x0)
+#define RESETS_WDSEL_UART0_BITS _u(0x00400000)
+#define RESETS_WDSEL_UART0_MSB _u(22)
+#define RESETS_WDSEL_UART0_LSB _u(22)
#define RESETS_WDSEL_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TIMER
// Description : None
-#define RESETS_WDSEL_TIMER_RESET _U(0x0)
-#define RESETS_WDSEL_TIMER_BITS _U(0x00200000)
-#define RESETS_WDSEL_TIMER_MSB _U(21)
-#define RESETS_WDSEL_TIMER_LSB _U(21)
+#define RESETS_WDSEL_TIMER_RESET _u(0x0)
+#define RESETS_WDSEL_TIMER_BITS _u(0x00200000)
+#define RESETS_WDSEL_TIMER_MSB _u(21)
+#define RESETS_WDSEL_TIMER_LSB _u(21)
#define RESETS_WDSEL_TIMER_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TBMAN
// Description : None
-#define RESETS_WDSEL_TBMAN_RESET _U(0x0)
-#define RESETS_WDSEL_TBMAN_BITS _U(0x00100000)
-#define RESETS_WDSEL_TBMAN_MSB _U(20)
-#define RESETS_WDSEL_TBMAN_LSB _U(20)
+#define RESETS_WDSEL_TBMAN_RESET _u(0x0)
+#define RESETS_WDSEL_TBMAN_BITS _u(0x00100000)
+#define RESETS_WDSEL_TBMAN_MSB _u(20)
+#define RESETS_WDSEL_TBMAN_LSB _u(20)
#define RESETS_WDSEL_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SYSINFO
// Description : None
-#define RESETS_WDSEL_SYSINFO_RESET _U(0x0)
-#define RESETS_WDSEL_SYSINFO_BITS _U(0x00080000)
-#define RESETS_WDSEL_SYSINFO_MSB _U(19)
-#define RESETS_WDSEL_SYSINFO_LSB _U(19)
+#define RESETS_WDSEL_SYSINFO_RESET _u(0x0)
+#define RESETS_WDSEL_SYSINFO_BITS _u(0x00080000)
+#define RESETS_WDSEL_SYSINFO_MSB _u(19)
+#define RESETS_WDSEL_SYSINFO_LSB _u(19)
#define RESETS_WDSEL_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SYSCFG
// Description : None
-#define RESETS_WDSEL_SYSCFG_RESET _U(0x0)
-#define RESETS_WDSEL_SYSCFG_BITS _U(0x00040000)
-#define RESETS_WDSEL_SYSCFG_MSB _U(18)
-#define RESETS_WDSEL_SYSCFG_LSB _U(18)
+#define RESETS_WDSEL_SYSCFG_RESET _u(0x0)
+#define RESETS_WDSEL_SYSCFG_BITS _u(0x00040000)
+#define RESETS_WDSEL_SYSCFG_MSB _u(18)
+#define RESETS_WDSEL_SYSCFG_LSB _u(18)
#define RESETS_WDSEL_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SPI1
// Description : None
-#define RESETS_WDSEL_SPI1_RESET _U(0x0)
-#define RESETS_WDSEL_SPI1_BITS _U(0x00020000)
-#define RESETS_WDSEL_SPI1_MSB _U(17)
-#define RESETS_WDSEL_SPI1_LSB _U(17)
+#define RESETS_WDSEL_SPI1_RESET _u(0x0)
+#define RESETS_WDSEL_SPI1_BITS _u(0x00020000)
+#define RESETS_WDSEL_SPI1_MSB _u(17)
+#define RESETS_WDSEL_SPI1_LSB _u(17)
#define RESETS_WDSEL_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SPI0
// Description : None
-#define RESETS_WDSEL_SPI0_RESET _U(0x0)
-#define RESETS_WDSEL_SPI0_BITS _U(0x00010000)
-#define RESETS_WDSEL_SPI0_MSB _U(16)
-#define RESETS_WDSEL_SPI0_LSB _U(16)
+#define RESETS_WDSEL_SPI0_RESET _u(0x0)
+#define RESETS_WDSEL_SPI0_BITS _u(0x00010000)
+#define RESETS_WDSEL_SPI0_MSB _u(16)
+#define RESETS_WDSEL_SPI0_LSB _u(16)
#define RESETS_WDSEL_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_RTC
// Description : None
-#define RESETS_WDSEL_RTC_RESET _U(0x0)
-#define RESETS_WDSEL_RTC_BITS _U(0x00008000)
-#define RESETS_WDSEL_RTC_MSB _U(15)
-#define RESETS_WDSEL_RTC_LSB _U(15)
+#define RESETS_WDSEL_RTC_RESET _u(0x0)
+#define RESETS_WDSEL_RTC_BITS _u(0x00008000)
+#define RESETS_WDSEL_RTC_MSB _u(15)
+#define RESETS_WDSEL_RTC_LSB _u(15)
#define RESETS_WDSEL_RTC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PWM
// Description : None
-#define RESETS_WDSEL_PWM_RESET _U(0x0)
-#define RESETS_WDSEL_PWM_BITS _U(0x00004000)
-#define RESETS_WDSEL_PWM_MSB _U(14)
-#define RESETS_WDSEL_PWM_LSB _U(14)
+#define RESETS_WDSEL_PWM_RESET _u(0x0)
+#define RESETS_WDSEL_PWM_BITS _u(0x00004000)
+#define RESETS_WDSEL_PWM_MSB _u(14)
+#define RESETS_WDSEL_PWM_LSB _u(14)
#define RESETS_WDSEL_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PLL_USB
// Description : None
-#define RESETS_WDSEL_PLL_USB_RESET _U(0x0)
-#define RESETS_WDSEL_PLL_USB_BITS _U(0x00002000)
-#define RESETS_WDSEL_PLL_USB_MSB _U(13)
-#define RESETS_WDSEL_PLL_USB_LSB _U(13)
+#define RESETS_WDSEL_PLL_USB_RESET _u(0x0)
+#define RESETS_WDSEL_PLL_USB_BITS _u(0x00002000)
+#define RESETS_WDSEL_PLL_USB_MSB _u(13)
+#define RESETS_WDSEL_PLL_USB_LSB _u(13)
#define RESETS_WDSEL_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PLL_SYS
// Description : None
-#define RESETS_WDSEL_PLL_SYS_RESET _U(0x0)
-#define RESETS_WDSEL_PLL_SYS_BITS _U(0x00001000)
-#define RESETS_WDSEL_PLL_SYS_MSB _U(12)
-#define RESETS_WDSEL_PLL_SYS_LSB _U(12)
+#define RESETS_WDSEL_PLL_SYS_RESET _u(0x0)
+#define RESETS_WDSEL_PLL_SYS_BITS _u(0x00001000)
+#define RESETS_WDSEL_PLL_SYS_MSB _u(12)
+#define RESETS_WDSEL_PLL_SYS_LSB _u(12)
#define RESETS_WDSEL_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO1
// Description : None
-#define RESETS_WDSEL_PIO1_RESET _U(0x0)
-#define RESETS_WDSEL_PIO1_BITS _U(0x00000800)
-#define RESETS_WDSEL_PIO1_MSB _U(11)
-#define RESETS_WDSEL_PIO1_LSB _U(11)
+#define RESETS_WDSEL_PIO1_RESET _u(0x0)
+#define RESETS_WDSEL_PIO1_BITS _u(0x00000800)
+#define RESETS_WDSEL_PIO1_MSB _u(11)
+#define RESETS_WDSEL_PIO1_LSB _u(11)
#define RESETS_WDSEL_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO0
// Description : None
-#define RESETS_WDSEL_PIO0_RESET _U(0x0)
-#define RESETS_WDSEL_PIO0_BITS _U(0x00000400)
-#define RESETS_WDSEL_PIO0_MSB _U(10)
-#define RESETS_WDSEL_PIO0_LSB _U(10)
+#define RESETS_WDSEL_PIO0_RESET _u(0x0)
+#define RESETS_WDSEL_PIO0_BITS _u(0x00000400)
+#define RESETS_WDSEL_PIO0_MSB _u(10)
+#define RESETS_WDSEL_PIO0_LSB _u(10)
#define RESETS_WDSEL_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PADS_QSPI
// Description : None
-#define RESETS_WDSEL_PADS_QSPI_RESET _U(0x0)
-#define RESETS_WDSEL_PADS_QSPI_BITS _U(0x00000200)
-#define RESETS_WDSEL_PADS_QSPI_MSB _U(9)
-#define RESETS_WDSEL_PADS_QSPI_LSB _U(9)
+#define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0)
+#define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000200)
+#define RESETS_WDSEL_PADS_QSPI_MSB _u(9)
+#define RESETS_WDSEL_PADS_QSPI_LSB _u(9)
#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PADS_BANK0
// Description : None
-#define RESETS_WDSEL_PADS_BANK0_RESET _U(0x0)
-#define RESETS_WDSEL_PADS_BANK0_BITS _U(0x00000100)
-#define RESETS_WDSEL_PADS_BANK0_MSB _U(8)
-#define RESETS_WDSEL_PADS_BANK0_LSB _U(8)
+#define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0)
+#define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000100)
+#define RESETS_WDSEL_PADS_BANK0_MSB _u(8)
+#define RESETS_WDSEL_PADS_BANK0_LSB _u(8)
#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_JTAG
// Description : None
-#define RESETS_WDSEL_JTAG_RESET _U(0x0)
-#define RESETS_WDSEL_JTAG_BITS _U(0x00000080)
-#define RESETS_WDSEL_JTAG_MSB _U(7)
-#define RESETS_WDSEL_JTAG_LSB _U(7)
+#define RESETS_WDSEL_JTAG_RESET _u(0x0)
+#define RESETS_WDSEL_JTAG_BITS _u(0x00000080)
+#define RESETS_WDSEL_JTAG_MSB _u(7)
+#define RESETS_WDSEL_JTAG_LSB _u(7)
#define RESETS_WDSEL_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_IO_QSPI
// Description : None
-#define RESETS_WDSEL_IO_QSPI_RESET _U(0x0)
-#define RESETS_WDSEL_IO_QSPI_BITS _U(0x00000040)
-#define RESETS_WDSEL_IO_QSPI_MSB _U(6)
-#define RESETS_WDSEL_IO_QSPI_LSB _U(6)
+#define RESETS_WDSEL_IO_QSPI_RESET _u(0x0)
+#define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000040)
+#define RESETS_WDSEL_IO_QSPI_MSB _u(6)
+#define RESETS_WDSEL_IO_QSPI_LSB _u(6)
#define RESETS_WDSEL_IO_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_IO_BANK0
// Description : None
-#define RESETS_WDSEL_IO_BANK0_RESET _U(0x0)
-#define RESETS_WDSEL_IO_BANK0_BITS _U(0x00000020)
-#define RESETS_WDSEL_IO_BANK0_MSB _U(5)
-#define RESETS_WDSEL_IO_BANK0_LSB _U(5)
+#define RESETS_WDSEL_IO_BANK0_RESET _u(0x0)
+#define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000020)
+#define RESETS_WDSEL_IO_BANK0_MSB _u(5)
+#define RESETS_WDSEL_IO_BANK0_LSB _u(5)
#define RESETS_WDSEL_IO_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_I2C1
// Description : None
-#define RESETS_WDSEL_I2C1_RESET _U(0x0)
-#define RESETS_WDSEL_I2C1_BITS _U(0x00000010)
-#define RESETS_WDSEL_I2C1_MSB _U(4)
-#define RESETS_WDSEL_I2C1_LSB _U(4)
+#define RESETS_WDSEL_I2C1_RESET _u(0x0)
+#define RESETS_WDSEL_I2C1_BITS _u(0x00000010)
+#define RESETS_WDSEL_I2C1_MSB _u(4)
+#define RESETS_WDSEL_I2C1_LSB _u(4)
#define RESETS_WDSEL_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_I2C0
// Description : None
-#define RESETS_WDSEL_I2C0_RESET _U(0x0)
-#define RESETS_WDSEL_I2C0_BITS _U(0x00000008)
-#define RESETS_WDSEL_I2C0_MSB _U(3)
-#define RESETS_WDSEL_I2C0_LSB _U(3)
+#define RESETS_WDSEL_I2C0_RESET _u(0x0)
+#define RESETS_WDSEL_I2C0_BITS _u(0x00000008)
+#define RESETS_WDSEL_I2C0_MSB _u(3)
+#define RESETS_WDSEL_I2C0_LSB _u(3)
#define RESETS_WDSEL_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_DMA
// Description : None
-#define RESETS_WDSEL_DMA_RESET _U(0x0)
-#define RESETS_WDSEL_DMA_BITS _U(0x00000004)
-#define RESETS_WDSEL_DMA_MSB _U(2)
-#define RESETS_WDSEL_DMA_LSB _U(2)
+#define RESETS_WDSEL_DMA_RESET _u(0x0)
+#define RESETS_WDSEL_DMA_BITS _u(0x00000004)
+#define RESETS_WDSEL_DMA_MSB _u(2)
+#define RESETS_WDSEL_DMA_LSB _u(2)
#define RESETS_WDSEL_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_BUSCTRL
// Description : None
-#define RESETS_WDSEL_BUSCTRL_RESET _U(0x0)
-#define RESETS_WDSEL_BUSCTRL_BITS _U(0x00000002)
-#define RESETS_WDSEL_BUSCTRL_MSB _U(1)
-#define RESETS_WDSEL_BUSCTRL_LSB _U(1)
+#define RESETS_WDSEL_BUSCTRL_RESET _u(0x0)
+#define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002)
+#define RESETS_WDSEL_BUSCTRL_MSB _u(1)
+#define RESETS_WDSEL_BUSCTRL_LSB _u(1)
#define RESETS_WDSEL_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_ADC
// Description : None
-#define RESETS_WDSEL_ADC_RESET _U(0x0)
-#define RESETS_WDSEL_ADC_BITS _U(0x00000001)
-#define RESETS_WDSEL_ADC_MSB _U(0)
-#define RESETS_WDSEL_ADC_LSB _U(0)
+#define RESETS_WDSEL_ADC_RESET _u(0x0)
+#define RESETS_WDSEL_ADC_BITS _u(0x00000001)
+#define RESETS_WDSEL_ADC_MSB _u(0)
+#define RESETS_WDSEL_ADC_LSB _u(0)
#define RESETS_WDSEL_ADC_ACCESS "RW"
// =============================================================================
// Register : RESETS_RESET_DONE
// Description : Reset done. If a bit is set then a reset done signal has been
// returned by the peripheral. This indicates that the
// peripheral's registers are ready to be accessed.
-#define RESETS_RESET_DONE_OFFSET _U(0x00000008)
-#define RESETS_RESET_DONE_BITS _U(0x01ffffff)
-#define RESETS_RESET_DONE_RESET _U(0x00000000)
+#define RESETS_RESET_DONE_OFFSET _u(0x00000008)
+#define RESETS_RESET_DONE_BITS _u(0x01ffffff)
+#define RESETS_RESET_DONE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_USBCTRL
// Description : None
-#define RESETS_RESET_DONE_USBCTRL_RESET _U(0x0)
-#define RESETS_RESET_DONE_USBCTRL_BITS _U(0x01000000)
-#define RESETS_RESET_DONE_USBCTRL_MSB _U(24)
-#define RESETS_RESET_DONE_USBCTRL_LSB _U(24)
+#define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0)
+#define RESETS_RESET_DONE_USBCTRL_BITS _u(0x01000000)
+#define RESETS_RESET_DONE_USBCTRL_MSB _u(24)
+#define RESETS_RESET_DONE_USBCTRL_LSB _u(24)
#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_UART1
// Description : None
-#define RESETS_RESET_DONE_UART1_RESET _U(0x0)
-#define RESETS_RESET_DONE_UART1_BITS _U(0x00800000)
-#define RESETS_RESET_DONE_UART1_MSB _U(23)
-#define RESETS_RESET_DONE_UART1_LSB _U(23)
+#define RESETS_RESET_DONE_UART1_RESET _u(0x0)
+#define RESETS_RESET_DONE_UART1_BITS _u(0x00800000)
+#define RESETS_RESET_DONE_UART1_MSB _u(23)
+#define RESETS_RESET_DONE_UART1_LSB _u(23)
#define RESETS_RESET_DONE_UART1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_UART0
// Description : None
-#define RESETS_RESET_DONE_UART0_RESET _U(0x0)
-#define RESETS_RESET_DONE_UART0_BITS _U(0x00400000)
-#define RESETS_RESET_DONE_UART0_MSB _U(22)
-#define RESETS_RESET_DONE_UART0_LSB _U(22)
+#define RESETS_RESET_DONE_UART0_RESET _u(0x0)
+#define RESETS_RESET_DONE_UART0_BITS _u(0x00400000)
+#define RESETS_RESET_DONE_UART0_MSB _u(22)
+#define RESETS_RESET_DONE_UART0_LSB _u(22)
#define RESETS_RESET_DONE_UART0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TIMER
// Description : None
-#define RESETS_RESET_DONE_TIMER_RESET _U(0x0)
-#define RESETS_RESET_DONE_TIMER_BITS _U(0x00200000)
-#define RESETS_RESET_DONE_TIMER_MSB _U(21)
-#define RESETS_RESET_DONE_TIMER_LSB _U(21)
+#define RESETS_RESET_DONE_TIMER_RESET _u(0x0)
+#define RESETS_RESET_DONE_TIMER_BITS _u(0x00200000)
+#define RESETS_RESET_DONE_TIMER_MSB _u(21)
+#define RESETS_RESET_DONE_TIMER_LSB _u(21)
#define RESETS_RESET_DONE_TIMER_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TBMAN
// Description : None
-#define RESETS_RESET_DONE_TBMAN_RESET _U(0x0)
-#define RESETS_RESET_DONE_TBMAN_BITS _U(0x00100000)
-#define RESETS_RESET_DONE_TBMAN_MSB _U(20)
-#define RESETS_RESET_DONE_TBMAN_LSB _U(20)
+#define RESETS_RESET_DONE_TBMAN_RESET _u(0x0)
+#define RESETS_RESET_DONE_TBMAN_BITS _u(0x00100000)
+#define RESETS_RESET_DONE_TBMAN_MSB _u(20)
+#define RESETS_RESET_DONE_TBMAN_LSB _u(20)
#define RESETS_RESET_DONE_TBMAN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SYSINFO
// Description : None
-#define RESETS_RESET_DONE_SYSINFO_RESET _U(0x0)
-#define RESETS_RESET_DONE_SYSINFO_BITS _U(0x00080000)
-#define RESETS_RESET_DONE_SYSINFO_MSB _U(19)
-#define RESETS_RESET_DONE_SYSINFO_LSB _U(19)
+#define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0)
+#define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00080000)
+#define RESETS_RESET_DONE_SYSINFO_MSB _u(19)
+#define RESETS_RESET_DONE_SYSINFO_LSB _u(19)
#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SYSCFG
// Description : None
-#define RESETS_RESET_DONE_SYSCFG_RESET _U(0x0)
-#define RESETS_RESET_DONE_SYSCFG_BITS _U(0x00040000)
-#define RESETS_RESET_DONE_SYSCFG_MSB _U(18)
-#define RESETS_RESET_DONE_SYSCFG_LSB _U(18)
+#define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0)
+#define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00040000)
+#define RESETS_RESET_DONE_SYSCFG_MSB _u(18)
+#define RESETS_RESET_DONE_SYSCFG_LSB _u(18)
#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SPI1
// Description : None
-#define RESETS_RESET_DONE_SPI1_RESET _U(0x0)
-#define RESETS_RESET_DONE_SPI1_BITS _U(0x00020000)
-#define RESETS_RESET_DONE_SPI1_MSB _U(17)
-#define RESETS_RESET_DONE_SPI1_LSB _U(17)
+#define RESETS_RESET_DONE_SPI1_RESET _u(0x0)
+#define RESETS_RESET_DONE_SPI1_BITS _u(0x00020000)
+#define RESETS_RESET_DONE_SPI1_MSB _u(17)
+#define RESETS_RESET_DONE_SPI1_LSB _u(17)
#define RESETS_RESET_DONE_SPI1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SPI0
// Description : None
-#define RESETS_RESET_DONE_SPI0_RESET _U(0x0)
-#define RESETS_RESET_DONE_SPI0_BITS _U(0x00010000)
-#define RESETS_RESET_DONE_SPI0_MSB _U(16)
-#define RESETS_RESET_DONE_SPI0_LSB _U(16)
+#define RESETS_RESET_DONE_SPI0_RESET _u(0x0)
+#define RESETS_RESET_DONE_SPI0_BITS _u(0x00010000)
+#define RESETS_RESET_DONE_SPI0_MSB _u(16)
+#define RESETS_RESET_DONE_SPI0_LSB _u(16)
#define RESETS_RESET_DONE_SPI0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_RTC
// Description : None
-#define RESETS_RESET_DONE_RTC_RESET _U(0x0)
-#define RESETS_RESET_DONE_RTC_BITS _U(0x00008000)
-#define RESETS_RESET_DONE_RTC_MSB _U(15)
-#define RESETS_RESET_DONE_RTC_LSB _U(15)
+#define RESETS_RESET_DONE_RTC_RESET _u(0x0)
+#define RESETS_RESET_DONE_RTC_BITS _u(0x00008000)
+#define RESETS_RESET_DONE_RTC_MSB _u(15)
+#define RESETS_RESET_DONE_RTC_LSB _u(15)
#define RESETS_RESET_DONE_RTC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PWM
// Description : None
-#define RESETS_RESET_DONE_PWM_RESET _U(0x0)
-#define RESETS_RESET_DONE_PWM_BITS _U(0x00004000)
-#define RESETS_RESET_DONE_PWM_MSB _U(14)
-#define RESETS_RESET_DONE_PWM_LSB _U(14)
+#define RESETS_RESET_DONE_PWM_RESET _u(0x0)
+#define RESETS_RESET_DONE_PWM_BITS _u(0x00004000)
+#define RESETS_RESET_DONE_PWM_MSB _u(14)
+#define RESETS_RESET_DONE_PWM_LSB _u(14)
#define RESETS_RESET_DONE_PWM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PLL_USB
// Description : None
-#define RESETS_RESET_DONE_PLL_USB_RESET _U(0x0)
-#define RESETS_RESET_DONE_PLL_USB_BITS _U(0x00002000)
-#define RESETS_RESET_DONE_PLL_USB_MSB _U(13)
-#define RESETS_RESET_DONE_PLL_USB_LSB _U(13)
+#define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0)
+#define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00002000)
+#define RESETS_RESET_DONE_PLL_USB_MSB _u(13)
+#define RESETS_RESET_DONE_PLL_USB_LSB _u(13)
#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PLL_SYS
// Description : None
-#define RESETS_RESET_DONE_PLL_SYS_RESET _U(0x0)
-#define RESETS_RESET_DONE_PLL_SYS_BITS _U(0x00001000)
-#define RESETS_RESET_DONE_PLL_SYS_MSB _U(12)
-#define RESETS_RESET_DONE_PLL_SYS_LSB _U(12)
+#define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0)
+#define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00001000)
+#define RESETS_RESET_DONE_PLL_SYS_MSB _u(12)
+#define RESETS_RESET_DONE_PLL_SYS_LSB _u(12)
#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO1
// Description : None
-#define RESETS_RESET_DONE_PIO1_RESET _U(0x0)
-#define RESETS_RESET_DONE_PIO1_BITS _U(0x00000800)
-#define RESETS_RESET_DONE_PIO1_MSB _U(11)
-#define RESETS_RESET_DONE_PIO1_LSB _U(11)
+#define RESETS_RESET_DONE_PIO1_RESET _u(0x0)
+#define RESETS_RESET_DONE_PIO1_BITS _u(0x00000800)
+#define RESETS_RESET_DONE_PIO1_MSB _u(11)
+#define RESETS_RESET_DONE_PIO1_LSB _u(11)
#define RESETS_RESET_DONE_PIO1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO0
// Description : None
-#define RESETS_RESET_DONE_PIO0_RESET _U(0x0)
-#define RESETS_RESET_DONE_PIO0_BITS _U(0x00000400)
-#define RESETS_RESET_DONE_PIO0_MSB _U(10)
-#define RESETS_RESET_DONE_PIO0_LSB _U(10)
+#define RESETS_RESET_DONE_PIO0_RESET _u(0x0)
+#define RESETS_RESET_DONE_PIO0_BITS _u(0x00000400)
+#define RESETS_RESET_DONE_PIO0_MSB _u(10)
+#define RESETS_RESET_DONE_PIO0_LSB _u(10)
#define RESETS_RESET_DONE_PIO0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PADS_QSPI
// Description : None
-#define RESETS_RESET_DONE_PADS_QSPI_RESET _U(0x0)
-#define RESETS_RESET_DONE_PADS_QSPI_BITS _U(0x00000200)
-#define RESETS_RESET_DONE_PADS_QSPI_MSB _U(9)
-#define RESETS_RESET_DONE_PADS_QSPI_LSB _U(9)
+#define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0)
+#define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000200)
+#define RESETS_RESET_DONE_PADS_QSPI_MSB _u(9)
+#define RESETS_RESET_DONE_PADS_QSPI_LSB _u(9)
#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PADS_BANK0
// Description : None
-#define RESETS_RESET_DONE_PADS_BANK0_RESET _U(0x0)
-#define RESETS_RESET_DONE_PADS_BANK0_BITS _U(0x00000100)
-#define RESETS_RESET_DONE_PADS_BANK0_MSB _U(8)
-#define RESETS_RESET_DONE_PADS_BANK0_LSB _U(8)
+#define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0)
+#define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000100)
+#define RESETS_RESET_DONE_PADS_BANK0_MSB _u(8)
+#define RESETS_RESET_DONE_PADS_BANK0_LSB _u(8)
#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_JTAG
// Description : None
-#define RESETS_RESET_DONE_JTAG_RESET _U(0x0)
-#define RESETS_RESET_DONE_JTAG_BITS _U(0x00000080)
-#define RESETS_RESET_DONE_JTAG_MSB _U(7)
-#define RESETS_RESET_DONE_JTAG_LSB _U(7)
+#define RESETS_RESET_DONE_JTAG_RESET _u(0x0)
+#define RESETS_RESET_DONE_JTAG_BITS _u(0x00000080)
+#define RESETS_RESET_DONE_JTAG_MSB _u(7)
+#define RESETS_RESET_DONE_JTAG_LSB _u(7)
#define RESETS_RESET_DONE_JTAG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_IO_QSPI
// Description : None
-#define RESETS_RESET_DONE_IO_QSPI_RESET _U(0x0)
-#define RESETS_RESET_DONE_IO_QSPI_BITS _U(0x00000040)
-#define RESETS_RESET_DONE_IO_QSPI_MSB _U(6)
-#define RESETS_RESET_DONE_IO_QSPI_LSB _U(6)
+#define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0)
+#define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000040)
+#define RESETS_RESET_DONE_IO_QSPI_MSB _u(6)
+#define RESETS_RESET_DONE_IO_QSPI_LSB _u(6)
#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_IO_BANK0
// Description : None
-#define RESETS_RESET_DONE_IO_BANK0_RESET _U(0x0)
-#define RESETS_RESET_DONE_IO_BANK0_BITS _U(0x00000020)
-#define RESETS_RESET_DONE_IO_BANK0_MSB _U(5)
-#define RESETS_RESET_DONE_IO_BANK0_LSB _U(5)
+#define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0)
+#define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000020)
+#define RESETS_RESET_DONE_IO_BANK0_MSB _u(5)
+#define RESETS_RESET_DONE_IO_BANK0_LSB _u(5)
#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_I2C1
// Description : None
-#define RESETS_RESET_DONE_I2C1_RESET _U(0x0)
-#define RESETS_RESET_DONE_I2C1_BITS _U(0x00000010)
-#define RESETS_RESET_DONE_I2C1_MSB _U(4)
-#define RESETS_RESET_DONE_I2C1_LSB _U(4)
+#define RESETS_RESET_DONE_I2C1_RESET _u(0x0)
+#define RESETS_RESET_DONE_I2C1_BITS _u(0x00000010)
+#define RESETS_RESET_DONE_I2C1_MSB _u(4)
+#define RESETS_RESET_DONE_I2C1_LSB _u(4)
#define RESETS_RESET_DONE_I2C1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_I2C0
// Description : None
-#define RESETS_RESET_DONE_I2C0_RESET _U(0x0)
-#define RESETS_RESET_DONE_I2C0_BITS _U(0x00000008)
-#define RESETS_RESET_DONE_I2C0_MSB _U(3)
-#define RESETS_RESET_DONE_I2C0_LSB _U(3)
+#define RESETS_RESET_DONE_I2C0_RESET _u(0x0)
+#define RESETS_RESET_DONE_I2C0_BITS _u(0x00000008)
+#define RESETS_RESET_DONE_I2C0_MSB _u(3)
+#define RESETS_RESET_DONE_I2C0_LSB _u(3)
#define RESETS_RESET_DONE_I2C0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_DMA
// Description : None
-#define RESETS_RESET_DONE_DMA_RESET _U(0x0)
-#define RESETS_RESET_DONE_DMA_BITS _U(0x00000004)
-#define RESETS_RESET_DONE_DMA_MSB _U(2)
-#define RESETS_RESET_DONE_DMA_LSB _U(2)
+#define RESETS_RESET_DONE_DMA_RESET _u(0x0)
+#define RESETS_RESET_DONE_DMA_BITS _u(0x00000004)
+#define RESETS_RESET_DONE_DMA_MSB _u(2)
+#define RESETS_RESET_DONE_DMA_LSB _u(2)
#define RESETS_RESET_DONE_DMA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_BUSCTRL
// Description : None
-#define RESETS_RESET_DONE_BUSCTRL_RESET _U(0x0)
-#define RESETS_RESET_DONE_BUSCTRL_BITS _U(0x00000002)
-#define RESETS_RESET_DONE_BUSCTRL_MSB _U(1)
-#define RESETS_RESET_DONE_BUSCTRL_LSB _U(1)
+#define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0)
+#define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002)
+#define RESETS_RESET_DONE_BUSCTRL_MSB _u(1)
+#define RESETS_RESET_DONE_BUSCTRL_LSB _u(1)
#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_ADC
// Description : None
-#define RESETS_RESET_DONE_ADC_RESET _U(0x0)
-#define RESETS_RESET_DONE_ADC_BITS _U(0x00000001)
-#define RESETS_RESET_DONE_ADC_MSB _U(0)
-#define RESETS_RESET_DONE_ADC_LSB _U(0)
+#define RESETS_RESET_DONE_ADC_RESET _u(0x0)
+#define RESETS_RESET_DONE_ADC_BITS _u(0x00000001)
+#define RESETS_RESET_DONE_ADC_MSB _u(0)
+#define RESETS_RESET_DONE_ADC_LSB _u(0)
#define RESETS_RESET_DONE_ADC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_RESETS_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/rosc.h b/src/rp2040/hardware_regs/include/hardware/regs/rosc.h
index ba8930f..694f749 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/rosc.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/rosc.h
@@ -14,9 +14,9 @@
// =============================================================================
// Register : ROSC_CTRL
// Description : Ring Oscillator control
-#define ROSC_CTRL_OFFSET _U(0x00000000)
-#define ROSC_CTRL_BITS _U(0x00ffffff)
-#define ROSC_CTRL_RESET _U(0x00000aa0)
+#define ROSC_CTRL_OFFSET _u(0x00000000)
+#define ROSC_CTRL_BITS _u(0x00ffffff)
+#define ROSC_CTRL_RESET _u(0x00000aa0)
// -----------------------------------------------------------------------------
// Field : ROSC_CTRL_ENABLE
// Description : On power-up this field is initialised to ENABLE
@@ -28,12 +28,12 @@
// 0xd1e -> DISABLE
// 0xfab -> ENABLE
#define ROSC_CTRL_ENABLE_RESET "-"
-#define ROSC_CTRL_ENABLE_BITS _U(0x00fff000)
-#define ROSC_CTRL_ENABLE_MSB _U(23)
-#define ROSC_CTRL_ENABLE_LSB _U(12)
+#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000)
+#define ROSC_CTRL_ENABLE_MSB _u(23)
+#define ROSC_CTRL_ENABLE_LSB _u(12)
#define ROSC_CTRL_ENABLE_ACCESS "RW"
-#define ROSC_CTRL_ENABLE_VALUE_DISABLE _U(0xd1e)
-#define ROSC_CTRL_ENABLE_VALUE_ENABLE _U(0xfab)
+#define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
+#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
// -----------------------------------------------------------------------------
// Field : ROSC_CTRL_FREQ_RANGE
// Description : Controls the number of delay stages in the ROSC ring
@@ -51,15 +51,15 @@
// 0xfa5 -> MEDIUM
// 0xfa7 -> HIGH
// 0xfa6 -> TOOHIGH
-#define ROSC_CTRL_FREQ_RANGE_RESET _U(0xaa0)
-#define ROSC_CTRL_FREQ_RANGE_BITS _U(0x00000fff)
-#define ROSC_CTRL_FREQ_RANGE_MSB _U(11)
-#define ROSC_CTRL_FREQ_RANGE_LSB _U(0)
+#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0)
+#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff)
+#define ROSC_CTRL_FREQ_RANGE_MSB _u(11)
+#define ROSC_CTRL_FREQ_RANGE_LSB _u(0)
#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW"
-#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _U(0xfa4)
-#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _U(0xfa5)
-#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _U(0xfa7)
-#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _U(0xfa6)
+#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4)
+#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5)
+#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7)
+#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6)
// =============================================================================
// Register : ROSC_FREQA
// Description : The FREQA & FREQB registers control the frequency by
@@ -72,100 +72,100 @@
// 1 bit set doubles the drive strength
// 2 bits set triples drive strength
// 3 bits set quadruples drive strength
-#define ROSC_FREQA_OFFSET _U(0x00000004)
-#define ROSC_FREQA_BITS _U(0xffff7777)
-#define ROSC_FREQA_RESET _U(0x00000000)
+#define ROSC_FREQA_OFFSET _u(0x00000004)
+#define ROSC_FREQA_BITS _u(0xffff7777)
+#define ROSC_FREQA_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_PASSWD
// Description : Set to 0x9696 to apply the settings
// Any other value in this field will set all drive strengths to 0
// 0x9696 -> PASS
-#define ROSC_FREQA_PASSWD_RESET _U(0x0000)
-#define ROSC_FREQA_PASSWD_BITS _U(0xffff0000)
-#define ROSC_FREQA_PASSWD_MSB _U(31)
-#define ROSC_FREQA_PASSWD_LSB _U(16)
+#define ROSC_FREQA_PASSWD_RESET _u(0x0000)
+#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000)
+#define ROSC_FREQA_PASSWD_MSB _u(31)
+#define ROSC_FREQA_PASSWD_LSB _u(16)
#define ROSC_FREQA_PASSWD_ACCESS "RW"
-#define ROSC_FREQA_PASSWD_VALUE_PASS _U(0x9696)
+#define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS3
// Description : Stage 3 drive strength
-#define ROSC_FREQA_DS3_RESET _U(0x0)
-#define ROSC_FREQA_DS3_BITS _U(0x00007000)
-#define ROSC_FREQA_DS3_MSB _U(14)
-#define ROSC_FREQA_DS3_LSB _U(12)
+#define ROSC_FREQA_DS3_RESET _u(0x0)
+#define ROSC_FREQA_DS3_BITS _u(0x00007000)
+#define ROSC_FREQA_DS3_MSB _u(14)
+#define ROSC_FREQA_DS3_LSB _u(12)
#define ROSC_FREQA_DS3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS2
// Description : Stage 2 drive strength
-#define ROSC_FREQA_DS2_RESET _U(0x0)
-#define ROSC_FREQA_DS2_BITS _U(0x00000700)
-#define ROSC_FREQA_DS2_MSB _U(10)
-#define ROSC_FREQA_DS2_LSB _U(8)
+#define ROSC_FREQA_DS2_RESET _u(0x0)
+#define ROSC_FREQA_DS2_BITS _u(0x00000700)
+#define ROSC_FREQA_DS2_MSB _u(10)
+#define ROSC_FREQA_DS2_LSB _u(8)
#define ROSC_FREQA_DS2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS1
// Description : Stage 1 drive strength
-#define ROSC_FREQA_DS1_RESET _U(0x0)
-#define ROSC_FREQA_DS1_BITS _U(0x00000070)
-#define ROSC_FREQA_DS1_MSB _U(6)
-#define ROSC_FREQA_DS1_LSB _U(4)
+#define ROSC_FREQA_DS1_RESET _u(0x0)
+#define ROSC_FREQA_DS1_BITS _u(0x00000070)
+#define ROSC_FREQA_DS1_MSB _u(6)
+#define ROSC_FREQA_DS1_LSB _u(4)
#define ROSC_FREQA_DS1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS0
// Description : Stage 0 drive strength
-#define ROSC_FREQA_DS0_RESET _U(0x0)
-#define ROSC_FREQA_DS0_BITS _U(0x00000007)
-#define ROSC_FREQA_DS0_MSB _U(2)
-#define ROSC_FREQA_DS0_LSB _U(0)
+#define ROSC_FREQA_DS0_RESET _u(0x0)
+#define ROSC_FREQA_DS0_BITS _u(0x00000007)
+#define ROSC_FREQA_DS0_MSB _u(2)
+#define ROSC_FREQA_DS0_LSB _u(0)
#define ROSC_FREQA_DS0_ACCESS "RW"
// =============================================================================
// Register : ROSC_FREQB
// Description : For a detailed description see freqa register
-#define ROSC_FREQB_OFFSET _U(0x00000008)
-#define ROSC_FREQB_BITS _U(0xffff7777)
-#define ROSC_FREQB_RESET _U(0x00000000)
+#define ROSC_FREQB_OFFSET _u(0x00000008)
+#define ROSC_FREQB_BITS _u(0xffff7777)
+#define ROSC_FREQB_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_PASSWD
// Description : Set to 0x9696 to apply the settings
// Any other value in this field will set all drive strengths to 0
// 0x9696 -> PASS
-#define ROSC_FREQB_PASSWD_RESET _U(0x0000)
-#define ROSC_FREQB_PASSWD_BITS _U(0xffff0000)
-#define ROSC_FREQB_PASSWD_MSB _U(31)
-#define ROSC_FREQB_PASSWD_LSB _U(16)
+#define ROSC_FREQB_PASSWD_RESET _u(0x0000)
+#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000)
+#define ROSC_FREQB_PASSWD_MSB _u(31)
+#define ROSC_FREQB_PASSWD_LSB _u(16)
#define ROSC_FREQB_PASSWD_ACCESS "RW"
-#define ROSC_FREQB_PASSWD_VALUE_PASS _U(0x9696)
+#define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS7
// Description : Stage 7 drive strength
-#define ROSC_FREQB_DS7_RESET _U(0x0)
-#define ROSC_FREQB_DS7_BITS _U(0x00007000)
-#define ROSC_FREQB_DS7_MSB _U(14)
-#define ROSC_FREQB_DS7_LSB _U(12)
+#define ROSC_FREQB_DS7_RESET _u(0x0)
+#define ROSC_FREQB_DS7_BITS _u(0x00007000)
+#define ROSC_FREQB_DS7_MSB _u(14)
+#define ROSC_FREQB_DS7_LSB _u(12)
#define ROSC_FREQB_DS7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS6
// Description : Stage 6 drive strength
-#define ROSC_FREQB_DS6_RESET _U(0x0)
-#define ROSC_FREQB_DS6_BITS _U(0x00000700)
-#define ROSC_FREQB_DS6_MSB _U(10)
-#define ROSC_FREQB_DS6_LSB _U(8)
+#define ROSC_FREQB_DS6_RESET _u(0x0)
+#define ROSC_FREQB_DS6_BITS _u(0x00000700)
+#define ROSC_FREQB_DS6_MSB _u(10)
+#define ROSC_FREQB_DS6_LSB _u(8)
#define ROSC_FREQB_DS6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS5
// Description : Stage 5 drive strength
-#define ROSC_FREQB_DS5_RESET _U(0x0)
-#define ROSC_FREQB_DS5_BITS _U(0x00000070)
-#define ROSC_FREQB_DS5_MSB _U(6)
-#define ROSC_FREQB_DS5_LSB _U(4)
+#define ROSC_FREQB_DS5_RESET _u(0x0)
+#define ROSC_FREQB_DS5_BITS _u(0x00000070)
+#define ROSC_FREQB_DS5_MSB _u(6)
+#define ROSC_FREQB_DS5_LSB _u(4)
#define ROSC_FREQB_DS5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS4
// Description : Stage 4 drive strength
-#define ROSC_FREQB_DS4_RESET _U(0x0)
-#define ROSC_FREQB_DS4_BITS _U(0x00000007)
-#define ROSC_FREQB_DS4_MSB _U(2)
-#define ROSC_FREQB_DS4_LSB _U(0)
+#define ROSC_FREQB_DS4_RESET _u(0x0)
+#define ROSC_FREQB_DS4_BITS _u(0x00000007)
+#define ROSC_FREQB_DS4_MSB _u(2)
+#define ROSC_FREQB_DS4_LSB _u(0)
#define ROSC_FREQB_DS4_ACCESS "RW"
// =============================================================================
// Register : ROSC_DORMANT
@@ -176,14 +176,14 @@
// Warning: setup the irq before selecting dormant mode
// 0x636f6d61 -> DORMANT
// 0x77616b65 -> WAKE
-#define ROSC_DORMANT_OFFSET _U(0x0000000c)
-#define ROSC_DORMANT_BITS _U(0xffffffff)
+#define ROSC_DORMANT_OFFSET _u(0x0000000c)
+#define ROSC_DORMANT_BITS _u(0xffffffff)
#define ROSC_DORMANT_RESET "-"
-#define ROSC_DORMANT_MSB _U(31)
-#define ROSC_DORMANT_LSB _U(0)
+#define ROSC_DORMANT_MSB _u(31)
+#define ROSC_DORMANT_LSB _u(0)
#define ROSC_DORMANT_ACCESS "RW"
-#define ROSC_DORMANT_VALUE_DORMANT _U(0x636f6d61)
-#define ROSC_DORMANT_VALUE_WAKE _U(0x77616b65)
+#define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
+#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65)
// =============================================================================
// Register : ROSC_DIV
// Description : Controls the output divider
@@ -193,107 +193,107 @@
// any other value sets div=0 and therefore divides by 32
// this register resets to div=16
// 0xaa0 -> PASS
-#define ROSC_DIV_OFFSET _U(0x00000010)
-#define ROSC_DIV_BITS _U(0x00000fff)
+#define ROSC_DIV_OFFSET _u(0x00000010)
+#define ROSC_DIV_BITS _u(0x00000fff)
#define ROSC_DIV_RESET "-"
-#define ROSC_DIV_MSB _U(11)
-#define ROSC_DIV_LSB _U(0)
+#define ROSC_DIV_MSB _u(11)
+#define ROSC_DIV_LSB _u(0)
#define ROSC_DIV_ACCESS "RW"
-#define ROSC_DIV_VALUE_PASS _U(0xaa0)
+#define ROSC_DIV_VALUE_PASS _u(0xaa0)
// =============================================================================
// Register : ROSC_PHASE
// Description : Controls the phase shifted output
-#define ROSC_PHASE_OFFSET _U(0x00000014)
-#define ROSC_PHASE_BITS _U(0x00000fff)
-#define ROSC_PHASE_RESET _U(0x00000008)
+#define ROSC_PHASE_OFFSET _u(0x00000014)
+#define ROSC_PHASE_BITS _u(0x00000fff)
+#define ROSC_PHASE_RESET _u(0x00000008)
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_PASSWD
// Description : set to 0xaa0
// any other value enables the output with shift=0
-#define ROSC_PHASE_PASSWD_RESET _U(0x00)
-#define ROSC_PHASE_PASSWD_BITS _U(0x00000ff0)
-#define ROSC_PHASE_PASSWD_MSB _U(11)
-#define ROSC_PHASE_PASSWD_LSB _U(4)
+#define ROSC_PHASE_PASSWD_RESET _u(0x00)
+#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0)
+#define ROSC_PHASE_PASSWD_MSB _u(11)
+#define ROSC_PHASE_PASSWD_LSB _u(4)
#define ROSC_PHASE_PASSWD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_ENABLE
// Description : enable the phase-shifted output
// this can be changed on-the-fly
-#define ROSC_PHASE_ENABLE_RESET _U(0x1)
-#define ROSC_PHASE_ENABLE_BITS _U(0x00000008)
-#define ROSC_PHASE_ENABLE_MSB _U(3)
-#define ROSC_PHASE_ENABLE_LSB _U(3)
+#define ROSC_PHASE_ENABLE_RESET _u(0x1)
+#define ROSC_PHASE_ENABLE_BITS _u(0x00000008)
+#define ROSC_PHASE_ENABLE_MSB _u(3)
+#define ROSC_PHASE_ENABLE_LSB _u(3)
#define ROSC_PHASE_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_FLIP
// Description : invert the phase-shifted output
// this is ignored when div=1
-#define ROSC_PHASE_FLIP_RESET _U(0x0)
-#define ROSC_PHASE_FLIP_BITS _U(0x00000004)
-#define ROSC_PHASE_FLIP_MSB _U(2)
-#define ROSC_PHASE_FLIP_LSB _U(2)
+#define ROSC_PHASE_FLIP_RESET _u(0x0)
+#define ROSC_PHASE_FLIP_BITS _u(0x00000004)
+#define ROSC_PHASE_FLIP_MSB _u(2)
+#define ROSC_PHASE_FLIP_LSB _u(2)
#define ROSC_PHASE_FLIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_SHIFT
// Description : phase shift the phase-shifted output by SHIFT input clocks
// this can be changed on-the-fly
// must be set to 0 before setting div=1
-#define ROSC_PHASE_SHIFT_RESET _U(0x0)
-#define ROSC_PHASE_SHIFT_BITS _U(0x00000003)
-#define ROSC_PHASE_SHIFT_MSB _U(1)
-#define ROSC_PHASE_SHIFT_LSB _U(0)
+#define ROSC_PHASE_SHIFT_RESET _u(0x0)
+#define ROSC_PHASE_SHIFT_BITS _u(0x00000003)
+#define ROSC_PHASE_SHIFT_MSB _u(1)
+#define ROSC_PHASE_SHIFT_LSB _u(0)
#define ROSC_PHASE_SHIFT_ACCESS "RW"
// =============================================================================
// Register : ROSC_STATUS
// Description : Ring Oscillator Status
-#define ROSC_STATUS_OFFSET _U(0x00000018)
-#define ROSC_STATUS_BITS _U(0x81011000)
-#define ROSC_STATUS_RESET _U(0x00000000)
+#define ROSC_STATUS_OFFSET _u(0x00000018)
+#define ROSC_STATUS_BITS _u(0x81011000)
+#define ROSC_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_STABLE
// Description : Oscillator is running and stable
-#define ROSC_STATUS_STABLE_RESET _U(0x0)
-#define ROSC_STATUS_STABLE_BITS _U(0x80000000)
-#define ROSC_STATUS_STABLE_MSB _U(31)
-#define ROSC_STATUS_STABLE_LSB _U(31)
+#define ROSC_STATUS_STABLE_RESET _u(0x0)
+#define ROSC_STATUS_STABLE_BITS _u(0x80000000)
+#define ROSC_STATUS_STABLE_MSB _u(31)
+#define ROSC_STATUS_STABLE_LSB _u(31)
#define ROSC_STATUS_STABLE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_BADWRITE
// Description : An invalid value has been written to CTRL_ENABLE or
// CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT
-#define ROSC_STATUS_BADWRITE_RESET _U(0x0)
-#define ROSC_STATUS_BADWRITE_BITS _U(0x01000000)
-#define ROSC_STATUS_BADWRITE_MSB _U(24)
-#define ROSC_STATUS_BADWRITE_LSB _U(24)
+#define ROSC_STATUS_BADWRITE_RESET _u(0x0)
+#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000)
+#define ROSC_STATUS_BADWRITE_MSB _u(24)
+#define ROSC_STATUS_BADWRITE_LSB _u(24)
#define ROSC_STATUS_BADWRITE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_DIV_RUNNING
// Description : post-divider is running
// this resets to 0 but transitions to 1 during chip startup
#define ROSC_STATUS_DIV_RUNNING_RESET "-"
-#define ROSC_STATUS_DIV_RUNNING_BITS _U(0x00010000)
-#define ROSC_STATUS_DIV_RUNNING_MSB _U(16)
-#define ROSC_STATUS_DIV_RUNNING_LSB _U(16)
+#define ROSC_STATUS_DIV_RUNNING_BITS _u(0x00010000)
+#define ROSC_STATUS_DIV_RUNNING_MSB _u(16)
+#define ROSC_STATUS_DIV_RUNNING_LSB _u(16)
#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_ENABLED
// Description : Oscillator is enabled but not necessarily running and stable
// this resets to 0 but transitions to 1 during chip startup
#define ROSC_STATUS_ENABLED_RESET "-"
-#define ROSC_STATUS_ENABLED_BITS _U(0x00001000)
-#define ROSC_STATUS_ENABLED_MSB _U(12)
-#define ROSC_STATUS_ENABLED_LSB _U(12)
+#define ROSC_STATUS_ENABLED_BITS _u(0x00001000)
+#define ROSC_STATUS_ENABLED_MSB _u(12)
+#define ROSC_STATUS_ENABLED_LSB _u(12)
#define ROSC_STATUS_ENABLED_ACCESS "RO"
// =============================================================================
// Register : ROSC_RANDOMBIT
// Description : This just reads the state of the oscillator output so
// randomness is compromised if the ring oscillator is stopped or
// run at a harmonic of the bus frequency
-#define ROSC_RANDOMBIT_OFFSET _U(0x0000001c)
-#define ROSC_RANDOMBIT_BITS _U(0x00000001)
-#define ROSC_RANDOMBIT_RESET _U(0x00000001)
-#define ROSC_RANDOMBIT_MSB _U(0)
-#define ROSC_RANDOMBIT_LSB _U(0)
+#define ROSC_RANDOMBIT_OFFSET _u(0x0000001c)
+#define ROSC_RANDOMBIT_BITS _u(0x00000001)
+#define ROSC_RANDOMBIT_RESET _u(0x00000001)
+#define ROSC_RANDOMBIT_MSB _u(0)
+#define ROSC_RANDOMBIT_LSB _u(0)
#define ROSC_RANDOMBIT_ACCESS "RO"
// =============================================================================
// Register : ROSC_COUNT
@@ -302,11 +302,11 @@
// To start the counter write a non-zero value.
// Can be used for short software pauses when setting up time
// sensitive hardware.
-#define ROSC_COUNT_OFFSET _U(0x00000020)
-#define ROSC_COUNT_BITS _U(0x000000ff)
-#define ROSC_COUNT_RESET _U(0x00000000)
-#define ROSC_COUNT_MSB _U(7)
-#define ROSC_COUNT_LSB _U(0)
+#define ROSC_COUNT_OFFSET _u(0x00000020)
+#define ROSC_COUNT_BITS _u(0x000000ff)
+#define ROSC_COUNT_RESET _u(0x00000000)
+#define ROSC_COUNT_MSB _u(7)
+#define ROSC_COUNT_LSB _u(0)
#define ROSC_COUNT_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_ROSC_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/rtc.h b/src/rp2040/hardware_regs/include/hardware/regs/rtc.h
index 925c6e5..7d62c9d 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/rtc.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/rtc.h
@@ -15,384 +15,384 @@
// Register : RTC_CLKDIV_M1
// Description : Divider minus 1 for the 1 second counter. Safe to change the
// value when RTC is not enabled.
-#define RTC_CLKDIV_M1_OFFSET _U(0x00000000)
-#define RTC_CLKDIV_M1_BITS _U(0x0000ffff)
-#define RTC_CLKDIV_M1_RESET _U(0x00000000)
-#define RTC_CLKDIV_M1_MSB _U(15)
-#define RTC_CLKDIV_M1_LSB _U(0)
+#define RTC_CLKDIV_M1_OFFSET _u(0x00000000)
+#define RTC_CLKDIV_M1_BITS _u(0x0000ffff)
+#define RTC_CLKDIV_M1_RESET _u(0x00000000)
+#define RTC_CLKDIV_M1_MSB _u(15)
+#define RTC_CLKDIV_M1_LSB _u(0)
#define RTC_CLKDIV_M1_ACCESS "RW"
// =============================================================================
// Register : RTC_SETUP_0
// Description : RTC setup register 0
-#define RTC_SETUP_0_OFFSET _U(0x00000004)
-#define RTC_SETUP_0_BITS _U(0x00ffff1f)
-#define RTC_SETUP_0_RESET _U(0x00000000)
+#define RTC_SETUP_0_OFFSET _u(0x00000004)
+#define RTC_SETUP_0_BITS _u(0x00ffff1f)
+#define RTC_SETUP_0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_0_YEAR
// Description : Year
-#define RTC_SETUP_0_YEAR_RESET _U(0x000)
-#define RTC_SETUP_0_YEAR_BITS _U(0x00fff000)
-#define RTC_SETUP_0_YEAR_MSB _U(23)
-#define RTC_SETUP_0_YEAR_LSB _U(12)
+#define RTC_SETUP_0_YEAR_RESET _u(0x000)
+#define RTC_SETUP_0_YEAR_BITS _u(0x00fff000)
+#define RTC_SETUP_0_YEAR_MSB _u(23)
+#define RTC_SETUP_0_YEAR_LSB _u(12)
#define RTC_SETUP_0_YEAR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_0_MONTH
// Description : Month (1..12)
-#define RTC_SETUP_0_MONTH_RESET _U(0x0)
-#define RTC_SETUP_0_MONTH_BITS _U(0x00000f00)
-#define RTC_SETUP_0_MONTH_MSB _U(11)
-#define RTC_SETUP_0_MONTH_LSB _U(8)
+#define RTC_SETUP_0_MONTH_RESET _u(0x0)
+#define RTC_SETUP_0_MONTH_BITS _u(0x00000f00)
+#define RTC_SETUP_0_MONTH_MSB _u(11)
+#define RTC_SETUP_0_MONTH_LSB _u(8)
#define RTC_SETUP_0_MONTH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_0_DAY
// Description : Day of the month (1..31)
-#define RTC_SETUP_0_DAY_RESET _U(0x00)
-#define RTC_SETUP_0_DAY_BITS _U(0x0000001f)
-#define RTC_SETUP_0_DAY_MSB _U(4)
-#define RTC_SETUP_0_DAY_LSB _U(0)
+#define RTC_SETUP_0_DAY_RESET _u(0x00)
+#define RTC_SETUP_0_DAY_BITS _u(0x0000001f)
+#define RTC_SETUP_0_DAY_MSB _u(4)
+#define RTC_SETUP_0_DAY_LSB _u(0)
#define RTC_SETUP_0_DAY_ACCESS "RW"
// =============================================================================
// Register : RTC_SETUP_1
// Description : RTC setup register 1
-#define RTC_SETUP_1_OFFSET _U(0x00000008)
-#define RTC_SETUP_1_BITS _U(0x071f3f3f)
-#define RTC_SETUP_1_RESET _U(0x00000000)
+#define RTC_SETUP_1_OFFSET _u(0x00000008)
+#define RTC_SETUP_1_BITS _u(0x071f3f3f)
+#define RTC_SETUP_1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_1_DOTW
// Description : Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7
-#define RTC_SETUP_1_DOTW_RESET _U(0x0)
-#define RTC_SETUP_1_DOTW_BITS _U(0x07000000)
-#define RTC_SETUP_1_DOTW_MSB _U(26)
-#define RTC_SETUP_1_DOTW_LSB _U(24)
+#define RTC_SETUP_1_DOTW_RESET _u(0x0)
+#define RTC_SETUP_1_DOTW_BITS _u(0x07000000)
+#define RTC_SETUP_1_DOTW_MSB _u(26)
+#define RTC_SETUP_1_DOTW_LSB _u(24)
#define RTC_SETUP_1_DOTW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_1_HOUR
// Description : Hours
-#define RTC_SETUP_1_HOUR_RESET _U(0x00)
-#define RTC_SETUP_1_HOUR_BITS _U(0x001f0000)
-#define RTC_SETUP_1_HOUR_MSB _U(20)
-#define RTC_SETUP_1_HOUR_LSB _U(16)
+#define RTC_SETUP_1_HOUR_RESET _u(0x00)
+#define RTC_SETUP_1_HOUR_BITS _u(0x001f0000)
+#define RTC_SETUP_1_HOUR_MSB _u(20)
+#define RTC_SETUP_1_HOUR_LSB _u(16)
#define RTC_SETUP_1_HOUR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_1_MIN
// Description : Minutes
-#define RTC_SETUP_1_MIN_RESET _U(0x00)
-#define RTC_SETUP_1_MIN_BITS _U(0x00003f00)
-#define RTC_SETUP_1_MIN_MSB _U(13)
-#define RTC_SETUP_1_MIN_LSB _U(8)
+#define RTC_SETUP_1_MIN_RESET _u(0x00)
+#define RTC_SETUP_1_MIN_BITS _u(0x00003f00)
+#define RTC_SETUP_1_MIN_MSB _u(13)
+#define RTC_SETUP_1_MIN_LSB _u(8)
#define RTC_SETUP_1_MIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_1_SEC
// Description : Seconds
-#define RTC_SETUP_1_SEC_RESET _U(0x00)
-#define RTC_SETUP_1_SEC_BITS _U(0x0000003f)
-#define RTC_SETUP_1_SEC_MSB _U(5)
-#define RTC_SETUP_1_SEC_LSB _U(0)
+#define RTC_SETUP_1_SEC_RESET _u(0x00)
+#define RTC_SETUP_1_SEC_BITS _u(0x0000003f)
+#define RTC_SETUP_1_SEC_MSB _u(5)
+#define RTC_SETUP_1_SEC_LSB _u(0)
#define RTC_SETUP_1_SEC_ACCESS "RW"
// =============================================================================
// Register : RTC_CTRL
// Description : RTC Control and status
-#define RTC_CTRL_OFFSET _U(0x0000000c)
-#define RTC_CTRL_BITS _U(0x00000113)
-#define RTC_CTRL_RESET _U(0x00000000)
+#define RTC_CTRL_OFFSET _u(0x0000000c)
+#define RTC_CTRL_BITS _u(0x00000113)
+#define RTC_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_CTRL_FORCE_NOTLEAPYEAR
// Description : If set, leapyear is forced off.
// Useful for years divisible by 100 but not by 400
-#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET _U(0x0)
-#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS _U(0x00000100)
-#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB _U(8)
-#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB _U(8)
+#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET _u(0x0)
+#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS _u(0x00000100)
+#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB _u(8)
+#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB _u(8)
#define RTC_CTRL_FORCE_NOTLEAPYEAR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_CTRL_LOAD
// Description : Load RTC
-#define RTC_CTRL_LOAD_RESET _U(0x0)
-#define RTC_CTRL_LOAD_BITS _U(0x00000010)
-#define RTC_CTRL_LOAD_MSB _U(4)
-#define RTC_CTRL_LOAD_LSB _U(4)
+#define RTC_CTRL_LOAD_RESET _u(0x0)
+#define RTC_CTRL_LOAD_BITS _u(0x00000010)
+#define RTC_CTRL_LOAD_MSB _u(4)
+#define RTC_CTRL_LOAD_LSB _u(4)
#define RTC_CTRL_LOAD_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : RTC_CTRL_RTC_ACTIVE
// Description : RTC enabled (running)
#define RTC_CTRL_RTC_ACTIVE_RESET "-"
-#define RTC_CTRL_RTC_ACTIVE_BITS _U(0x00000002)
-#define RTC_CTRL_RTC_ACTIVE_MSB _U(1)
-#define RTC_CTRL_RTC_ACTIVE_LSB _U(1)
+#define RTC_CTRL_RTC_ACTIVE_BITS _u(0x00000002)
+#define RTC_CTRL_RTC_ACTIVE_MSB _u(1)
+#define RTC_CTRL_RTC_ACTIVE_LSB _u(1)
#define RTC_CTRL_RTC_ACTIVE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RTC_CTRL_RTC_ENABLE
// Description : Enable RTC
-#define RTC_CTRL_RTC_ENABLE_RESET _U(0x0)
-#define RTC_CTRL_RTC_ENABLE_BITS _U(0x00000001)
-#define RTC_CTRL_RTC_ENABLE_MSB _U(0)
-#define RTC_CTRL_RTC_ENABLE_LSB _U(0)
+#define RTC_CTRL_RTC_ENABLE_RESET _u(0x0)
+#define RTC_CTRL_RTC_ENABLE_BITS _u(0x00000001)
+#define RTC_CTRL_RTC_ENABLE_MSB _u(0)
+#define RTC_CTRL_RTC_ENABLE_LSB _u(0)
#define RTC_CTRL_RTC_ENABLE_ACCESS "RW"
// =============================================================================
// Register : RTC_IRQ_SETUP_0
// Description : Interrupt setup register 0
-#define RTC_IRQ_SETUP_0_OFFSET _U(0x00000010)
-#define RTC_IRQ_SETUP_0_BITS _U(0x37ffff1f)
-#define RTC_IRQ_SETUP_0_RESET _U(0x00000000)
+#define RTC_IRQ_SETUP_0_OFFSET _u(0x00000010)
+#define RTC_IRQ_SETUP_0_BITS _u(0x37ffff1f)
+#define RTC_IRQ_SETUP_0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE
// Description : None
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-"
-#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS _U(0x20000000)
-#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB _U(29)
-#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB _U(29)
+#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS _u(0x20000000)
+#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB _u(29)
+#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB _u(29)
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MATCH_ENA
// Description : Global match enable. Don't change any other value while this
// one is enabled
-#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET _U(0x0)
-#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS _U(0x10000000)
-#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB _U(28)
-#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB _U(28)
+#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET _u(0x0)
+#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS _u(0x10000000)
+#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB _u(28)
+#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB _u(28)
#define RTC_IRQ_SETUP_0_MATCH_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_YEAR_ENA
// Description : Enable year matching
-#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET _U(0x0)
-#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS _U(0x04000000)
-#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB _U(26)
-#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB _U(26)
+#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET _u(0x0)
+#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS _u(0x04000000)
+#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB _u(26)
+#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB _u(26)
#define RTC_IRQ_SETUP_0_YEAR_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MONTH_ENA
// Description : Enable month matching
-#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET _U(0x0)
-#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS _U(0x02000000)
-#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB _U(25)
-#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB _U(25)
+#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET _u(0x0)
+#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS _u(0x02000000)
+#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB _u(25)
+#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB _u(25)
#define RTC_IRQ_SETUP_0_MONTH_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_DAY_ENA
// Description : Enable day matching
-#define RTC_IRQ_SETUP_0_DAY_ENA_RESET _U(0x0)
-#define RTC_IRQ_SETUP_0_DAY_ENA_BITS _U(0x01000000)
-#define RTC_IRQ_SETUP_0_DAY_ENA_MSB _U(24)
-#define RTC_IRQ_SETUP_0_DAY_ENA_LSB _U(24)
+#define RTC_IRQ_SETUP_0_DAY_ENA_RESET _u(0x0)
+#define RTC_IRQ_SETUP_0_DAY_ENA_BITS _u(0x01000000)
+#define RTC_IRQ_SETUP_0_DAY_ENA_MSB _u(24)
+#define RTC_IRQ_SETUP_0_DAY_ENA_LSB _u(24)
#define RTC_IRQ_SETUP_0_DAY_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_YEAR
// Description : Year
-#define RTC_IRQ_SETUP_0_YEAR_RESET _U(0x000)
-#define RTC_IRQ_SETUP_0_YEAR_BITS _U(0x00fff000)
-#define RTC_IRQ_SETUP_0_YEAR_MSB _U(23)
-#define RTC_IRQ_SETUP_0_YEAR_LSB _U(12)
+#define RTC_IRQ_SETUP_0_YEAR_RESET _u(0x000)
+#define RTC_IRQ_SETUP_0_YEAR_BITS _u(0x00fff000)
+#define RTC_IRQ_SETUP_0_YEAR_MSB _u(23)
+#define RTC_IRQ_SETUP_0_YEAR_LSB _u(12)
#define RTC_IRQ_SETUP_0_YEAR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MONTH
// Description : Month (1..12)
-#define RTC_IRQ_SETUP_0_MONTH_RESET _U(0x0)
-#define RTC_IRQ_SETUP_0_MONTH_BITS _U(0x00000f00)
-#define RTC_IRQ_SETUP_0_MONTH_MSB _U(11)
-#define RTC_IRQ_SETUP_0_MONTH_LSB _U(8)
+#define RTC_IRQ_SETUP_0_MONTH_RESET _u(0x0)
+#define RTC_IRQ_SETUP_0_MONTH_BITS _u(0x00000f00)
+#define RTC_IRQ_SETUP_0_MONTH_MSB _u(11)
+#define RTC_IRQ_SETUP_0_MONTH_LSB _u(8)
#define RTC_IRQ_SETUP_0_MONTH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_DAY
// Description : Day of the month (1..31)
-#define RTC_IRQ_SETUP_0_DAY_RESET _U(0x00)
-#define RTC_IRQ_SETUP_0_DAY_BITS _U(0x0000001f)
-#define RTC_IRQ_SETUP_0_DAY_MSB _U(4)
-#define RTC_IRQ_SETUP_0_DAY_LSB _U(0)
+#define RTC_IRQ_SETUP_0_DAY_RESET _u(0x00)
+#define RTC_IRQ_SETUP_0_DAY_BITS _u(0x0000001f)
+#define RTC_IRQ_SETUP_0_DAY_MSB _u(4)
+#define RTC_IRQ_SETUP_0_DAY_LSB _u(0)
#define RTC_IRQ_SETUP_0_DAY_ACCESS "RW"
// =============================================================================
// Register : RTC_IRQ_SETUP_1
// Description : Interrupt setup register 1
-#define RTC_IRQ_SETUP_1_OFFSET _U(0x00000014)
-#define RTC_IRQ_SETUP_1_BITS _U(0xf71f3f3f)
-#define RTC_IRQ_SETUP_1_RESET _U(0x00000000)
+#define RTC_IRQ_SETUP_1_OFFSET _u(0x00000014)
+#define RTC_IRQ_SETUP_1_BITS _u(0xf71f3f3f)
+#define RTC_IRQ_SETUP_1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_DOTW_ENA
// Description : Enable day of the week matching
-#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET _U(0x0)
-#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS _U(0x80000000)
-#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB _U(31)
-#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB _U(31)
+#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET _u(0x0)
+#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS _u(0x80000000)
+#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB _u(31)
+#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB _u(31)
#define RTC_IRQ_SETUP_1_DOTW_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_HOUR_ENA
// Description : Enable hour matching
-#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET _U(0x0)
-#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS _U(0x40000000)
-#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB _U(30)
-#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB _U(30)
+#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET _u(0x0)
+#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS _u(0x40000000)
+#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB _u(30)
+#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB _u(30)
#define RTC_IRQ_SETUP_1_HOUR_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_MIN_ENA
// Description : Enable minute matching
-#define RTC_IRQ_SETUP_1_MIN_ENA_RESET _U(0x0)
-#define RTC_IRQ_SETUP_1_MIN_ENA_BITS _U(0x20000000)
-#define RTC_IRQ_SETUP_1_MIN_ENA_MSB _U(29)
-#define RTC_IRQ_SETUP_1_MIN_ENA_LSB _U(29)
+#define RTC_IRQ_SETUP_1_MIN_ENA_RESET _u(0x0)
+#define RTC_IRQ_SETUP_1_MIN_ENA_BITS _u(0x20000000)
+#define RTC_IRQ_SETUP_1_MIN_ENA_MSB _u(29)
+#define RTC_IRQ_SETUP_1_MIN_ENA_LSB _u(29)
#define RTC_IRQ_SETUP_1_MIN_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_SEC_ENA
// Description : Enable second matching
-#define RTC_IRQ_SETUP_1_SEC_ENA_RESET _U(0x0)
-#define RTC_IRQ_SETUP_1_SEC_ENA_BITS _U(0x10000000)
-#define RTC_IRQ_SETUP_1_SEC_ENA_MSB _U(28)
-#define RTC_IRQ_SETUP_1_SEC_ENA_LSB _U(28)
+#define RTC_IRQ_SETUP_1_SEC_ENA_RESET _u(0x0)
+#define RTC_IRQ_SETUP_1_SEC_ENA_BITS _u(0x10000000)
+#define RTC_IRQ_SETUP_1_SEC_ENA_MSB _u(28)
+#define RTC_IRQ_SETUP_1_SEC_ENA_LSB _u(28)
#define RTC_IRQ_SETUP_1_SEC_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_DOTW
// Description : Day of the week
-#define RTC_IRQ_SETUP_1_DOTW_RESET _U(0x0)
-#define RTC_IRQ_SETUP_1_DOTW_BITS _U(0x07000000)
-#define RTC_IRQ_SETUP_1_DOTW_MSB _U(26)
-#define RTC_IRQ_SETUP_1_DOTW_LSB _U(24)
+#define RTC_IRQ_SETUP_1_DOTW_RESET _u(0x0)
+#define RTC_IRQ_SETUP_1_DOTW_BITS _u(0x07000000)
+#define RTC_IRQ_SETUP_1_DOTW_MSB _u(26)
+#define RTC_IRQ_SETUP_1_DOTW_LSB _u(24)
#define RTC_IRQ_SETUP_1_DOTW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_HOUR
// Description : Hours
-#define RTC_IRQ_SETUP_1_HOUR_RESET _U(0x00)
-#define RTC_IRQ_SETUP_1_HOUR_BITS _U(0x001f0000)
-#define RTC_IRQ_SETUP_1_HOUR_MSB _U(20)
-#define RTC_IRQ_SETUP_1_HOUR_LSB _U(16)
+#define RTC_IRQ_SETUP_1_HOUR_RESET _u(0x00)
+#define RTC_IRQ_SETUP_1_HOUR_BITS _u(0x001f0000)
+#define RTC_IRQ_SETUP_1_HOUR_MSB _u(20)
+#define RTC_IRQ_SETUP_1_HOUR_LSB _u(16)
#define RTC_IRQ_SETUP_1_HOUR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_MIN
// Description : Minutes
-#define RTC_IRQ_SETUP_1_MIN_RESET _U(0x00)
-#define RTC_IRQ_SETUP_1_MIN_BITS _U(0x00003f00)
-#define RTC_IRQ_SETUP_1_MIN_MSB _U(13)
-#define RTC_IRQ_SETUP_1_MIN_LSB _U(8)
+#define RTC_IRQ_SETUP_1_MIN_RESET _u(0x00)
+#define RTC_IRQ_SETUP_1_MIN_BITS _u(0x00003f00)
+#define RTC_IRQ_SETUP_1_MIN_MSB _u(13)
+#define RTC_IRQ_SETUP_1_MIN_LSB _u(8)
#define RTC_IRQ_SETUP_1_MIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_SEC
// Description : Seconds
-#define RTC_IRQ_SETUP_1_SEC_RESET _U(0x00)
-#define RTC_IRQ_SETUP_1_SEC_BITS _U(0x0000003f)
-#define RTC_IRQ_SETUP_1_SEC_MSB _U(5)
-#define RTC_IRQ_SETUP_1_SEC_LSB _U(0)
+#define RTC_IRQ_SETUP_1_SEC_RESET _u(0x00)
+#define RTC_IRQ_SETUP_1_SEC_BITS _u(0x0000003f)
+#define RTC_IRQ_SETUP_1_SEC_MSB _u(5)
+#define RTC_IRQ_SETUP_1_SEC_LSB _u(0)
#define RTC_IRQ_SETUP_1_SEC_ACCESS "RW"
// =============================================================================
// Register : RTC_RTC_1
// Description : RTC register 1.
-#define RTC_RTC_1_OFFSET _U(0x00000018)
-#define RTC_RTC_1_BITS _U(0x00ffff1f)
-#define RTC_RTC_1_RESET _U(0x00000000)
+#define RTC_RTC_1_OFFSET _u(0x00000018)
+#define RTC_RTC_1_BITS _u(0x00ffff1f)
+#define RTC_RTC_1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_RTC_1_YEAR
// Description : Year
#define RTC_RTC_1_YEAR_RESET "-"
-#define RTC_RTC_1_YEAR_BITS _U(0x00fff000)
-#define RTC_RTC_1_YEAR_MSB _U(23)
-#define RTC_RTC_1_YEAR_LSB _U(12)
+#define RTC_RTC_1_YEAR_BITS _u(0x00fff000)
+#define RTC_RTC_1_YEAR_MSB _u(23)
+#define RTC_RTC_1_YEAR_LSB _u(12)
#define RTC_RTC_1_YEAR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_1_MONTH
// Description : Month (1..12)
#define RTC_RTC_1_MONTH_RESET "-"
-#define RTC_RTC_1_MONTH_BITS _U(0x00000f00)
-#define RTC_RTC_1_MONTH_MSB _U(11)
-#define RTC_RTC_1_MONTH_LSB _U(8)
+#define RTC_RTC_1_MONTH_BITS _u(0x00000f00)
+#define RTC_RTC_1_MONTH_MSB _u(11)
+#define RTC_RTC_1_MONTH_LSB _u(8)
#define RTC_RTC_1_MONTH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_1_DAY
// Description : Day of the month (1..31)
#define RTC_RTC_1_DAY_RESET "-"
-#define RTC_RTC_1_DAY_BITS _U(0x0000001f)
-#define RTC_RTC_1_DAY_MSB _U(4)
-#define RTC_RTC_1_DAY_LSB _U(0)
+#define RTC_RTC_1_DAY_BITS _u(0x0000001f)
+#define RTC_RTC_1_DAY_MSB _u(4)
+#define RTC_RTC_1_DAY_LSB _u(0)
#define RTC_RTC_1_DAY_ACCESS "RO"
// =============================================================================
// Register : RTC_RTC_0
// Description : RTC register 0
// Read this before RTC 1!
-#define RTC_RTC_0_OFFSET _U(0x0000001c)
-#define RTC_RTC_0_BITS _U(0x071f3f3f)
-#define RTC_RTC_0_RESET _U(0x00000000)
+#define RTC_RTC_0_OFFSET _u(0x0000001c)
+#define RTC_RTC_0_BITS _u(0x071f3f3f)
+#define RTC_RTC_0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_RTC_0_DOTW
// Description : Day of the week
#define RTC_RTC_0_DOTW_RESET "-"
-#define RTC_RTC_0_DOTW_BITS _U(0x07000000)
-#define RTC_RTC_0_DOTW_MSB _U(26)
-#define RTC_RTC_0_DOTW_LSB _U(24)
+#define RTC_RTC_0_DOTW_BITS _u(0x07000000)
+#define RTC_RTC_0_DOTW_MSB _u(26)
+#define RTC_RTC_0_DOTW_LSB _u(24)
#define RTC_RTC_0_DOTW_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_0_HOUR
// Description : Hours
#define RTC_RTC_0_HOUR_RESET "-"
-#define RTC_RTC_0_HOUR_BITS _U(0x001f0000)
-#define RTC_RTC_0_HOUR_MSB _U(20)
-#define RTC_RTC_0_HOUR_LSB _U(16)
+#define RTC_RTC_0_HOUR_BITS _u(0x001f0000)
+#define RTC_RTC_0_HOUR_MSB _u(20)
+#define RTC_RTC_0_HOUR_LSB _u(16)
#define RTC_RTC_0_HOUR_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_0_MIN
// Description : Minutes
#define RTC_RTC_0_MIN_RESET "-"
-#define RTC_RTC_0_MIN_BITS _U(0x00003f00)
-#define RTC_RTC_0_MIN_MSB _U(13)
-#define RTC_RTC_0_MIN_LSB _U(8)
+#define RTC_RTC_0_MIN_BITS _u(0x00003f00)
+#define RTC_RTC_0_MIN_MSB _u(13)
+#define RTC_RTC_0_MIN_LSB _u(8)
#define RTC_RTC_0_MIN_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_0_SEC
// Description : Seconds
#define RTC_RTC_0_SEC_RESET "-"
-#define RTC_RTC_0_SEC_BITS _U(0x0000003f)
-#define RTC_RTC_0_SEC_MSB _U(5)
-#define RTC_RTC_0_SEC_LSB _U(0)
+#define RTC_RTC_0_SEC_BITS _u(0x0000003f)
+#define RTC_RTC_0_SEC_MSB _u(5)
+#define RTC_RTC_0_SEC_LSB _u(0)
#define RTC_RTC_0_SEC_ACCESS "RF"
// =============================================================================
// Register : RTC_INTR
// Description : Raw Interrupts
-#define RTC_INTR_OFFSET _U(0x00000020)
-#define RTC_INTR_BITS _U(0x00000001)
-#define RTC_INTR_RESET _U(0x00000000)
+#define RTC_INTR_OFFSET _u(0x00000020)
+#define RTC_INTR_BITS _u(0x00000001)
+#define RTC_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_INTR_RTC
// Description : None
-#define RTC_INTR_RTC_RESET _U(0x0)
-#define RTC_INTR_RTC_BITS _U(0x00000001)
-#define RTC_INTR_RTC_MSB _U(0)
-#define RTC_INTR_RTC_LSB _U(0)
+#define RTC_INTR_RTC_RESET _u(0x0)
+#define RTC_INTR_RTC_BITS _u(0x00000001)
+#define RTC_INTR_RTC_MSB _u(0)
+#define RTC_INTR_RTC_LSB _u(0)
#define RTC_INTR_RTC_ACCESS "RO"
// =============================================================================
// Register : RTC_INTE
// Description : Interrupt Enable
-#define RTC_INTE_OFFSET _U(0x00000024)
-#define RTC_INTE_BITS _U(0x00000001)
-#define RTC_INTE_RESET _U(0x00000000)
+#define RTC_INTE_OFFSET _u(0x00000024)
+#define RTC_INTE_BITS _u(0x00000001)
+#define RTC_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_INTE_RTC
// Description : None
-#define RTC_INTE_RTC_RESET _U(0x0)
-#define RTC_INTE_RTC_BITS _U(0x00000001)
-#define RTC_INTE_RTC_MSB _U(0)
-#define RTC_INTE_RTC_LSB _U(0)
+#define RTC_INTE_RTC_RESET _u(0x0)
+#define RTC_INTE_RTC_BITS _u(0x00000001)
+#define RTC_INTE_RTC_MSB _u(0)
+#define RTC_INTE_RTC_LSB _u(0)
#define RTC_INTE_RTC_ACCESS "RW"
// =============================================================================
// Register : RTC_INTF
// Description : Interrupt Force
-#define RTC_INTF_OFFSET _U(0x00000028)
-#define RTC_INTF_BITS _U(0x00000001)
-#define RTC_INTF_RESET _U(0x00000000)
+#define RTC_INTF_OFFSET _u(0x00000028)
+#define RTC_INTF_BITS _u(0x00000001)
+#define RTC_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_INTF_RTC
// Description : None
-#define RTC_INTF_RTC_RESET _U(0x0)
-#define RTC_INTF_RTC_BITS _U(0x00000001)
-#define RTC_INTF_RTC_MSB _U(0)
-#define RTC_INTF_RTC_LSB _U(0)
+#define RTC_INTF_RTC_RESET _u(0x0)
+#define RTC_INTF_RTC_BITS _u(0x00000001)
+#define RTC_INTF_RTC_MSB _u(0)
+#define RTC_INTF_RTC_LSB _u(0)
#define RTC_INTF_RTC_ACCESS "RW"
// =============================================================================
// Register : RTC_INTS
// Description : Interrupt status after masking & forcing
-#define RTC_INTS_OFFSET _U(0x0000002c)
-#define RTC_INTS_BITS _U(0x00000001)
-#define RTC_INTS_RESET _U(0x00000000)
+#define RTC_INTS_OFFSET _u(0x0000002c)
+#define RTC_INTS_BITS _u(0x00000001)
+#define RTC_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_INTS_RTC
// Description : None
-#define RTC_INTS_RTC_RESET _U(0x0)
-#define RTC_INTS_RTC_BITS _U(0x00000001)
-#define RTC_INTS_RTC_MSB _U(0)
-#define RTC_INTS_RTC_LSB _U(0)
+#define RTC_INTS_RTC_RESET _u(0x0)
+#define RTC_INTS_RTC_BITS _u(0x00000001)
+#define RTC_INTS_RTC_MSB _u(0)
+#define RTC_INTS_RTC_LSB _u(0)
#define RTC_INTS_RTC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_RTC_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/sio.h b/src/rp2040/hardware_regs/include/hardware/regs/sio.h
index b61cccd..37ee2c1 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/sio.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/sio.h
@@ -18,32 +18,32 @@
// Description : Processor core identifier
// Value is 0 when read from processor core 0, and 1 when read
// from processor core 1.
-#define SIO_CPUID_OFFSET _U(0x00000000)
-#define SIO_CPUID_BITS _U(0xffffffff)
+#define SIO_CPUID_OFFSET _u(0x00000000)
+#define SIO_CPUID_BITS _u(0xffffffff)
#define SIO_CPUID_RESET "-"
-#define SIO_CPUID_MSB _U(31)
-#define SIO_CPUID_LSB _U(0)
+#define SIO_CPUID_MSB _u(31)
+#define SIO_CPUID_LSB _u(0)
#define SIO_CPUID_ACCESS "RO"
// =============================================================================
// Register : SIO_GPIO_IN
// Description : Input value for GPIO pins
// Input value for GPIO0...29
-#define SIO_GPIO_IN_OFFSET _U(0x00000004)
-#define SIO_GPIO_IN_BITS _U(0x3fffffff)
-#define SIO_GPIO_IN_RESET _U(0x00000000)
-#define SIO_GPIO_IN_MSB _U(29)
-#define SIO_GPIO_IN_LSB _U(0)
+#define SIO_GPIO_IN_OFFSET _u(0x00000004)
+#define SIO_GPIO_IN_BITS _u(0x3fffffff)
+#define SIO_GPIO_IN_RESET _u(0x00000000)
+#define SIO_GPIO_IN_MSB _u(29)
+#define SIO_GPIO_IN_LSB _u(0)
#define SIO_GPIO_IN_ACCESS "RO"
// =============================================================================
// Register : SIO_GPIO_HI_IN
// Description : Input value for QSPI pins
// Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2,
// SD3
-#define SIO_GPIO_HI_IN_OFFSET _U(0x00000008)
-#define SIO_GPIO_HI_IN_BITS _U(0x0000003f)
-#define SIO_GPIO_HI_IN_RESET _U(0x00000000)
-#define SIO_GPIO_HI_IN_MSB _U(5)
-#define SIO_GPIO_HI_IN_LSB _U(0)
+#define SIO_GPIO_HI_IN_OFFSET _u(0x00000008)
+#define SIO_GPIO_HI_IN_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_IN_RESET _u(0x00000000)
+#define SIO_GPIO_HI_IN_MSB _u(5)
+#define SIO_GPIO_HI_IN_LSB _u(0)
#define SIO_GPIO_HI_IN_ACCESS "RO"
// =============================================================================
// Register : SIO_GPIO_OUT
@@ -56,43 +56,43 @@
// the result is as though the write from core 0 took place first,
// and the write from core 1 was then applied to that intermediate
// result.
-#define SIO_GPIO_OUT_OFFSET _U(0x00000010)
-#define SIO_GPIO_OUT_BITS _U(0x3fffffff)
-#define SIO_GPIO_OUT_RESET _U(0x00000000)
-#define SIO_GPIO_OUT_MSB _U(29)
-#define SIO_GPIO_OUT_LSB _U(0)
+#define SIO_GPIO_OUT_OFFSET _u(0x00000010)
+#define SIO_GPIO_OUT_BITS _u(0x3fffffff)
+#define SIO_GPIO_OUT_RESET _u(0x00000000)
+#define SIO_GPIO_OUT_MSB _u(29)
+#define SIO_GPIO_OUT_LSB _u(0)
#define SIO_GPIO_OUT_ACCESS "RW"
// =============================================================================
// Register : SIO_GPIO_OUT_SET
// Description : GPIO output value set
// Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`
-#define SIO_GPIO_OUT_SET_OFFSET _U(0x00000014)
-#define SIO_GPIO_OUT_SET_BITS _U(0x3fffffff)
-#define SIO_GPIO_OUT_SET_RESET _U(0x00000000)
-#define SIO_GPIO_OUT_SET_MSB _U(29)
-#define SIO_GPIO_OUT_SET_LSB _U(0)
+#define SIO_GPIO_OUT_SET_OFFSET _u(0x00000014)
+#define SIO_GPIO_OUT_SET_BITS _u(0x3fffffff)
+#define SIO_GPIO_OUT_SET_RESET _u(0x00000000)
+#define SIO_GPIO_OUT_SET_MSB _u(29)
+#define SIO_GPIO_OUT_SET_LSB _u(0)
#define SIO_GPIO_OUT_SET_ACCESS "RW"
// =============================================================================
// Register : SIO_GPIO_OUT_CLR
// Description : GPIO output value clear
// Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &=
// ~wdata`
-#define SIO_GPIO_OUT_CLR_OFFSET _U(0x00000018)
-#define SIO_GPIO_OUT_CLR_BITS _U(0x3fffffff)
-#define SIO_GPIO_OUT_CLR_RESET _U(0x00000000)
-#define SIO_GPIO_OUT_CLR_MSB _U(29)
-#define SIO_GPIO_OUT_CLR_LSB _U(0)
+#define SIO_GPIO_OUT_CLR_OFFSET _u(0x00000018)
+#define SIO_GPIO_OUT_CLR_BITS _u(0x3fffffff)
+#define SIO_GPIO_OUT_CLR_RESET _u(0x00000000)
+#define SIO_GPIO_OUT_CLR_MSB _u(29)
+#define SIO_GPIO_OUT_CLR_LSB _u(0)
#define SIO_GPIO_OUT_CLR_ACCESS "RW"
// =============================================================================
// Register : SIO_GPIO_OUT_XOR
// Description : GPIO output value XOR
// Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^=
// wdata`
-#define SIO_GPIO_OUT_XOR_OFFSET _U(0x0000001c)
-#define SIO_GPIO_OUT_XOR_BITS _U(0x3fffffff)
-#define SIO_GPIO_OUT_XOR_RESET _U(0x00000000)
-#define SIO_GPIO_OUT_XOR_MSB _U(29)
-#define SIO_GPIO_OUT_XOR_LSB _U(0)
+#define SIO_GPIO_OUT_XOR_OFFSET _u(0x0000001c)
+#define SIO_GPIO_OUT_XOR_BITS _u(0x3fffffff)
+#define SIO_GPIO_OUT_XOR_RESET _u(0x00000000)
+#define SIO_GPIO_OUT_XOR_MSB _u(29)
+#define SIO_GPIO_OUT_XOR_LSB _u(0)
#define SIO_GPIO_OUT_XOR_ACCESS "RW"
// =============================================================================
// Register : SIO_GPIO_OE
@@ -104,43 +104,43 @@
// the result is as though the write from core 0 took place first,
// and the write from core 1 was then applied to that intermediate
// result.
-#define SIO_GPIO_OE_OFFSET _U(0x00000020)
-#define SIO_GPIO_OE_BITS _U(0x3fffffff)
-#define SIO_GPIO_OE_RESET _U(0x00000000)
-#define SIO_GPIO_OE_MSB _U(29)
-#define SIO_GPIO_OE_LSB _U(0)
+#define SIO_GPIO_OE_OFFSET _u(0x00000020)
+#define SIO_GPIO_OE_BITS _u(0x3fffffff)
+#define SIO_GPIO_OE_RESET _u(0x00000000)
+#define SIO_GPIO_OE_MSB _u(29)
+#define SIO_GPIO_OE_LSB _u(0)
#define SIO_GPIO_OE_ACCESS "RW"
// =============================================================================
// Register : SIO_GPIO_OE_SET
// Description : GPIO output enable set
// Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`
-#define SIO_GPIO_OE_SET_OFFSET _U(0x00000024)
-#define SIO_GPIO_OE_SET_BITS _U(0x3fffffff)
-#define SIO_GPIO_OE_SET_RESET _U(0x00000000)
-#define SIO_GPIO_OE_SET_MSB _U(29)
-#define SIO_GPIO_OE_SET_LSB _U(0)
+#define SIO_GPIO_OE_SET_OFFSET _u(0x00000024)
+#define SIO_GPIO_OE_SET_BITS _u(0x3fffffff)
+#define SIO_GPIO_OE_SET_RESET _u(0x00000000)
+#define SIO_GPIO_OE_SET_MSB _u(29)
+#define SIO_GPIO_OE_SET_LSB _u(0)
#define SIO_GPIO_OE_SET_ACCESS "RW"
// =============================================================================
// Register : SIO_GPIO_OE_CLR
// Description : GPIO output enable clear
// Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &=
// ~wdata`
-#define SIO_GPIO_OE_CLR_OFFSET _U(0x00000028)
-#define SIO_GPIO_OE_CLR_BITS _U(0x3fffffff)
-#define SIO_GPIO_OE_CLR_RESET _U(0x00000000)
-#define SIO_GPIO_OE_CLR_MSB _U(29)
-#define SIO_GPIO_OE_CLR_LSB _U(0)
+#define SIO_GPIO_OE_CLR_OFFSET _u(0x00000028)
+#define SIO_GPIO_OE_CLR_BITS _u(0x3fffffff)
+#define SIO_GPIO_OE_CLR_RESET _u(0x00000000)
+#define SIO_GPIO_OE_CLR_MSB _u(29)
+#define SIO_GPIO_OE_CLR_LSB _u(0)
#define SIO_GPIO_OE_CLR_ACCESS "RW"
// =============================================================================
// Register : SIO_GPIO_OE_XOR
// Description : GPIO output enable XOR
// Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^=
// wdata`
-#define SIO_GPIO_OE_XOR_OFFSET _U(0x0000002c)
-#define SIO_GPIO_OE_XOR_BITS _U(0x3fffffff)
-#define SIO_GPIO_OE_XOR_RESET _U(0x00000000)
-#define SIO_GPIO_OE_XOR_MSB _U(29)
-#define SIO_GPIO_OE_XOR_LSB _U(0)
+#define SIO_GPIO_OE_XOR_OFFSET _u(0x0000002c)
+#define SIO_GPIO_OE_XOR_BITS _u(0x3fffffff)
+#define SIO_GPIO_OE_XOR_RESET _u(0x00000000)
+#define SIO_GPIO_OE_XOR_MSB _u(29)
+#define SIO_GPIO_OE_XOR_LSB _u(0)
#define SIO_GPIO_OE_XOR_ACCESS "RW"
// =============================================================================
// Register : SIO_GPIO_HI_OUT
@@ -153,44 +153,44 @@
// the result is as though the write from core 0 took place first,
// and the write from core 1 was then applied to that intermediate
// result.
-#define SIO_GPIO_HI_OUT_OFFSET _U(0x00000030)
-#define SIO_GPIO_HI_OUT_BITS _U(0x0000003f)
-#define SIO_GPIO_HI_OUT_RESET _U(0x00000000)
-#define SIO_GPIO_HI_OUT_MSB _U(5)
-#define SIO_GPIO_HI_OUT_LSB _U(0)
+#define SIO_GPIO_HI_OUT_OFFSET _u(0x00000030)
+#define SIO_GPIO_HI_OUT_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_OUT_RESET _u(0x00000000)
+#define SIO_GPIO_HI_OUT_MSB _u(5)
+#define SIO_GPIO_HI_OUT_LSB _u(0)
#define SIO_GPIO_HI_OUT_ACCESS "RW"
// =============================================================================
// Register : SIO_GPIO_HI_OUT_SET
// Description : QSPI output value set
// Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |=
// wdata`
-#define SIO_GPIO_HI_OUT_SET_OFFSET _U(0x00000034)
-#define SIO_GPIO_HI_OUT_SET_BITS _U(0x0000003f)
-#define SIO_GPIO_HI_OUT_SET_RESET _U(0x00000000)
-#define SIO_GPIO_HI_OUT_SET_MSB _U(5)
-#define SIO_GPIO_HI_OUT_SET_LSB _U(0)
+#define SIO_GPIO_HI_OUT_SET_OFFSET _u(0x00000034)
+#define SIO_GPIO_HI_OUT_SET_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_OUT_SET_RESET _u(0x00000000)
+#define SIO_GPIO_HI_OUT_SET_MSB _u(5)
+#define SIO_GPIO_HI_OUT_SET_LSB _u(0)
#define SIO_GPIO_HI_OUT_SET_ACCESS "RW"
// =============================================================================
// Register : SIO_GPIO_HI_OUT_CLR
// Description : QSPI output value clear
// Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT
// &= ~wdata`
-#define SIO_GPIO_HI_OUT_CLR_OFFSET _U(0x00000038)
-#define SIO_GPIO_HI_OUT_CLR_BITS _U(0x0000003f)
-#define SIO_GPIO_HI_OUT_CLR_RESET _U(0x00000000)
-#define SIO_GPIO_HI_OUT_CLR_MSB _U(5)
-#define SIO_GPIO_HI_OUT_CLR_LSB _U(0)
+#define SIO_GPIO_HI_OUT_CLR_OFFSET _u(0x00000038)
+#define SIO_GPIO_HI_OUT_CLR_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_OUT_CLR_RESET _u(0x00000000)
+#define SIO_GPIO_HI_OUT_CLR_MSB _u(5)
+#define SIO_GPIO_HI_OUT_CLR_LSB _u(0)
#define SIO_GPIO_HI_OUT_CLR_ACCESS "RW"
// =============================================================================
// Register : SIO_GPIO_HI_OUT_XOR
// Description : QSPI output value XOR
// Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT
// ^= wdata`
-#define SIO_GPIO_HI_OUT_XOR_OFFSET _U(0x0000003c)
-#define SIO_GPIO_HI_OUT_XOR_BITS _U(0x0000003f)
-#define SIO_GPIO_HI_OUT_XOR_RESET _U(0x00000000)
-#define SIO_GPIO_HI_OUT_XOR_MSB _U(5)
-#define SIO_GPIO_HI_OUT_XOR_LSB _U(0)
+#define SIO_GPIO_HI_OUT_XOR_OFFSET _u(0x0000003c)
+#define SIO_GPIO_HI_OUT_XOR_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_OUT_XOR_RESET _u(0x00000000)
+#define SIO_GPIO_HI_OUT_XOR_MSB _u(5)
+#define SIO_GPIO_HI_OUT_XOR_LSB _u(0)
#define SIO_GPIO_HI_OUT_XOR_ACCESS "RW"
// =============================================================================
// Register : SIO_GPIO_HI_OE
@@ -202,44 +202,44 @@
// the result is as though the write from core 0 took place first,
// and the write from core 1 was then applied to that intermediate
// result.
-#define SIO_GPIO_HI_OE_OFFSET _U(0x00000040)
-#define SIO_GPIO_HI_OE_BITS _U(0x0000003f)
-#define SIO_GPIO_HI_OE_RESET _U(0x00000000)
-#define SIO_GPIO_HI_OE_MSB _U(5)
-#define SIO_GPIO_HI_OE_LSB _U(0)
+#define SIO_GPIO_HI_OE_OFFSET _u(0x00000040)
+#define SIO_GPIO_HI_OE_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_OE_RESET _u(0x00000000)
+#define SIO_GPIO_HI_OE_MSB _u(5)
+#define SIO_GPIO_HI_OE_LSB _u(0)
#define SIO_GPIO_HI_OE_ACCESS "RW"
// =============================================================================
// Register : SIO_GPIO_HI_OE_SET
// Description : QSPI output enable set
// Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |=
// wdata`
-#define SIO_GPIO_HI_OE_SET_OFFSET _U(0x00000044)
-#define SIO_GPIO_HI_OE_SET_BITS _U(0x0000003f)
-#define SIO_GPIO_HI_OE_SET_RESET _U(0x00000000)
-#define SIO_GPIO_HI_OE_SET_MSB _U(5)
-#define SIO_GPIO_HI_OE_SET_LSB _U(0)
+#define SIO_GPIO_HI_OE_SET_OFFSET _u(0x00000044)
+#define SIO_GPIO_HI_OE_SET_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_OE_SET_RESET _u(0x00000000)
+#define SIO_GPIO_HI_OE_SET_MSB _u(5)
+#define SIO_GPIO_HI_OE_SET_LSB _u(0)
#define SIO_GPIO_HI_OE_SET_ACCESS "RW"
// =============================================================================
// Register : SIO_GPIO_HI_OE_CLR
// Description : QSPI output enable clear
// Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &=
// ~wdata`
-#define SIO_GPIO_HI_OE_CLR_OFFSET _U(0x00000048)
-#define SIO_GPIO_HI_OE_CLR_BITS _U(0x0000003f)
-#define SIO_GPIO_HI_OE_CLR_RESET _U(0x00000000)
-#define SIO_GPIO_HI_OE_CLR_MSB _U(5)
-#define SIO_GPIO_HI_OE_CLR_LSB _U(0)
+#define SIO_GPIO_HI_OE_CLR_OFFSET _u(0x00000048)
+#define SIO_GPIO_HI_OE_CLR_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_OE_CLR_RESET _u(0x00000000)
+#define SIO_GPIO_HI_OE_CLR_MSB _u(5)
+#define SIO_GPIO_HI_OE_CLR_LSB _u(0)
#define SIO_GPIO_HI_OE_CLR_ACCESS "RW"
// =============================================================================
// Register : SIO_GPIO_HI_OE_XOR
// Description : QSPI output enable XOR
// Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE
// ^= wdata`
-#define SIO_GPIO_HI_OE_XOR_OFFSET _U(0x0000004c)
-#define SIO_GPIO_HI_OE_XOR_BITS _U(0x0000003f)
-#define SIO_GPIO_HI_OE_XOR_RESET _U(0x00000000)
-#define SIO_GPIO_HI_OE_XOR_MSB _U(5)
-#define SIO_GPIO_HI_OE_XOR_LSB _U(0)
+#define SIO_GPIO_HI_OE_XOR_OFFSET _u(0x0000004c)
+#define SIO_GPIO_HI_OE_XOR_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_OE_XOR_RESET _u(0x00000000)
+#define SIO_GPIO_HI_OE_XOR_MSB _u(5)
+#define SIO_GPIO_HI_OE_XOR_LSB _u(0)
#define SIO_GPIO_HI_OE_XOR_ACCESS "RW"
// =============================================================================
// Register : SIO_FIFO_ST
@@ -252,73 +252,73 @@
// write side of 1->0 FIFO (TX).
// The SIO IRQ for each core is the logical OR of the VLD, WOF and
// ROE fields of its FIFO_ST register.
-#define SIO_FIFO_ST_OFFSET _U(0x00000050)
-#define SIO_FIFO_ST_BITS _U(0x0000000f)
-#define SIO_FIFO_ST_RESET _U(0x00000002)
+#define SIO_FIFO_ST_OFFSET _u(0x00000050)
+#define SIO_FIFO_ST_BITS _u(0x0000000f)
+#define SIO_FIFO_ST_RESET _u(0x00000002)
// -----------------------------------------------------------------------------
// Field : SIO_FIFO_ST_ROE
// Description : Sticky flag indicating the RX FIFO was read when empty. This
// read was ignored by the FIFO.
-#define SIO_FIFO_ST_ROE_RESET _U(0x0)
-#define SIO_FIFO_ST_ROE_BITS _U(0x00000008)
-#define SIO_FIFO_ST_ROE_MSB _U(3)
-#define SIO_FIFO_ST_ROE_LSB _U(3)
+#define SIO_FIFO_ST_ROE_RESET _u(0x0)
+#define SIO_FIFO_ST_ROE_BITS _u(0x00000008)
+#define SIO_FIFO_ST_ROE_MSB _u(3)
+#define SIO_FIFO_ST_ROE_LSB _u(3)
#define SIO_FIFO_ST_ROE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : SIO_FIFO_ST_WOF
// Description : Sticky flag indicating the TX FIFO was written when full. This
// write was ignored by the FIFO.
-#define SIO_FIFO_ST_WOF_RESET _U(0x0)
-#define SIO_FIFO_ST_WOF_BITS _U(0x00000004)
-#define SIO_FIFO_ST_WOF_MSB _U(2)
-#define SIO_FIFO_ST_WOF_LSB _U(2)
+#define SIO_FIFO_ST_WOF_RESET _u(0x0)
+#define SIO_FIFO_ST_WOF_BITS _u(0x00000004)
+#define SIO_FIFO_ST_WOF_MSB _u(2)
+#define SIO_FIFO_ST_WOF_LSB _u(2)
#define SIO_FIFO_ST_WOF_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : SIO_FIFO_ST_RDY
// Description : Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR
// is ready for more data)
-#define SIO_FIFO_ST_RDY_RESET _U(0x1)
-#define SIO_FIFO_ST_RDY_BITS _U(0x00000002)
-#define SIO_FIFO_ST_RDY_MSB _U(1)
-#define SIO_FIFO_ST_RDY_LSB _U(1)
+#define SIO_FIFO_ST_RDY_RESET _u(0x1)
+#define SIO_FIFO_ST_RDY_BITS _u(0x00000002)
+#define SIO_FIFO_ST_RDY_MSB _u(1)
+#define SIO_FIFO_ST_RDY_LSB _u(1)
#define SIO_FIFO_ST_RDY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SIO_FIFO_ST_VLD
// Description : Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD
// is valid)
-#define SIO_FIFO_ST_VLD_RESET _U(0x0)
-#define SIO_FIFO_ST_VLD_BITS _U(0x00000001)
-#define SIO_FIFO_ST_VLD_MSB _U(0)
-#define SIO_FIFO_ST_VLD_LSB _U(0)
+#define SIO_FIFO_ST_VLD_RESET _u(0x0)
+#define SIO_FIFO_ST_VLD_BITS _u(0x00000001)
+#define SIO_FIFO_ST_VLD_MSB _u(0)
+#define SIO_FIFO_ST_VLD_LSB _u(0)
#define SIO_FIFO_ST_VLD_ACCESS "RO"
// =============================================================================
// Register : SIO_FIFO_WR
// Description : Write access to this core's TX FIFO
-#define SIO_FIFO_WR_OFFSET _U(0x00000054)
-#define SIO_FIFO_WR_BITS _U(0xffffffff)
-#define SIO_FIFO_WR_RESET _U(0x00000000)
-#define SIO_FIFO_WR_MSB _U(31)
-#define SIO_FIFO_WR_LSB _U(0)
+#define SIO_FIFO_WR_OFFSET _u(0x00000054)
+#define SIO_FIFO_WR_BITS _u(0xffffffff)
+#define SIO_FIFO_WR_RESET _u(0x00000000)
+#define SIO_FIFO_WR_MSB _u(31)
+#define SIO_FIFO_WR_LSB _u(0)
#define SIO_FIFO_WR_ACCESS "WF"
// =============================================================================
// Register : SIO_FIFO_RD
// Description : Read access to this core's RX FIFO
-#define SIO_FIFO_RD_OFFSET _U(0x00000058)
-#define SIO_FIFO_RD_BITS _U(0xffffffff)
+#define SIO_FIFO_RD_OFFSET _u(0x00000058)
+#define SIO_FIFO_RD_BITS _u(0xffffffff)
#define SIO_FIFO_RD_RESET "-"
-#define SIO_FIFO_RD_MSB _U(31)
-#define SIO_FIFO_RD_LSB _U(0)
+#define SIO_FIFO_RD_MSB _u(31)
+#define SIO_FIFO_RD_LSB _u(0)
#define SIO_FIFO_RD_ACCESS "RF"
// =============================================================================
// Register : SIO_SPINLOCK_ST
// Description : Spinlock state
// A bitmap containing the state of all 32 spinlocks (1=locked).
// Mainly intended for debugging.
-#define SIO_SPINLOCK_ST_OFFSET _U(0x0000005c)
-#define SIO_SPINLOCK_ST_BITS _U(0xffffffff)
-#define SIO_SPINLOCK_ST_RESET _U(0x00000000)
-#define SIO_SPINLOCK_ST_MSB _U(31)
-#define SIO_SPINLOCK_ST_LSB _U(0)
+#define SIO_SPINLOCK_ST_OFFSET _u(0x0000005c)
+#define SIO_SPINLOCK_ST_BITS _u(0xffffffff)
+#define SIO_SPINLOCK_ST_RESET _u(0x00000000)
+#define SIO_SPINLOCK_ST_MSB _u(31)
+#define SIO_SPINLOCK_ST_LSB _u(0)
#define SIO_SPINLOCK_ST_ACCESS "RO"
// =============================================================================
// Register : SIO_DIV_UDIVIDEND
@@ -331,11 +331,11 @@
// The U alias starts an
// unsigned calculation, and the S alias starts a signed
// calculation.
-#define SIO_DIV_UDIVIDEND_OFFSET _U(0x00000060)
-#define SIO_DIV_UDIVIDEND_BITS _U(0xffffffff)
-#define SIO_DIV_UDIVIDEND_RESET _U(0x00000000)
-#define SIO_DIV_UDIVIDEND_MSB _U(31)
-#define SIO_DIV_UDIVIDEND_LSB _U(0)
+#define SIO_DIV_UDIVIDEND_OFFSET _u(0x00000060)
+#define SIO_DIV_UDIVIDEND_BITS _u(0xffffffff)
+#define SIO_DIV_UDIVIDEND_RESET _u(0x00000000)
+#define SIO_DIV_UDIVIDEND_MSB _u(31)
+#define SIO_DIV_UDIVIDEND_LSB _u(0)
#define SIO_DIV_UDIVIDEND_ACCESS "RW"
// =============================================================================
// Register : SIO_DIV_UDIVISOR
@@ -348,33 +348,33 @@
// The U alias starts an
// unsigned calculation, and the S alias starts a signed
// calculation.
-#define SIO_DIV_UDIVISOR_OFFSET _U(0x00000064)
-#define SIO_DIV_UDIVISOR_BITS _U(0xffffffff)
-#define SIO_DIV_UDIVISOR_RESET _U(0x00000000)
-#define SIO_DIV_UDIVISOR_MSB _U(31)
-#define SIO_DIV_UDIVISOR_LSB _U(0)
+#define SIO_DIV_UDIVISOR_OFFSET _u(0x00000064)
+#define SIO_DIV_UDIVISOR_BITS _u(0xffffffff)
+#define SIO_DIV_UDIVISOR_RESET _u(0x00000000)
+#define SIO_DIV_UDIVISOR_MSB _u(31)
+#define SIO_DIV_UDIVISOR_LSB _u(0)
#define SIO_DIV_UDIVISOR_ACCESS "RW"
// =============================================================================
// Register : SIO_DIV_SDIVIDEND
// Description : Divider signed dividend
// The same as UDIVIDEND, but starts a signed calculation, rather
// than unsigned.
-#define SIO_DIV_SDIVIDEND_OFFSET _U(0x00000068)
-#define SIO_DIV_SDIVIDEND_BITS _U(0xffffffff)
-#define SIO_DIV_SDIVIDEND_RESET _U(0x00000000)
-#define SIO_DIV_SDIVIDEND_MSB _U(31)
-#define SIO_DIV_SDIVIDEND_LSB _U(0)
+#define SIO_DIV_SDIVIDEND_OFFSET _u(0x00000068)
+#define SIO_DIV_SDIVIDEND_BITS _u(0xffffffff)
+#define SIO_DIV_SDIVIDEND_RESET _u(0x00000000)
+#define SIO_DIV_SDIVIDEND_MSB _u(31)
+#define SIO_DIV_SDIVIDEND_LSB _u(0)
#define SIO_DIV_SDIVIDEND_ACCESS "RW"
// =============================================================================
// Register : SIO_DIV_SDIVISOR
// Description : Divider signed divisor
// The same as UDIVISOR, but starts a signed calculation, rather
// than unsigned.
-#define SIO_DIV_SDIVISOR_OFFSET _U(0x0000006c)
-#define SIO_DIV_SDIVISOR_BITS _U(0xffffffff)
-#define SIO_DIV_SDIVISOR_RESET _U(0x00000000)
-#define SIO_DIV_SDIVISOR_MSB _U(31)
-#define SIO_DIV_SDIVISOR_LSB _U(0)
+#define SIO_DIV_SDIVISOR_OFFSET _u(0x0000006c)
+#define SIO_DIV_SDIVISOR_BITS _u(0xffffffff)
+#define SIO_DIV_SDIVISOR_RESET _u(0x00000000)
+#define SIO_DIV_SDIVISOR_MSB _u(31)
+#define SIO_DIV_SDIVISOR_LSB _u(0)
#define SIO_DIV_SDIVISOR_ACCESS "RW"
// =============================================================================
// Register : SIO_DIV_QUOTIENT
@@ -390,11 +390,11 @@
// Reading from QUOTIENT clears the CSR_DIRTY flag, so should read
// results in the order
// REMAINDER, QUOTIENT if CSR_DIRTY is used.
-#define SIO_DIV_QUOTIENT_OFFSET _U(0x00000070)
-#define SIO_DIV_QUOTIENT_BITS _U(0xffffffff)
-#define SIO_DIV_QUOTIENT_RESET _U(0x00000000)
-#define SIO_DIV_QUOTIENT_MSB _U(31)
-#define SIO_DIV_QUOTIENT_LSB _U(0)
+#define SIO_DIV_QUOTIENT_OFFSET _u(0x00000070)
+#define SIO_DIV_QUOTIENT_BITS _u(0xffffffff)
+#define SIO_DIV_QUOTIENT_RESET _u(0x00000000)
+#define SIO_DIV_QUOTIENT_MSB _u(31)
+#define SIO_DIV_QUOTIENT_LSB _u(0)
#define SIO_DIV_QUOTIENT_ACCESS "RW"
// =============================================================================
// Register : SIO_DIV_REMAINDER
@@ -407,18 +407,18 @@
// save/restore purposes. This halts any
// in-progress calculation and sets the CSR_READY and CSR_DIRTY
// flags.
-#define SIO_DIV_REMAINDER_OFFSET _U(0x00000074)
-#define SIO_DIV_REMAINDER_BITS _U(0xffffffff)
-#define SIO_DIV_REMAINDER_RESET _U(0x00000000)
-#define SIO_DIV_REMAINDER_MSB _U(31)
-#define SIO_DIV_REMAINDER_LSB _U(0)
+#define SIO_DIV_REMAINDER_OFFSET _u(0x00000074)
+#define SIO_DIV_REMAINDER_BITS _u(0xffffffff)
+#define SIO_DIV_REMAINDER_RESET _u(0x00000000)
+#define SIO_DIV_REMAINDER_MSB _u(31)
+#define SIO_DIV_REMAINDER_LSB _u(0)
#define SIO_DIV_REMAINDER_ACCESS "RW"
// =============================================================================
// Register : SIO_DIV_CSR
// Description : Control and status register for divider.
-#define SIO_DIV_CSR_OFFSET _U(0x00000078)
-#define SIO_DIV_CSR_BITS _U(0x00000003)
-#define SIO_DIV_CSR_RESET _U(0x00000001)
+#define SIO_DIV_CSR_OFFSET _u(0x00000078)
+#define SIO_DIV_CSR_BITS _u(0x00000003)
+#define SIO_DIV_CSR_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : SIO_DIV_CSR_DIRTY
// Description : Changes to 1 when any register is written, and back to 0 when
@@ -429,10 +429,10 @@
// read QUOTIENT only,
// or REMAINDER and then QUOTIENT, to prevent data loss on context
// switch.
-#define SIO_DIV_CSR_DIRTY_RESET _U(0x0)
-#define SIO_DIV_CSR_DIRTY_BITS _U(0x00000002)
-#define SIO_DIV_CSR_DIRTY_MSB _U(1)
-#define SIO_DIV_CSR_DIRTY_LSB _U(1)
+#define SIO_DIV_CSR_DIRTY_RESET _u(0x0)
+#define SIO_DIV_CSR_DIRTY_BITS _u(0x00000002)
+#define SIO_DIV_CSR_DIRTY_MSB _u(1)
+#define SIO_DIV_CSR_DIRTY_LSB _u(1)
#define SIO_DIV_CSR_DIRTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SIO_DIV_CSR_READY
@@ -443,142 +443,142 @@
// Writing to a result register will immediately terminate any
// in-progress calculation
// and set the READY and DIRTY flags.
-#define SIO_DIV_CSR_READY_RESET _U(0x1)
-#define SIO_DIV_CSR_READY_BITS _U(0x00000001)
-#define SIO_DIV_CSR_READY_MSB _U(0)
-#define SIO_DIV_CSR_READY_LSB _U(0)
+#define SIO_DIV_CSR_READY_RESET _u(0x1)
+#define SIO_DIV_CSR_READY_BITS _u(0x00000001)
+#define SIO_DIV_CSR_READY_MSB _u(0)
+#define SIO_DIV_CSR_READY_LSB _u(0)
#define SIO_DIV_CSR_READY_ACCESS "RO"
// =============================================================================
// Register : SIO_INTERP0_ACCUM0
// Description : Read/write access to accumulator 0
-#define SIO_INTERP0_ACCUM0_OFFSET _U(0x00000080)
-#define SIO_INTERP0_ACCUM0_BITS _U(0xffffffff)
-#define SIO_INTERP0_ACCUM0_RESET _U(0x00000000)
-#define SIO_INTERP0_ACCUM0_MSB _U(31)
-#define SIO_INTERP0_ACCUM0_LSB _U(0)
+#define SIO_INTERP0_ACCUM0_OFFSET _u(0x00000080)
+#define SIO_INTERP0_ACCUM0_BITS _u(0xffffffff)
+#define SIO_INTERP0_ACCUM0_RESET _u(0x00000000)
+#define SIO_INTERP0_ACCUM0_MSB _u(31)
+#define SIO_INTERP0_ACCUM0_LSB _u(0)
#define SIO_INTERP0_ACCUM0_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP0_ACCUM1
// Description : Read/write access to accumulator 1
-#define SIO_INTERP0_ACCUM1_OFFSET _U(0x00000084)
-#define SIO_INTERP0_ACCUM1_BITS _U(0xffffffff)
-#define SIO_INTERP0_ACCUM1_RESET _U(0x00000000)
-#define SIO_INTERP0_ACCUM1_MSB _U(31)
-#define SIO_INTERP0_ACCUM1_LSB _U(0)
+#define SIO_INTERP0_ACCUM1_OFFSET _u(0x00000084)
+#define SIO_INTERP0_ACCUM1_BITS _u(0xffffffff)
+#define SIO_INTERP0_ACCUM1_RESET _u(0x00000000)
+#define SIO_INTERP0_ACCUM1_MSB _u(31)
+#define SIO_INTERP0_ACCUM1_LSB _u(0)
#define SIO_INTERP0_ACCUM1_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP0_BASE0
// Description : Read/write access to BASE0 register.
-#define SIO_INTERP0_BASE0_OFFSET _U(0x00000088)
-#define SIO_INTERP0_BASE0_BITS _U(0xffffffff)
-#define SIO_INTERP0_BASE0_RESET _U(0x00000000)
-#define SIO_INTERP0_BASE0_MSB _U(31)
-#define SIO_INTERP0_BASE0_LSB _U(0)
+#define SIO_INTERP0_BASE0_OFFSET _u(0x00000088)
+#define SIO_INTERP0_BASE0_BITS _u(0xffffffff)
+#define SIO_INTERP0_BASE0_RESET _u(0x00000000)
+#define SIO_INTERP0_BASE0_MSB _u(31)
+#define SIO_INTERP0_BASE0_LSB _u(0)
#define SIO_INTERP0_BASE0_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP0_BASE1
// Description : Read/write access to BASE1 register.
-#define SIO_INTERP0_BASE1_OFFSET _U(0x0000008c)
-#define SIO_INTERP0_BASE1_BITS _U(0xffffffff)
-#define SIO_INTERP0_BASE1_RESET _U(0x00000000)
-#define SIO_INTERP0_BASE1_MSB _U(31)
-#define SIO_INTERP0_BASE1_LSB _U(0)
+#define SIO_INTERP0_BASE1_OFFSET _u(0x0000008c)
+#define SIO_INTERP0_BASE1_BITS _u(0xffffffff)
+#define SIO_INTERP0_BASE1_RESET _u(0x00000000)
+#define SIO_INTERP0_BASE1_MSB _u(31)
+#define SIO_INTERP0_BASE1_LSB _u(0)
#define SIO_INTERP0_BASE1_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP0_BASE2
// Description : Read/write access to BASE2 register.
-#define SIO_INTERP0_BASE2_OFFSET _U(0x00000090)
-#define SIO_INTERP0_BASE2_BITS _U(0xffffffff)
-#define SIO_INTERP0_BASE2_RESET _U(0x00000000)
-#define SIO_INTERP0_BASE2_MSB _U(31)
-#define SIO_INTERP0_BASE2_LSB _U(0)
+#define SIO_INTERP0_BASE2_OFFSET _u(0x00000090)
+#define SIO_INTERP0_BASE2_BITS _u(0xffffffff)
+#define SIO_INTERP0_BASE2_RESET _u(0x00000000)
+#define SIO_INTERP0_BASE2_MSB _u(31)
+#define SIO_INTERP0_BASE2_LSB _u(0)
#define SIO_INTERP0_BASE2_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP0_POP_LANE0
// Description : Read LANE0 result, and simultaneously write lane results to
// both accumulators (POP).
-#define SIO_INTERP0_POP_LANE0_OFFSET _U(0x00000094)
-#define SIO_INTERP0_POP_LANE0_BITS _U(0xffffffff)
-#define SIO_INTERP0_POP_LANE0_RESET _U(0x00000000)
-#define SIO_INTERP0_POP_LANE0_MSB _U(31)
-#define SIO_INTERP0_POP_LANE0_LSB _U(0)
+#define SIO_INTERP0_POP_LANE0_OFFSET _u(0x00000094)
+#define SIO_INTERP0_POP_LANE0_BITS _u(0xffffffff)
+#define SIO_INTERP0_POP_LANE0_RESET _u(0x00000000)
+#define SIO_INTERP0_POP_LANE0_MSB _u(31)
+#define SIO_INTERP0_POP_LANE0_LSB _u(0)
#define SIO_INTERP0_POP_LANE0_ACCESS "RO"
// =============================================================================
// Register : SIO_INTERP0_POP_LANE1
// Description : Read LANE1 result, and simultaneously write lane results to
// both accumulators (POP).
-#define SIO_INTERP0_POP_LANE1_OFFSET _U(0x00000098)
-#define SIO_INTERP0_POP_LANE1_BITS _U(0xffffffff)
-#define SIO_INTERP0_POP_LANE1_RESET _U(0x00000000)
-#define SIO_INTERP0_POP_LANE1_MSB _U(31)
-#define SIO_INTERP0_POP_LANE1_LSB _U(0)
+#define SIO_INTERP0_POP_LANE1_OFFSET _u(0x00000098)
+#define SIO_INTERP0_POP_LANE1_BITS _u(0xffffffff)
+#define SIO_INTERP0_POP_LANE1_RESET _u(0x00000000)
+#define SIO_INTERP0_POP_LANE1_MSB _u(31)
+#define SIO_INTERP0_POP_LANE1_LSB _u(0)
#define SIO_INTERP0_POP_LANE1_ACCESS "RO"
// =============================================================================
// Register : SIO_INTERP0_POP_FULL
// Description : Read FULL result, and simultaneously write lane results to both
// accumulators (POP).
-#define SIO_INTERP0_POP_FULL_OFFSET _U(0x0000009c)
-#define SIO_INTERP0_POP_FULL_BITS _U(0xffffffff)
-#define SIO_INTERP0_POP_FULL_RESET _U(0x00000000)
-#define SIO_INTERP0_POP_FULL_MSB _U(31)
-#define SIO_INTERP0_POP_FULL_LSB _U(0)
+#define SIO_INTERP0_POP_FULL_OFFSET _u(0x0000009c)
+#define SIO_INTERP0_POP_FULL_BITS _u(0xffffffff)
+#define SIO_INTERP0_POP_FULL_RESET _u(0x00000000)
+#define SIO_INTERP0_POP_FULL_MSB _u(31)
+#define SIO_INTERP0_POP_FULL_LSB _u(0)
#define SIO_INTERP0_POP_FULL_ACCESS "RO"
// =============================================================================
// Register : SIO_INTERP0_PEEK_LANE0
// Description : Read LANE0 result, without altering any internal state (PEEK).
-#define SIO_INTERP0_PEEK_LANE0_OFFSET _U(0x000000a0)
-#define SIO_INTERP0_PEEK_LANE0_BITS _U(0xffffffff)
-#define SIO_INTERP0_PEEK_LANE0_RESET _U(0x00000000)
-#define SIO_INTERP0_PEEK_LANE0_MSB _U(31)
-#define SIO_INTERP0_PEEK_LANE0_LSB _U(0)
+#define SIO_INTERP0_PEEK_LANE0_OFFSET _u(0x000000a0)
+#define SIO_INTERP0_PEEK_LANE0_BITS _u(0xffffffff)
+#define SIO_INTERP0_PEEK_LANE0_RESET _u(0x00000000)
+#define SIO_INTERP0_PEEK_LANE0_MSB _u(31)
+#define SIO_INTERP0_PEEK_LANE0_LSB _u(0)
#define SIO_INTERP0_PEEK_LANE0_ACCESS "RO"
// =============================================================================
// Register : SIO_INTERP0_PEEK_LANE1
// Description : Read LANE1 result, without altering any internal state (PEEK).
-#define SIO_INTERP0_PEEK_LANE1_OFFSET _U(0x000000a4)
-#define SIO_INTERP0_PEEK_LANE1_BITS _U(0xffffffff)
-#define SIO_INTERP0_PEEK_LANE1_RESET _U(0x00000000)
-#define SIO_INTERP0_PEEK_LANE1_MSB _U(31)
-#define SIO_INTERP0_PEEK_LANE1_LSB _U(0)
+#define SIO_INTERP0_PEEK_LANE1_OFFSET _u(0x000000a4)
+#define SIO_INTERP0_PEEK_LANE1_BITS _u(0xffffffff)
+#define SIO_INTERP0_PEEK_LANE1_RESET _u(0x00000000)
+#define SIO_INTERP0_PEEK_LANE1_MSB _u(31)
+#define SIO_INTERP0_PEEK_LANE1_LSB _u(0)
#define SIO_INTERP0_PEEK_LANE1_ACCESS "RO"
// =============================================================================
// Register : SIO_INTERP0_PEEK_FULL
// Description : Read FULL result, without altering any internal state (PEEK).
-#define SIO_INTERP0_PEEK_FULL_OFFSET _U(0x000000a8)
-#define SIO_INTERP0_PEEK_FULL_BITS _U(0xffffffff)
-#define SIO_INTERP0_PEEK_FULL_RESET _U(0x00000000)
-#define SIO_INTERP0_PEEK_FULL_MSB _U(31)
-#define SIO_INTERP0_PEEK_FULL_LSB _U(0)
+#define SIO_INTERP0_PEEK_FULL_OFFSET _u(0x000000a8)
+#define SIO_INTERP0_PEEK_FULL_BITS _u(0xffffffff)
+#define SIO_INTERP0_PEEK_FULL_RESET _u(0x00000000)
+#define SIO_INTERP0_PEEK_FULL_MSB _u(31)
+#define SIO_INTERP0_PEEK_FULL_LSB _u(0)
#define SIO_INTERP0_PEEK_FULL_ACCESS "RO"
// =============================================================================
// Register : SIO_INTERP0_CTRL_LANE0
// Description : Control register for lane 0
-#define SIO_INTERP0_CTRL_LANE0_OFFSET _U(0x000000ac)
-#define SIO_INTERP0_CTRL_LANE0_BITS _U(0x03bfffff)
-#define SIO_INTERP0_CTRL_LANE0_RESET _U(0x00000000)
+#define SIO_INTERP0_CTRL_LANE0_OFFSET _u(0x000000ac)
+#define SIO_INTERP0_CTRL_LANE0_BITS _u(0x03bfffff)
+#define SIO_INTERP0_CTRL_LANE0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE0_OVERF
// Description : Set if either OVERF0 or OVERF1 is set.
-#define SIO_INTERP0_CTRL_LANE0_OVERF_RESET _U(0x0)
-#define SIO_INTERP0_CTRL_LANE0_OVERF_BITS _U(0x02000000)
-#define SIO_INTERP0_CTRL_LANE0_OVERF_MSB _U(25)
-#define SIO_INTERP0_CTRL_LANE0_OVERF_LSB _U(25)
+#define SIO_INTERP0_CTRL_LANE0_OVERF_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_OVERF_BITS _u(0x02000000)
+#define SIO_INTERP0_CTRL_LANE0_OVERF_MSB _u(25)
+#define SIO_INTERP0_CTRL_LANE0_OVERF_LSB _u(25)
#define SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE0_OVERF1
// Description : Indicates if any masked-off MSBs in ACCUM1 are set.
-#define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET _U(0x0)
-#define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS _U(0x01000000)
-#define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB _U(24)
-#define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB _U(24)
+#define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS _u(0x01000000)
+#define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB _u(24)
+#define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB _u(24)
#define SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE0_OVERF0
// Description : Indicates if any masked-off MSBs in ACCUM0 are set.
-#define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET _U(0x0)
-#define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS _U(0x00800000)
-#define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB _U(23)
-#define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB _U(23)
+#define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS _u(0x00800000)
+#define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB _u(23)
+#define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB _u(23)
#define SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE0_BLEND
@@ -594,10 +594,10 @@
// (BASE2 + lane 0 shift+mask)
// LANE1 SIGNED flag controls whether the interpolation is signed
// or unsigned.
-#define SIO_INTERP0_CTRL_LANE0_BLEND_RESET _U(0x0)
-#define SIO_INTERP0_CTRL_LANE0_BLEND_BITS _U(0x00200000)
-#define SIO_INTERP0_CTRL_LANE0_BLEND_MSB _U(21)
-#define SIO_INTERP0_CTRL_LANE0_BLEND_LSB _U(21)
+#define SIO_INTERP0_CTRL_LANE0_BLEND_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_BLEND_BITS _u(0x00200000)
+#define SIO_INTERP0_CTRL_LANE0_BLEND_MSB _u(21)
+#define SIO_INTERP0_CTRL_LANE0_BLEND_LSB _u(21)
#define SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE0_FORCE_MSB
@@ -606,28 +606,28 @@
// No effect on the internal 32-bit datapath. Handy for using a
// lane to generate sequence
// of pointers into flash or SRAM.
-#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET _U(0x0)
-#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS _U(0x00180000)
-#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB _U(20)
-#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB _U(19)
+#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000)
+#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB _u(20)
+#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB _u(19)
#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE0_ADD_RAW
// Description : If 1, mask + shift is bypassed for LANE0 result. This does not
// affect FULL result.
-#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET _U(0x0)
-#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS _U(0x00040000)
-#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB _U(18)
-#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB _U(18)
+#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000)
+#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB _u(18)
+#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB _u(18)
#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE0_CROSS_RESULT
// Description : If 1, feed the opposite lane's result into this lane's
// accumulator on POP.
-#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET _U(0x0)
-#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS _U(0x00020000)
-#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB _U(17)
-#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB _U(17)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB _u(17)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB _u(17)
#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE0_CROSS_INPUT
@@ -635,10 +635,10 @@
// shift + mask hardware.
// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is
// before the shift+mask bypass)
-#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET _U(0x0)
-#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS _U(0x00010000)
-#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB _U(16)
-#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB _U(16)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB _u(16)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB _u(16)
#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE0_SIGNED
@@ -646,44 +646,44 @@
// sign-extended to 32 bits
// before adding to BASE0, and LANE0 PEEK/POP appear extended to
// 32 bits when read by processor.
-#define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET _U(0x0)
-#define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS _U(0x00008000)
-#define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB _U(15)
-#define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB _U(15)
+#define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS _u(0x00008000)
+#define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB _u(15)
+#define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB _u(15)
#define SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE0_MASK_MSB
// Description : The most-significant bit allowed to pass by the mask
// (inclusive)
// Setting MSB < LSB may cause chip to turn inside-out
-#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET _U(0x00)
-#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS _U(0x00007c00)
-#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB _U(14)
-#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB _U(10)
+#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET _u(0x00)
+#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00)
+#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB _u(14)
+#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB _u(10)
#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE0_MASK_LSB
// Description : The least-significant bit allowed to pass by the mask
// (inclusive)
-#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET _U(0x00)
-#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS _U(0x000003e0)
-#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB _U(9)
-#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB _U(5)
+#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET _u(0x00)
+#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0)
+#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB _u(9)
+#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB _u(5)
#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE0_SHIFT
// Description : Logical right-shift applied to accumulator before masking
-#define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET _U(0x00)
-#define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS _U(0x0000001f)
-#define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB _U(4)
-#define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB _U(0)
+#define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET _u(0x00)
+#define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS _u(0x0000001f)
+#define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB _u(4)
+#define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB _u(0)
#define SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP0_CTRL_LANE1
// Description : Control register for lane 1
-#define SIO_INTERP0_CTRL_LANE1_OFFSET _U(0x000000b0)
-#define SIO_INTERP0_CTRL_LANE1_BITS _U(0x001fffff)
-#define SIO_INTERP0_CTRL_LANE1_RESET _U(0x00000000)
+#define SIO_INTERP0_CTRL_LANE1_OFFSET _u(0x000000b0)
+#define SIO_INTERP0_CTRL_LANE1_BITS _u(0x001fffff)
+#define SIO_INTERP0_CTRL_LANE1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE1_FORCE_MSB
// Description : ORed into bits 29:28 of the lane result presented to the
@@ -691,28 +691,28 @@
// No effect on the internal 32-bit datapath. Handy for using a
// lane to generate sequence
// of pointers into flash or SRAM.
-#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET _U(0x0)
-#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS _U(0x00180000)
-#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB _U(20)
-#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB _U(19)
+#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000)
+#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB _u(20)
+#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB _u(19)
#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE1_ADD_RAW
// Description : If 1, mask + shift is bypassed for LANE1 result. This does not
// affect FULL result.
-#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET _U(0x0)
-#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS _U(0x00040000)
-#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB _U(18)
-#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB _U(18)
+#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000)
+#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB _u(18)
+#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB _u(18)
#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE1_CROSS_RESULT
// Description : If 1, feed the opposite lane's result into this lane's
// accumulator on POP.
-#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET _U(0x0)
-#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS _U(0x00020000)
-#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB _U(17)
-#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB _U(17)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB _u(17)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB _u(17)
#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE1_CROSS_INPUT
@@ -720,10 +720,10 @@
// shift + mask hardware.
// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is
// before the shift+mask bypass)
-#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET _U(0x0)
-#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS _U(0x00010000)
-#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB _U(16)
-#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB _U(16)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB _u(16)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB _u(16)
#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE1_SIGNED
@@ -731,59 +731,59 @@
// sign-extended to 32 bits
// before adding to BASE1, and LANE1 PEEK/POP appear extended to
// 32 bits when read by processor.
-#define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET _U(0x0)
-#define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS _U(0x00008000)
-#define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB _U(15)
-#define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB _U(15)
+#define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS _u(0x00008000)
+#define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB _u(15)
+#define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB _u(15)
#define SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE1_MASK_MSB
// Description : The most-significant bit allowed to pass by the mask
// (inclusive)
// Setting MSB < LSB may cause chip to turn inside-out
-#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET _U(0x00)
-#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS _U(0x00007c00)
-#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB _U(14)
-#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB _U(10)
+#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET _u(0x00)
+#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00)
+#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB _u(14)
+#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB _u(10)
#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE1_MASK_LSB
// Description : The least-significant bit allowed to pass by the mask
// (inclusive)
-#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET _U(0x00)
-#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS _U(0x000003e0)
-#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB _U(9)
-#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB _U(5)
+#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET _u(0x00)
+#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0)
+#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB _u(9)
+#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB _u(5)
#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP0_CTRL_LANE1_SHIFT
// Description : Logical right-shift applied to accumulator before masking
-#define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET _U(0x00)
-#define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS _U(0x0000001f)
-#define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB _U(4)
-#define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB _U(0)
+#define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET _u(0x00)
+#define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS _u(0x0000001f)
+#define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB _u(4)
+#define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB _u(0)
#define SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP0_ACCUM0_ADD
// Description : Values written here are atomically added to ACCUM0
// Reading yields lane 0's raw shift and mask value (BASE0 not
// added).
-#define SIO_INTERP0_ACCUM0_ADD_OFFSET _U(0x000000b4)
-#define SIO_INTERP0_ACCUM0_ADD_BITS _U(0x00ffffff)
-#define SIO_INTERP0_ACCUM0_ADD_RESET _U(0x00000000)
-#define SIO_INTERP0_ACCUM0_ADD_MSB _U(23)
-#define SIO_INTERP0_ACCUM0_ADD_LSB _U(0)
+#define SIO_INTERP0_ACCUM0_ADD_OFFSET _u(0x000000b4)
+#define SIO_INTERP0_ACCUM0_ADD_BITS _u(0x00ffffff)
+#define SIO_INTERP0_ACCUM0_ADD_RESET _u(0x00000000)
+#define SIO_INTERP0_ACCUM0_ADD_MSB _u(23)
+#define SIO_INTERP0_ACCUM0_ADD_LSB _u(0)
#define SIO_INTERP0_ACCUM0_ADD_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP0_ACCUM1_ADD
// Description : Values written here are atomically added to ACCUM1
// Reading yields lane 1's raw shift and mask value (BASE1 not
// added).
-#define SIO_INTERP0_ACCUM1_ADD_OFFSET _U(0x000000b8)
-#define SIO_INTERP0_ACCUM1_ADD_BITS _U(0x00ffffff)
-#define SIO_INTERP0_ACCUM1_ADD_RESET _U(0x00000000)
-#define SIO_INTERP0_ACCUM1_ADD_MSB _U(23)
-#define SIO_INTERP0_ACCUM1_ADD_LSB _U(0)
+#define SIO_INTERP0_ACCUM1_ADD_OFFSET _u(0x000000b8)
+#define SIO_INTERP0_ACCUM1_ADD_BITS _u(0x00ffffff)
+#define SIO_INTERP0_ACCUM1_ADD_RESET _u(0x00000000)
+#define SIO_INTERP0_ACCUM1_ADD_MSB _u(23)
+#define SIO_INTERP0_ACCUM1_ADD_LSB _u(0)
#define SIO_INTERP0_ACCUM1_ADD_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP0_BASE_1AND0
@@ -791,143 +791,143 @@
// simultaneously.
// Each half is sign-extended to 32 bits if that lane's SIGNED
// flag is set.
-#define SIO_INTERP0_BASE_1AND0_OFFSET _U(0x000000bc)
-#define SIO_INTERP0_BASE_1AND0_BITS _U(0xffffffff)
-#define SIO_INTERP0_BASE_1AND0_RESET _U(0x00000000)
-#define SIO_INTERP0_BASE_1AND0_MSB _U(31)
-#define SIO_INTERP0_BASE_1AND0_LSB _U(0)
+#define SIO_INTERP0_BASE_1AND0_OFFSET _u(0x000000bc)
+#define SIO_INTERP0_BASE_1AND0_BITS _u(0xffffffff)
+#define SIO_INTERP0_BASE_1AND0_RESET _u(0x00000000)
+#define SIO_INTERP0_BASE_1AND0_MSB _u(31)
+#define SIO_INTERP0_BASE_1AND0_LSB _u(0)
#define SIO_INTERP0_BASE_1AND0_ACCESS "WO"
// =============================================================================
// Register : SIO_INTERP1_ACCUM0
// Description : Read/write access to accumulator 0
-#define SIO_INTERP1_ACCUM0_OFFSET _U(0x000000c0)
-#define SIO_INTERP1_ACCUM0_BITS _U(0xffffffff)
-#define SIO_INTERP1_ACCUM0_RESET _U(0x00000000)
-#define SIO_INTERP1_ACCUM0_MSB _U(31)
-#define SIO_INTERP1_ACCUM0_LSB _U(0)
+#define SIO_INTERP1_ACCUM0_OFFSET _u(0x000000c0)
+#define SIO_INTERP1_ACCUM0_BITS _u(0xffffffff)
+#define SIO_INTERP1_ACCUM0_RESET _u(0x00000000)
+#define SIO_INTERP1_ACCUM0_MSB _u(31)
+#define SIO_INTERP1_ACCUM0_LSB _u(0)
#define SIO_INTERP1_ACCUM0_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP1_ACCUM1
// Description : Read/write access to accumulator 1
-#define SIO_INTERP1_ACCUM1_OFFSET _U(0x000000c4)
-#define SIO_INTERP1_ACCUM1_BITS _U(0xffffffff)
-#define SIO_INTERP1_ACCUM1_RESET _U(0x00000000)
-#define SIO_INTERP1_ACCUM1_MSB _U(31)
-#define SIO_INTERP1_ACCUM1_LSB _U(0)
+#define SIO_INTERP1_ACCUM1_OFFSET _u(0x000000c4)
+#define SIO_INTERP1_ACCUM1_BITS _u(0xffffffff)
+#define SIO_INTERP1_ACCUM1_RESET _u(0x00000000)
+#define SIO_INTERP1_ACCUM1_MSB _u(31)
+#define SIO_INTERP1_ACCUM1_LSB _u(0)
#define SIO_INTERP1_ACCUM1_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP1_BASE0
// Description : Read/write access to BASE0 register.
-#define SIO_INTERP1_BASE0_OFFSET _U(0x000000c8)
-#define SIO_INTERP1_BASE0_BITS _U(0xffffffff)
-#define SIO_INTERP1_BASE0_RESET _U(0x00000000)
-#define SIO_INTERP1_BASE0_MSB _U(31)
-#define SIO_INTERP1_BASE0_LSB _U(0)
+#define SIO_INTERP1_BASE0_OFFSET _u(0x000000c8)
+#define SIO_INTERP1_BASE0_BITS _u(0xffffffff)
+#define SIO_INTERP1_BASE0_RESET _u(0x00000000)
+#define SIO_INTERP1_BASE0_MSB _u(31)
+#define SIO_INTERP1_BASE0_LSB _u(0)
#define SIO_INTERP1_BASE0_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP1_BASE1
// Description : Read/write access to BASE1 register.
-#define SIO_INTERP1_BASE1_OFFSET _U(0x000000cc)
-#define SIO_INTERP1_BASE1_BITS _U(0xffffffff)
-#define SIO_INTERP1_BASE1_RESET _U(0x00000000)
-#define SIO_INTERP1_BASE1_MSB _U(31)
-#define SIO_INTERP1_BASE1_LSB _U(0)
+#define SIO_INTERP1_BASE1_OFFSET _u(0x000000cc)
+#define SIO_INTERP1_BASE1_BITS _u(0xffffffff)
+#define SIO_INTERP1_BASE1_RESET _u(0x00000000)
+#define SIO_INTERP1_BASE1_MSB _u(31)
+#define SIO_INTERP1_BASE1_LSB _u(0)
#define SIO_INTERP1_BASE1_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP1_BASE2
// Description : Read/write access to BASE2 register.
-#define SIO_INTERP1_BASE2_OFFSET _U(0x000000d0)
-#define SIO_INTERP1_BASE2_BITS _U(0xffffffff)
-#define SIO_INTERP1_BASE2_RESET _U(0x00000000)
-#define SIO_INTERP1_BASE2_MSB _U(31)
-#define SIO_INTERP1_BASE2_LSB _U(0)
+#define SIO_INTERP1_BASE2_OFFSET _u(0x000000d0)
+#define SIO_INTERP1_BASE2_BITS _u(0xffffffff)
+#define SIO_INTERP1_BASE2_RESET _u(0x00000000)
+#define SIO_INTERP1_BASE2_MSB _u(31)
+#define SIO_INTERP1_BASE2_LSB _u(0)
#define SIO_INTERP1_BASE2_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP1_POP_LANE0
// Description : Read LANE0 result, and simultaneously write lane results to
// both accumulators (POP).
-#define SIO_INTERP1_POP_LANE0_OFFSET _U(0x000000d4)
-#define SIO_INTERP1_POP_LANE0_BITS _U(0xffffffff)
-#define SIO_INTERP1_POP_LANE0_RESET _U(0x00000000)
-#define SIO_INTERP1_POP_LANE0_MSB _U(31)
-#define SIO_INTERP1_POP_LANE0_LSB _U(0)
+#define SIO_INTERP1_POP_LANE0_OFFSET _u(0x000000d4)
+#define SIO_INTERP1_POP_LANE0_BITS _u(0xffffffff)
+#define SIO_INTERP1_POP_LANE0_RESET _u(0x00000000)
+#define SIO_INTERP1_POP_LANE0_MSB _u(31)
+#define SIO_INTERP1_POP_LANE0_LSB _u(0)
#define SIO_INTERP1_POP_LANE0_ACCESS "RO"
// =============================================================================
// Register : SIO_INTERP1_POP_LANE1
// Description : Read LANE1 result, and simultaneously write lane results to
// both accumulators (POP).
-#define SIO_INTERP1_POP_LANE1_OFFSET _U(0x000000d8)
-#define SIO_INTERP1_POP_LANE1_BITS _U(0xffffffff)
-#define SIO_INTERP1_POP_LANE1_RESET _U(0x00000000)
-#define SIO_INTERP1_POP_LANE1_MSB _U(31)
-#define SIO_INTERP1_POP_LANE1_LSB _U(0)
+#define SIO_INTERP1_POP_LANE1_OFFSET _u(0x000000d8)
+#define SIO_INTERP1_POP_LANE1_BITS _u(0xffffffff)
+#define SIO_INTERP1_POP_LANE1_RESET _u(0x00000000)
+#define SIO_INTERP1_POP_LANE1_MSB _u(31)
+#define SIO_INTERP1_POP_LANE1_LSB _u(0)
#define SIO_INTERP1_POP_LANE1_ACCESS "RO"
// =============================================================================
// Register : SIO_INTERP1_POP_FULL
// Description : Read FULL result, and simultaneously write lane results to both
// accumulators (POP).
-#define SIO_INTERP1_POP_FULL_OFFSET _U(0x000000dc)
-#define SIO_INTERP1_POP_FULL_BITS _U(0xffffffff)
-#define SIO_INTERP1_POP_FULL_RESET _U(0x00000000)
-#define SIO_INTERP1_POP_FULL_MSB _U(31)
-#define SIO_INTERP1_POP_FULL_LSB _U(0)
+#define SIO_INTERP1_POP_FULL_OFFSET _u(0x000000dc)
+#define SIO_INTERP1_POP_FULL_BITS _u(0xffffffff)
+#define SIO_INTERP1_POP_FULL_RESET _u(0x00000000)
+#define SIO_INTERP1_POP_FULL_MSB _u(31)
+#define SIO_INTERP1_POP_FULL_LSB _u(0)
#define SIO_INTERP1_POP_FULL_ACCESS "RO"
// =============================================================================
// Register : SIO_INTERP1_PEEK_LANE0
// Description : Read LANE0 result, without altering any internal state (PEEK).
-#define SIO_INTERP1_PEEK_LANE0_OFFSET _U(0x000000e0)
-#define SIO_INTERP1_PEEK_LANE0_BITS _U(0xffffffff)
-#define SIO_INTERP1_PEEK_LANE0_RESET _U(0x00000000)
-#define SIO_INTERP1_PEEK_LANE0_MSB _U(31)
-#define SIO_INTERP1_PEEK_LANE0_LSB _U(0)
+#define SIO_INTERP1_PEEK_LANE0_OFFSET _u(0x000000e0)
+#define SIO_INTERP1_PEEK_LANE0_BITS _u(0xffffffff)
+#define SIO_INTERP1_PEEK_LANE0_RESET _u(0x00000000)
+#define SIO_INTERP1_PEEK_LANE0_MSB _u(31)
+#define SIO_INTERP1_PEEK_LANE0_LSB _u(0)
#define SIO_INTERP1_PEEK_LANE0_ACCESS "RO"
// =============================================================================
// Register : SIO_INTERP1_PEEK_LANE1
// Description : Read LANE1 result, without altering any internal state (PEEK).
-#define SIO_INTERP1_PEEK_LANE1_OFFSET _U(0x000000e4)
-#define SIO_INTERP1_PEEK_LANE1_BITS _U(0xffffffff)
-#define SIO_INTERP1_PEEK_LANE1_RESET _U(0x00000000)
-#define SIO_INTERP1_PEEK_LANE1_MSB _U(31)
-#define SIO_INTERP1_PEEK_LANE1_LSB _U(0)
+#define SIO_INTERP1_PEEK_LANE1_OFFSET _u(0x000000e4)
+#define SIO_INTERP1_PEEK_LANE1_BITS _u(0xffffffff)
+#define SIO_INTERP1_PEEK_LANE1_RESET _u(0x00000000)
+#define SIO_INTERP1_PEEK_LANE1_MSB _u(31)
+#define SIO_INTERP1_PEEK_LANE1_LSB _u(0)
#define SIO_INTERP1_PEEK_LANE1_ACCESS "RO"
// =============================================================================
// Register : SIO_INTERP1_PEEK_FULL
// Description : Read FULL result, without altering any internal state (PEEK).
-#define SIO_INTERP1_PEEK_FULL_OFFSET _U(0x000000e8)
-#define SIO_INTERP1_PEEK_FULL_BITS _U(0xffffffff)
-#define SIO_INTERP1_PEEK_FULL_RESET _U(0x00000000)
-#define SIO_INTERP1_PEEK_FULL_MSB _U(31)
-#define SIO_INTERP1_PEEK_FULL_LSB _U(0)
+#define SIO_INTERP1_PEEK_FULL_OFFSET _u(0x000000e8)
+#define SIO_INTERP1_PEEK_FULL_BITS _u(0xffffffff)
+#define SIO_INTERP1_PEEK_FULL_RESET _u(0x00000000)
+#define SIO_INTERP1_PEEK_FULL_MSB _u(31)
+#define SIO_INTERP1_PEEK_FULL_LSB _u(0)
#define SIO_INTERP1_PEEK_FULL_ACCESS "RO"
// =============================================================================
// Register : SIO_INTERP1_CTRL_LANE0
// Description : Control register for lane 0
-#define SIO_INTERP1_CTRL_LANE0_OFFSET _U(0x000000ec)
-#define SIO_INTERP1_CTRL_LANE0_BITS _U(0x03dfffff)
-#define SIO_INTERP1_CTRL_LANE0_RESET _U(0x00000000)
+#define SIO_INTERP1_CTRL_LANE0_OFFSET _u(0x000000ec)
+#define SIO_INTERP1_CTRL_LANE0_BITS _u(0x03dfffff)
+#define SIO_INTERP1_CTRL_LANE0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE0_OVERF
// Description : Set if either OVERF0 or OVERF1 is set.
-#define SIO_INTERP1_CTRL_LANE0_OVERF_RESET _U(0x0)
-#define SIO_INTERP1_CTRL_LANE0_OVERF_BITS _U(0x02000000)
-#define SIO_INTERP1_CTRL_LANE0_OVERF_MSB _U(25)
-#define SIO_INTERP1_CTRL_LANE0_OVERF_LSB _U(25)
+#define SIO_INTERP1_CTRL_LANE0_OVERF_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_OVERF_BITS _u(0x02000000)
+#define SIO_INTERP1_CTRL_LANE0_OVERF_MSB _u(25)
+#define SIO_INTERP1_CTRL_LANE0_OVERF_LSB _u(25)
#define SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE0_OVERF1
// Description : Indicates if any masked-off MSBs in ACCUM1 are set.
-#define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET _U(0x0)
-#define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS _U(0x01000000)
-#define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB _U(24)
-#define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB _U(24)
+#define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS _u(0x01000000)
+#define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB _u(24)
+#define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB _u(24)
#define SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE0_OVERF0
// Description : Indicates if any masked-off MSBs in ACCUM0 are set.
-#define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET _U(0x0)
-#define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS _U(0x00800000)
-#define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB _U(23)
-#define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB _U(23)
+#define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS _u(0x00800000)
+#define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB _u(23)
+#define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB _u(23)
#define SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE0_CLAMP
@@ -937,10 +937,10 @@
// BASE0 and an upper bound of BASE1.
// - Signedness of these comparisons is determined by
// LANE0_CTRL_SIGNED
-#define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET _U(0x0)
-#define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS _U(0x00400000)
-#define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB _U(22)
-#define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB _U(22)
+#define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS _u(0x00400000)
+#define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB _u(22)
+#define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB _u(22)
#define SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE0_FORCE_MSB
@@ -949,28 +949,28 @@
// No effect on the internal 32-bit datapath. Handy for using a
// lane to generate sequence
// of pointers into flash or SRAM.
-#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET _U(0x0)
-#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS _U(0x00180000)
-#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB _U(20)
-#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB _U(19)
+#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000)
+#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB _u(20)
+#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB _u(19)
#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE0_ADD_RAW
// Description : If 1, mask + shift is bypassed for LANE0 result. This does not
// affect FULL result.
-#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET _U(0x0)
-#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS _U(0x00040000)
-#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB _U(18)
-#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB _U(18)
+#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000)
+#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB _u(18)
+#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB _u(18)
#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE0_CROSS_RESULT
// Description : If 1, feed the opposite lane's result into this lane's
// accumulator on POP.
-#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET _U(0x0)
-#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS _U(0x00020000)
-#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB _U(17)
-#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB _U(17)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB _u(17)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB _u(17)
#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE0_CROSS_INPUT
@@ -978,10 +978,10 @@
// shift + mask hardware.
// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is
// before the shift+mask bypass)
-#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET _U(0x0)
-#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS _U(0x00010000)
-#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB _U(16)
-#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB _U(16)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB _u(16)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB _u(16)
#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE0_SIGNED
@@ -989,44 +989,44 @@
// sign-extended to 32 bits
// before adding to BASE0, and LANE0 PEEK/POP appear extended to
// 32 bits when read by processor.
-#define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET _U(0x0)
-#define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS _U(0x00008000)
-#define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB _U(15)
-#define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB _U(15)
+#define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS _u(0x00008000)
+#define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB _u(15)
+#define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB _u(15)
#define SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE0_MASK_MSB
// Description : The most-significant bit allowed to pass by the mask
// (inclusive)
// Setting MSB < LSB may cause chip to turn inside-out
-#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET _U(0x00)
-#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS _U(0x00007c00)
-#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB _U(14)
-#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB _U(10)
+#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET _u(0x00)
+#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00)
+#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB _u(14)
+#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB _u(10)
#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE0_MASK_LSB
// Description : The least-significant bit allowed to pass by the mask
// (inclusive)
-#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET _U(0x00)
-#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS _U(0x000003e0)
-#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB _U(9)
-#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB _U(5)
+#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET _u(0x00)
+#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0)
+#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB _u(9)
+#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB _u(5)
#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE0_SHIFT
// Description : Logical right-shift applied to accumulator before masking
-#define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET _U(0x00)
-#define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS _U(0x0000001f)
-#define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB _U(4)
-#define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB _U(0)
+#define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET _u(0x00)
+#define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS _u(0x0000001f)
+#define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB _u(4)
+#define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB _u(0)
#define SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP1_CTRL_LANE1
// Description : Control register for lane 1
-#define SIO_INTERP1_CTRL_LANE1_OFFSET _U(0x000000f0)
-#define SIO_INTERP1_CTRL_LANE1_BITS _U(0x001fffff)
-#define SIO_INTERP1_CTRL_LANE1_RESET _U(0x00000000)
+#define SIO_INTERP1_CTRL_LANE1_OFFSET _u(0x000000f0)
+#define SIO_INTERP1_CTRL_LANE1_BITS _u(0x001fffff)
+#define SIO_INTERP1_CTRL_LANE1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE1_FORCE_MSB
// Description : ORed into bits 29:28 of the lane result presented to the
@@ -1034,28 +1034,28 @@
// No effect on the internal 32-bit datapath. Handy for using a
// lane to generate sequence
// of pointers into flash or SRAM.
-#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET _U(0x0)
-#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS _U(0x00180000)
-#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB _U(20)
-#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB _U(19)
+#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000)
+#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB _u(20)
+#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB _u(19)
#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE1_ADD_RAW
// Description : If 1, mask + shift is bypassed for LANE1 result. This does not
// affect FULL result.
-#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET _U(0x0)
-#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS _U(0x00040000)
-#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB _U(18)
-#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB _U(18)
+#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000)
+#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB _u(18)
+#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB _u(18)
#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE1_CROSS_RESULT
// Description : If 1, feed the opposite lane's result into this lane's
// accumulator on POP.
-#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET _U(0x0)
-#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS _U(0x00020000)
-#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB _U(17)
-#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB _U(17)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB _u(17)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB _u(17)
#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE1_CROSS_INPUT
@@ -1063,10 +1063,10 @@
// shift + mask hardware.
// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is
// before the shift+mask bypass)
-#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET _U(0x0)
-#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS _U(0x00010000)
-#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB _U(16)
-#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB _U(16)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB _u(16)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB _u(16)
#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE1_SIGNED
@@ -1074,59 +1074,59 @@
// sign-extended to 32 bits
// before adding to BASE1, and LANE1 PEEK/POP appear extended to
// 32 bits when read by processor.
-#define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET _U(0x0)
-#define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS _U(0x00008000)
-#define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB _U(15)
-#define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB _U(15)
+#define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS _u(0x00008000)
+#define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB _u(15)
+#define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB _u(15)
#define SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE1_MASK_MSB
// Description : The most-significant bit allowed to pass by the mask
// (inclusive)
// Setting MSB < LSB may cause chip to turn inside-out
-#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET _U(0x00)
-#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS _U(0x00007c00)
-#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB _U(14)
-#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB _U(10)
+#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET _u(0x00)
+#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00)
+#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB _u(14)
+#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB _u(10)
#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE1_MASK_LSB
// Description : The least-significant bit allowed to pass by the mask
// (inclusive)
-#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET _U(0x00)
-#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS _U(0x000003e0)
-#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB _U(9)
-#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB _U(5)
+#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET _u(0x00)
+#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0)
+#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB _u(9)
+#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB _u(5)
#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SIO_INTERP1_CTRL_LANE1_SHIFT
// Description : Logical right-shift applied to accumulator before masking
-#define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET _U(0x00)
-#define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS _U(0x0000001f)
-#define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB _U(4)
-#define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB _U(0)
+#define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET _u(0x00)
+#define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS _u(0x0000001f)
+#define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB _u(4)
+#define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB _u(0)
#define SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP1_ACCUM0_ADD
// Description : Values written here are atomically added to ACCUM0
// Reading yields lane 0's raw shift and mask value (BASE0 not
// added).
-#define SIO_INTERP1_ACCUM0_ADD_OFFSET _U(0x000000f4)
-#define SIO_INTERP1_ACCUM0_ADD_BITS _U(0x00ffffff)
-#define SIO_INTERP1_ACCUM0_ADD_RESET _U(0x00000000)
-#define SIO_INTERP1_ACCUM0_ADD_MSB _U(23)
-#define SIO_INTERP1_ACCUM0_ADD_LSB _U(0)
+#define SIO_INTERP1_ACCUM0_ADD_OFFSET _u(0x000000f4)
+#define SIO_INTERP1_ACCUM0_ADD_BITS _u(0x00ffffff)
+#define SIO_INTERP1_ACCUM0_ADD_RESET _u(0x00000000)
+#define SIO_INTERP1_ACCUM0_ADD_MSB _u(23)
+#define SIO_INTERP1_ACCUM0_ADD_LSB _u(0)
#define SIO_INTERP1_ACCUM0_ADD_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP1_ACCUM1_ADD
// Description : Values written here are atomically added to ACCUM1
// Reading yields lane 1's raw shift and mask value (BASE1 not
// added).
-#define SIO_INTERP1_ACCUM1_ADD_OFFSET _U(0x000000f8)
-#define SIO_INTERP1_ACCUM1_ADD_BITS _U(0x00ffffff)
-#define SIO_INTERP1_ACCUM1_ADD_RESET _U(0x00000000)
-#define SIO_INTERP1_ACCUM1_ADD_MSB _U(23)
-#define SIO_INTERP1_ACCUM1_ADD_LSB _U(0)
+#define SIO_INTERP1_ACCUM1_ADD_OFFSET _u(0x000000f8)
+#define SIO_INTERP1_ACCUM1_ADD_BITS _u(0x00ffffff)
+#define SIO_INTERP1_ACCUM1_ADD_RESET _u(0x00000000)
+#define SIO_INTERP1_ACCUM1_ADD_MSB _u(23)
+#define SIO_INTERP1_ACCUM1_ADD_LSB _u(0)
#define SIO_INTERP1_ACCUM1_ADD_ACCESS "RW"
// =============================================================================
// Register : SIO_INTERP1_BASE_1AND0
@@ -1134,11 +1134,11 @@
// simultaneously.
// Each half is sign-extended to 32 bits if that lane's SIGNED
// flag is set.
-#define SIO_INTERP1_BASE_1AND0_OFFSET _U(0x000000fc)
-#define SIO_INTERP1_BASE_1AND0_BITS _U(0xffffffff)
-#define SIO_INTERP1_BASE_1AND0_RESET _U(0x00000000)
-#define SIO_INTERP1_BASE_1AND0_MSB _U(31)
-#define SIO_INTERP1_BASE_1AND0_LSB _U(0)
+#define SIO_INTERP1_BASE_1AND0_OFFSET _u(0x000000fc)
+#define SIO_INTERP1_BASE_1AND0_BITS _u(0xffffffff)
+#define SIO_INTERP1_BASE_1AND0_RESET _u(0x00000000)
+#define SIO_INTERP1_BASE_1AND0_MSB _u(31)
+#define SIO_INTERP1_BASE_1AND0_LSB _u(0)
#define SIO_INTERP1_BASE_1AND0_ACCESS "WO"
// =============================================================================
// Register : SIO_SPINLOCK0
@@ -1150,11 +1150,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK0_OFFSET _U(0x00000100)
-#define SIO_SPINLOCK0_BITS _U(0xffffffff)
-#define SIO_SPINLOCK0_RESET _U(0x00000000)
-#define SIO_SPINLOCK0_MSB _U(31)
-#define SIO_SPINLOCK0_LSB _U(0)
+#define SIO_SPINLOCK0_OFFSET _u(0x00000100)
+#define SIO_SPINLOCK0_BITS _u(0xffffffff)
+#define SIO_SPINLOCK0_RESET _u(0x00000000)
+#define SIO_SPINLOCK0_MSB _u(31)
+#define SIO_SPINLOCK0_LSB _u(0)
#define SIO_SPINLOCK0_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK1
@@ -1166,11 +1166,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK1_OFFSET _U(0x00000104)
-#define SIO_SPINLOCK1_BITS _U(0xffffffff)
-#define SIO_SPINLOCK1_RESET _U(0x00000000)
-#define SIO_SPINLOCK1_MSB _U(31)
-#define SIO_SPINLOCK1_LSB _U(0)
+#define SIO_SPINLOCK1_OFFSET _u(0x00000104)
+#define SIO_SPINLOCK1_BITS _u(0xffffffff)
+#define SIO_SPINLOCK1_RESET _u(0x00000000)
+#define SIO_SPINLOCK1_MSB _u(31)
+#define SIO_SPINLOCK1_LSB _u(0)
#define SIO_SPINLOCK1_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK2
@@ -1182,11 +1182,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK2_OFFSET _U(0x00000108)
-#define SIO_SPINLOCK2_BITS _U(0xffffffff)
-#define SIO_SPINLOCK2_RESET _U(0x00000000)
-#define SIO_SPINLOCK2_MSB _U(31)
-#define SIO_SPINLOCK2_LSB _U(0)
+#define SIO_SPINLOCK2_OFFSET _u(0x00000108)
+#define SIO_SPINLOCK2_BITS _u(0xffffffff)
+#define SIO_SPINLOCK2_RESET _u(0x00000000)
+#define SIO_SPINLOCK2_MSB _u(31)
+#define SIO_SPINLOCK2_LSB _u(0)
#define SIO_SPINLOCK2_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK3
@@ -1198,11 +1198,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK3_OFFSET _U(0x0000010c)
-#define SIO_SPINLOCK3_BITS _U(0xffffffff)
-#define SIO_SPINLOCK3_RESET _U(0x00000000)
-#define SIO_SPINLOCK3_MSB _U(31)
-#define SIO_SPINLOCK3_LSB _U(0)
+#define SIO_SPINLOCK3_OFFSET _u(0x0000010c)
+#define SIO_SPINLOCK3_BITS _u(0xffffffff)
+#define SIO_SPINLOCK3_RESET _u(0x00000000)
+#define SIO_SPINLOCK3_MSB _u(31)
+#define SIO_SPINLOCK3_LSB _u(0)
#define SIO_SPINLOCK3_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK4
@@ -1214,11 +1214,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK4_OFFSET _U(0x00000110)
-#define SIO_SPINLOCK4_BITS _U(0xffffffff)
-#define SIO_SPINLOCK4_RESET _U(0x00000000)
-#define SIO_SPINLOCK4_MSB _U(31)
-#define SIO_SPINLOCK4_LSB _U(0)
+#define SIO_SPINLOCK4_OFFSET _u(0x00000110)
+#define SIO_SPINLOCK4_BITS _u(0xffffffff)
+#define SIO_SPINLOCK4_RESET _u(0x00000000)
+#define SIO_SPINLOCK4_MSB _u(31)
+#define SIO_SPINLOCK4_LSB _u(0)
#define SIO_SPINLOCK4_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK5
@@ -1230,11 +1230,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK5_OFFSET _U(0x00000114)
-#define SIO_SPINLOCK5_BITS _U(0xffffffff)
-#define SIO_SPINLOCK5_RESET _U(0x00000000)
-#define SIO_SPINLOCK5_MSB _U(31)
-#define SIO_SPINLOCK5_LSB _U(0)
+#define SIO_SPINLOCK5_OFFSET _u(0x00000114)
+#define SIO_SPINLOCK5_BITS _u(0xffffffff)
+#define SIO_SPINLOCK5_RESET _u(0x00000000)
+#define SIO_SPINLOCK5_MSB _u(31)
+#define SIO_SPINLOCK5_LSB _u(0)
#define SIO_SPINLOCK5_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK6
@@ -1246,11 +1246,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK6_OFFSET _U(0x00000118)
-#define SIO_SPINLOCK6_BITS _U(0xffffffff)
-#define SIO_SPINLOCK6_RESET _U(0x00000000)
-#define SIO_SPINLOCK6_MSB _U(31)
-#define SIO_SPINLOCK6_LSB _U(0)
+#define SIO_SPINLOCK6_OFFSET _u(0x00000118)
+#define SIO_SPINLOCK6_BITS _u(0xffffffff)
+#define SIO_SPINLOCK6_RESET _u(0x00000000)
+#define SIO_SPINLOCK6_MSB _u(31)
+#define SIO_SPINLOCK6_LSB _u(0)
#define SIO_SPINLOCK6_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK7
@@ -1262,11 +1262,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK7_OFFSET _U(0x0000011c)
-#define SIO_SPINLOCK7_BITS _U(0xffffffff)
-#define SIO_SPINLOCK7_RESET _U(0x00000000)
-#define SIO_SPINLOCK7_MSB _U(31)
-#define SIO_SPINLOCK7_LSB _U(0)
+#define SIO_SPINLOCK7_OFFSET _u(0x0000011c)
+#define SIO_SPINLOCK7_BITS _u(0xffffffff)
+#define SIO_SPINLOCK7_RESET _u(0x00000000)
+#define SIO_SPINLOCK7_MSB _u(31)
+#define SIO_SPINLOCK7_LSB _u(0)
#define SIO_SPINLOCK7_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK8
@@ -1278,11 +1278,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK8_OFFSET _U(0x00000120)
-#define SIO_SPINLOCK8_BITS _U(0xffffffff)
-#define SIO_SPINLOCK8_RESET _U(0x00000000)
-#define SIO_SPINLOCK8_MSB _U(31)
-#define SIO_SPINLOCK8_LSB _U(0)
+#define SIO_SPINLOCK8_OFFSET _u(0x00000120)
+#define SIO_SPINLOCK8_BITS _u(0xffffffff)
+#define SIO_SPINLOCK8_RESET _u(0x00000000)
+#define SIO_SPINLOCK8_MSB _u(31)
+#define SIO_SPINLOCK8_LSB _u(0)
#define SIO_SPINLOCK8_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK9
@@ -1294,11 +1294,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK9_OFFSET _U(0x00000124)
-#define SIO_SPINLOCK9_BITS _U(0xffffffff)
-#define SIO_SPINLOCK9_RESET _U(0x00000000)
-#define SIO_SPINLOCK9_MSB _U(31)
-#define SIO_SPINLOCK9_LSB _U(0)
+#define SIO_SPINLOCK9_OFFSET _u(0x00000124)
+#define SIO_SPINLOCK9_BITS _u(0xffffffff)
+#define SIO_SPINLOCK9_RESET _u(0x00000000)
+#define SIO_SPINLOCK9_MSB _u(31)
+#define SIO_SPINLOCK9_LSB _u(0)
#define SIO_SPINLOCK9_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK10
@@ -1310,11 +1310,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK10_OFFSET _U(0x00000128)
-#define SIO_SPINLOCK10_BITS _U(0xffffffff)
-#define SIO_SPINLOCK10_RESET _U(0x00000000)
-#define SIO_SPINLOCK10_MSB _U(31)
-#define SIO_SPINLOCK10_LSB _U(0)
+#define SIO_SPINLOCK10_OFFSET _u(0x00000128)
+#define SIO_SPINLOCK10_BITS _u(0xffffffff)
+#define SIO_SPINLOCK10_RESET _u(0x00000000)
+#define SIO_SPINLOCK10_MSB _u(31)
+#define SIO_SPINLOCK10_LSB _u(0)
#define SIO_SPINLOCK10_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK11
@@ -1326,11 +1326,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK11_OFFSET _U(0x0000012c)
-#define SIO_SPINLOCK11_BITS _U(0xffffffff)
-#define SIO_SPINLOCK11_RESET _U(0x00000000)
-#define SIO_SPINLOCK11_MSB _U(31)
-#define SIO_SPINLOCK11_LSB _U(0)
+#define SIO_SPINLOCK11_OFFSET _u(0x0000012c)
+#define SIO_SPINLOCK11_BITS _u(0xffffffff)
+#define SIO_SPINLOCK11_RESET _u(0x00000000)
+#define SIO_SPINLOCK11_MSB _u(31)
+#define SIO_SPINLOCK11_LSB _u(0)
#define SIO_SPINLOCK11_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK12
@@ -1342,11 +1342,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK12_OFFSET _U(0x00000130)
-#define SIO_SPINLOCK12_BITS _U(0xffffffff)
-#define SIO_SPINLOCK12_RESET _U(0x00000000)
-#define SIO_SPINLOCK12_MSB _U(31)
-#define SIO_SPINLOCK12_LSB _U(0)
+#define SIO_SPINLOCK12_OFFSET _u(0x00000130)
+#define SIO_SPINLOCK12_BITS _u(0xffffffff)
+#define SIO_SPINLOCK12_RESET _u(0x00000000)
+#define SIO_SPINLOCK12_MSB _u(31)
+#define SIO_SPINLOCK12_LSB _u(0)
#define SIO_SPINLOCK12_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK13
@@ -1358,11 +1358,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK13_OFFSET _U(0x00000134)
-#define SIO_SPINLOCK13_BITS _U(0xffffffff)
-#define SIO_SPINLOCK13_RESET _U(0x00000000)
-#define SIO_SPINLOCK13_MSB _U(31)
-#define SIO_SPINLOCK13_LSB _U(0)
+#define SIO_SPINLOCK13_OFFSET _u(0x00000134)
+#define SIO_SPINLOCK13_BITS _u(0xffffffff)
+#define SIO_SPINLOCK13_RESET _u(0x00000000)
+#define SIO_SPINLOCK13_MSB _u(31)
+#define SIO_SPINLOCK13_LSB _u(0)
#define SIO_SPINLOCK13_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK14
@@ -1374,11 +1374,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK14_OFFSET _U(0x00000138)
-#define SIO_SPINLOCK14_BITS _U(0xffffffff)
-#define SIO_SPINLOCK14_RESET _U(0x00000000)
-#define SIO_SPINLOCK14_MSB _U(31)
-#define SIO_SPINLOCK14_LSB _U(0)
+#define SIO_SPINLOCK14_OFFSET _u(0x00000138)
+#define SIO_SPINLOCK14_BITS _u(0xffffffff)
+#define SIO_SPINLOCK14_RESET _u(0x00000000)
+#define SIO_SPINLOCK14_MSB _u(31)
+#define SIO_SPINLOCK14_LSB _u(0)
#define SIO_SPINLOCK14_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK15
@@ -1390,11 +1390,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK15_OFFSET _U(0x0000013c)
-#define SIO_SPINLOCK15_BITS _U(0xffffffff)
-#define SIO_SPINLOCK15_RESET _U(0x00000000)
-#define SIO_SPINLOCK15_MSB _U(31)
-#define SIO_SPINLOCK15_LSB _U(0)
+#define SIO_SPINLOCK15_OFFSET _u(0x0000013c)
+#define SIO_SPINLOCK15_BITS _u(0xffffffff)
+#define SIO_SPINLOCK15_RESET _u(0x00000000)
+#define SIO_SPINLOCK15_MSB _u(31)
+#define SIO_SPINLOCK15_LSB _u(0)
#define SIO_SPINLOCK15_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK16
@@ -1406,11 +1406,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK16_OFFSET _U(0x00000140)
-#define SIO_SPINLOCK16_BITS _U(0xffffffff)
-#define SIO_SPINLOCK16_RESET _U(0x00000000)
-#define SIO_SPINLOCK16_MSB _U(31)
-#define SIO_SPINLOCK16_LSB _U(0)
+#define SIO_SPINLOCK16_OFFSET _u(0x00000140)
+#define SIO_SPINLOCK16_BITS _u(0xffffffff)
+#define SIO_SPINLOCK16_RESET _u(0x00000000)
+#define SIO_SPINLOCK16_MSB _u(31)
+#define SIO_SPINLOCK16_LSB _u(0)
#define SIO_SPINLOCK16_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK17
@@ -1422,11 +1422,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK17_OFFSET _U(0x00000144)
-#define SIO_SPINLOCK17_BITS _U(0xffffffff)
-#define SIO_SPINLOCK17_RESET _U(0x00000000)
-#define SIO_SPINLOCK17_MSB _U(31)
-#define SIO_SPINLOCK17_LSB _U(0)
+#define SIO_SPINLOCK17_OFFSET _u(0x00000144)
+#define SIO_SPINLOCK17_BITS _u(0xffffffff)
+#define SIO_SPINLOCK17_RESET _u(0x00000000)
+#define SIO_SPINLOCK17_MSB _u(31)
+#define SIO_SPINLOCK17_LSB _u(0)
#define SIO_SPINLOCK17_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK18
@@ -1438,11 +1438,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK18_OFFSET _U(0x00000148)
-#define SIO_SPINLOCK18_BITS _U(0xffffffff)
-#define SIO_SPINLOCK18_RESET _U(0x00000000)
-#define SIO_SPINLOCK18_MSB _U(31)
-#define SIO_SPINLOCK18_LSB _U(0)
+#define SIO_SPINLOCK18_OFFSET _u(0x00000148)
+#define SIO_SPINLOCK18_BITS _u(0xffffffff)
+#define SIO_SPINLOCK18_RESET _u(0x00000000)
+#define SIO_SPINLOCK18_MSB _u(31)
+#define SIO_SPINLOCK18_LSB _u(0)
#define SIO_SPINLOCK18_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK19
@@ -1454,11 +1454,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK19_OFFSET _U(0x0000014c)
-#define SIO_SPINLOCK19_BITS _U(0xffffffff)
-#define SIO_SPINLOCK19_RESET _U(0x00000000)
-#define SIO_SPINLOCK19_MSB _U(31)
-#define SIO_SPINLOCK19_LSB _U(0)
+#define SIO_SPINLOCK19_OFFSET _u(0x0000014c)
+#define SIO_SPINLOCK19_BITS _u(0xffffffff)
+#define SIO_SPINLOCK19_RESET _u(0x00000000)
+#define SIO_SPINLOCK19_MSB _u(31)
+#define SIO_SPINLOCK19_LSB _u(0)
#define SIO_SPINLOCK19_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK20
@@ -1470,11 +1470,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK20_OFFSET _U(0x00000150)
-#define SIO_SPINLOCK20_BITS _U(0xffffffff)
-#define SIO_SPINLOCK20_RESET _U(0x00000000)
-#define SIO_SPINLOCK20_MSB _U(31)
-#define SIO_SPINLOCK20_LSB _U(0)
+#define SIO_SPINLOCK20_OFFSET _u(0x00000150)
+#define SIO_SPINLOCK20_BITS _u(0xffffffff)
+#define SIO_SPINLOCK20_RESET _u(0x00000000)
+#define SIO_SPINLOCK20_MSB _u(31)
+#define SIO_SPINLOCK20_LSB _u(0)
#define SIO_SPINLOCK20_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK21
@@ -1486,11 +1486,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK21_OFFSET _U(0x00000154)
-#define SIO_SPINLOCK21_BITS _U(0xffffffff)
-#define SIO_SPINLOCK21_RESET _U(0x00000000)
-#define SIO_SPINLOCK21_MSB _U(31)
-#define SIO_SPINLOCK21_LSB _U(0)
+#define SIO_SPINLOCK21_OFFSET _u(0x00000154)
+#define SIO_SPINLOCK21_BITS _u(0xffffffff)
+#define SIO_SPINLOCK21_RESET _u(0x00000000)
+#define SIO_SPINLOCK21_MSB _u(31)
+#define SIO_SPINLOCK21_LSB _u(0)
#define SIO_SPINLOCK21_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK22
@@ -1502,11 +1502,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK22_OFFSET _U(0x00000158)
-#define SIO_SPINLOCK22_BITS _U(0xffffffff)
-#define SIO_SPINLOCK22_RESET _U(0x00000000)
-#define SIO_SPINLOCK22_MSB _U(31)
-#define SIO_SPINLOCK22_LSB _U(0)
+#define SIO_SPINLOCK22_OFFSET _u(0x00000158)
+#define SIO_SPINLOCK22_BITS _u(0xffffffff)
+#define SIO_SPINLOCK22_RESET _u(0x00000000)
+#define SIO_SPINLOCK22_MSB _u(31)
+#define SIO_SPINLOCK22_LSB _u(0)
#define SIO_SPINLOCK22_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK23
@@ -1518,11 +1518,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK23_OFFSET _U(0x0000015c)
-#define SIO_SPINLOCK23_BITS _U(0xffffffff)
-#define SIO_SPINLOCK23_RESET _U(0x00000000)
-#define SIO_SPINLOCK23_MSB _U(31)
-#define SIO_SPINLOCK23_LSB _U(0)
+#define SIO_SPINLOCK23_OFFSET _u(0x0000015c)
+#define SIO_SPINLOCK23_BITS _u(0xffffffff)
+#define SIO_SPINLOCK23_RESET _u(0x00000000)
+#define SIO_SPINLOCK23_MSB _u(31)
+#define SIO_SPINLOCK23_LSB _u(0)
#define SIO_SPINLOCK23_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK24
@@ -1534,11 +1534,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK24_OFFSET _U(0x00000160)
-#define SIO_SPINLOCK24_BITS _U(0xffffffff)
-#define SIO_SPINLOCK24_RESET _U(0x00000000)
-#define SIO_SPINLOCK24_MSB _U(31)
-#define SIO_SPINLOCK24_LSB _U(0)
+#define SIO_SPINLOCK24_OFFSET _u(0x00000160)
+#define SIO_SPINLOCK24_BITS _u(0xffffffff)
+#define SIO_SPINLOCK24_RESET _u(0x00000000)
+#define SIO_SPINLOCK24_MSB _u(31)
+#define SIO_SPINLOCK24_LSB _u(0)
#define SIO_SPINLOCK24_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK25
@@ -1550,11 +1550,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK25_OFFSET _U(0x00000164)
-#define SIO_SPINLOCK25_BITS _U(0xffffffff)
-#define SIO_SPINLOCK25_RESET _U(0x00000000)
-#define SIO_SPINLOCK25_MSB _U(31)
-#define SIO_SPINLOCK25_LSB _U(0)
+#define SIO_SPINLOCK25_OFFSET _u(0x00000164)
+#define SIO_SPINLOCK25_BITS _u(0xffffffff)
+#define SIO_SPINLOCK25_RESET _u(0x00000000)
+#define SIO_SPINLOCK25_MSB _u(31)
+#define SIO_SPINLOCK25_LSB _u(0)
#define SIO_SPINLOCK25_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK26
@@ -1566,11 +1566,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK26_OFFSET _U(0x00000168)
-#define SIO_SPINLOCK26_BITS _U(0xffffffff)
-#define SIO_SPINLOCK26_RESET _U(0x00000000)
-#define SIO_SPINLOCK26_MSB _U(31)
-#define SIO_SPINLOCK26_LSB _U(0)
+#define SIO_SPINLOCK26_OFFSET _u(0x00000168)
+#define SIO_SPINLOCK26_BITS _u(0xffffffff)
+#define SIO_SPINLOCK26_RESET _u(0x00000000)
+#define SIO_SPINLOCK26_MSB _u(31)
+#define SIO_SPINLOCK26_LSB _u(0)
#define SIO_SPINLOCK26_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK27
@@ -1582,11 +1582,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK27_OFFSET _U(0x0000016c)
-#define SIO_SPINLOCK27_BITS _U(0xffffffff)
-#define SIO_SPINLOCK27_RESET _U(0x00000000)
-#define SIO_SPINLOCK27_MSB _U(31)
-#define SIO_SPINLOCK27_LSB _U(0)
+#define SIO_SPINLOCK27_OFFSET _u(0x0000016c)
+#define SIO_SPINLOCK27_BITS _u(0xffffffff)
+#define SIO_SPINLOCK27_RESET _u(0x00000000)
+#define SIO_SPINLOCK27_MSB _u(31)
+#define SIO_SPINLOCK27_LSB _u(0)
#define SIO_SPINLOCK27_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK28
@@ -1598,11 +1598,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK28_OFFSET _U(0x00000170)
-#define SIO_SPINLOCK28_BITS _U(0xffffffff)
-#define SIO_SPINLOCK28_RESET _U(0x00000000)
-#define SIO_SPINLOCK28_MSB _U(31)
-#define SIO_SPINLOCK28_LSB _U(0)
+#define SIO_SPINLOCK28_OFFSET _u(0x00000170)
+#define SIO_SPINLOCK28_BITS _u(0xffffffff)
+#define SIO_SPINLOCK28_RESET _u(0x00000000)
+#define SIO_SPINLOCK28_MSB _u(31)
+#define SIO_SPINLOCK28_LSB _u(0)
#define SIO_SPINLOCK28_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK29
@@ -1614,11 +1614,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK29_OFFSET _U(0x00000174)
-#define SIO_SPINLOCK29_BITS _U(0xffffffff)
-#define SIO_SPINLOCK29_RESET _U(0x00000000)
-#define SIO_SPINLOCK29_MSB _U(31)
-#define SIO_SPINLOCK29_LSB _U(0)
+#define SIO_SPINLOCK29_OFFSET _u(0x00000174)
+#define SIO_SPINLOCK29_BITS _u(0xffffffff)
+#define SIO_SPINLOCK29_RESET _u(0x00000000)
+#define SIO_SPINLOCK29_MSB _u(31)
+#define SIO_SPINLOCK29_LSB _u(0)
#define SIO_SPINLOCK29_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK30
@@ -1630,11 +1630,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK30_OFFSET _U(0x00000178)
-#define SIO_SPINLOCK30_BITS _U(0xffffffff)
-#define SIO_SPINLOCK30_RESET _U(0x00000000)
-#define SIO_SPINLOCK30_MSB _U(31)
-#define SIO_SPINLOCK30_LSB _U(0)
+#define SIO_SPINLOCK30_OFFSET _u(0x00000178)
+#define SIO_SPINLOCK30_BITS _u(0xffffffff)
+#define SIO_SPINLOCK30_RESET _u(0x00000000)
+#define SIO_SPINLOCK30_MSB _u(31)
+#define SIO_SPINLOCK30_LSB _u(0)
#define SIO_SPINLOCK30_ACCESS "RO"
// =============================================================================
// Register : SIO_SPINLOCK31
@@ -1646,11 +1646,11 @@
// If core 0 and core 1 attempt to claim the same lock
// simultaneously, core 0 wins.
// The value returned on success is 0x1 << lock number.
-#define SIO_SPINLOCK31_OFFSET _U(0x0000017c)
-#define SIO_SPINLOCK31_BITS _U(0xffffffff)
-#define SIO_SPINLOCK31_RESET _U(0x00000000)
-#define SIO_SPINLOCK31_MSB _U(31)
-#define SIO_SPINLOCK31_LSB _U(0)
+#define SIO_SPINLOCK31_OFFSET _u(0x0000017c)
+#define SIO_SPINLOCK31_BITS _u(0xffffffff)
+#define SIO_SPINLOCK31_RESET _u(0x00000000)
+#define SIO_SPINLOCK31_MSB _u(31)
+#define SIO_SPINLOCK31_LSB _u(0)
#define SIO_SPINLOCK31_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_SIO_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/spi.h b/src/rp2040/hardware_regs/include/hardware/regs/spi.h
index 348dd0f..816e150 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/spi.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/spi.h
@@ -14,9 +14,9 @@
// =============================================================================
// Register : SPI_SSPCR0
// Description : Control register 0, SSPCR0 on page 3-4
-#define SPI_SSPCR0_OFFSET _U(0x00000000)
-#define SPI_SSPCR0_BITS _U(0x0000ffff)
-#define SPI_SSPCR0_RESET _U(0x00000000)
+#define SPI_SSPCR0_OFFSET _u(0x00000000)
+#define SPI_SSPCR0_BITS _u(0x0000ffff)
+#define SPI_SSPCR0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SCR
// Description : Serial clock rate. The value SCR is used to generate the
@@ -24,38 +24,38 @@
// rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even
// value from 2-254, programmed through the SSPCPSR register and
// SCR is a value from 0-255.
-#define SPI_SSPCR0_SCR_RESET _U(0x00)
-#define SPI_SSPCR0_SCR_BITS _U(0x0000ff00)
-#define SPI_SSPCR0_SCR_MSB _U(15)
-#define SPI_SSPCR0_SCR_LSB _U(8)
+#define SPI_SSPCR0_SCR_RESET _u(0x00)
+#define SPI_SSPCR0_SCR_BITS _u(0x0000ff00)
+#define SPI_SSPCR0_SCR_MSB _u(15)
+#define SPI_SSPCR0_SCR_LSB _u(8)
#define SPI_SSPCR0_SCR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SPH
// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only.
// See Motorola SPI frame format on page 2-10.
-#define SPI_SSPCR0_SPH_RESET _U(0x0)
-#define SPI_SSPCR0_SPH_BITS _U(0x00000080)
-#define SPI_SSPCR0_SPH_MSB _U(7)
-#define SPI_SSPCR0_SPH_LSB _U(7)
+#define SPI_SSPCR0_SPH_RESET _u(0x0)
+#define SPI_SSPCR0_SPH_BITS _u(0x00000080)
+#define SPI_SSPCR0_SPH_MSB _u(7)
+#define SPI_SSPCR0_SPH_LSB _u(7)
#define SPI_SSPCR0_SPH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SPO
// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format
// only. See Motorola SPI frame format on page 2-10.
-#define SPI_SSPCR0_SPO_RESET _U(0x0)
-#define SPI_SSPCR0_SPO_BITS _U(0x00000040)
-#define SPI_SSPCR0_SPO_MSB _U(6)
-#define SPI_SSPCR0_SPO_LSB _U(6)
+#define SPI_SSPCR0_SPO_RESET _u(0x0)
+#define SPI_SSPCR0_SPO_BITS _u(0x00000040)
+#define SPI_SSPCR0_SPO_MSB _u(6)
+#define SPI_SSPCR0_SPO_LSB _u(6)
#define SPI_SSPCR0_SPO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_FRF
// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous
// serial frame format. 10 National Microwire frame format. 11
// Reserved, undefined operation.
-#define SPI_SSPCR0_FRF_RESET _U(0x0)
-#define SPI_SSPCR0_FRF_BITS _U(0x00000030)
-#define SPI_SSPCR0_FRF_MSB _U(5)
-#define SPI_SSPCR0_FRF_LSB _U(4)
+#define SPI_SSPCR0_FRF_RESET _u(0x0)
+#define SPI_SSPCR0_FRF_BITS _u(0x00000030)
+#define SPI_SSPCR0_FRF_MSB _u(5)
+#define SPI_SSPCR0_FRF_LSB _u(4)
#define SPI_SSPCR0_FRF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_DSS
@@ -65,17 +65,17 @@
// 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit
// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data.
// 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.
-#define SPI_SSPCR0_DSS_RESET _U(0x0)
-#define SPI_SSPCR0_DSS_BITS _U(0x0000000f)
-#define SPI_SSPCR0_DSS_MSB _U(3)
-#define SPI_SSPCR0_DSS_LSB _U(0)
+#define SPI_SSPCR0_DSS_RESET _u(0x0)
+#define SPI_SSPCR0_DSS_BITS _u(0x0000000f)
+#define SPI_SSPCR0_DSS_MSB _u(3)
+#define SPI_SSPCR0_DSS_LSB _u(0)
#define SPI_SSPCR0_DSS_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPCR1
// Description : Control register 1, SSPCR1 on page 3-5
-#define SPI_SSPCR1_OFFSET _U(0x00000004)
-#define SPI_SSPCR1_BITS _U(0x0000000f)
-#define SPI_SSPCR1_RESET _U(0x00000000)
+#define SPI_SSPCR1_OFFSET _u(0x00000004)
+#define SPI_SSPCR1_BITS _u(0x0000000f)
+#define SPI_SSPCR1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_SOD
// Description : Slave-mode output disable. This bit is relevant only in the
@@ -88,45 +88,45 @@
// not supposed to drive the SSPTXD line: 0 SSP can drive the
// SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD
// output in slave mode.
-#define SPI_SSPCR1_SOD_RESET _U(0x0)
-#define SPI_SSPCR1_SOD_BITS _U(0x00000008)
-#define SPI_SSPCR1_SOD_MSB _U(3)
-#define SPI_SSPCR1_SOD_LSB _U(3)
+#define SPI_SSPCR1_SOD_RESET _u(0x0)
+#define SPI_SSPCR1_SOD_BITS _u(0x00000008)
+#define SPI_SSPCR1_SOD_MSB _u(3)
+#define SPI_SSPCR1_SOD_LSB _u(3)
#define SPI_SSPCR1_SOD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_MS
// Description : Master or slave mode select. This bit can be modified only when
// the PrimeCell SSP is disabled, SSE=0: 0 Device configured as
// master, default. 1 Device configured as slave.
-#define SPI_SSPCR1_MS_RESET _U(0x0)
-#define SPI_SSPCR1_MS_BITS _U(0x00000004)
-#define SPI_SSPCR1_MS_MSB _U(2)
-#define SPI_SSPCR1_MS_LSB _U(2)
+#define SPI_SSPCR1_MS_RESET _u(0x0)
+#define SPI_SSPCR1_MS_BITS _u(0x00000004)
+#define SPI_SSPCR1_MS_MSB _u(2)
+#define SPI_SSPCR1_MS_LSB _u(2)
#define SPI_SSPCR1_MS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_SSE
// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP
// operation enabled.
-#define SPI_SSPCR1_SSE_RESET _U(0x0)
-#define SPI_SSPCR1_SSE_BITS _U(0x00000002)
-#define SPI_SSPCR1_SSE_MSB _U(1)
-#define SPI_SSPCR1_SSE_LSB _U(1)
+#define SPI_SSPCR1_SSE_RESET _u(0x0)
+#define SPI_SSPCR1_SSE_BITS _u(0x00000002)
+#define SPI_SSPCR1_SSE_MSB _u(1)
+#define SPI_SSPCR1_SSE_LSB _u(1)
#define SPI_SSPCR1_SSE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_LBM
// Description : Loop back mode: 0 Normal serial port operation enabled. 1
// Output of transmit serial shifter is connected to input of
// receive serial shifter internally.
-#define SPI_SSPCR1_LBM_RESET _U(0x0)
-#define SPI_SSPCR1_LBM_BITS _U(0x00000001)
-#define SPI_SSPCR1_LBM_MSB _U(0)
-#define SPI_SSPCR1_LBM_LSB _U(0)
+#define SPI_SSPCR1_LBM_RESET _u(0x0)
+#define SPI_SSPCR1_LBM_BITS _u(0x00000001)
+#define SPI_SSPCR1_LBM_MSB _u(0)
+#define SPI_SSPCR1_LBM_LSB _u(0)
#define SPI_SSPCR1_LBM_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPDR
// Description : Data register, SSPDR on page 3-6
-#define SPI_SSPDR_OFFSET _U(0x00000008)
-#define SPI_SSPDR_BITS _U(0x0000ffff)
+#define SPI_SSPDR_OFFSET _u(0x00000008)
+#define SPI_SSPDR_BITS _u(0x0000ffff)
#define SPI_SSPDR_RESET "-"
// -----------------------------------------------------------------------------
// Field : SPI_SSPDR_DATA
@@ -136,103 +136,103 @@
// bits at the top are ignored by transmit logic. The receive
// logic automatically right-justifies.
#define SPI_SSPDR_DATA_RESET "-"
-#define SPI_SSPDR_DATA_BITS _U(0x0000ffff)
-#define SPI_SSPDR_DATA_MSB _U(15)
-#define SPI_SSPDR_DATA_LSB _U(0)
+#define SPI_SSPDR_DATA_BITS _u(0x0000ffff)
+#define SPI_SSPDR_DATA_MSB _u(15)
+#define SPI_SSPDR_DATA_LSB _u(0)
#define SPI_SSPDR_DATA_ACCESS "RWF"
// =============================================================================
// Register : SPI_SSPSR
// Description : Status register, SSPSR on page 3-7
-#define SPI_SSPSR_OFFSET _U(0x0000000c)
-#define SPI_SSPSR_BITS _U(0x0000001f)
-#define SPI_SSPSR_RESET _U(0x00000003)
+#define SPI_SSPSR_OFFSET _u(0x0000000c)
+#define SPI_SSPSR_BITS _u(0x0000001f)
+#define SPI_SSPSR_RESET _u(0x00000003)
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_BSY
// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently
// transmitting and/or receiving a frame or the transmit FIFO is
// not empty.
-#define SPI_SSPSR_BSY_RESET _U(0x0)
-#define SPI_SSPSR_BSY_BITS _U(0x00000010)
-#define SPI_SSPSR_BSY_MSB _U(4)
-#define SPI_SSPSR_BSY_LSB _U(4)
+#define SPI_SSPSR_BSY_RESET _u(0x0)
+#define SPI_SSPSR_BSY_BITS _u(0x00000010)
+#define SPI_SSPSR_BSY_MSB _u(4)
+#define SPI_SSPSR_BSY_LSB _u(4)
#define SPI_SSPSR_BSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_RFF
// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive
// FIFO is full.
-#define SPI_SSPSR_RFF_RESET _U(0x0)
-#define SPI_SSPSR_RFF_BITS _U(0x00000008)
-#define SPI_SSPSR_RFF_MSB _U(3)
-#define SPI_SSPSR_RFF_LSB _U(3)
+#define SPI_SSPSR_RFF_RESET _u(0x0)
+#define SPI_SSPSR_RFF_BITS _u(0x00000008)
+#define SPI_SSPSR_RFF_MSB _u(3)
+#define SPI_SSPSR_RFF_LSB _u(3)
#define SPI_SSPSR_RFF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_RNE
// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive
// FIFO is not empty.
-#define SPI_SSPSR_RNE_RESET _U(0x0)
-#define SPI_SSPSR_RNE_BITS _U(0x00000004)
-#define SPI_SSPSR_RNE_MSB _U(2)
-#define SPI_SSPSR_RNE_LSB _U(2)
+#define SPI_SSPSR_RNE_RESET _u(0x0)
+#define SPI_SSPSR_RNE_BITS _u(0x00000004)
+#define SPI_SSPSR_RNE_MSB _u(2)
+#define SPI_SSPSR_RNE_LSB _u(2)
#define SPI_SSPSR_RNE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_TNF
// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit
// FIFO is not full.
-#define SPI_SSPSR_TNF_RESET _U(0x1)
-#define SPI_SSPSR_TNF_BITS _U(0x00000002)
-#define SPI_SSPSR_TNF_MSB _U(1)
-#define SPI_SSPSR_TNF_LSB _U(1)
+#define SPI_SSPSR_TNF_RESET _u(0x1)
+#define SPI_SSPSR_TNF_BITS _u(0x00000002)
+#define SPI_SSPSR_TNF_MSB _u(1)
+#define SPI_SSPSR_TNF_LSB _u(1)
#define SPI_SSPSR_TNF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_TFE
// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1
// Transmit FIFO is empty.
-#define SPI_SSPSR_TFE_RESET _U(0x1)
-#define SPI_SSPSR_TFE_BITS _U(0x00000001)
-#define SPI_SSPSR_TFE_MSB _U(0)
-#define SPI_SSPSR_TFE_LSB _U(0)
+#define SPI_SSPSR_TFE_RESET _u(0x1)
+#define SPI_SSPSR_TFE_BITS _u(0x00000001)
+#define SPI_SSPSR_TFE_MSB _u(0)
+#define SPI_SSPSR_TFE_LSB _u(0)
#define SPI_SSPSR_TFE_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPCPSR
// Description : Clock prescale register, SSPCPSR on page 3-8
-#define SPI_SSPCPSR_OFFSET _U(0x00000010)
-#define SPI_SSPCPSR_BITS _U(0x000000ff)
-#define SPI_SSPCPSR_RESET _U(0x00000000)
+#define SPI_SSPCPSR_OFFSET _u(0x00000010)
+#define SPI_SSPCPSR_BITS _u(0x000000ff)
+#define SPI_SSPCPSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCPSR_CPSDVSR
// Description : Clock prescale divisor. Must be an even number from 2-254,
// depending on the frequency of SSPCLK. The least significant bit
// always returns zero on reads.
-#define SPI_SSPCPSR_CPSDVSR_RESET _U(0x00)
-#define SPI_SSPCPSR_CPSDVSR_BITS _U(0x000000ff)
-#define SPI_SSPCPSR_CPSDVSR_MSB _U(7)
-#define SPI_SSPCPSR_CPSDVSR_LSB _U(0)
+#define SPI_SSPCPSR_CPSDVSR_RESET _u(0x00)
+#define SPI_SSPCPSR_CPSDVSR_BITS _u(0x000000ff)
+#define SPI_SSPCPSR_CPSDVSR_MSB _u(7)
+#define SPI_SSPCPSR_CPSDVSR_LSB _u(0)
#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPIMSC
// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9
-#define SPI_SSPIMSC_OFFSET _U(0x00000014)
-#define SPI_SSPIMSC_BITS _U(0x0000000f)
-#define SPI_SSPIMSC_RESET _U(0x00000000)
+#define SPI_SSPIMSC_OFFSET _u(0x00000014)
+#define SPI_SSPIMSC_BITS _u(0x0000000f)
+#define SPI_SSPIMSC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_TXIM
// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or
// less condition interrupt is masked. 1 Transmit FIFO half empty
// or less condition interrupt is not masked.
-#define SPI_SSPIMSC_TXIM_RESET _U(0x0)
-#define SPI_SSPIMSC_TXIM_BITS _U(0x00000008)
-#define SPI_SSPIMSC_TXIM_MSB _U(3)
-#define SPI_SSPIMSC_TXIM_LSB _U(3)
+#define SPI_SSPIMSC_TXIM_RESET _u(0x0)
+#define SPI_SSPIMSC_TXIM_BITS _u(0x00000008)
+#define SPI_SSPIMSC_TXIM_MSB _u(3)
+#define SPI_SSPIMSC_TXIM_LSB _u(3)
#define SPI_SSPIMSC_TXIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RXIM
// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less
// condition interrupt is masked. 1 Receive FIFO half full or less
// condition interrupt is not masked.
-#define SPI_SSPIMSC_RXIM_RESET _U(0x0)
-#define SPI_SSPIMSC_RXIM_BITS _U(0x00000004)
-#define SPI_SSPIMSC_RXIM_MSB _U(2)
-#define SPI_SSPIMSC_RXIM_LSB _U(2)
+#define SPI_SSPIMSC_RXIM_RESET _u(0x0)
+#define SPI_SSPIMSC_RXIM_BITS _u(0x00000004)
+#define SPI_SSPIMSC_RXIM_MSB _u(2)
+#define SPI_SSPIMSC_RXIM_LSB _u(2)
#define SPI_SSPIMSC_RXIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RTIM
@@ -240,282 +240,282 @@
// read prior to timeout period interrupt is masked. 1 Receive
// FIFO not empty and no read prior to timeout period interrupt is
// not masked.
-#define SPI_SSPIMSC_RTIM_RESET _U(0x0)
-#define SPI_SSPIMSC_RTIM_BITS _U(0x00000002)
-#define SPI_SSPIMSC_RTIM_MSB _U(1)
-#define SPI_SSPIMSC_RTIM_LSB _U(1)
+#define SPI_SSPIMSC_RTIM_RESET _u(0x0)
+#define SPI_SSPIMSC_RTIM_BITS _u(0x00000002)
+#define SPI_SSPIMSC_RTIM_MSB _u(1)
+#define SPI_SSPIMSC_RTIM_LSB _u(1)
#define SPI_SSPIMSC_RTIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RORIM
// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while
// full condition interrupt is masked. 1 Receive FIFO written to
// while full condition interrupt is not masked.
-#define SPI_SSPIMSC_RORIM_RESET _U(0x0)
-#define SPI_SSPIMSC_RORIM_BITS _U(0x00000001)
-#define SPI_SSPIMSC_RORIM_MSB _U(0)
-#define SPI_SSPIMSC_RORIM_LSB _U(0)
+#define SPI_SSPIMSC_RORIM_RESET _u(0x0)
+#define SPI_SSPIMSC_RORIM_BITS _u(0x00000001)
+#define SPI_SSPIMSC_RORIM_MSB _u(0)
+#define SPI_SSPIMSC_RORIM_LSB _u(0)
#define SPI_SSPIMSC_RORIM_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPRIS
// Description : Raw interrupt status register, SSPRIS on page 3-10
-#define SPI_SSPRIS_OFFSET _U(0x00000018)
-#define SPI_SSPRIS_BITS _U(0x0000000f)
-#define SPI_SSPRIS_RESET _U(0x00000008)
+#define SPI_SSPRIS_OFFSET _u(0x00000018)
+#define SPI_SSPRIS_BITS _u(0x0000000f)
+#define SPI_SSPRIS_RESET _u(0x00000008)
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_TXRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPTXINTR interrupt
-#define SPI_SSPRIS_TXRIS_RESET _U(0x1)
-#define SPI_SSPRIS_TXRIS_BITS _U(0x00000008)
-#define SPI_SSPRIS_TXRIS_MSB _U(3)
-#define SPI_SSPRIS_TXRIS_LSB _U(3)
+#define SPI_SSPRIS_TXRIS_RESET _u(0x1)
+#define SPI_SSPRIS_TXRIS_BITS _u(0x00000008)
+#define SPI_SSPRIS_TXRIS_MSB _u(3)
+#define SPI_SSPRIS_TXRIS_LSB _u(3)
#define SPI_SSPRIS_TXRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RXRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRXINTR interrupt
-#define SPI_SSPRIS_RXRIS_RESET _U(0x0)
-#define SPI_SSPRIS_RXRIS_BITS _U(0x00000004)
-#define SPI_SSPRIS_RXRIS_MSB _U(2)
-#define SPI_SSPRIS_RXRIS_LSB _U(2)
+#define SPI_SSPRIS_RXRIS_RESET _u(0x0)
+#define SPI_SSPRIS_RXRIS_BITS _u(0x00000004)
+#define SPI_SSPRIS_RXRIS_MSB _u(2)
+#define SPI_SSPRIS_RXRIS_LSB _u(2)
#define SPI_SSPRIS_RXRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RTRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRTINTR interrupt
-#define SPI_SSPRIS_RTRIS_RESET _U(0x0)
-#define SPI_SSPRIS_RTRIS_BITS _U(0x00000002)
-#define SPI_SSPRIS_RTRIS_MSB _U(1)
-#define SPI_SSPRIS_RTRIS_LSB _U(1)
+#define SPI_SSPRIS_RTRIS_RESET _u(0x0)
+#define SPI_SSPRIS_RTRIS_BITS _u(0x00000002)
+#define SPI_SSPRIS_RTRIS_MSB _u(1)
+#define SPI_SSPRIS_RTRIS_LSB _u(1)
#define SPI_SSPRIS_RTRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RORRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRORINTR interrupt
-#define SPI_SSPRIS_RORRIS_RESET _U(0x0)
-#define SPI_SSPRIS_RORRIS_BITS _U(0x00000001)
-#define SPI_SSPRIS_RORRIS_MSB _U(0)
-#define SPI_SSPRIS_RORRIS_LSB _U(0)
+#define SPI_SSPRIS_RORRIS_RESET _u(0x0)
+#define SPI_SSPRIS_RORRIS_BITS _u(0x00000001)
+#define SPI_SSPRIS_RORRIS_MSB _u(0)
+#define SPI_SSPRIS_RORRIS_LSB _u(0)
#define SPI_SSPRIS_RORRIS_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPMIS
// Description : Masked interrupt status register, SSPMIS on page 3-11
-#define SPI_SSPMIS_OFFSET _U(0x0000001c)
-#define SPI_SSPMIS_BITS _U(0x0000000f)
-#define SPI_SSPMIS_RESET _U(0x00000000)
+#define SPI_SSPMIS_OFFSET _u(0x0000001c)
+#define SPI_SSPMIS_BITS _u(0x0000000f)
+#define SPI_SSPMIS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_TXMIS
// Description : Gives the transmit FIFO masked interrupt state, after masking,
// of the SSPTXINTR interrupt
-#define SPI_SSPMIS_TXMIS_RESET _U(0x0)
-#define SPI_SSPMIS_TXMIS_BITS _U(0x00000008)
-#define SPI_SSPMIS_TXMIS_MSB _U(3)
-#define SPI_SSPMIS_TXMIS_LSB _U(3)
+#define SPI_SSPMIS_TXMIS_RESET _u(0x0)
+#define SPI_SSPMIS_TXMIS_BITS _u(0x00000008)
+#define SPI_SSPMIS_TXMIS_MSB _u(3)
+#define SPI_SSPMIS_TXMIS_LSB _u(3)
#define SPI_SSPMIS_TXMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RXMIS
// Description : Gives the receive FIFO masked interrupt state, after masking,
// of the SSPRXINTR interrupt
-#define SPI_SSPMIS_RXMIS_RESET _U(0x0)
-#define SPI_SSPMIS_RXMIS_BITS _U(0x00000004)
-#define SPI_SSPMIS_RXMIS_MSB _U(2)
-#define SPI_SSPMIS_RXMIS_LSB _U(2)
+#define SPI_SSPMIS_RXMIS_RESET _u(0x0)
+#define SPI_SSPMIS_RXMIS_BITS _u(0x00000004)
+#define SPI_SSPMIS_RXMIS_MSB _u(2)
+#define SPI_SSPMIS_RXMIS_LSB _u(2)
#define SPI_SSPMIS_RXMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RTMIS
// Description : Gives the receive timeout masked interrupt state, after
// masking, of the SSPRTINTR interrupt
-#define SPI_SSPMIS_RTMIS_RESET _U(0x0)
-#define SPI_SSPMIS_RTMIS_BITS _U(0x00000002)
-#define SPI_SSPMIS_RTMIS_MSB _U(1)
-#define SPI_SSPMIS_RTMIS_LSB _U(1)
+#define SPI_SSPMIS_RTMIS_RESET _u(0x0)
+#define SPI_SSPMIS_RTMIS_BITS _u(0x00000002)
+#define SPI_SSPMIS_RTMIS_MSB _u(1)
+#define SPI_SSPMIS_RTMIS_LSB _u(1)
#define SPI_SSPMIS_RTMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RORMIS
// Description : Gives the receive over run masked interrupt status, after
// masking, of the SSPRORINTR interrupt
-#define SPI_SSPMIS_RORMIS_RESET _U(0x0)
-#define SPI_SSPMIS_RORMIS_BITS _U(0x00000001)
-#define SPI_SSPMIS_RORMIS_MSB _U(0)
-#define SPI_SSPMIS_RORMIS_LSB _U(0)
+#define SPI_SSPMIS_RORMIS_RESET _u(0x0)
+#define SPI_SSPMIS_RORMIS_BITS _u(0x00000001)
+#define SPI_SSPMIS_RORMIS_MSB _u(0)
+#define SPI_SSPMIS_RORMIS_LSB _u(0)
#define SPI_SSPMIS_RORMIS_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPICR
// Description : Interrupt clear register, SSPICR on page 3-11
-#define SPI_SSPICR_OFFSET _U(0x00000020)
-#define SPI_SSPICR_BITS _U(0x00000003)
-#define SPI_SSPICR_RESET _U(0x00000000)
+#define SPI_SSPICR_OFFSET _u(0x00000020)
+#define SPI_SSPICR_BITS _u(0x00000003)
+#define SPI_SSPICR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPICR_RTIC
// Description : Clears the SSPRTINTR interrupt
-#define SPI_SSPICR_RTIC_RESET _U(0x0)
-#define SPI_SSPICR_RTIC_BITS _U(0x00000002)
-#define SPI_SSPICR_RTIC_MSB _U(1)
-#define SPI_SSPICR_RTIC_LSB _U(1)
+#define SPI_SSPICR_RTIC_RESET _u(0x0)
+#define SPI_SSPICR_RTIC_BITS _u(0x00000002)
+#define SPI_SSPICR_RTIC_MSB _u(1)
+#define SPI_SSPICR_RTIC_LSB _u(1)
#define SPI_SSPICR_RTIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : SPI_SSPICR_RORIC
// Description : Clears the SSPRORINTR interrupt
-#define SPI_SSPICR_RORIC_RESET _U(0x0)
-#define SPI_SSPICR_RORIC_BITS _U(0x00000001)
-#define SPI_SSPICR_RORIC_MSB _U(0)
-#define SPI_SSPICR_RORIC_LSB _U(0)
+#define SPI_SSPICR_RORIC_RESET _u(0x0)
+#define SPI_SSPICR_RORIC_BITS _u(0x00000001)
+#define SPI_SSPICR_RORIC_MSB _u(0)
+#define SPI_SSPICR_RORIC_LSB _u(0)
#define SPI_SSPICR_RORIC_ACCESS "WC"
// =============================================================================
// Register : SPI_SSPDMACR
// Description : DMA control register, SSPDMACR on page 3-12
-#define SPI_SSPDMACR_OFFSET _U(0x00000024)
-#define SPI_SSPDMACR_BITS _U(0x00000003)
-#define SPI_SSPDMACR_RESET _U(0x00000000)
+#define SPI_SSPDMACR_OFFSET _u(0x00000024)
+#define SPI_SSPDMACR_BITS _u(0x00000003)
+#define SPI_SSPDMACR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPDMACR_TXDMAE
// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the
// transmit FIFO is enabled.
-#define SPI_SSPDMACR_TXDMAE_RESET _U(0x0)
-#define SPI_SSPDMACR_TXDMAE_BITS _U(0x00000002)
-#define SPI_SSPDMACR_TXDMAE_MSB _U(1)
-#define SPI_SSPDMACR_TXDMAE_LSB _U(1)
+#define SPI_SSPDMACR_TXDMAE_RESET _u(0x0)
+#define SPI_SSPDMACR_TXDMAE_BITS _u(0x00000002)
+#define SPI_SSPDMACR_TXDMAE_MSB _u(1)
+#define SPI_SSPDMACR_TXDMAE_LSB _u(1)
#define SPI_SSPDMACR_TXDMAE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPDMACR_RXDMAE
// Description : Receive DMA Enable. If this bit is set to 1, DMA for the
// receive FIFO is enabled.
-#define SPI_SSPDMACR_RXDMAE_RESET _U(0x0)
-#define SPI_SSPDMACR_RXDMAE_BITS _U(0x00000001)
-#define SPI_SSPDMACR_RXDMAE_MSB _U(0)
-#define SPI_SSPDMACR_RXDMAE_LSB _U(0)
+#define SPI_SSPDMACR_RXDMAE_RESET _u(0x0)
+#define SPI_SSPDMACR_RXDMAE_BITS _u(0x00000001)
+#define SPI_SSPDMACR_RXDMAE_MSB _u(0)
+#define SPI_SSPDMACR_RXDMAE_LSB _u(0)
#define SPI_SSPDMACR_RXDMAE_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPPERIPHID0
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
-#define SPI_SSPPERIPHID0_OFFSET _U(0x00000fe0)
-#define SPI_SSPPERIPHID0_BITS _U(0x000000ff)
-#define SPI_SSPPERIPHID0_RESET _U(0x00000022)
+#define SPI_SSPPERIPHID0_OFFSET _u(0x00000fe0)
+#define SPI_SSPPERIPHID0_BITS _u(0x000000ff)
+#define SPI_SSPPERIPHID0_RESET _u(0x00000022)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID0_PARTNUMBER0
// Description : These bits read back as 0x22
-#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _U(0x22)
-#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _U(0x000000ff)
-#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _U(7)
-#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _U(0)
+#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _u(0x22)
+#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff)
+#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _u(7)
+#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _u(0)
#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID1
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
-#define SPI_SSPPERIPHID1_OFFSET _U(0x00000fe4)
-#define SPI_SSPPERIPHID1_BITS _U(0x000000ff)
-#define SPI_SSPPERIPHID1_RESET _U(0x00000010)
+#define SPI_SSPPERIPHID1_OFFSET _u(0x00000fe4)
+#define SPI_SSPPERIPHID1_BITS _u(0x000000ff)
+#define SPI_SSPPERIPHID1_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID1_DESIGNER0
// Description : These bits read back as 0x1
-#define SPI_SSPPERIPHID1_DESIGNER0_RESET _U(0x1)
-#define SPI_SSPPERIPHID1_DESIGNER0_BITS _U(0x000000f0)
-#define SPI_SSPPERIPHID1_DESIGNER0_MSB _U(7)
-#define SPI_SSPPERIPHID1_DESIGNER0_LSB _U(4)
+#define SPI_SSPPERIPHID1_DESIGNER0_RESET _u(0x1)
+#define SPI_SSPPERIPHID1_DESIGNER0_BITS _u(0x000000f0)
+#define SPI_SSPPERIPHID1_DESIGNER0_MSB _u(7)
+#define SPI_SSPPERIPHID1_DESIGNER0_LSB _u(4)
#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID1_PARTNUMBER1
// Description : These bits read back as 0x0
-#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _U(0x0)
-#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _U(0x0000000f)
-#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _U(3)
-#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _U(0)
+#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _u(0x0)
+#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f)
+#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _u(3)
+#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _u(0)
#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID2
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
-#define SPI_SSPPERIPHID2_OFFSET _U(0x00000fe8)
-#define SPI_SSPPERIPHID2_BITS _U(0x000000ff)
-#define SPI_SSPPERIPHID2_RESET _U(0x00000034)
+#define SPI_SSPPERIPHID2_OFFSET _u(0x00000fe8)
+#define SPI_SSPPERIPHID2_BITS _u(0x000000ff)
+#define SPI_SSPPERIPHID2_RESET _u(0x00000034)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID2_REVISION
// Description : These bits return the peripheral revision
-#define SPI_SSPPERIPHID2_REVISION_RESET _U(0x3)
-#define SPI_SSPPERIPHID2_REVISION_BITS _U(0x000000f0)
-#define SPI_SSPPERIPHID2_REVISION_MSB _U(7)
-#define SPI_SSPPERIPHID2_REVISION_LSB _U(4)
+#define SPI_SSPPERIPHID2_REVISION_RESET _u(0x3)
+#define SPI_SSPPERIPHID2_REVISION_BITS _u(0x000000f0)
+#define SPI_SSPPERIPHID2_REVISION_MSB _u(7)
+#define SPI_SSPPERIPHID2_REVISION_LSB _u(4)
#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID2_DESIGNER1
// Description : These bits read back as 0x4
-#define SPI_SSPPERIPHID2_DESIGNER1_RESET _U(0x4)
-#define SPI_SSPPERIPHID2_DESIGNER1_BITS _U(0x0000000f)
-#define SPI_SSPPERIPHID2_DESIGNER1_MSB _U(3)
-#define SPI_SSPPERIPHID2_DESIGNER1_LSB _U(0)
+#define SPI_SSPPERIPHID2_DESIGNER1_RESET _u(0x4)
+#define SPI_SSPPERIPHID2_DESIGNER1_BITS _u(0x0000000f)
+#define SPI_SSPPERIPHID2_DESIGNER1_MSB _u(3)
+#define SPI_SSPPERIPHID2_DESIGNER1_LSB _u(0)
#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID3
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
-#define SPI_SSPPERIPHID3_OFFSET _U(0x00000fec)
-#define SPI_SSPPERIPHID3_BITS _U(0x000000ff)
-#define SPI_SSPPERIPHID3_RESET _U(0x00000000)
+#define SPI_SSPPERIPHID3_OFFSET _u(0x00000fec)
+#define SPI_SSPPERIPHID3_BITS _u(0x000000ff)
+#define SPI_SSPPERIPHID3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID3_CONFIGURATION
// Description : These bits read back as 0x00
-#define SPI_SSPPERIPHID3_CONFIGURATION_RESET _U(0x00)
-#define SPI_SSPPERIPHID3_CONFIGURATION_BITS _U(0x000000ff)
-#define SPI_SSPPERIPHID3_CONFIGURATION_MSB _U(7)
-#define SPI_SSPPERIPHID3_CONFIGURATION_LSB _U(0)
+#define SPI_SSPPERIPHID3_CONFIGURATION_RESET _u(0x00)
+#define SPI_SSPPERIPHID3_CONFIGURATION_BITS _u(0x000000ff)
+#define SPI_SSPPERIPHID3_CONFIGURATION_MSB _u(7)
+#define SPI_SSPPERIPHID3_CONFIGURATION_LSB _u(0)
#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID0
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-#define SPI_SSPPCELLID0_OFFSET _U(0x00000ff0)
-#define SPI_SSPPCELLID0_BITS _U(0x000000ff)
-#define SPI_SSPPCELLID0_RESET _U(0x0000000d)
+#define SPI_SSPPCELLID0_OFFSET _u(0x00000ff0)
+#define SPI_SSPPCELLID0_BITS _u(0x000000ff)
+#define SPI_SSPPCELLID0_RESET _u(0x0000000d)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID0_SSPPCELLID0
// Description : These bits read back as 0x0D
-#define SPI_SSPPCELLID0_SSPPCELLID0_RESET _U(0x0d)
-#define SPI_SSPPCELLID0_SSPPCELLID0_BITS _U(0x000000ff)
-#define SPI_SSPPCELLID0_SSPPCELLID0_MSB _U(7)
-#define SPI_SSPPCELLID0_SSPPCELLID0_LSB _U(0)
+#define SPI_SSPPCELLID0_SSPPCELLID0_RESET _u(0x0d)
+#define SPI_SSPPCELLID0_SSPPCELLID0_BITS _u(0x000000ff)
+#define SPI_SSPPCELLID0_SSPPCELLID0_MSB _u(7)
+#define SPI_SSPPCELLID0_SSPPCELLID0_LSB _u(0)
#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID1
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-#define SPI_SSPPCELLID1_OFFSET _U(0x00000ff4)
-#define SPI_SSPPCELLID1_BITS _U(0x000000ff)
-#define SPI_SSPPCELLID1_RESET _U(0x000000f0)
+#define SPI_SSPPCELLID1_OFFSET _u(0x00000ff4)
+#define SPI_SSPPCELLID1_BITS _u(0x000000ff)
+#define SPI_SSPPCELLID1_RESET _u(0x000000f0)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID1_SSPPCELLID1
// Description : These bits read back as 0xF0
-#define SPI_SSPPCELLID1_SSPPCELLID1_RESET _U(0xf0)
-#define SPI_SSPPCELLID1_SSPPCELLID1_BITS _U(0x000000ff)
-#define SPI_SSPPCELLID1_SSPPCELLID1_MSB _U(7)
-#define SPI_SSPPCELLID1_SSPPCELLID1_LSB _U(0)
+#define SPI_SSPPCELLID1_SSPPCELLID1_RESET _u(0xf0)
+#define SPI_SSPPCELLID1_SSPPCELLID1_BITS _u(0x000000ff)
+#define SPI_SSPPCELLID1_SSPPCELLID1_MSB _u(7)
+#define SPI_SSPPCELLID1_SSPPCELLID1_LSB _u(0)
#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID2
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-#define SPI_SSPPCELLID2_OFFSET _U(0x00000ff8)
-#define SPI_SSPPCELLID2_BITS _U(0x000000ff)
-#define SPI_SSPPCELLID2_RESET _U(0x00000005)
+#define SPI_SSPPCELLID2_OFFSET _u(0x00000ff8)
+#define SPI_SSPPCELLID2_BITS _u(0x000000ff)
+#define SPI_SSPPCELLID2_RESET _u(0x00000005)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID2_SSPPCELLID2
// Description : These bits read back as 0x05
-#define SPI_SSPPCELLID2_SSPPCELLID2_RESET _U(0x05)
-#define SPI_SSPPCELLID2_SSPPCELLID2_BITS _U(0x000000ff)
-#define SPI_SSPPCELLID2_SSPPCELLID2_MSB _U(7)
-#define SPI_SSPPCELLID2_SSPPCELLID2_LSB _U(0)
+#define SPI_SSPPCELLID2_SSPPCELLID2_RESET _u(0x05)
+#define SPI_SSPPCELLID2_SSPPCELLID2_BITS _u(0x000000ff)
+#define SPI_SSPPCELLID2_SSPPCELLID2_MSB _u(7)
+#define SPI_SSPPCELLID2_SSPPCELLID2_LSB _u(0)
#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID3
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-#define SPI_SSPPCELLID3_OFFSET _U(0x00000ffc)
-#define SPI_SSPPCELLID3_BITS _U(0x000000ff)
-#define SPI_SSPPCELLID3_RESET _U(0x000000b1)
+#define SPI_SSPPCELLID3_OFFSET _u(0x00000ffc)
+#define SPI_SSPPCELLID3_BITS _u(0x000000ff)
+#define SPI_SSPPCELLID3_RESET _u(0x000000b1)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID3_SSPPCELLID3
// Description : These bits read back as 0xB1
-#define SPI_SSPPCELLID3_SSPPCELLID3_RESET _U(0xb1)
-#define SPI_SSPPCELLID3_SSPPCELLID3_BITS _U(0x000000ff)
-#define SPI_SSPPCELLID3_SSPPCELLID3_MSB _U(7)
-#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _U(0)
+#define SPI_SSPPCELLID3_SSPPCELLID3_RESET _u(0xb1)
+#define SPI_SSPPCELLID3_SSPPCELLID3_BITS _u(0x000000ff)
+#define SPI_SSPPCELLID3_SSPPCELLID3_MSB _u(7)
+#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0)
#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_SPI_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/ssi.h b/src/rp2040/hardware_regs/include/hardware/regs/ssi.h
index 034ed48..67fddc0 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/ssi.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/ssi.h
@@ -74,16 +74,16 @@
// =============================================================================
// Register : SSI_CTRLR0
// Description : Control register 0
-#define SSI_CTRLR0_OFFSET _U(0x00000000)
-#define SSI_CTRLR0_BITS _U(0x017fffff)
-#define SSI_CTRLR0_RESET _U(0x00000000)
+#define SSI_CTRLR0_OFFSET _u(0x00000000)
+#define SSI_CTRLR0_BITS _u(0x017fffff)
+#define SSI_CTRLR0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_SSTE
// Description : Slave select toggle enable
-#define SSI_CTRLR0_SSTE_RESET _U(0x0)
-#define SSI_CTRLR0_SSTE_BITS _U(0x01000000)
-#define SSI_CTRLR0_SSTE_MSB _U(24)
-#define SSI_CTRLR0_SSTE_LSB _U(24)
+#define SSI_CTRLR0_SSTE_RESET _u(0x0)
+#define SSI_CTRLR0_SSTE_BITS _u(0x01000000)
+#define SSI_CTRLR0_SSTE_MSB _u(24)
+#define SSI_CTRLR0_SSTE_LSB _u(24)
#define SSI_CTRLR0_SSTE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_SPI_FRF
@@ -92,47 +92,47 @@
// full-duplex
// 0x1 -> Dual-SPI frame format; two bits per SCK, half-duplex
// 0x2 -> Quad-SPI frame format; four bits per SCK, half-duplex
-#define SSI_CTRLR0_SPI_FRF_RESET _U(0x0)
-#define SSI_CTRLR0_SPI_FRF_BITS _U(0x00600000)
-#define SSI_CTRLR0_SPI_FRF_MSB _U(22)
-#define SSI_CTRLR0_SPI_FRF_LSB _U(21)
+#define SSI_CTRLR0_SPI_FRF_RESET _u(0x0)
+#define SSI_CTRLR0_SPI_FRF_BITS _u(0x00600000)
+#define SSI_CTRLR0_SPI_FRF_MSB _u(22)
+#define SSI_CTRLR0_SPI_FRF_LSB _u(21)
#define SSI_CTRLR0_SPI_FRF_ACCESS "RW"
-#define SSI_CTRLR0_SPI_FRF_VALUE_STD _U(0x0)
-#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL _U(0x1)
-#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD _U(0x2)
+#define SSI_CTRLR0_SPI_FRF_VALUE_STD _u(0x0)
+#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL _u(0x1)
+#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD _u(0x2)
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_DFS_32
// Description : Data frame size in 32b transfer mode
// Value of n -> n+1 clocks per frame.
-#define SSI_CTRLR0_DFS_32_RESET _U(0x00)
-#define SSI_CTRLR0_DFS_32_BITS _U(0x001f0000)
-#define SSI_CTRLR0_DFS_32_MSB _U(20)
-#define SSI_CTRLR0_DFS_32_LSB _U(16)
+#define SSI_CTRLR0_DFS_32_RESET _u(0x00)
+#define SSI_CTRLR0_DFS_32_BITS _u(0x001f0000)
+#define SSI_CTRLR0_DFS_32_MSB _u(20)
+#define SSI_CTRLR0_DFS_32_LSB _u(16)
#define SSI_CTRLR0_DFS_32_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_CFS
// Description : Control frame size
// Value of n -> n+1 clocks per frame.
-#define SSI_CTRLR0_CFS_RESET _U(0x0)
-#define SSI_CTRLR0_CFS_BITS _U(0x0000f000)
-#define SSI_CTRLR0_CFS_MSB _U(15)
-#define SSI_CTRLR0_CFS_LSB _U(12)
+#define SSI_CTRLR0_CFS_RESET _u(0x0)
+#define SSI_CTRLR0_CFS_BITS _u(0x0000f000)
+#define SSI_CTRLR0_CFS_MSB _u(15)
+#define SSI_CTRLR0_CFS_LSB _u(12)
#define SSI_CTRLR0_CFS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_SRL
// Description : Shift register loop (test mode)
-#define SSI_CTRLR0_SRL_RESET _U(0x0)
-#define SSI_CTRLR0_SRL_BITS _U(0x00000800)
-#define SSI_CTRLR0_SRL_MSB _U(11)
-#define SSI_CTRLR0_SRL_LSB _U(11)
+#define SSI_CTRLR0_SRL_RESET _u(0x0)
+#define SSI_CTRLR0_SRL_BITS _u(0x00000800)
+#define SSI_CTRLR0_SRL_MSB _u(11)
+#define SSI_CTRLR0_SRL_LSB _u(11)
#define SSI_CTRLR0_SRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_SLV_OE
// Description : Slave output enable
-#define SSI_CTRLR0_SLV_OE_RESET _U(0x0)
-#define SSI_CTRLR0_SLV_OE_BITS _U(0x00000400)
-#define SSI_CTRLR0_SLV_OE_MSB _U(10)
-#define SSI_CTRLR0_SLV_OE_LSB _U(10)
+#define SSI_CTRLR0_SLV_OE_RESET _u(0x0)
+#define SSI_CTRLR0_SLV_OE_BITS _u(0x00000400)
+#define SSI_CTRLR0_SLV_OE_MSB _u(10)
+#define SSI_CTRLR0_SLV_OE_LSB _u(10)
#define SSI_CTRLR0_SLV_OE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_TMOD
@@ -142,104 +142,104 @@
// 0x2 -> Receive only (not for FRF == 0, standard SPI mode)
// 0x3 -> EEPROM read mode (TX then RX; RX starts after control
// data TX'd)
-#define SSI_CTRLR0_TMOD_RESET _U(0x0)
-#define SSI_CTRLR0_TMOD_BITS _U(0x00000300)
-#define SSI_CTRLR0_TMOD_MSB _U(9)
-#define SSI_CTRLR0_TMOD_LSB _U(8)
+#define SSI_CTRLR0_TMOD_RESET _u(0x0)
+#define SSI_CTRLR0_TMOD_BITS _u(0x00000300)
+#define SSI_CTRLR0_TMOD_MSB _u(9)
+#define SSI_CTRLR0_TMOD_LSB _u(8)
#define SSI_CTRLR0_TMOD_ACCESS "RW"
-#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX _U(0x0)
-#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY _U(0x1)
-#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY _U(0x2)
-#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ _U(0x3)
+#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX _u(0x0)
+#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY _u(0x1)
+#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY _u(0x2)
+#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ _u(0x3)
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_SCPOL
// Description : Serial clock polarity
-#define SSI_CTRLR0_SCPOL_RESET _U(0x0)
-#define SSI_CTRLR0_SCPOL_BITS _U(0x00000080)
-#define SSI_CTRLR0_SCPOL_MSB _U(7)
-#define SSI_CTRLR0_SCPOL_LSB _U(7)
+#define SSI_CTRLR0_SCPOL_RESET _u(0x0)
+#define SSI_CTRLR0_SCPOL_BITS _u(0x00000080)
+#define SSI_CTRLR0_SCPOL_MSB _u(7)
+#define SSI_CTRLR0_SCPOL_LSB _u(7)
#define SSI_CTRLR0_SCPOL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_SCPH
// Description : Serial clock phase
-#define SSI_CTRLR0_SCPH_RESET _U(0x0)
-#define SSI_CTRLR0_SCPH_BITS _U(0x00000040)
-#define SSI_CTRLR0_SCPH_MSB _U(6)
-#define SSI_CTRLR0_SCPH_LSB _U(6)
+#define SSI_CTRLR0_SCPH_RESET _u(0x0)
+#define SSI_CTRLR0_SCPH_BITS _u(0x00000040)
+#define SSI_CTRLR0_SCPH_MSB _u(6)
+#define SSI_CTRLR0_SCPH_LSB _u(6)
#define SSI_CTRLR0_SCPH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_FRF
// Description : Frame format
-#define SSI_CTRLR0_FRF_RESET _U(0x0)
-#define SSI_CTRLR0_FRF_BITS _U(0x00000030)
-#define SSI_CTRLR0_FRF_MSB _U(5)
-#define SSI_CTRLR0_FRF_LSB _U(4)
+#define SSI_CTRLR0_FRF_RESET _u(0x0)
+#define SSI_CTRLR0_FRF_BITS _u(0x00000030)
+#define SSI_CTRLR0_FRF_MSB _u(5)
+#define SSI_CTRLR0_FRF_LSB _u(4)
#define SSI_CTRLR0_FRF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_DFS
// Description : Data frame size
-#define SSI_CTRLR0_DFS_RESET _U(0x0)
-#define SSI_CTRLR0_DFS_BITS _U(0x0000000f)
-#define SSI_CTRLR0_DFS_MSB _U(3)
-#define SSI_CTRLR0_DFS_LSB _U(0)
+#define SSI_CTRLR0_DFS_RESET _u(0x0)
+#define SSI_CTRLR0_DFS_BITS _u(0x0000000f)
+#define SSI_CTRLR0_DFS_MSB _u(3)
+#define SSI_CTRLR0_DFS_LSB _u(0)
#define SSI_CTRLR0_DFS_ACCESS "RW"
// =============================================================================
// Register : SSI_CTRLR1
// Description : Master Control register 1
-#define SSI_CTRLR1_OFFSET _U(0x00000004)
-#define SSI_CTRLR1_BITS _U(0x0000ffff)
-#define SSI_CTRLR1_RESET _U(0x00000000)
+#define SSI_CTRLR1_OFFSET _u(0x00000004)
+#define SSI_CTRLR1_BITS _u(0x0000ffff)
+#define SSI_CTRLR1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR1_NDF
// Description : Number of data frames
-#define SSI_CTRLR1_NDF_RESET _U(0x0000)
-#define SSI_CTRLR1_NDF_BITS _U(0x0000ffff)
-#define SSI_CTRLR1_NDF_MSB _U(15)
-#define SSI_CTRLR1_NDF_LSB _U(0)
+#define SSI_CTRLR1_NDF_RESET _u(0x0000)
+#define SSI_CTRLR1_NDF_BITS _u(0x0000ffff)
+#define SSI_CTRLR1_NDF_MSB _u(15)
+#define SSI_CTRLR1_NDF_LSB _u(0)
#define SSI_CTRLR1_NDF_ACCESS "RW"
// =============================================================================
// Register : SSI_SSIENR
// Description : SSI Enable
-#define SSI_SSIENR_OFFSET _U(0x00000008)
-#define SSI_SSIENR_BITS _U(0x00000001)
-#define SSI_SSIENR_RESET _U(0x00000000)
+#define SSI_SSIENR_OFFSET _u(0x00000008)
+#define SSI_SSIENR_BITS _u(0x00000001)
+#define SSI_SSIENR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_SSIENR_SSI_EN
// Description : SSI enable
-#define SSI_SSIENR_SSI_EN_RESET _U(0x0)
-#define SSI_SSIENR_SSI_EN_BITS _U(0x00000001)
-#define SSI_SSIENR_SSI_EN_MSB _U(0)
-#define SSI_SSIENR_SSI_EN_LSB _U(0)
+#define SSI_SSIENR_SSI_EN_RESET _u(0x0)
+#define SSI_SSIENR_SSI_EN_BITS _u(0x00000001)
+#define SSI_SSIENR_SSI_EN_MSB _u(0)
+#define SSI_SSIENR_SSI_EN_LSB _u(0)
#define SSI_SSIENR_SSI_EN_ACCESS "RW"
// =============================================================================
// Register : SSI_MWCR
// Description : Microwire Control
-#define SSI_MWCR_OFFSET _U(0x0000000c)
-#define SSI_MWCR_BITS _U(0x00000007)
-#define SSI_MWCR_RESET _U(0x00000000)
+#define SSI_MWCR_OFFSET _u(0x0000000c)
+#define SSI_MWCR_BITS _u(0x00000007)
+#define SSI_MWCR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_MWCR_MHS
// Description : Microwire handshaking
-#define SSI_MWCR_MHS_RESET _U(0x0)
-#define SSI_MWCR_MHS_BITS _U(0x00000004)
-#define SSI_MWCR_MHS_MSB _U(2)
-#define SSI_MWCR_MHS_LSB _U(2)
+#define SSI_MWCR_MHS_RESET _u(0x0)
+#define SSI_MWCR_MHS_BITS _u(0x00000004)
+#define SSI_MWCR_MHS_MSB _u(2)
+#define SSI_MWCR_MHS_LSB _u(2)
#define SSI_MWCR_MHS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_MWCR_MDD
// Description : Microwire control
-#define SSI_MWCR_MDD_RESET _U(0x0)
-#define SSI_MWCR_MDD_BITS _U(0x00000002)
-#define SSI_MWCR_MDD_MSB _U(1)
-#define SSI_MWCR_MDD_LSB _U(1)
+#define SSI_MWCR_MDD_RESET _u(0x0)
+#define SSI_MWCR_MDD_BITS _u(0x00000002)
+#define SSI_MWCR_MDD_MSB _u(1)
+#define SSI_MWCR_MDD_LSB _u(1)
#define SSI_MWCR_MDD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_MWCR_MWMOD
// Description : Microwire transfer mode
-#define SSI_MWCR_MWMOD_RESET _U(0x0)
-#define SSI_MWCR_MWMOD_BITS _U(0x00000001)
-#define SSI_MWCR_MWMOD_MSB _U(0)
-#define SSI_MWCR_MWMOD_LSB _U(0)
+#define SSI_MWCR_MWMOD_RESET _u(0x0)
+#define SSI_MWCR_MWMOD_BITS _u(0x00000001)
+#define SSI_MWCR_MWMOD_MSB _u(0)
+#define SSI_MWCR_MWMOD_LSB _u(0)
#define SSI_MWCR_MWMOD_ACCESS "RW"
// =============================================================================
// Register : SSI_SER
@@ -247,509 +247,509 @@
// For each bit:
// 0 -> slave not selected
// 1 -> slave selected
-#define SSI_SER_OFFSET _U(0x00000010)
-#define SSI_SER_BITS _U(0x00000001)
-#define SSI_SER_RESET _U(0x00000000)
-#define SSI_SER_MSB _U(0)
-#define SSI_SER_LSB _U(0)
+#define SSI_SER_OFFSET _u(0x00000010)
+#define SSI_SER_BITS _u(0x00000001)
+#define SSI_SER_RESET _u(0x00000000)
+#define SSI_SER_MSB _u(0)
+#define SSI_SER_LSB _u(0)
#define SSI_SER_ACCESS "RW"
// =============================================================================
// Register : SSI_BAUDR
// Description : Baud rate
-#define SSI_BAUDR_OFFSET _U(0x00000014)
-#define SSI_BAUDR_BITS _U(0x0000ffff)
-#define SSI_BAUDR_RESET _U(0x00000000)
+#define SSI_BAUDR_OFFSET _u(0x00000014)
+#define SSI_BAUDR_BITS _u(0x0000ffff)
+#define SSI_BAUDR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_BAUDR_SCKDV
// Description : SSI clock divider
-#define SSI_BAUDR_SCKDV_RESET _U(0x0000)
-#define SSI_BAUDR_SCKDV_BITS _U(0x0000ffff)
-#define SSI_BAUDR_SCKDV_MSB _U(15)
-#define SSI_BAUDR_SCKDV_LSB _U(0)
+#define SSI_BAUDR_SCKDV_RESET _u(0x0000)
+#define SSI_BAUDR_SCKDV_BITS _u(0x0000ffff)
+#define SSI_BAUDR_SCKDV_MSB _u(15)
+#define SSI_BAUDR_SCKDV_LSB _u(0)
#define SSI_BAUDR_SCKDV_ACCESS "RW"
// =============================================================================
// Register : SSI_TXFTLR
// Description : TX FIFO threshold level
-#define SSI_TXFTLR_OFFSET _U(0x00000018)
-#define SSI_TXFTLR_BITS _U(0x000000ff)
-#define SSI_TXFTLR_RESET _U(0x00000000)
+#define SSI_TXFTLR_OFFSET _u(0x00000018)
+#define SSI_TXFTLR_BITS _u(0x000000ff)
+#define SSI_TXFTLR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_TXFTLR_TFT
// Description : Transmit FIFO threshold
-#define SSI_TXFTLR_TFT_RESET _U(0x00)
-#define SSI_TXFTLR_TFT_BITS _U(0x000000ff)
-#define SSI_TXFTLR_TFT_MSB _U(7)
-#define SSI_TXFTLR_TFT_LSB _U(0)
+#define SSI_TXFTLR_TFT_RESET _u(0x00)
+#define SSI_TXFTLR_TFT_BITS _u(0x000000ff)
+#define SSI_TXFTLR_TFT_MSB _u(7)
+#define SSI_TXFTLR_TFT_LSB _u(0)
#define SSI_TXFTLR_TFT_ACCESS "RW"
// =============================================================================
// Register : SSI_RXFTLR
// Description : RX FIFO threshold level
-#define SSI_RXFTLR_OFFSET _U(0x0000001c)
-#define SSI_RXFTLR_BITS _U(0x000000ff)
-#define SSI_RXFTLR_RESET _U(0x00000000)
+#define SSI_RXFTLR_OFFSET _u(0x0000001c)
+#define SSI_RXFTLR_BITS _u(0x000000ff)
+#define SSI_RXFTLR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_RXFTLR_RFT
// Description : Receive FIFO threshold
-#define SSI_RXFTLR_RFT_RESET _U(0x00)
-#define SSI_RXFTLR_RFT_BITS _U(0x000000ff)
-#define SSI_RXFTLR_RFT_MSB _U(7)
-#define SSI_RXFTLR_RFT_LSB _U(0)
+#define SSI_RXFTLR_RFT_RESET _u(0x00)
+#define SSI_RXFTLR_RFT_BITS _u(0x000000ff)
+#define SSI_RXFTLR_RFT_MSB _u(7)
+#define SSI_RXFTLR_RFT_LSB _u(0)
#define SSI_RXFTLR_RFT_ACCESS "RW"
// =============================================================================
// Register : SSI_TXFLR
// Description : TX FIFO level
-#define SSI_TXFLR_OFFSET _U(0x00000020)
-#define SSI_TXFLR_BITS _U(0x000000ff)
-#define SSI_TXFLR_RESET _U(0x00000000)
+#define SSI_TXFLR_OFFSET _u(0x00000020)
+#define SSI_TXFLR_BITS _u(0x000000ff)
+#define SSI_TXFLR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_TXFLR_TFTFL
// Description : Transmit FIFO level
-#define SSI_TXFLR_TFTFL_RESET _U(0x00)
-#define SSI_TXFLR_TFTFL_BITS _U(0x000000ff)
-#define SSI_TXFLR_TFTFL_MSB _U(7)
-#define SSI_TXFLR_TFTFL_LSB _U(0)
+#define SSI_TXFLR_TFTFL_RESET _u(0x00)
+#define SSI_TXFLR_TFTFL_BITS _u(0x000000ff)
+#define SSI_TXFLR_TFTFL_MSB _u(7)
+#define SSI_TXFLR_TFTFL_LSB _u(0)
#define SSI_TXFLR_TFTFL_ACCESS "RO"
// =============================================================================
// Register : SSI_RXFLR
// Description : RX FIFO level
-#define SSI_RXFLR_OFFSET _U(0x00000024)
-#define SSI_RXFLR_BITS _U(0x000000ff)
-#define SSI_RXFLR_RESET _U(0x00000000)
+#define SSI_RXFLR_OFFSET _u(0x00000024)
+#define SSI_RXFLR_BITS _u(0x000000ff)
+#define SSI_RXFLR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_RXFLR_RXTFL
// Description : Receive FIFO level
-#define SSI_RXFLR_RXTFL_RESET _U(0x00)
-#define SSI_RXFLR_RXTFL_BITS _U(0x000000ff)
-#define SSI_RXFLR_RXTFL_MSB _U(7)
-#define SSI_RXFLR_RXTFL_LSB _U(0)
+#define SSI_RXFLR_RXTFL_RESET _u(0x00)
+#define SSI_RXFLR_RXTFL_BITS _u(0x000000ff)
+#define SSI_RXFLR_RXTFL_MSB _u(7)
+#define SSI_RXFLR_RXTFL_LSB _u(0)
#define SSI_RXFLR_RXTFL_ACCESS "RO"
// =============================================================================
// Register : SSI_SR
// Description : Status register
-#define SSI_SR_OFFSET _U(0x00000028)
-#define SSI_SR_BITS _U(0x0000007f)
-#define SSI_SR_RESET _U(0x00000000)
+#define SSI_SR_OFFSET _u(0x00000028)
+#define SSI_SR_BITS _u(0x0000007f)
+#define SSI_SR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_SR_DCOL
// Description : Data collision error
-#define SSI_SR_DCOL_RESET _U(0x0)
-#define SSI_SR_DCOL_BITS _U(0x00000040)
-#define SSI_SR_DCOL_MSB _U(6)
-#define SSI_SR_DCOL_LSB _U(6)
+#define SSI_SR_DCOL_RESET _u(0x0)
+#define SSI_SR_DCOL_BITS _u(0x00000040)
+#define SSI_SR_DCOL_MSB _u(6)
+#define SSI_SR_DCOL_LSB _u(6)
#define SSI_SR_DCOL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_SR_TXE
// Description : Transmission error
-#define SSI_SR_TXE_RESET _U(0x0)
-#define SSI_SR_TXE_BITS _U(0x00000020)
-#define SSI_SR_TXE_MSB _U(5)
-#define SSI_SR_TXE_LSB _U(5)
+#define SSI_SR_TXE_RESET _u(0x0)
+#define SSI_SR_TXE_BITS _u(0x00000020)
+#define SSI_SR_TXE_MSB _u(5)
+#define SSI_SR_TXE_LSB _u(5)
#define SSI_SR_TXE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_SR_RFF
// Description : Receive FIFO full
-#define SSI_SR_RFF_RESET _U(0x0)
-#define SSI_SR_RFF_BITS _U(0x00000010)
-#define SSI_SR_RFF_MSB _U(4)
-#define SSI_SR_RFF_LSB _U(4)
+#define SSI_SR_RFF_RESET _u(0x0)
+#define SSI_SR_RFF_BITS _u(0x00000010)
+#define SSI_SR_RFF_MSB _u(4)
+#define SSI_SR_RFF_LSB _u(4)
#define SSI_SR_RFF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_SR_RFNE
// Description : Receive FIFO not empty
-#define SSI_SR_RFNE_RESET _U(0x0)
-#define SSI_SR_RFNE_BITS _U(0x00000008)
-#define SSI_SR_RFNE_MSB _U(3)
-#define SSI_SR_RFNE_LSB _U(3)
+#define SSI_SR_RFNE_RESET _u(0x0)
+#define SSI_SR_RFNE_BITS _u(0x00000008)
+#define SSI_SR_RFNE_MSB _u(3)
+#define SSI_SR_RFNE_LSB _u(3)
#define SSI_SR_RFNE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_SR_TFE
// Description : Transmit FIFO empty
-#define SSI_SR_TFE_RESET _U(0x0)
-#define SSI_SR_TFE_BITS _U(0x00000004)
-#define SSI_SR_TFE_MSB _U(2)
-#define SSI_SR_TFE_LSB _U(2)
+#define SSI_SR_TFE_RESET _u(0x0)
+#define SSI_SR_TFE_BITS _u(0x00000004)
+#define SSI_SR_TFE_MSB _u(2)
+#define SSI_SR_TFE_LSB _u(2)
#define SSI_SR_TFE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_SR_TFNF
// Description : Transmit FIFO not full
-#define SSI_SR_TFNF_RESET _U(0x0)
-#define SSI_SR_TFNF_BITS _U(0x00000002)
-#define SSI_SR_TFNF_MSB _U(1)
-#define SSI_SR_TFNF_LSB _U(1)
+#define SSI_SR_TFNF_RESET _u(0x0)
+#define SSI_SR_TFNF_BITS _u(0x00000002)
+#define SSI_SR_TFNF_MSB _u(1)
+#define SSI_SR_TFNF_LSB _u(1)
#define SSI_SR_TFNF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_SR_BUSY
// Description : SSI busy flag
-#define SSI_SR_BUSY_RESET _U(0x0)
-#define SSI_SR_BUSY_BITS _U(0x00000001)
-#define SSI_SR_BUSY_MSB _U(0)
-#define SSI_SR_BUSY_LSB _U(0)
+#define SSI_SR_BUSY_RESET _u(0x0)
+#define SSI_SR_BUSY_BITS _u(0x00000001)
+#define SSI_SR_BUSY_MSB _u(0)
+#define SSI_SR_BUSY_LSB _u(0)
#define SSI_SR_BUSY_ACCESS "RO"
// =============================================================================
// Register : SSI_IMR
// Description : Interrupt mask
-#define SSI_IMR_OFFSET _U(0x0000002c)
-#define SSI_IMR_BITS _U(0x0000003f)
-#define SSI_IMR_RESET _U(0x00000000)
+#define SSI_IMR_OFFSET _u(0x0000002c)
+#define SSI_IMR_BITS _u(0x0000003f)
+#define SSI_IMR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_IMR_MSTIM
// Description : Multi-master contention interrupt mask
-#define SSI_IMR_MSTIM_RESET _U(0x0)
-#define SSI_IMR_MSTIM_BITS _U(0x00000020)
-#define SSI_IMR_MSTIM_MSB _U(5)
-#define SSI_IMR_MSTIM_LSB _U(5)
+#define SSI_IMR_MSTIM_RESET _u(0x0)
+#define SSI_IMR_MSTIM_BITS _u(0x00000020)
+#define SSI_IMR_MSTIM_MSB _u(5)
+#define SSI_IMR_MSTIM_LSB _u(5)
#define SSI_IMR_MSTIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_IMR_RXFIM
// Description : Receive FIFO full interrupt mask
-#define SSI_IMR_RXFIM_RESET _U(0x0)
-#define SSI_IMR_RXFIM_BITS _U(0x00000010)
-#define SSI_IMR_RXFIM_MSB _U(4)
-#define SSI_IMR_RXFIM_LSB _U(4)
+#define SSI_IMR_RXFIM_RESET _u(0x0)
+#define SSI_IMR_RXFIM_BITS _u(0x00000010)
+#define SSI_IMR_RXFIM_MSB _u(4)
+#define SSI_IMR_RXFIM_LSB _u(4)
#define SSI_IMR_RXFIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_IMR_RXOIM
// Description : Receive FIFO overflow interrupt mask
-#define SSI_IMR_RXOIM_RESET _U(0x0)
-#define SSI_IMR_RXOIM_BITS _U(0x00000008)
-#define SSI_IMR_RXOIM_MSB _U(3)
-#define SSI_IMR_RXOIM_LSB _U(3)
+#define SSI_IMR_RXOIM_RESET _u(0x0)
+#define SSI_IMR_RXOIM_BITS _u(0x00000008)
+#define SSI_IMR_RXOIM_MSB _u(3)
+#define SSI_IMR_RXOIM_LSB _u(3)
#define SSI_IMR_RXOIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_IMR_RXUIM
// Description : Receive FIFO underflow interrupt mask
-#define SSI_IMR_RXUIM_RESET _U(0x0)
-#define SSI_IMR_RXUIM_BITS _U(0x00000004)
-#define SSI_IMR_RXUIM_MSB _U(2)
-#define SSI_IMR_RXUIM_LSB _U(2)
+#define SSI_IMR_RXUIM_RESET _u(0x0)
+#define SSI_IMR_RXUIM_BITS _u(0x00000004)
+#define SSI_IMR_RXUIM_MSB _u(2)
+#define SSI_IMR_RXUIM_LSB _u(2)
#define SSI_IMR_RXUIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_IMR_TXOIM
// Description : Transmit FIFO overflow interrupt mask
-#define SSI_IMR_TXOIM_RESET _U(0x0)
-#define SSI_IMR_TXOIM_BITS _U(0x00000002)
-#define SSI_IMR_TXOIM_MSB _U(1)
-#define SSI_IMR_TXOIM_LSB _U(1)
+#define SSI_IMR_TXOIM_RESET _u(0x0)
+#define SSI_IMR_TXOIM_BITS _u(0x00000002)
+#define SSI_IMR_TXOIM_MSB _u(1)
+#define SSI_IMR_TXOIM_LSB _u(1)
#define SSI_IMR_TXOIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_IMR_TXEIM
// Description : Transmit FIFO empty interrupt mask
-#define SSI_IMR_TXEIM_RESET _U(0x0)
-#define SSI_IMR_TXEIM_BITS _U(0x00000001)
-#define SSI_IMR_TXEIM_MSB _U(0)
-#define SSI_IMR_TXEIM_LSB _U(0)
+#define SSI_IMR_TXEIM_RESET _u(0x0)
+#define SSI_IMR_TXEIM_BITS _u(0x00000001)
+#define SSI_IMR_TXEIM_MSB _u(0)
+#define SSI_IMR_TXEIM_LSB _u(0)
#define SSI_IMR_TXEIM_ACCESS "RW"
// =============================================================================
// Register : SSI_ISR
// Description : Interrupt status
-#define SSI_ISR_OFFSET _U(0x00000030)
-#define SSI_ISR_BITS _U(0x0000003f)
-#define SSI_ISR_RESET _U(0x00000000)
+#define SSI_ISR_OFFSET _u(0x00000030)
+#define SSI_ISR_BITS _u(0x0000003f)
+#define SSI_ISR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_ISR_MSTIS
// Description : Multi-master contention interrupt status
-#define SSI_ISR_MSTIS_RESET _U(0x0)
-#define SSI_ISR_MSTIS_BITS _U(0x00000020)
-#define SSI_ISR_MSTIS_MSB _U(5)
-#define SSI_ISR_MSTIS_LSB _U(5)
+#define SSI_ISR_MSTIS_RESET _u(0x0)
+#define SSI_ISR_MSTIS_BITS _u(0x00000020)
+#define SSI_ISR_MSTIS_MSB _u(5)
+#define SSI_ISR_MSTIS_LSB _u(5)
#define SSI_ISR_MSTIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_ISR_RXFIS
// Description : Receive FIFO full interrupt status
-#define SSI_ISR_RXFIS_RESET _U(0x0)
-#define SSI_ISR_RXFIS_BITS _U(0x00000010)
-#define SSI_ISR_RXFIS_MSB _U(4)
-#define SSI_ISR_RXFIS_LSB _U(4)
+#define SSI_ISR_RXFIS_RESET _u(0x0)
+#define SSI_ISR_RXFIS_BITS _u(0x00000010)
+#define SSI_ISR_RXFIS_MSB _u(4)
+#define SSI_ISR_RXFIS_LSB _u(4)
#define SSI_ISR_RXFIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_ISR_RXOIS
// Description : Receive FIFO overflow interrupt status
-#define SSI_ISR_RXOIS_RESET _U(0x0)
-#define SSI_ISR_RXOIS_BITS _U(0x00000008)
-#define SSI_ISR_RXOIS_MSB _U(3)
-#define SSI_ISR_RXOIS_LSB _U(3)
+#define SSI_ISR_RXOIS_RESET _u(0x0)
+#define SSI_ISR_RXOIS_BITS _u(0x00000008)
+#define SSI_ISR_RXOIS_MSB _u(3)
+#define SSI_ISR_RXOIS_LSB _u(3)
#define SSI_ISR_RXOIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_ISR_RXUIS
// Description : Receive FIFO underflow interrupt status
-#define SSI_ISR_RXUIS_RESET _U(0x0)
-#define SSI_ISR_RXUIS_BITS _U(0x00000004)
-#define SSI_ISR_RXUIS_MSB _U(2)
-#define SSI_ISR_RXUIS_LSB _U(2)
+#define SSI_ISR_RXUIS_RESET _u(0x0)
+#define SSI_ISR_RXUIS_BITS _u(0x00000004)
+#define SSI_ISR_RXUIS_MSB _u(2)
+#define SSI_ISR_RXUIS_LSB _u(2)
#define SSI_ISR_RXUIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_ISR_TXOIS
// Description : Transmit FIFO overflow interrupt status
-#define SSI_ISR_TXOIS_RESET _U(0x0)
-#define SSI_ISR_TXOIS_BITS _U(0x00000002)
-#define SSI_ISR_TXOIS_MSB _U(1)
-#define SSI_ISR_TXOIS_LSB _U(1)
+#define SSI_ISR_TXOIS_RESET _u(0x0)
+#define SSI_ISR_TXOIS_BITS _u(0x00000002)
+#define SSI_ISR_TXOIS_MSB _u(1)
+#define SSI_ISR_TXOIS_LSB _u(1)
#define SSI_ISR_TXOIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_ISR_TXEIS
// Description : Transmit FIFO empty interrupt status
-#define SSI_ISR_TXEIS_RESET _U(0x0)
-#define SSI_ISR_TXEIS_BITS _U(0x00000001)
-#define SSI_ISR_TXEIS_MSB _U(0)
-#define SSI_ISR_TXEIS_LSB _U(0)
+#define SSI_ISR_TXEIS_RESET _u(0x0)
+#define SSI_ISR_TXEIS_BITS _u(0x00000001)
+#define SSI_ISR_TXEIS_MSB _u(0)
+#define SSI_ISR_TXEIS_LSB _u(0)
#define SSI_ISR_TXEIS_ACCESS "RO"
// =============================================================================
// Register : SSI_RISR
// Description : Raw interrupt status
-#define SSI_RISR_OFFSET _U(0x00000034)
-#define SSI_RISR_BITS _U(0x0000003f)
-#define SSI_RISR_RESET _U(0x00000000)
+#define SSI_RISR_OFFSET _u(0x00000034)
+#define SSI_RISR_BITS _u(0x0000003f)
+#define SSI_RISR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_RISR_MSTIR
// Description : Multi-master contention raw interrupt status
-#define SSI_RISR_MSTIR_RESET _U(0x0)
-#define SSI_RISR_MSTIR_BITS _U(0x00000020)
-#define SSI_RISR_MSTIR_MSB _U(5)
-#define SSI_RISR_MSTIR_LSB _U(5)
+#define SSI_RISR_MSTIR_RESET _u(0x0)
+#define SSI_RISR_MSTIR_BITS _u(0x00000020)
+#define SSI_RISR_MSTIR_MSB _u(5)
+#define SSI_RISR_MSTIR_LSB _u(5)
#define SSI_RISR_MSTIR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_RISR_RXFIR
// Description : Receive FIFO full raw interrupt status
-#define SSI_RISR_RXFIR_RESET _U(0x0)
-#define SSI_RISR_RXFIR_BITS _U(0x00000010)
-#define SSI_RISR_RXFIR_MSB _U(4)
-#define SSI_RISR_RXFIR_LSB _U(4)
+#define SSI_RISR_RXFIR_RESET _u(0x0)
+#define SSI_RISR_RXFIR_BITS _u(0x00000010)
+#define SSI_RISR_RXFIR_MSB _u(4)
+#define SSI_RISR_RXFIR_LSB _u(4)
#define SSI_RISR_RXFIR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_RISR_RXOIR
// Description : Receive FIFO overflow raw interrupt status
-#define SSI_RISR_RXOIR_RESET _U(0x0)
-#define SSI_RISR_RXOIR_BITS _U(0x00000008)
-#define SSI_RISR_RXOIR_MSB _U(3)
-#define SSI_RISR_RXOIR_LSB _U(3)
+#define SSI_RISR_RXOIR_RESET _u(0x0)
+#define SSI_RISR_RXOIR_BITS _u(0x00000008)
+#define SSI_RISR_RXOIR_MSB _u(3)
+#define SSI_RISR_RXOIR_LSB _u(3)
#define SSI_RISR_RXOIR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_RISR_RXUIR
// Description : Receive FIFO underflow raw interrupt status
-#define SSI_RISR_RXUIR_RESET _U(0x0)
-#define SSI_RISR_RXUIR_BITS _U(0x00000004)
-#define SSI_RISR_RXUIR_MSB _U(2)
-#define SSI_RISR_RXUIR_LSB _U(2)
+#define SSI_RISR_RXUIR_RESET _u(0x0)
+#define SSI_RISR_RXUIR_BITS _u(0x00000004)
+#define SSI_RISR_RXUIR_MSB _u(2)
+#define SSI_RISR_RXUIR_LSB _u(2)
#define SSI_RISR_RXUIR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_RISR_TXOIR
// Description : Transmit FIFO overflow raw interrupt status
-#define SSI_RISR_TXOIR_RESET _U(0x0)
-#define SSI_RISR_TXOIR_BITS _U(0x00000002)
-#define SSI_RISR_TXOIR_MSB _U(1)
-#define SSI_RISR_TXOIR_LSB _U(1)
+#define SSI_RISR_TXOIR_RESET _u(0x0)
+#define SSI_RISR_TXOIR_BITS _u(0x00000002)
+#define SSI_RISR_TXOIR_MSB _u(1)
+#define SSI_RISR_TXOIR_LSB _u(1)
#define SSI_RISR_TXOIR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_RISR_TXEIR
// Description : Transmit FIFO empty raw interrupt status
-#define SSI_RISR_TXEIR_RESET _U(0x0)
-#define SSI_RISR_TXEIR_BITS _U(0x00000001)
-#define SSI_RISR_TXEIR_MSB _U(0)
-#define SSI_RISR_TXEIR_LSB _U(0)
+#define SSI_RISR_TXEIR_RESET _u(0x0)
+#define SSI_RISR_TXEIR_BITS _u(0x00000001)
+#define SSI_RISR_TXEIR_MSB _u(0)
+#define SSI_RISR_TXEIR_LSB _u(0)
#define SSI_RISR_TXEIR_ACCESS "RO"
// =============================================================================
// Register : SSI_TXOICR
// Description : TX FIFO overflow interrupt clear
// Clear-on-read transmit FIFO overflow interrupt
-#define SSI_TXOICR_OFFSET _U(0x00000038)
-#define SSI_TXOICR_BITS _U(0x00000001)
-#define SSI_TXOICR_RESET _U(0x00000000)
-#define SSI_TXOICR_MSB _U(0)
-#define SSI_TXOICR_LSB _U(0)
+#define SSI_TXOICR_OFFSET _u(0x00000038)
+#define SSI_TXOICR_BITS _u(0x00000001)
+#define SSI_TXOICR_RESET _u(0x00000000)
+#define SSI_TXOICR_MSB _u(0)
+#define SSI_TXOICR_LSB _u(0)
#define SSI_TXOICR_ACCESS "RO"
// =============================================================================
// Register : SSI_RXOICR
// Description : RX FIFO overflow interrupt clear
// Clear-on-read receive FIFO overflow interrupt
-#define SSI_RXOICR_OFFSET _U(0x0000003c)
-#define SSI_RXOICR_BITS _U(0x00000001)
-#define SSI_RXOICR_RESET _U(0x00000000)
-#define SSI_RXOICR_MSB _U(0)
-#define SSI_RXOICR_LSB _U(0)
+#define SSI_RXOICR_OFFSET _u(0x0000003c)
+#define SSI_RXOICR_BITS _u(0x00000001)
+#define SSI_RXOICR_RESET _u(0x00000000)
+#define SSI_RXOICR_MSB _u(0)
+#define SSI_RXOICR_LSB _u(0)
#define SSI_RXOICR_ACCESS "RO"
// =============================================================================
// Register : SSI_RXUICR
// Description : RX FIFO underflow interrupt clear
// Clear-on-read receive FIFO underflow interrupt
-#define SSI_RXUICR_OFFSET _U(0x00000040)
-#define SSI_RXUICR_BITS _U(0x00000001)
-#define SSI_RXUICR_RESET _U(0x00000000)
-#define SSI_RXUICR_MSB _U(0)
-#define SSI_RXUICR_LSB _U(0)
+#define SSI_RXUICR_OFFSET _u(0x00000040)
+#define SSI_RXUICR_BITS _u(0x00000001)
+#define SSI_RXUICR_RESET _u(0x00000000)
+#define SSI_RXUICR_MSB _u(0)
+#define SSI_RXUICR_LSB _u(0)
#define SSI_RXUICR_ACCESS "RO"
// =============================================================================
// Register : SSI_MSTICR
// Description : Multi-master interrupt clear
// Clear-on-read multi-master contention interrupt
-#define SSI_MSTICR_OFFSET _U(0x00000044)
-#define SSI_MSTICR_BITS _U(0x00000001)
-#define SSI_MSTICR_RESET _U(0x00000000)
-#define SSI_MSTICR_MSB _U(0)
-#define SSI_MSTICR_LSB _U(0)
+#define SSI_MSTICR_OFFSET _u(0x00000044)
+#define SSI_MSTICR_BITS _u(0x00000001)
+#define SSI_MSTICR_RESET _u(0x00000000)
+#define SSI_MSTICR_MSB _u(0)
+#define SSI_MSTICR_LSB _u(0)
#define SSI_MSTICR_ACCESS "RO"
// =============================================================================
// Register : SSI_ICR
// Description : Interrupt clear
// Clear-on-read all active interrupts
-#define SSI_ICR_OFFSET _U(0x00000048)
-#define SSI_ICR_BITS _U(0x00000001)
-#define SSI_ICR_RESET _U(0x00000000)
-#define SSI_ICR_MSB _U(0)
-#define SSI_ICR_LSB _U(0)
+#define SSI_ICR_OFFSET _u(0x00000048)
+#define SSI_ICR_BITS _u(0x00000001)
+#define SSI_ICR_RESET _u(0x00000000)
+#define SSI_ICR_MSB _u(0)
+#define SSI_ICR_LSB _u(0)
#define SSI_ICR_ACCESS "RO"
// =============================================================================
// Register : SSI_DMACR
// Description : DMA control
-#define SSI_DMACR_OFFSET _U(0x0000004c)
-#define SSI_DMACR_BITS _U(0x00000003)
-#define SSI_DMACR_RESET _U(0x00000000)
+#define SSI_DMACR_OFFSET _u(0x0000004c)
+#define SSI_DMACR_BITS _u(0x00000003)
+#define SSI_DMACR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_DMACR_TDMAE
// Description : Transmit DMA enable
-#define SSI_DMACR_TDMAE_RESET _U(0x0)
-#define SSI_DMACR_TDMAE_BITS _U(0x00000002)
-#define SSI_DMACR_TDMAE_MSB _U(1)
-#define SSI_DMACR_TDMAE_LSB _U(1)
+#define SSI_DMACR_TDMAE_RESET _u(0x0)
+#define SSI_DMACR_TDMAE_BITS _u(0x00000002)
+#define SSI_DMACR_TDMAE_MSB _u(1)
+#define SSI_DMACR_TDMAE_LSB _u(1)
#define SSI_DMACR_TDMAE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_DMACR_RDMAE
// Description : Receive DMA enable
-#define SSI_DMACR_RDMAE_RESET _U(0x0)
-#define SSI_DMACR_RDMAE_BITS _U(0x00000001)
-#define SSI_DMACR_RDMAE_MSB _U(0)
-#define SSI_DMACR_RDMAE_LSB _U(0)
+#define SSI_DMACR_RDMAE_RESET _u(0x0)
+#define SSI_DMACR_RDMAE_BITS _u(0x00000001)
+#define SSI_DMACR_RDMAE_MSB _u(0)
+#define SSI_DMACR_RDMAE_LSB _u(0)
#define SSI_DMACR_RDMAE_ACCESS "RW"
// =============================================================================
// Register : SSI_DMATDLR
// Description : DMA TX data level
-#define SSI_DMATDLR_OFFSET _U(0x00000050)
-#define SSI_DMATDLR_BITS _U(0x000000ff)
-#define SSI_DMATDLR_RESET _U(0x00000000)
+#define SSI_DMATDLR_OFFSET _u(0x00000050)
+#define SSI_DMATDLR_BITS _u(0x000000ff)
+#define SSI_DMATDLR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_DMATDLR_DMATDL
// Description : Transmit data watermark level
-#define SSI_DMATDLR_DMATDL_RESET _U(0x00)
-#define SSI_DMATDLR_DMATDL_BITS _U(0x000000ff)
-#define SSI_DMATDLR_DMATDL_MSB _U(7)
-#define SSI_DMATDLR_DMATDL_LSB _U(0)
+#define SSI_DMATDLR_DMATDL_RESET _u(0x00)
+#define SSI_DMATDLR_DMATDL_BITS _u(0x000000ff)
+#define SSI_DMATDLR_DMATDL_MSB _u(7)
+#define SSI_DMATDLR_DMATDL_LSB _u(0)
#define SSI_DMATDLR_DMATDL_ACCESS "RW"
// =============================================================================
// Register : SSI_DMARDLR
// Description : DMA RX data level
-#define SSI_DMARDLR_OFFSET _U(0x00000054)
-#define SSI_DMARDLR_BITS _U(0x000000ff)
-#define SSI_DMARDLR_RESET _U(0x00000000)
+#define SSI_DMARDLR_OFFSET _u(0x00000054)
+#define SSI_DMARDLR_BITS _u(0x000000ff)
+#define SSI_DMARDLR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_DMARDLR_DMARDL
// Description : Receive data watermark level (DMARDLR+1)
-#define SSI_DMARDLR_DMARDL_RESET _U(0x00)
-#define SSI_DMARDLR_DMARDL_BITS _U(0x000000ff)
-#define SSI_DMARDLR_DMARDL_MSB _U(7)
-#define SSI_DMARDLR_DMARDL_LSB _U(0)
+#define SSI_DMARDLR_DMARDL_RESET _u(0x00)
+#define SSI_DMARDLR_DMARDL_BITS _u(0x000000ff)
+#define SSI_DMARDLR_DMARDL_MSB _u(7)
+#define SSI_DMARDLR_DMARDL_LSB _u(0)
#define SSI_DMARDLR_DMARDL_ACCESS "RW"
// =============================================================================
// Register : SSI_IDR
// Description : Identification register
-#define SSI_IDR_OFFSET _U(0x00000058)
-#define SSI_IDR_BITS _U(0xffffffff)
-#define SSI_IDR_RESET _U(0x51535049)
+#define SSI_IDR_OFFSET _u(0x00000058)
+#define SSI_IDR_BITS _u(0xffffffff)
+#define SSI_IDR_RESET _u(0x51535049)
// -----------------------------------------------------------------------------
// Field : SSI_IDR_IDCODE
// Description : Peripheral dentification code
-#define SSI_IDR_IDCODE_RESET _U(0x51535049)
-#define SSI_IDR_IDCODE_BITS _U(0xffffffff)
-#define SSI_IDR_IDCODE_MSB _U(31)
-#define SSI_IDR_IDCODE_LSB _U(0)
+#define SSI_IDR_IDCODE_RESET _u(0x51535049)
+#define SSI_IDR_IDCODE_BITS _u(0xffffffff)
+#define SSI_IDR_IDCODE_MSB _u(31)
+#define SSI_IDR_IDCODE_LSB _u(0)
#define SSI_IDR_IDCODE_ACCESS "RO"
// =============================================================================
// Register : SSI_SSI_VERSION_ID
// Description : Version ID
-#define SSI_SSI_VERSION_ID_OFFSET _U(0x0000005c)
-#define SSI_SSI_VERSION_ID_BITS _U(0xffffffff)
-#define SSI_SSI_VERSION_ID_RESET _U(0x3430312a)
+#define SSI_SSI_VERSION_ID_OFFSET _u(0x0000005c)
+#define SSI_SSI_VERSION_ID_BITS _u(0xffffffff)
+#define SSI_SSI_VERSION_ID_RESET _u(0x3430312a)
// -----------------------------------------------------------------------------
// Field : SSI_SSI_VERSION_ID_SSI_COMP_VERSION
// Description : SNPS component version (format X.YY)
-#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_RESET _U(0x3430312a)
-#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_BITS _U(0xffffffff)
-#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_MSB _U(31)
-#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_LSB _U(0)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_RESET _u(0x3430312a)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_BITS _u(0xffffffff)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_MSB _u(31)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_LSB _u(0)
#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_ACCESS "RO"
// =============================================================================
// Register : SSI_DR0
// Description : Data Register 0 (of 36)
-#define SSI_DR0_OFFSET _U(0x00000060)
-#define SSI_DR0_BITS _U(0xffffffff)
-#define SSI_DR0_RESET _U(0x00000000)
+#define SSI_DR0_OFFSET _u(0x00000060)
+#define SSI_DR0_BITS _u(0xffffffff)
+#define SSI_DR0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_DR0_DR
// Description : First data register of 36
-#define SSI_DR0_DR_RESET _U(0x00000000)
-#define SSI_DR0_DR_BITS _U(0xffffffff)
-#define SSI_DR0_DR_MSB _U(31)
-#define SSI_DR0_DR_LSB _U(0)
+#define SSI_DR0_DR_RESET _u(0x00000000)
+#define SSI_DR0_DR_BITS _u(0xffffffff)
+#define SSI_DR0_DR_MSB _u(31)
+#define SSI_DR0_DR_LSB _u(0)
#define SSI_DR0_DR_ACCESS "RW"
// =============================================================================
// Register : SSI_RX_SAMPLE_DLY
// Description : RX sample delay
-#define SSI_RX_SAMPLE_DLY_OFFSET _U(0x000000f0)
-#define SSI_RX_SAMPLE_DLY_BITS _U(0x000000ff)
-#define SSI_RX_SAMPLE_DLY_RESET _U(0x00000000)
+#define SSI_RX_SAMPLE_DLY_OFFSET _u(0x000000f0)
+#define SSI_RX_SAMPLE_DLY_BITS _u(0x000000ff)
+#define SSI_RX_SAMPLE_DLY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_RX_SAMPLE_DLY_RSD
// Description : RXD sample delay (in SCLK cycles)
-#define SSI_RX_SAMPLE_DLY_RSD_RESET _U(0x00)
-#define SSI_RX_SAMPLE_DLY_RSD_BITS _U(0x000000ff)
-#define SSI_RX_SAMPLE_DLY_RSD_MSB _U(7)
-#define SSI_RX_SAMPLE_DLY_RSD_LSB _U(0)
+#define SSI_RX_SAMPLE_DLY_RSD_RESET _u(0x00)
+#define SSI_RX_SAMPLE_DLY_RSD_BITS _u(0x000000ff)
+#define SSI_RX_SAMPLE_DLY_RSD_MSB _u(7)
+#define SSI_RX_SAMPLE_DLY_RSD_LSB _u(0)
#define SSI_RX_SAMPLE_DLY_RSD_ACCESS "RW"
// =============================================================================
// Register : SSI_SPI_CTRLR0
// Description : SPI control
-#define SSI_SPI_CTRLR0_OFFSET _U(0x000000f4)
-#define SSI_SPI_CTRLR0_BITS _U(0xff07fb3f)
-#define SSI_SPI_CTRLR0_RESET _U(0x03000000)
+#define SSI_SPI_CTRLR0_OFFSET _u(0x000000f4)
+#define SSI_SPI_CTRLR0_BITS _u(0xff07fb3f)
+#define SSI_SPI_CTRLR0_RESET _u(0x03000000)
// -----------------------------------------------------------------------------
// Field : SSI_SPI_CTRLR0_XIP_CMD
// Description : SPI Command to send in XIP mode (INST_L = 8-bit) or to append
// to Address (INST_L = 0-bit)
-#define SSI_SPI_CTRLR0_XIP_CMD_RESET _U(0x03)
-#define SSI_SPI_CTRLR0_XIP_CMD_BITS _U(0xff000000)
-#define SSI_SPI_CTRLR0_XIP_CMD_MSB _U(31)
-#define SSI_SPI_CTRLR0_XIP_CMD_LSB _U(24)
+#define SSI_SPI_CTRLR0_XIP_CMD_RESET _u(0x03)
+#define SSI_SPI_CTRLR0_XIP_CMD_BITS _u(0xff000000)
+#define SSI_SPI_CTRLR0_XIP_CMD_MSB _u(31)
+#define SSI_SPI_CTRLR0_XIP_CMD_LSB _u(24)
#define SSI_SPI_CTRLR0_XIP_CMD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_SPI_CTRLR0_SPI_RXDS_EN
// Description : Read data strobe enable
-#define SSI_SPI_CTRLR0_SPI_RXDS_EN_RESET _U(0x0)
-#define SSI_SPI_CTRLR0_SPI_RXDS_EN_BITS _U(0x00040000)
-#define SSI_SPI_CTRLR0_SPI_RXDS_EN_MSB _U(18)
-#define SSI_SPI_CTRLR0_SPI_RXDS_EN_LSB _U(18)
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_RESET _u(0x0)
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_BITS _u(0x00040000)
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_MSB _u(18)
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_LSB _u(18)
#define SSI_SPI_CTRLR0_SPI_RXDS_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_SPI_CTRLR0_INST_DDR_EN
// Description : Instruction DDR transfer enable
-#define SSI_SPI_CTRLR0_INST_DDR_EN_RESET _U(0x0)
-#define SSI_SPI_CTRLR0_INST_DDR_EN_BITS _U(0x00020000)
-#define SSI_SPI_CTRLR0_INST_DDR_EN_MSB _U(17)
-#define SSI_SPI_CTRLR0_INST_DDR_EN_LSB _U(17)
+#define SSI_SPI_CTRLR0_INST_DDR_EN_RESET _u(0x0)
+#define SSI_SPI_CTRLR0_INST_DDR_EN_BITS _u(0x00020000)
+#define SSI_SPI_CTRLR0_INST_DDR_EN_MSB _u(17)
+#define SSI_SPI_CTRLR0_INST_DDR_EN_LSB _u(17)
#define SSI_SPI_CTRLR0_INST_DDR_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_SPI_CTRLR0_SPI_DDR_EN
// Description : SPI DDR transfer enable
-#define SSI_SPI_CTRLR0_SPI_DDR_EN_RESET _U(0x0)
-#define SSI_SPI_CTRLR0_SPI_DDR_EN_BITS _U(0x00010000)
-#define SSI_SPI_CTRLR0_SPI_DDR_EN_MSB _U(16)
-#define SSI_SPI_CTRLR0_SPI_DDR_EN_LSB _U(16)
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_RESET _u(0x0)
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_BITS _u(0x00010000)
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_MSB _u(16)
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_LSB _u(16)
#define SSI_SPI_CTRLR0_SPI_DDR_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_SPI_CTRLR0_WAIT_CYCLES
// Description : Wait cycles between control frame transmit and data reception
// (in SCLK cycles)
-#define SSI_SPI_CTRLR0_WAIT_CYCLES_RESET _U(0x00)
-#define SSI_SPI_CTRLR0_WAIT_CYCLES_BITS _U(0x0000f800)
-#define SSI_SPI_CTRLR0_WAIT_CYCLES_MSB _U(15)
-#define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB _U(11)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_RESET _u(0x00)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_BITS _u(0x0000f800)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_MSB _u(15)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB _u(11)
#define SSI_SPI_CTRLR0_WAIT_CYCLES_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_SPI_CTRLR0_INST_L
@@ -758,22 +758,22 @@
// 0x1 -> 4-bit instruction
// 0x2 -> 8-bit instruction
// 0x3 -> 16-bit instruction
-#define SSI_SPI_CTRLR0_INST_L_RESET _U(0x0)
-#define SSI_SPI_CTRLR0_INST_L_BITS _U(0x00000300)
-#define SSI_SPI_CTRLR0_INST_L_MSB _U(9)
-#define SSI_SPI_CTRLR0_INST_L_LSB _U(8)
+#define SSI_SPI_CTRLR0_INST_L_RESET _u(0x0)
+#define SSI_SPI_CTRLR0_INST_L_BITS _u(0x00000300)
+#define SSI_SPI_CTRLR0_INST_L_MSB _u(9)
+#define SSI_SPI_CTRLR0_INST_L_LSB _u(8)
#define SSI_SPI_CTRLR0_INST_L_ACCESS "RW"
-#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE _U(0x0)
-#define SSI_SPI_CTRLR0_INST_L_VALUE_4B _U(0x1)
-#define SSI_SPI_CTRLR0_INST_L_VALUE_8B _U(0x2)
-#define SSI_SPI_CTRLR0_INST_L_VALUE_16B _U(0x3)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE _u(0x0)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_4B _u(0x1)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_8B _u(0x2)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_16B _u(0x3)
// -----------------------------------------------------------------------------
// Field : SSI_SPI_CTRLR0_ADDR_L
// Description : Address length (0b-60b in 4b increments)
-#define SSI_SPI_CTRLR0_ADDR_L_RESET _U(0x0)
-#define SSI_SPI_CTRLR0_ADDR_L_BITS _U(0x0000003c)
-#define SSI_SPI_CTRLR0_ADDR_L_MSB _U(5)
-#define SSI_SPI_CTRLR0_ADDR_L_LSB _U(2)
+#define SSI_SPI_CTRLR0_ADDR_L_RESET _u(0x0)
+#define SSI_SPI_CTRLR0_ADDR_L_BITS _u(0x0000003c)
+#define SSI_SPI_CTRLR0_ADDR_L_MSB _u(5)
+#define SSI_SPI_CTRLR0_ADDR_L_LSB _u(2)
#define SSI_SPI_CTRLR0_ADDR_L_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_SPI_CTRLR0_TRANS_TYPE
@@ -783,27 +783,27 @@
// specified by FRF
// 0x2 -> Command and address both in format specified by FRF
// (e.g. Dual-SPI)
-#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET _U(0x0)
-#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS _U(0x00000003)
-#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB _U(1)
-#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB _U(0)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET _u(0x0)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS _u(0x00000003)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB _u(1)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB _u(0)
#define SSI_SPI_CTRLR0_TRANS_TYPE_ACCESS "RW"
-#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A _U(0x0)
-#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A _U(0x1)
-#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A _U(0x2)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A _u(0x0)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A _u(0x1)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A _u(0x2)
// =============================================================================
// Register : SSI_TXD_DRIVE_EDGE
// Description : TX drive edge
-#define SSI_TXD_DRIVE_EDGE_OFFSET _U(0x000000f8)
-#define SSI_TXD_DRIVE_EDGE_BITS _U(0x000000ff)
-#define SSI_TXD_DRIVE_EDGE_RESET _U(0x00000000)
+#define SSI_TXD_DRIVE_EDGE_OFFSET _u(0x000000f8)
+#define SSI_TXD_DRIVE_EDGE_BITS _u(0x000000ff)
+#define SSI_TXD_DRIVE_EDGE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SSI_TXD_DRIVE_EDGE_TDE
// Description : TXD drive edge
-#define SSI_TXD_DRIVE_EDGE_TDE_RESET _U(0x00)
-#define SSI_TXD_DRIVE_EDGE_TDE_BITS _U(0x000000ff)
-#define SSI_TXD_DRIVE_EDGE_TDE_MSB _U(7)
-#define SSI_TXD_DRIVE_EDGE_TDE_LSB _U(0)
+#define SSI_TXD_DRIVE_EDGE_TDE_RESET _u(0x00)
+#define SSI_TXD_DRIVE_EDGE_TDE_BITS _u(0x000000ff)
+#define SSI_TXD_DRIVE_EDGE_TDE_MSB _u(7)
+#define SSI_TXD_DRIVE_EDGE_TDE_LSB _u(0)
#define SSI_TXD_DRIVE_EDGE_TDE_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_SSI_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/syscfg.h b/src/rp2040/hardware_regs/include/hardware/regs/syscfg.h
index b79d9ba..2bf09e2 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/syscfg.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/syscfg.h
@@ -15,38 +15,38 @@
// Register : SYSCFG_PROC0_NMI_MASK
// Description : Processor core 0 NMI source mask
// Set a bit high to enable NMI from that IRQ
-#define SYSCFG_PROC0_NMI_MASK_OFFSET _U(0x00000000)
-#define SYSCFG_PROC0_NMI_MASK_BITS _U(0xffffffff)
-#define SYSCFG_PROC0_NMI_MASK_RESET _U(0x00000000)
-#define SYSCFG_PROC0_NMI_MASK_MSB _U(31)
-#define SYSCFG_PROC0_NMI_MASK_LSB _U(0)
+#define SYSCFG_PROC0_NMI_MASK_OFFSET _u(0x00000000)
+#define SYSCFG_PROC0_NMI_MASK_BITS _u(0xffffffff)
+#define SYSCFG_PROC0_NMI_MASK_RESET _u(0x00000000)
+#define SYSCFG_PROC0_NMI_MASK_MSB _u(31)
+#define SYSCFG_PROC0_NMI_MASK_LSB _u(0)
#define SYSCFG_PROC0_NMI_MASK_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_PROC1_NMI_MASK
// Description : Processor core 1 NMI source mask
// Set a bit high to enable NMI from that IRQ
-#define SYSCFG_PROC1_NMI_MASK_OFFSET _U(0x00000004)
-#define SYSCFG_PROC1_NMI_MASK_BITS _U(0xffffffff)
-#define SYSCFG_PROC1_NMI_MASK_RESET _U(0x00000000)
-#define SYSCFG_PROC1_NMI_MASK_MSB _U(31)
-#define SYSCFG_PROC1_NMI_MASK_LSB _U(0)
+#define SYSCFG_PROC1_NMI_MASK_OFFSET _u(0x00000004)
+#define SYSCFG_PROC1_NMI_MASK_BITS _u(0xffffffff)
+#define SYSCFG_PROC1_NMI_MASK_RESET _u(0x00000000)
+#define SYSCFG_PROC1_NMI_MASK_MSB _u(31)
+#define SYSCFG_PROC1_NMI_MASK_LSB _u(0)
#define SYSCFG_PROC1_NMI_MASK_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_PROC_CONFIG
// Description : Configuration for processors
-#define SYSCFG_PROC_CONFIG_OFFSET _U(0x00000008)
-#define SYSCFG_PROC_CONFIG_BITS _U(0xff000003)
-#define SYSCFG_PROC_CONFIG_RESET _U(0x10000000)
+#define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000008)
+#define SYSCFG_PROC_CONFIG_BITS _u(0xff000003)
+#define SYSCFG_PROC_CONFIG_RESET _u(0x10000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID
// Description : Configure proc1 DAP instance ID.
// Recommend that this is NOT changed until you require debug
// access in multi-chip environment
// WARNING: do not set to 15 as this is reserved for RescueDP
-#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET _U(0x1)
-#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS _U(0xf0000000)
-#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB _U(31)
-#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB _U(28)
+#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET _u(0x1)
+#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS _u(0xf0000000)
+#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB _u(31)
+#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB _u(28)
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID
@@ -54,26 +54,26 @@
// Recommend that this is NOT changed until you require debug
// access in multi-chip environment
// WARNING: do not set to 15 as this is reserved for RescueDP
-#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET _U(0x0)
-#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS _U(0x0f000000)
-#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB _U(27)
-#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB _U(24)
+#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET _u(0x0)
+#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS _u(0x0f000000)
+#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB _u(27)
+#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB _u(24)
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED
// Description : Indication that proc1 has halted
-#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _U(0x0)
-#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _U(0x00000002)
-#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _U(1)
-#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _U(1)
+#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _u(0x0)
+#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _u(0x00000002)
+#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _u(1)
+#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _u(1)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED
// Description : Indication that proc0 has halted
-#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _U(0x0)
-#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _U(0x00000001)
-#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _U(0)
-#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _U(0)
+#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _u(0x0)
+#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _u(0x00000001)
+#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _u(0)
+#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _u(0)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO"
// =============================================================================
// Register : SYSCFG_PROC_IN_SYNC_BYPASS
@@ -86,11 +86,11 @@
// If you're feeling brave, you can bypass to save two cycles of
// input
// latency. This register applies to GPIO 0...29.
-#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _U(0x0000000c)
-#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _U(0x3fffffff)
-#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _U(0x00000000)
-#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB _U(29)
-#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB _U(0)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x0000000c)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _u(0x3fffffff)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _u(0x00000000)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB _u(29)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB _u(0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI
@@ -103,155 +103,155 @@
// If you're feeling brave, you can bypass to save two cycles of
// input
// latency. This register applies to GPIO 30...35 (the QSPI IOs).
-#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _U(0x00000010)
-#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _U(0x0000003f)
-#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _U(0x00000000)
-#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB _U(5)
-#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB _U(0)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000010)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _u(0x0000003f)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _u(0x00000000)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB _u(5)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB _u(0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_DBGFORCE
// Description : Directly control the SWD debug port of either processor
-#define SYSCFG_DBGFORCE_OFFSET _U(0x00000014)
-#define SYSCFG_DBGFORCE_BITS _U(0x000000ff)
-#define SYSCFG_DBGFORCE_RESET _U(0x00000066)
+#define SYSCFG_DBGFORCE_OFFSET _u(0x00000014)
+#define SYSCFG_DBGFORCE_BITS _u(0x000000ff)
+#define SYSCFG_DBGFORCE_RESET _u(0x00000066)
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC1_ATTACH
// Description : Attach processor 1 debug port to syscfg controls, and
// disconnect it from external SWD pads.
-#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET _U(0x0)
-#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS _U(0x00000080)
-#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB _U(7)
-#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB _U(7)
+#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET _u(0x0)
+#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS _u(0x00000080)
+#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB _u(7)
+#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB _u(7)
#define SYSCFG_DBGFORCE_PROC1_ATTACH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC1_SWCLK
// Description : Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
-#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET _U(0x1)
-#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS _U(0x00000040)
-#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB _U(6)
-#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB _U(6)
+#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET _u(0x1)
+#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS _u(0x00000040)
+#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB _u(6)
+#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB _u(6)
#define SYSCFG_DBGFORCE_PROC1_SWCLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC1_SWDI
// Description : Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
-#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET _U(0x1)
-#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS _U(0x00000020)
-#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB _U(5)
-#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB _U(5)
+#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET _u(0x1)
+#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS _u(0x00000020)
+#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB _u(5)
+#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB _u(5)
#define SYSCFG_DBGFORCE_PROC1_SWDI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC1_SWDO
// Description : Observe the value of processor 1 SWDIO output.
#define SYSCFG_DBGFORCE_PROC1_SWDO_RESET "-"
-#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS _U(0x00000010)
-#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB _U(4)
-#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB _U(4)
+#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS _u(0x00000010)
+#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB _u(4)
+#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB _u(4)
#define SYSCFG_DBGFORCE_PROC1_SWDO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC0_ATTACH
// Description : Attach processor 0 debug port to syscfg controls, and
// disconnect it from external SWD pads.
-#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET _U(0x0)
-#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS _U(0x00000008)
-#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB _U(3)
-#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB _U(3)
+#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET _u(0x0)
+#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS _u(0x00000008)
+#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB _u(3)
+#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB _u(3)
#define SYSCFG_DBGFORCE_PROC0_ATTACH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC0_SWCLK
// Description : Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
-#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET _U(0x1)
-#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS _U(0x00000004)
-#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB _U(2)
-#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB _U(2)
+#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET _u(0x1)
+#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS _u(0x00000004)
+#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB _u(2)
+#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB _u(2)
#define SYSCFG_DBGFORCE_PROC0_SWCLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC0_SWDI
// Description : Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
-#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET _U(0x1)
-#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS _U(0x00000002)
-#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB _U(1)
-#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB _U(1)
+#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET _u(0x1)
+#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS _u(0x00000002)
+#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB _u(1)
+#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB _u(1)
#define SYSCFG_DBGFORCE_PROC0_SWDI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC0_SWDO
// Description : Observe the value of processor 0 SWDIO output.
#define SYSCFG_DBGFORCE_PROC0_SWDO_RESET "-"
-#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS _U(0x00000001)
-#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB _U(0)
-#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB _U(0)
+#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS _u(0x00000001)
+#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB _u(0)
+#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB _u(0)
#define SYSCFG_DBGFORCE_PROC0_SWDO_ACCESS "RO"
// =============================================================================
// Register : SYSCFG_MEMPOWERDOWN
// Description : Control power downs to memories. Set high to power down
// memories.
// Use with extreme caution
-#define SYSCFG_MEMPOWERDOWN_OFFSET _U(0x00000018)
-#define SYSCFG_MEMPOWERDOWN_BITS _U(0x000000ff)
-#define SYSCFG_MEMPOWERDOWN_RESET _U(0x00000000)
+#define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000018)
+#define SYSCFG_MEMPOWERDOWN_BITS _u(0x000000ff)
+#define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_ROM
// Description : None
-#define SYSCFG_MEMPOWERDOWN_ROM_RESET _U(0x0)
-#define SYSCFG_MEMPOWERDOWN_ROM_BITS _U(0x00000080)
-#define SYSCFG_MEMPOWERDOWN_ROM_MSB _U(7)
-#define SYSCFG_MEMPOWERDOWN_ROM_LSB _U(7)
+#define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000080)
+#define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(7)
+#define SYSCFG_MEMPOWERDOWN_ROM_LSB _u(7)
#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_USB
// Description : None
-#define SYSCFG_MEMPOWERDOWN_USB_RESET _U(0x0)
-#define SYSCFG_MEMPOWERDOWN_USB_BITS _U(0x00000040)
-#define SYSCFG_MEMPOWERDOWN_USB_MSB _U(6)
-#define SYSCFG_MEMPOWERDOWN_USB_LSB _U(6)
+#define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000040)
+#define SYSCFG_MEMPOWERDOWN_USB_MSB _u(6)
+#define SYSCFG_MEMPOWERDOWN_USB_LSB _u(6)
#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM5
// Description : None
-#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _U(0x0)
-#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _U(0x00000020)
-#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _U(5)
-#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _U(5)
+#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020)
+#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5)
+#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _u(5)
#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM4
// Description : None
-#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _U(0x0)
-#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _U(0x00000010)
-#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _U(4)
-#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _U(4)
+#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010)
+#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4)
+#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _u(4)
#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM3
// Description : None
-#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _U(0x0)
-#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _U(0x00000008)
-#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _U(3)
-#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _U(3)
+#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008)
+#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3)
+#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _u(3)
#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM2
// Description : None
-#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _U(0x0)
-#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _U(0x00000004)
-#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _U(2)
-#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _U(2)
+#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004)
+#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2)
+#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _u(2)
#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM1
// Description : None
-#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _U(0x0)
-#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _U(0x00000002)
-#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _U(1)
-#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _U(1)
+#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002)
+#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1)
+#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _u(1)
#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM0
// Description : None
-#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _U(0x0)
-#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _U(0x00000001)
-#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _U(0)
-#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _U(0)
+#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001)
+#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0)
+#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_SYSCFG_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/sysinfo.h b/src/rp2040/hardware_regs/include/hardware/regs/sysinfo.h
index 38a126d..2a46658 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/sysinfo.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/sysinfo.h
@@ -14,64 +14,64 @@
// =============================================================================
// Register : SYSINFO_CHIP_ID
// Description : JEDEC JEP-106 compliant chip identifier.
-#define SYSINFO_CHIP_ID_OFFSET _U(0x00000000)
-#define SYSINFO_CHIP_ID_BITS _U(0xffffffff)
-#define SYSINFO_CHIP_ID_RESET _U(0x00000000)
+#define SYSINFO_CHIP_ID_OFFSET _u(0x00000000)
+#define SYSINFO_CHIP_ID_BITS _u(0xffffffff)
+#define SYSINFO_CHIP_ID_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_REVISION
// Description : None
#define SYSINFO_CHIP_ID_REVISION_RESET "-"
-#define SYSINFO_CHIP_ID_REVISION_BITS _U(0xf0000000)
-#define SYSINFO_CHIP_ID_REVISION_MSB _U(31)
-#define SYSINFO_CHIP_ID_REVISION_LSB _U(28)
+#define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000)
+#define SYSINFO_CHIP_ID_REVISION_MSB _u(31)
+#define SYSINFO_CHIP_ID_REVISION_LSB _u(28)
#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_PART
// Description : None
#define SYSINFO_CHIP_ID_PART_RESET "-"
-#define SYSINFO_CHIP_ID_PART_BITS _U(0x0ffff000)
-#define SYSINFO_CHIP_ID_PART_MSB _U(27)
-#define SYSINFO_CHIP_ID_PART_LSB _U(12)
+#define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000)
+#define SYSINFO_CHIP_ID_PART_MSB _u(27)
+#define SYSINFO_CHIP_ID_PART_LSB _u(12)
#define SYSINFO_CHIP_ID_PART_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_MANUFACTURER
// Description : None
#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-"
-#define SYSINFO_CHIP_ID_MANUFACTURER_BITS _U(0x00000fff)
-#define SYSINFO_CHIP_ID_MANUFACTURER_MSB _U(11)
-#define SYSINFO_CHIP_ID_MANUFACTURER_LSB _U(0)
+#define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000fff)
+#define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11)
+#define SYSINFO_CHIP_ID_MANUFACTURER_LSB _u(0)
#define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_PLATFORM
// Description : Platform register. Allows software to know what environment it
// is running in.
-#define SYSINFO_PLATFORM_OFFSET _U(0x00000004)
-#define SYSINFO_PLATFORM_BITS _U(0x00000003)
-#define SYSINFO_PLATFORM_RESET _U(0x00000000)
+#define SYSINFO_PLATFORM_OFFSET _u(0x00000004)
+#define SYSINFO_PLATFORM_BITS _u(0x00000003)
+#define SYSINFO_PLATFORM_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_ASIC
// Description : None
-#define SYSINFO_PLATFORM_ASIC_RESET _U(0x0)
-#define SYSINFO_PLATFORM_ASIC_BITS _U(0x00000002)
-#define SYSINFO_PLATFORM_ASIC_MSB _U(1)
-#define SYSINFO_PLATFORM_ASIC_LSB _U(1)
+#define SYSINFO_PLATFORM_ASIC_RESET _u(0x0)
+#define SYSINFO_PLATFORM_ASIC_BITS _u(0x00000002)
+#define SYSINFO_PLATFORM_ASIC_MSB _u(1)
+#define SYSINFO_PLATFORM_ASIC_LSB _u(1)
#define SYSINFO_PLATFORM_ASIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_FPGA
// Description : None
-#define SYSINFO_PLATFORM_FPGA_RESET _U(0x0)
-#define SYSINFO_PLATFORM_FPGA_BITS _U(0x00000001)
-#define SYSINFO_PLATFORM_FPGA_MSB _U(0)
-#define SYSINFO_PLATFORM_FPGA_LSB _U(0)
+#define SYSINFO_PLATFORM_FPGA_RESET _u(0x0)
+#define SYSINFO_PLATFORM_FPGA_BITS _u(0x00000001)
+#define SYSINFO_PLATFORM_FPGA_MSB _u(0)
+#define SYSINFO_PLATFORM_FPGA_LSB _u(0)
#define SYSINFO_PLATFORM_FPGA_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_GITREF_RP2040
// Description : Git hash of the chip source. Used to identify chip version.
-#define SYSINFO_GITREF_RP2040_OFFSET _U(0x00000040)
-#define SYSINFO_GITREF_RP2040_BITS _U(0xffffffff)
+#define SYSINFO_GITREF_RP2040_OFFSET _u(0x00000040)
+#define SYSINFO_GITREF_RP2040_BITS _u(0xffffffff)
#define SYSINFO_GITREF_RP2040_RESET "-"
-#define SYSINFO_GITREF_RP2040_MSB _U(31)
-#define SYSINFO_GITREF_RP2040_LSB _U(0)
+#define SYSINFO_GITREF_RP2040_MSB _u(31)
+#define SYSINFO_GITREF_RP2040_LSB _u(0)
#define SYSINFO_GITREF_RP2040_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_SYSINFO_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/tbman.h b/src/rp2040/hardware_regs/include/hardware/regs/tbman.h
index 7a39294..4f8f641 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/tbman.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/tbman.h
@@ -15,24 +15,24 @@
// =============================================================================
// Register : TBMAN_PLATFORM
// Description : Indicates the type of platform in use
-#define TBMAN_PLATFORM_OFFSET _U(0x00000000)
-#define TBMAN_PLATFORM_BITS _U(0x00000003)
-#define TBMAN_PLATFORM_RESET _U(0x00000005)
+#define TBMAN_PLATFORM_OFFSET _u(0x00000000)
+#define TBMAN_PLATFORM_BITS _u(0x00000003)
+#define TBMAN_PLATFORM_RESET _u(0x00000005)
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_FPGA
// Description : Indicates the platform is an FPGA
-#define TBMAN_PLATFORM_FPGA_RESET _U(0x0)
-#define TBMAN_PLATFORM_FPGA_BITS _U(0x00000002)
-#define TBMAN_PLATFORM_FPGA_MSB _U(1)
-#define TBMAN_PLATFORM_FPGA_LSB _U(1)
+#define TBMAN_PLATFORM_FPGA_RESET _u(0x0)
+#define TBMAN_PLATFORM_FPGA_BITS _u(0x00000002)
+#define TBMAN_PLATFORM_FPGA_MSB _u(1)
+#define TBMAN_PLATFORM_FPGA_LSB _u(1)
#define TBMAN_PLATFORM_FPGA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_ASIC
// Description : Indicates the platform is an ASIC
-#define TBMAN_PLATFORM_ASIC_RESET _U(0x1)
-#define TBMAN_PLATFORM_ASIC_BITS _U(0x00000001)
-#define TBMAN_PLATFORM_ASIC_MSB _U(0)
-#define TBMAN_PLATFORM_ASIC_LSB _U(0)
+#define TBMAN_PLATFORM_ASIC_RESET _u(0x1)
+#define TBMAN_PLATFORM_ASIC_BITS _u(0x00000001)
+#define TBMAN_PLATFORM_ASIC_MSB _u(0)
+#define TBMAN_PLATFORM_ASIC_LSB _u(0)
#define TBMAN_PLATFORM_ASIC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_TBMAN_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/timer.h b/src/rp2040/hardware_regs/include/hardware/regs/timer.h
index 6480cf6..c3ef0c5 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/timer.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/timer.h
@@ -31,40 +31,40 @@
// Register : TIMER_TIMEHW
// Description : Write to bits 63:32 of time
// always write timelw before timehw
-#define TIMER_TIMEHW_OFFSET _U(0x00000000)
-#define TIMER_TIMEHW_BITS _U(0xffffffff)
-#define TIMER_TIMEHW_RESET _U(0x00000000)
-#define TIMER_TIMEHW_MSB _U(31)
-#define TIMER_TIMEHW_LSB _U(0)
+#define TIMER_TIMEHW_OFFSET _u(0x00000000)
+#define TIMER_TIMEHW_BITS _u(0xffffffff)
+#define TIMER_TIMEHW_RESET _u(0x00000000)
+#define TIMER_TIMEHW_MSB _u(31)
+#define TIMER_TIMEHW_LSB _u(0)
#define TIMER_TIMEHW_ACCESS "WF"
// =============================================================================
// Register : TIMER_TIMELW
// Description : Write to bits 31:0 of time
// writes do not get copied to time until timehw is written
-#define TIMER_TIMELW_OFFSET _U(0x00000004)
-#define TIMER_TIMELW_BITS _U(0xffffffff)
-#define TIMER_TIMELW_RESET _U(0x00000000)
-#define TIMER_TIMELW_MSB _U(31)
-#define TIMER_TIMELW_LSB _U(0)
+#define TIMER_TIMELW_OFFSET _u(0x00000004)
+#define TIMER_TIMELW_BITS _u(0xffffffff)
+#define TIMER_TIMELW_RESET _u(0x00000000)
+#define TIMER_TIMELW_MSB _u(31)
+#define TIMER_TIMELW_LSB _u(0)
#define TIMER_TIMELW_ACCESS "WF"
// =============================================================================
// Register : TIMER_TIMEHR
// Description : Read from bits 63:32 of time
// always read timelr before timehr
-#define TIMER_TIMEHR_OFFSET _U(0x00000008)
-#define TIMER_TIMEHR_BITS _U(0xffffffff)
-#define TIMER_TIMEHR_RESET _U(0x00000000)
-#define TIMER_TIMEHR_MSB _U(31)
-#define TIMER_TIMEHR_LSB _U(0)
+#define TIMER_TIMEHR_OFFSET _u(0x00000008)
+#define TIMER_TIMEHR_BITS _u(0xffffffff)
+#define TIMER_TIMEHR_RESET _u(0x00000000)
+#define TIMER_TIMEHR_MSB _u(31)
+#define TIMER_TIMEHR_LSB _u(0)
#define TIMER_TIMEHR_ACCESS "RO"
// =============================================================================
// Register : TIMER_TIMELR
// Description : Read from bits 31:0 of time
-#define TIMER_TIMELR_OFFSET _U(0x0000000c)
-#define TIMER_TIMELR_BITS _U(0xffffffff)
-#define TIMER_TIMELR_RESET _U(0x00000000)
-#define TIMER_TIMELR_MSB _U(31)
-#define TIMER_TIMELR_LSB _U(0)
+#define TIMER_TIMELR_OFFSET _u(0x0000000c)
+#define TIMER_TIMELR_BITS _u(0xffffffff)
+#define TIMER_TIMELR_RESET _u(0x00000000)
+#define TIMER_TIMELR_MSB _u(31)
+#define TIMER_TIMELR_LSB _u(0)
#define TIMER_TIMELR_ACCESS "RO"
// =============================================================================
// Register : TIMER_ALARM0
@@ -72,11 +72,11 @@
// Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.
// The alarm will disarm itself once it fires, and can
// be disarmed early using the ARMED status register.
-#define TIMER_ALARM0_OFFSET _U(0x00000010)
-#define TIMER_ALARM0_BITS _U(0xffffffff)
-#define TIMER_ALARM0_RESET _U(0x00000000)
-#define TIMER_ALARM0_MSB _U(31)
-#define TIMER_ALARM0_LSB _U(0)
+#define TIMER_ALARM0_OFFSET _u(0x00000010)
+#define TIMER_ALARM0_BITS _u(0xffffffff)
+#define TIMER_ALARM0_RESET _u(0x00000000)
+#define TIMER_ALARM0_MSB _u(31)
+#define TIMER_ALARM0_LSB _u(0)
#define TIMER_ALARM0_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM1
@@ -84,11 +84,11 @@
// Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.
// The alarm will disarm itself once it fires, and can
// be disarmed early using the ARMED status register.
-#define TIMER_ALARM1_OFFSET _U(0x00000014)
-#define TIMER_ALARM1_BITS _U(0xffffffff)
-#define TIMER_ALARM1_RESET _U(0x00000000)
-#define TIMER_ALARM1_MSB _U(31)
-#define TIMER_ALARM1_LSB _U(0)
+#define TIMER_ALARM1_OFFSET _u(0x00000014)
+#define TIMER_ALARM1_BITS _u(0xffffffff)
+#define TIMER_ALARM1_RESET _u(0x00000000)
+#define TIMER_ALARM1_MSB _u(31)
+#define TIMER_ALARM1_LSB _u(0)
#define TIMER_ALARM1_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM2
@@ -96,11 +96,11 @@
// Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.
// The alarm will disarm itself once it fires, and can
// be disarmed early using the ARMED status register.
-#define TIMER_ALARM2_OFFSET _U(0x00000018)
-#define TIMER_ALARM2_BITS _U(0xffffffff)
-#define TIMER_ALARM2_RESET _U(0x00000000)
-#define TIMER_ALARM2_MSB _U(31)
-#define TIMER_ALARM2_LSB _U(0)
+#define TIMER_ALARM2_OFFSET _u(0x00000018)
+#define TIMER_ALARM2_BITS _u(0xffffffff)
+#define TIMER_ALARM2_RESET _u(0x00000000)
+#define TIMER_ALARM2_MSB _u(31)
+#define TIMER_ALARM2_LSB _u(0)
#define TIMER_ALARM2_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM3
@@ -108,11 +108,11 @@
// Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.
// The alarm will disarm itself once it fires, and can
// be disarmed early using the ARMED status register.
-#define TIMER_ALARM3_OFFSET _U(0x0000001c)
-#define TIMER_ALARM3_BITS _U(0xffffffff)
-#define TIMER_ALARM3_RESET _U(0x00000000)
-#define TIMER_ALARM3_MSB _U(31)
-#define TIMER_ALARM3_LSB _U(0)
+#define TIMER_ALARM3_OFFSET _u(0x0000001c)
+#define TIMER_ALARM3_BITS _u(0xffffffff)
+#define TIMER_ALARM3_RESET _u(0x00000000)
+#define TIMER_ALARM3_MSB _u(31)
+#define TIMER_ALARM3_LSB _u(0)
#define TIMER_ALARM3_ACCESS "RW"
// =============================================================================
// Register : TIMER_ARMED
@@ -120,213 +120,213 @@
// A write to the corresponding ALARMx register arms the alarm.
// Alarms automatically disarm upon firing, but writing ones here
// will disarm immediately without waiting to fire.
-#define TIMER_ARMED_OFFSET _U(0x00000020)
-#define TIMER_ARMED_BITS _U(0x0000000f)
-#define TIMER_ARMED_RESET _U(0x00000000)
-#define TIMER_ARMED_MSB _U(3)
-#define TIMER_ARMED_LSB _U(0)
+#define TIMER_ARMED_OFFSET _u(0x00000020)
+#define TIMER_ARMED_BITS _u(0x0000000f)
+#define TIMER_ARMED_RESET _u(0x00000000)
+#define TIMER_ARMED_MSB _u(3)
+#define TIMER_ARMED_LSB _u(0)
#define TIMER_ARMED_ACCESS "WC"
// =============================================================================
// Register : TIMER_TIMERAWH
// Description : Raw read from bits 63:32 of time (no side effects)
-#define TIMER_TIMERAWH_OFFSET _U(0x00000024)
-#define TIMER_TIMERAWH_BITS _U(0xffffffff)
-#define TIMER_TIMERAWH_RESET _U(0x00000000)
-#define TIMER_TIMERAWH_MSB _U(31)
-#define TIMER_TIMERAWH_LSB _U(0)
+#define TIMER_TIMERAWH_OFFSET _u(0x00000024)
+#define TIMER_TIMERAWH_BITS _u(0xffffffff)
+#define TIMER_TIMERAWH_RESET _u(0x00000000)
+#define TIMER_TIMERAWH_MSB _u(31)
+#define TIMER_TIMERAWH_LSB _u(0)
#define TIMER_TIMERAWH_ACCESS "RO"
// =============================================================================
// Register : TIMER_TIMERAWL
// Description : Raw read from bits 31:0 of time (no side effects)
-#define TIMER_TIMERAWL_OFFSET _U(0x00000028)
-#define TIMER_TIMERAWL_BITS _U(0xffffffff)
-#define TIMER_TIMERAWL_RESET _U(0x00000000)
-#define TIMER_TIMERAWL_MSB _U(31)
-#define TIMER_TIMERAWL_LSB _U(0)
+#define TIMER_TIMERAWL_OFFSET _u(0x00000028)
+#define TIMER_TIMERAWL_BITS _u(0xffffffff)
+#define TIMER_TIMERAWL_RESET _u(0x00000000)
+#define TIMER_TIMERAWL_MSB _u(31)
+#define TIMER_TIMERAWL_LSB _u(0)
#define TIMER_TIMERAWL_ACCESS "RO"
// =============================================================================
// Register : TIMER_DBGPAUSE
// Description : Set bits high to enable pause when the corresponding debug
// ports are active
-#define TIMER_DBGPAUSE_OFFSET _U(0x0000002c)
-#define TIMER_DBGPAUSE_BITS _U(0x00000006)
-#define TIMER_DBGPAUSE_RESET _U(0x00000007)
+#define TIMER_DBGPAUSE_OFFSET _u(0x0000002c)
+#define TIMER_DBGPAUSE_BITS _u(0x00000006)
+#define TIMER_DBGPAUSE_RESET _u(0x00000007)
// -----------------------------------------------------------------------------
// Field : TIMER_DBGPAUSE_DBG1
// Description : Pause when processor 1 is in debug mode
-#define TIMER_DBGPAUSE_DBG1_RESET _U(0x1)
-#define TIMER_DBGPAUSE_DBG1_BITS _U(0x00000004)
-#define TIMER_DBGPAUSE_DBG1_MSB _U(2)
-#define TIMER_DBGPAUSE_DBG1_LSB _U(2)
+#define TIMER_DBGPAUSE_DBG1_RESET _u(0x1)
+#define TIMER_DBGPAUSE_DBG1_BITS _u(0x00000004)
+#define TIMER_DBGPAUSE_DBG1_MSB _u(2)
+#define TIMER_DBGPAUSE_DBG1_LSB _u(2)
#define TIMER_DBGPAUSE_DBG1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_DBGPAUSE_DBG0
// Description : Pause when processor 0 is in debug mode
-#define TIMER_DBGPAUSE_DBG0_RESET _U(0x1)
-#define TIMER_DBGPAUSE_DBG0_BITS _U(0x00000002)
-#define TIMER_DBGPAUSE_DBG0_MSB _U(1)
-#define TIMER_DBGPAUSE_DBG0_LSB _U(1)
+#define TIMER_DBGPAUSE_DBG0_RESET _u(0x1)
+#define TIMER_DBGPAUSE_DBG0_BITS _u(0x00000002)
+#define TIMER_DBGPAUSE_DBG0_MSB _u(1)
+#define TIMER_DBGPAUSE_DBG0_LSB _u(1)
#define TIMER_DBGPAUSE_DBG0_ACCESS "RW"
// =============================================================================
// Register : TIMER_PAUSE
// Description : Set high to pause the timer
-#define TIMER_PAUSE_OFFSET _U(0x00000030)
-#define TIMER_PAUSE_BITS _U(0x00000001)
-#define TIMER_PAUSE_RESET _U(0x00000000)
-#define TIMER_PAUSE_MSB _U(0)
-#define TIMER_PAUSE_LSB _U(0)
+#define TIMER_PAUSE_OFFSET _u(0x00000030)
+#define TIMER_PAUSE_BITS _u(0x00000001)
+#define TIMER_PAUSE_RESET _u(0x00000000)
+#define TIMER_PAUSE_MSB _u(0)
+#define TIMER_PAUSE_LSB _u(0)
#define TIMER_PAUSE_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTR
// Description : Raw Interrupts
-#define TIMER_INTR_OFFSET _U(0x00000034)
-#define TIMER_INTR_BITS _U(0x0000000f)
-#define TIMER_INTR_RESET _U(0x00000000)
+#define TIMER_INTR_OFFSET _u(0x00000034)
+#define TIMER_INTR_BITS _u(0x0000000f)
+#define TIMER_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_3
// Description : None
-#define TIMER_INTR_ALARM_3_RESET _U(0x0)
-#define TIMER_INTR_ALARM_3_BITS _U(0x00000008)
-#define TIMER_INTR_ALARM_3_MSB _U(3)
-#define TIMER_INTR_ALARM_3_LSB _U(3)
+#define TIMER_INTR_ALARM_3_RESET _u(0x0)
+#define TIMER_INTR_ALARM_3_BITS _u(0x00000008)
+#define TIMER_INTR_ALARM_3_MSB _u(3)
+#define TIMER_INTR_ALARM_3_LSB _u(3)
#define TIMER_INTR_ALARM_3_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_2
// Description : None
-#define TIMER_INTR_ALARM_2_RESET _U(0x0)
-#define TIMER_INTR_ALARM_2_BITS _U(0x00000004)
-#define TIMER_INTR_ALARM_2_MSB _U(2)
-#define TIMER_INTR_ALARM_2_LSB _U(2)
+#define TIMER_INTR_ALARM_2_RESET _u(0x0)
+#define TIMER_INTR_ALARM_2_BITS _u(0x00000004)
+#define TIMER_INTR_ALARM_2_MSB _u(2)
+#define TIMER_INTR_ALARM_2_LSB _u(2)
#define TIMER_INTR_ALARM_2_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_1
// Description : None
-#define TIMER_INTR_ALARM_1_RESET _U(0x0)
-#define TIMER_INTR_ALARM_1_BITS _U(0x00000002)
-#define TIMER_INTR_ALARM_1_MSB _U(1)
-#define TIMER_INTR_ALARM_1_LSB _U(1)
+#define TIMER_INTR_ALARM_1_RESET _u(0x0)
+#define TIMER_INTR_ALARM_1_BITS _u(0x00000002)
+#define TIMER_INTR_ALARM_1_MSB _u(1)
+#define TIMER_INTR_ALARM_1_LSB _u(1)
#define TIMER_INTR_ALARM_1_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_0
// Description : None
-#define TIMER_INTR_ALARM_0_RESET _U(0x0)
-#define TIMER_INTR_ALARM_0_BITS _U(0x00000001)
-#define TIMER_INTR_ALARM_0_MSB _U(0)
-#define TIMER_INTR_ALARM_0_LSB _U(0)
+#define TIMER_INTR_ALARM_0_RESET _u(0x0)
+#define TIMER_INTR_ALARM_0_BITS _u(0x00000001)
+#define TIMER_INTR_ALARM_0_MSB _u(0)
+#define TIMER_INTR_ALARM_0_LSB _u(0)
#define TIMER_INTR_ALARM_0_ACCESS "WC"
// =============================================================================
// Register : TIMER_INTE
// Description : Interrupt Enable
-#define TIMER_INTE_OFFSET _U(0x00000038)
-#define TIMER_INTE_BITS _U(0x0000000f)
-#define TIMER_INTE_RESET _U(0x00000000)
+#define TIMER_INTE_OFFSET _u(0x00000038)
+#define TIMER_INTE_BITS _u(0x0000000f)
+#define TIMER_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_3
// Description : None
-#define TIMER_INTE_ALARM_3_RESET _U(0x0)
-#define TIMER_INTE_ALARM_3_BITS _U(0x00000008)
-#define TIMER_INTE_ALARM_3_MSB _U(3)
-#define TIMER_INTE_ALARM_3_LSB _U(3)
+#define TIMER_INTE_ALARM_3_RESET _u(0x0)
+#define TIMER_INTE_ALARM_3_BITS _u(0x00000008)
+#define TIMER_INTE_ALARM_3_MSB _u(3)
+#define TIMER_INTE_ALARM_3_LSB _u(3)
#define TIMER_INTE_ALARM_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_2
// Description : None
-#define TIMER_INTE_ALARM_2_RESET _U(0x0)
-#define TIMER_INTE_ALARM_2_BITS _U(0x00000004)
-#define TIMER_INTE_ALARM_2_MSB _U(2)
-#define TIMER_INTE_ALARM_2_LSB _U(2)
+#define TIMER_INTE_ALARM_2_RESET _u(0x0)
+#define TIMER_INTE_ALARM_2_BITS _u(0x00000004)
+#define TIMER_INTE_ALARM_2_MSB _u(2)
+#define TIMER_INTE_ALARM_2_LSB _u(2)
#define TIMER_INTE_ALARM_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_1
// Description : None
-#define TIMER_INTE_ALARM_1_RESET _U(0x0)
-#define TIMER_INTE_ALARM_1_BITS _U(0x00000002)
-#define TIMER_INTE_ALARM_1_MSB _U(1)
-#define TIMER_INTE_ALARM_1_LSB _U(1)
+#define TIMER_INTE_ALARM_1_RESET _u(0x0)
+#define TIMER_INTE_ALARM_1_BITS _u(0x00000002)
+#define TIMER_INTE_ALARM_1_MSB _u(1)
+#define TIMER_INTE_ALARM_1_LSB _u(1)
#define TIMER_INTE_ALARM_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_0
// Description : None
-#define TIMER_INTE_ALARM_0_RESET _U(0x0)
-#define TIMER_INTE_ALARM_0_BITS _U(0x00000001)
-#define TIMER_INTE_ALARM_0_MSB _U(0)
-#define TIMER_INTE_ALARM_0_LSB _U(0)
+#define TIMER_INTE_ALARM_0_RESET _u(0x0)
+#define TIMER_INTE_ALARM_0_BITS _u(0x00000001)
+#define TIMER_INTE_ALARM_0_MSB _u(0)
+#define TIMER_INTE_ALARM_0_LSB _u(0)
#define TIMER_INTE_ALARM_0_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTF
// Description : Interrupt Force
-#define TIMER_INTF_OFFSET _U(0x0000003c)
-#define TIMER_INTF_BITS _U(0x0000000f)
-#define TIMER_INTF_RESET _U(0x00000000)
+#define TIMER_INTF_OFFSET _u(0x0000003c)
+#define TIMER_INTF_BITS _u(0x0000000f)
+#define TIMER_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_3
// Description : None
-#define TIMER_INTF_ALARM_3_RESET _U(0x0)
-#define TIMER_INTF_ALARM_3_BITS _U(0x00000008)
-#define TIMER_INTF_ALARM_3_MSB _U(3)
-#define TIMER_INTF_ALARM_3_LSB _U(3)
+#define TIMER_INTF_ALARM_3_RESET _u(0x0)
+#define TIMER_INTF_ALARM_3_BITS _u(0x00000008)
+#define TIMER_INTF_ALARM_3_MSB _u(3)
+#define TIMER_INTF_ALARM_3_LSB _u(3)
#define TIMER_INTF_ALARM_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_2
// Description : None
-#define TIMER_INTF_ALARM_2_RESET _U(0x0)
-#define TIMER_INTF_ALARM_2_BITS _U(0x00000004)
-#define TIMER_INTF_ALARM_2_MSB _U(2)
-#define TIMER_INTF_ALARM_2_LSB _U(2)
+#define TIMER_INTF_ALARM_2_RESET _u(0x0)
+#define TIMER_INTF_ALARM_2_BITS _u(0x00000004)
+#define TIMER_INTF_ALARM_2_MSB _u(2)
+#define TIMER_INTF_ALARM_2_LSB _u(2)
#define TIMER_INTF_ALARM_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_1
// Description : None
-#define TIMER_INTF_ALARM_1_RESET _U(0x0)
-#define TIMER_INTF_ALARM_1_BITS _U(0x00000002)
-#define TIMER_INTF_ALARM_1_MSB _U(1)
-#define TIMER_INTF_ALARM_1_LSB _U(1)
+#define TIMER_INTF_ALARM_1_RESET _u(0x0)
+#define TIMER_INTF_ALARM_1_BITS _u(0x00000002)
+#define TIMER_INTF_ALARM_1_MSB _u(1)
+#define TIMER_INTF_ALARM_1_LSB _u(1)
#define TIMER_INTF_ALARM_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_0
// Description : None
-#define TIMER_INTF_ALARM_0_RESET _U(0x0)
-#define TIMER_INTF_ALARM_0_BITS _U(0x00000001)
-#define TIMER_INTF_ALARM_0_MSB _U(0)
-#define TIMER_INTF_ALARM_0_LSB _U(0)
+#define TIMER_INTF_ALARM_0_RESET _u(0x0)
+#define TIMER_INTF_ALARM_0_BITS _u(0x00000001)
+#define TIMER_INTF_ALARM_0_MSB _u(0)
+#define TIMER_INTF_ALARM_0_LSB _u(0)
#define TIMER_INTF_ALARM_0_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTS
// Description : Interrupt status after masking & forcing
-#define TIMER_INTS_OFFSET _U(0x00000040)
-#define TIMER_INTS_BITS _U(0x0000000f)
-#define TIMER_INTS_RESET _U(0x00000000)
+#define TIMER_INTS_OFFSET _u(0x00000040)
+#define TIMER_INTS_BITS _u(0x0000000f)
+#define TIMER_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_3
// Description : None
-#define TIMER_INTS_ALARM_3_RESET _U(0x0)
-#define TIMER_INTS_ALARM_3_BITS _U(0x00000008)
-#define TIMER_INTS_ALARM_3_MSB _U(3)
-#define TIMER_INTS_ALARM_3_LSB _U(3)
+#define TIMER_INTS_ALARM_3_RESET _u(0x0)
+#define TIMER_INTS_ALARM_3_BITS _u(0x00000008)
+#define TIMER_INTS_ALARM_3_MSB _u(3)
+#define TIMER_INTS_ALARM_3_LSB _u(3)
#define TIMER_INTS_ALARM_3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_2
// Description : None
-#define TIMER_INTS_ALARM_2_RESET _U(0x0)
-#define TIMER_INTS_ALARM_2_BITS _U(0x00000004)
-#define TIMER_INTS_ALARM_2_MSB _U(2)
-#define TIMER_INTS_ALARM_2_LSB _U(2)
+#define TIMER_INTS_ALARM_2_RESET _u(0x0)
+#define TIMER_INTS_ALARM_2_BITS _u(0x00000004)
+#define TIMER_INTS_ALARM_2_MSB _u(2)
+#define TIMER_INTS_ALARM_2_LSB _u(2)
#define TIMER_INTS_ALARM_2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_1
// Description : None
-#define TIMER_INTS_ALARM_1_RESET _U(0x0)
-#define TIMER_INTS_ALARM_1_BITS _U(0x00000002)
-#define TIMER_INTS_ALARM_1_MSB _U(1)
-#define TIMER_INTS_ALARM_1_LSB _U(1)
+#define TIMER_INTS_ALARM_1_RESET _u(0x0)
+#define TIMER_INTS_ALARM_1_BITS _u(0x00000002)
+#define TIMER_INTS_ALARM_1_MSB _u(1)
+#define TIMER_INTS_ALARM_1_LSB _u(1)
#define TIMER_INTS_ALARM_1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_0
// Description : None
-#define TIMER_INTS_ALARM_0_RESET _U(0x0)
-#define TIMER_INTS_ALARM_0_BITS _U(0x00000001)
-#define TIMER_INTS_ALARM_0_MSB _U(0)
-#define TIMER_INTS_ALARM_0_LSB _U(0)
+#define TIMER_INTS_ALARM_0_RESET _u(0x0)
+#define TIMER_INTS_ALARM_0_BITS _u(0x00000001)
+#define TIMER_INTS_ALARM_0_MSB _u(0)
+#define TIMER_INTS_ALARM_0_LSB _u(0)
#define TIMER_INTS_ALARM_0_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_TIMER_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/uart.h b/src/rp2040/hardware_regs/include/hardware/regs/uart.h
index 0c98dbd..409f598 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/uart.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/uart.h
@@ -14,9 +14,9 @@
// =============================================================================
// Register : UART_UARTDR
// Description : Data Register, UARTDR
-#define UART_UARTDR_OFFSET _U(0x00000000)
-#define UART_UARTDR_BITS _U(0x00000fff)
-#define UART_UARTDR_RESET _U(0x00000000)
+#define UART_UARTDR_OFFSET _u(0x00000000)
+#define UART_UARTDR_BITS _u(0x00000fff)
+#define UART_UARTDR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : UART_UARTDR_OE
// Description : Overrun error. This bit is set to 1 if data is received and the
@@ -24,9 +24,9 @@
// is an empty space in the FIFO and a new character can be
// written to it.
#define UART_UARTDR_OE_RESET "-"
-#define UART_UARTDR_OE_BITS _U(0x00000800)
-#define UART_UARTDR_OE_MSB _U(11)
-#define UART_UARTDR_OE_LSB _U(11)
+#define UART_UARTDR_OE_BITS _u(0x00000800)
+#define UART_UARTDR_OE_MSB _u(11)
+#define UART_UARTDR_OE_LSB _u(11)
#define UART_UARTDR_OE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTDR_BE
@@ -40,9 +40,9 @@
// goes to a 1 (marking state), and the next valid start bit is
// received.
#define UART_UARTDR_BE_RESET "-"
-#define UART_UARTDR_BE_BITS _U(0x00000400)
-#define UART_UARTDR_BE_MSB _U(10)
-#define UART_UARTDR_BE_LSB _U(10)
+#define UART_UARTDR_BE_BITS _u(0x00000400)
+#define UART_UARTDR_BE_MSB _u(10)
+#define UART_UARTDR_BE_LSB _u(10)
#define UART_UARTDR_BE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTDR_PE
@@ -52,9 +52,9 @@
// FIFO mode, this error is associated with the character at the
// top of the FIFO.
#define UART_UARTDR_PE_RESET "-"
-#define UART_UARTDR_PE_BITS _U(0x00000200)
-#define UART_UARTDR_PE_MSB _U(9)
-#define UART_UARTDR_PE_LSB _U(9)
+#define UART_UARTDR_PE_BITS _u(0x00000200)
+#define UART_UARTDR_PE_MSB _u(9)
+#define UART_UARTDR_PE_LSB _u(9)
#define UART_UARTDR_PE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTDR_FE
@@ -63,24 +63,24 @@
// 1). In FIFO mode, this error is associated with the character
// at the top of the FIFO.
#define UART_UARTDR_FE_RESET "-"
-#define UART_UARTDR_FE_BITS _U(0x00000100)
-#define UART_UARTDR_FE_MSB _U(8)
-#define UART_UARTDR_FE_LSB _U(8)
+#define UART_UARTDR_FE_BITS _u(0x00000100)
+#define UART_UARTDR_FE_MSB _u(8)
+#define UART_UARTDR_FE_LSB _u(8)
#define UART_UARTDR_FE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTDR_DATA
// Description : Receive (read) data character. Transmit (write) data character.
#define UART_UARTDR_DATA_RESET "-"
-#define UART_UARTDR_DATA_BITS _U(0x000000ff)
-#define UART_UARTDR_DATA_MSB _U(7)
-#define UART_UARTDR_DATA_LSB _U(0)
+#define UART_UARTDR_DATA_BITS _u(0x000000ff)
+#define UART_UARTDR_DATA_MSB _u(7)
+#define UART_UARTDR_DATA_LSB _u(0)
#define UART_UARTDR_DATA_ACCESS "RWF"
// =============================================================================
// Register : UART_UARTRSR
// Description : Receive Status Register/Error Clear Register, UARTRSR/UARTECR
-#define UART_UARTRSR_OFFSET _U(0x00000004)
-#define UART_UARTRSR_BITS _U(0x0000000f)
-#define UART_UARTRSR_RESET _U(0x00000000)
+#define UART_UARTRSR_OFFSET _u(0x00000004)
+#define UART_UARTRSR_BITS _u(0x0000000f)
+#define UART_UARTRSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : UART_UARTRSR_OE
// Description : Overrun error. This bit is set to 1 if data is received and the
@@ -89,10 +89,10 @@
// written when the FIFO is full, only the contents of the shift
// register are overwritten. The CPU must now read the data, to
// empty the FIFO.
-#define UART_UARTRSR_OE_RESET _U(0x0)
-#define UART_UARTRSR_OE_BITS _U(0x00000008)
-#define UART_UARTRSR_OE_MSB _U(3)
-#define UART_UARTRSR_OE_LSB _U(3)
+#define UART_UARTRSR_OE_RESET _u(0x0)
+#define UART_UARTRSR_OE_BITS _u(0x00000008)
+#define UART_UARTRSR_OE_MSB _u(3)
+#define UART_UARTRSR_OE_LSB _u(3)
#define UART_UARTRSR_OE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : UART_UARTRSR_BE
@@ -106,10 +106,10 @@
// next character is only enabled after the receive data input
// goes to a 1 (marking state) and the next valid start bit is
// received.
-#define UART_UARTRSR_BE_RESET _U(0x0)
-#define UART_UARTRSR_BE_BITS _U(0x00000004)
-#define UART_UARTRSR_BE_MSB _U(2)
-#define UART_UARTRSR_BE_LSB _U(2)
+#define UART_UARTRSR_BE_RESET _u(0x0)
+#define UART_UARTRSR_BE_BITS _u(0x00000004)
+#define UART_UARTRSR_BE_MSB _u(2)
+#define UART_UARTRSR_BE_LSB _u(2)
#define UART_UARTRSR_BE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : UART_UARTRSR_PE
@@ -118,10 +118,10 @@
// EPS and SPS bits in the Line Control Register, UARTLCR_H. This
// bit is cleared to 0 by a write to UARTECR. In FIFO mode, this
// error is associated with the character at the top of the FIFO.
-#define UART_UARTRSR_PE_RESET _U(0x0)
-#define UART_UARTRSR_PE_BITS _U(0x00000002)
-#define UART_UARTRSR_PE_MSB _U(1)
-#define UART_UARTRSR_PE_LSB _U(1)
+#define UART_UARTRSR_PE_RESET _u(0x0)
+#define UART_UARTRSR_PE_BITS _u(0x00000002)
+#define UART_UARTRSR_PE_MSB _u(1)
+#define UART_UARTRSR_PE_LSB _u(1)
#define UART_UARTRSR_PE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : UART_UARTRSR_FE
@@ -130,26 +130,26 @@
// 1). This bit is cleared to 0 by a write to UARTECR. In FIFO
// mode, this error is associated with the character at the top of
// the FIFO.
-#define UART_UARTRSR_FE_RESET _U(0x0)
-#define UART_UARTRSR_FE_BITS _U(0x00000001)
-#define UART_UARTRSR_FE_MSB _U(0)
-#define UART_UARTRSR_FE_LSB _U(0)
+#define UART_UARTRSR_FE_RESET _u(0x0)
+#define UART_UARTRSR_FE_BITS _u(0x00000001)
+#define UART_UARTRSR_FE_MSB _u(0)
+#define UART_UARTRSR_FE_LSB _u(0)
#define UART_UARTRSR_FE_ACCESS "WC"
// =============================================================================
// Register : UART_UARTFR
// Description : Flag Register, UARTFR
-#define UART_UARTFR_OFFSET _U(0x00000018)
-#define UART_UARTFR_BITS _U(0x000001ff)
-#define UART_UARTFR_RESET _U(0x00000090)
+#define UART_UARTFR_OFFSET _u(0x00000018)
+#define UART_UARTFR_BITS _u(0x000001ff)
+#define UART_UARTFR_RESET _u(0x00000090)
// -----------------------------------------------------------------------------
// Field : UART_UARTFR_RI
// Description : Ring indicator. This bit is the complement of the UART ring
// indicator, nUARTRI, modem status input. That is, the bit is 1
// when nUARTRI is LOW.
#define UART_UARTFR_RI_RESET "-"
-#define UART_UARTFR_RI_BITS _U(0x00000100)
-#define UART_UARTFR_RI_MSB _U(8)
-#define UART_UARTFR_RI_LSB _U(8)
+#define UART_UARTFR_RI_BITS _u(0x00000100)
+#define UART_UARTFR_RI_MSB _u(8)
+#define UART_UARTFR_RI_LSB _u(8)
#define UART_UARTFR_RI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTFR_TXFE
@@ -159,10 +159,10 @@
// holding register is empty. If the FIFO is enabled, the TXFE bit
// is set when the transmit FIFO is empty. This bit does not
// indicate if there is data in the transmit shift register.
-#define UART_UARTFR_TXFE_RESET _U(0x1)
-#define UART_UARTFR_TXFE_BITS _U(0x00000080)
-#define UART_UARTFR_TXFE_MSB _U(7)
-#define UART_UARTFR_TXFE_LSB _U(7)
+#define UART_UARTFR_TXFE_RESET _u(0x1)
+#define UART_UARTFR_TXFE_BITS _u(0x00000080)
+#define UART_UARTFR_TXFE_MSB _u(7)
+#define UART_UARTFR_TXFE_LSB _u(7)
#define UART_UARTFR_TXFE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTFR_RXFF
@@ -171,10 +171,10 @@
// disabled, this bit is set when the receive holding register is
// full. If the FIFO is enabled, the RXFF bit is set when the
// receive FIFO is full.
-#define UART_UARTFR_RXFF_RESET _U(0x0)
-#define UART_UARTFR_RXFF_BITS _U(0x00000040)
-#define UART_UARTFR_RXFF_MSB _U(6)
-#define UART_UARTFR_RXFF_LSB _U(6)
+#define UART_UARTFR_RXFF_RESET _u(0x0)
+#define UART_UARTFR_RXFF_BITS _u(0x00000040)
+#define UART_UARTFR_RXFF_MSB _u(6)
+#define UART_UARTFR_RXFF_LSB _u(6)
#define UART_UARTFR_RXFF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTFR_TXFF
@@ -183,10 +183,10 @@
// disabled, this bit is set when the transmit holding register is
// full. If the FIFO is enabled, the TXFF bit is set when the
// transmit FIFO is full.
-#define UART_UARTFR_TXFF_RESET _U(0x0)
-#define UART_UARTFR_TXFF_BITS _U(0x00000020)
-#define UART_UARTFR_TXFF_MSB _U(5)
-#define UART_UARTFR_TXFF_LSB _U(5)
+#define UART_UARTFR_TXFF_RESET _u(0x0)
+#define UART_UARTFR_TXFF_BITS _u(0x00000020)
+#define UART_UARTFR_TXFF_MSB _u(5)
+#define UART_UARTFR_TXFF_LSB _u(5)
#define UART_UARTFR_TXFF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTFR_RXFE
@@ -195,10 +195,10 @@
// disabled, this bit is set when the receive holding register is
// empty. If the FIFO is enabled, the RXFE bit is set when the
// receive FIFO is empty.
-#define UART_UARTFR_RXFE_RESET _U(0x1)
-#define UART_UARTFR_RXFE_BITS _U(0x00000010)
-#define UART_UARTFR_RXFE_MSB _U(4)
-#define UART_UARTFR_RXFE_LSB _U(4)
+#define UART_UARTFR_RXFE_RESET _u(0x1)
+#define UART_UARTFR_RXFE_BITS _u(0x00000010)
+#define UART_UARTFR_RXFE_MSB _u(4)
+#define UART_UARTFR_RXFE_LSB _u(4)
#define UART_UARTFR_RXFE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTFR_BUSY
@@ -207,10 +207,10 @@
// byte, including all the stop bits, has been sent from the shift
// register. This bit is set as soon as the transmit FIFO becomes
// non-empty, regardless of whether the UART is enabled or not.
-#define UART_UARTFR_BUSY_RESET _U(0x0)
-#define UART_UARTFR_BUSY_BITS _U(0x00000008)
-#define UART_UARTFR_BUSY_MSB _U(3)
-#define UART_UARTFR_BUSY_LSB _U(3)
+#define UART_UARTFR_BUSY_RESET _u(0x0)
+#define UART_UARTFR_BUSY_BITS _u(0x00000008)
+#define UART_UARTFR_BUSY_MSB _u(3)
+#define UART_UARTFR_BUSY_LSB _u(3)
#define UART_UARTFR_BUSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTFR_DCD
@@ -218,9 +218,9 @@
// data carrier detect, nUARTDCD, modem status input. That is, the
// bit is 1 when nUARTDCD is LOW.
#define UART_UARTFR_DCD_RESET "-"
-#define UART_UARTFR_DCD_BITS _U(0x00000004)
-#define UART_UARTFR_DCD_MSB _U(2)
-#define UART_UARTFR_DCD_LSB _U(2)
+#define UART_UARTFR_DCD_BITS _u(0x00000004)
+#define UART_UARTFR_DCD_MSB _u(2)
+#define UART_UARTFR_DCD_LSB _u(2)
#define UART_UARTFR_DCD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTFR_DSR
@@ -228,9 +228,9 @@
// ready, nUARTDSR, modem status input. That is, the bit is 1 when
// nUARTDSR is LOW.
#define UART_UARTFR_DSR_RESET "-"
-#define UART_UARTFR_DSR_BITS _U(0x00000002)
-#define UART_UARTFR_DSR_MSB _U(1)
-#define UART_UARTFR_DSR_LSB _U(1)
+#define UART_UARTFR_DSR_BITS _u(0x00000002)
+#define UART_UARTFR_DSR_MSB _u(1)
+#define UART_UARTFR_DSR_LSB _u(1)
#define UART_UARTFR_DSR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTFR_CTS
@@ -238,61 +238,61 @@
// send, nUARTCTS, modem status input. That is, the bit is 1 when
// nUARTCTS is LOW.
#define UART_UARTFR_CTS_RESET "-"
-#define UART_UARTFR_CTS_BITS _U(0x00000001)
-#define UART_UARTFR_CTS_MSB _U(0)
-#define UART_UARTFR_CTS_LSB _U(0)
+#define UART_UARTFR_CTS_BITS _u(0x00000001)
+#define UART_UARTFR_CTS_MSB _u(0)
+#define UART_UARTFR_CTS_LSB _u(0)
#define UART_UARTFR_CTS_ACCESS "RO"
// =============================================================================
// Register : UART_UARTILPR
// Description : IrDA Low-Power Counter Register, UARTILPR
-#define UART_UARTILPR_OFFSET _U(0x00000020)
-#define UART_UARTILPR_BITS _U(0x000000ff)
-#define UART_UARTILPR_RESET _U(0x00000000)
+#define UART_UARTILPR_OFFSET _u(0x00000020)
+#define UART_UARTILPR_BITS _u(0x000000ff)
+#define UART_UARTILPR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : UART_UARTILPR_ILPDVSR
// Description : 8-bit low-power divisor value. These bits are cleared to 0 at
// reset.
-#define UART_UARTILPR_ILPDVSR_RESET _U(0x00)
-#define UART_UARTILPR_ILPDVSR_BITS _U(0x000000ff)
-#define UART_UARTILPR_ILPDVSR_MSB _U(7)
-#define UART_UARTILPR_ILPDVSR_LSB _U(0)
+#define UART_UARTILPR_ILPDVSR_RESET _u(0x00)
+#define UART_UARTILPR_ILPDVSR_BITS _u(0x000000ff)
+#define UART_UARTILPR_ILPDVSR_MSB _u(7)
+#define UART_UARTILPR_ILPDVSR_LSB _u(0)
#define UART_UARTILPR_ILPDVSR_ACCESS "RW"
// =============================================================================
// Register : UART_UARTIBRD
// Description : Integer Baud Rate Register, UARTIBRD
-#define UART_UARTIBRD_OFFSET _U(0x00000024)
-#define UART_UARTIBRD_BITS _U(0x0000ffff)
-#define UART_UARTIBRD_RESET _U(0x00000000)
+#define UART_UARTIBRD_OFFSET _u(0x00000024)
+#define UART_UARTIBRD_BITS _u(0x0000ffff)
+#define UART_UARTIBRD_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : UART_UARTIBRD_BAUD_DIVINT
// Description : The integer baud rate divisor. These bits are cleared to 0 on
// reset.
-#define UART_UARTIBRD_BAUD_DIVINT_RESET _U(0x0000)
-#define UART_UARTIBRD_BAUD_DIVINT_BITS _U(0x0000ffff)
-#define UART_UARTIBRD_BAUD_DIVINT_MSB _U(15)
-#define UART_UARTIBRD_BAUD_DIVINT_LSB _U(0)
+#define UART_UARTIBRD_BAUD_DIVINT_RESET _u(0x0000)
+#define UART_UARTIBRD_BAUD_DIVINT_BITS _u(0x0000ffff)
+#define UART_UARTIBRD_BAUD_DIVINT_MSB _u(15)
+#define UART_UARTIBRD_BAUD_DIVINT_LSB _u(0)
#define UART_UARTIBRD_BAUD_DIVINT_ACCESS "RW"
// =============================================================================
// Register : UART_UARTFBRD
// Description : Fractional Baud Rate Register, UARTFBRD
-#define UART_UARTFBRD_OFFSET _U(0x00000028)
-#define UART_UARTFBRD_BITS _U(0x0000003f)
-#define UART_UARTFBRD_RESET _U(0x00000000)
+#define UART_UARTFBRD_OFFSET _u(0x00000028)
+#define UART_UARTFBRD_BITS _u(0x0000003f)
+#define UART_UARTFBRD_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : UART_UARTFBRD_BAUD_DIVFRAC
// Description : The fractional baud rate divisor. These bits are cleared to 0
// on reset.
-#define UART_UARTFBRD_BAUD_DIVFRAC_RESET _U(0x00)
-#define UART_UARTFBRD_BAUD_DIVFRAC_BITS _U(0x0000003f)
-#define UART_UARTFBRD_BAUD_DIVFRAC_MSB _U(5)
-#define UART_UARTFBRD_BAUD_DIVFRAC_LSB _U(0)
+#define UART_UARTFBRD_BAUD_DIVFRAC_RESET _u(0x00)
+#define UART_UARTFBRD_BAUD_DIVFRAC_BITS _u(0x0000003f)
+#define UART_UARTFBRD_BAUD_DIVFRAC_MSB _u(5)
+#define UART_UARTFBRD_BAUD_DIVFRAC_LSB _u(0)
#define UART_UARTFBRD_BAUD_DIVFRAC_ACCESS "RW"
// =============================================================================
// Register : UART_UARTLCR_H
// Description : Line Control Register, UARTLCR_H
-#define UART_UARTLCR_H_OFFSET _U(0x0000002c)
-#define UART_UARTLCR_H_BITS _U(0x000000ff)
-#define UART_UARTLCR_H_RESET _U(0x00000000)
+#define UART_UARTLCR_H_OFFSET _u(0x0000002c)
+#define UART_UARTLCR_H_BITS _u(0x000000ff)
+#define UART_UARTLCR_H_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : UART_UARTLCR_H_SPS
// Description : Stick parity select. 0 = stick parity is disabled 1 = either: *
@@ -300,40 +300,40 @@
// checked as a 1 * if the EPS bit is 1 then the parity bit is
// transmitted and checked as a 0. This bit has no effect when the
// PEN bit disables parity checking and generation.
-#define UART_UARTLCR_H_SPS_RESET _U(0x0)
-#define UART_UARTLCR_H_SPS_BITS _U(0x00000080)
-#define UART_UARTLCR_H_SPS_MSB _U(7)
-#define UART_UARTLCR_H_SPS_LSB _U(7)
+#define UART_UARTLCR_H_SPS_RESET _u(0x0)
+#define UART_UARTLCR_H_SPS_BITS _u(0x00000080)
+#define UART_UARTLCR_H_SPS_MSB _u(7)
+#define UART_UARTLCR_H_SPS_LSB _u(7)
#define UART_UARTLCR_H_SPS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTLCR_H_WLEN
// Description : Word length. These bits indicate the number of data bits
// transmitted or received in a frame as follows: b11 = 8 bits b10
// = 7 bits b01 = 6 bits b00 = 5 bits.
-#define UART_UARTLCR_H_WLEN_RESET _U(0x0)
-#define UART_UARTLCR_H_WLEN_BITS _U(0x00000060)
-#define UART_UARTLCR_H_WLEN_MSB _U(6)
-#define UART_UARTLCR_H_WLEN_LSB _U(5)
+#define UART_UARTLCR_H_WLEN_RESET _u(0x0)
+#define UART_UARTLCR_H_WLEN_BITS _u(0x00000060)
+#define UART_UARTLCR_H_WLEN_MSB _u(6)
+#define UART_UARTLCR_H_WLEN_LSB _u(5)
#define UART_UARTLCR_H_WLEN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTLCR_H_FEN
// Description : Enable FIFOs: 0 = FIFOs are disabled (character mode) that is,
// the FIFOs become 1-byte-deep holding registers 1 = transmit and
// receive FIFO buffers are enabled (FIFO mode).
-#define UART_UARTLCR_H_FEN_RESET _U(0x0)
-#define UART_UARTLCR_H_FEN_BITS _U(0x00000010)
-#define UART_UARTLCR_H_FEN_MSB _U(4)
-#define UART_UARTLCR_H_FEN_LSB _U(4)
+#define UART_UARTLCR_H_FEN_RESET _u(0x0)
+#define UART_UARTLCR_H_FEN_BITS _u(0x00000010)
+#define UART_UARTLCR_H_FEN_MSB _u(4)
+#define UART_UARTLCR_H_FEN_LSB _u(4)
#define UART_UARTLCR_H_FEN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTLCR_H_STP2
// Description : Two stop bits select. If this bit is set to 1, two stop bits
// are transmitted at the end of the frame. The receive logic does
// not check for two stop bits being received.
-#define UART_UARTLCR_H_STP2_RESET _U(0x0)
-#define UART_UARTLCR_H_STP2_BITS _U(0x00000008)
-#define UART_UARTLCR_H_STP2_MSB _U(3)
-#define UART_UARTLCR_H_STP2_LSB _U(3)
+#define UART_UARTLCR_H_STP2_RESET _u(0x0)
+#define UART_UARTLCR_H_STP2_BITS _u(0x00000008)
+#define UART_UARTLCR_H_STP2_MSB _u(3)
+#define UART_UARTLCR_H_STP2_LSB _u(3)
#define UART_UARTLCR_H_STP2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTLCR_H_EPS
@@ -344,20 +344,20 @@
// an even number of 1s in the data and parity bits. This bit has
// no effect when the PEN bit disables parity checking and
// generation.
-#define UART_UARTLCR_H_EPS_RESET _U(0x0)
-#define UART_UARTLCR_H_EPS_BITS _U(0x00000004)
-#define UART_UARTLCR_H_EPS_MSB _U(2)
-#define UART_UARTLCR_H_EPS_LSB _U(2)
+#define UART_UARTLCR_H_EPS_RESET _u(0x0)
+#define UART_UARTLCR_H_EPS_BITS _u(0x00000004)
+#define UART_UARTLCR_H_EPS_MSB _u(2)
+#define UART_UARTLCR_H_EPS_LSB _u(2)
#define UART_UARTLCR_H_EPS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTLCR_H_PEN
// Description : Parity enable: 0 = parity is disabled and no parity bit added
// to the data frame 1 = parity checking and generation is
// enabled.
-#define UART_UARTLCR_H_PEN_RESET _U(0x0)
-#define UART_UARTLCR_H_PEN_BITS _U(0x00000002)
-#define UART_UARTLCR_H_PEN_MSB _U(1)
-#define UART_UARTLCR_H_PEN_LSB _U(1)
+#define UART_UARTLCR_H_PEN_RESET _u(0x0)
+#define UART_UARTLCR_H_PEN_BITS _u(0x00000002)
+#define UART_UARTLCR_H_PEN_MSB _u(1)
+#define UART_UARTLCR_H_PEN_LSB _u(1)
#define UART_UARTLCR_H_PEN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTLCR_H_BRK
@@ -366,46 +366,46 @@
// the current character. For the proper execution of the break
// command, the software must set this bit for at least two
// complete frames. For normal use, this bit must be cleared to 0.
-#define UART_UARTLCR_H_BRK_RESET _U(0x0)
-#define UART_UARTLCR_H_BRK_BITS _U(0x00000001)
-#define UART_UARTLCR_H_BRK_MSB _U(0)
-#define UART_UARTLCR_H_BRK_LSB _U(0)
+#define UART_UARTLCR_H_BRK_RESET _u(0x0)
+#define UART_UARTLCR_H_BRK_BITS _u(0x00000001)
+#define UART_UARTLCR_H_BRK_MSB _u(0)
+#define UART_UARTLCR_H_BRK_LSB _u(0)
#define UART_UARTLCR_H_BRK_ACCESS "RW"
// =============================================================================
// Register : UART_UARTCR
// Description : Control Register, UARTCR
-#define UART_UARTCR_OFFSET _U(0x00000030)
-#define UART_UARTCR_BITS _U(0x0000ff87)
-#define UART_UARTCR_RESET _U(0x00000300)
+#define UART_UARTCR_OFFSET _u(0x00000030)
+#define UART_UARTCR_BITS _u(0x0000ff87)
+#define UART_UARTCR_RESET _u(0x00000300)
// -----------------------------------------------------------------------------
// Field : UART_UARTCR_CTSEN
// Description : CTS hardware flow control enable. If this bit is set to 1, CTS
// hardware flow control is enabled. Data is only transmitted when
// the nUARTCTS signal is asserted.
-#define UART_UARTCR_CTSEN_RESET _U(0x0)
-#define UART_UARTCR_CTSEN_BITS _U(0x00008000)
-#define UART_UARTCR_CTSEN_MSB _U(15)
-#define UART_UARTCR_CTSEN_LSB _U(15)
+#define UART_UARTCR_CTSEN_RESET _u(0x0)
+#define UART_UARTCR_CTSEN_BITS _u(0x00008000)
+#define UART_UARTCR_CTSEN_MSB _u(15)
+#define UART_UARTCR_CTSEN_LSB _u(15)
#define UART_UARTCR_CTSEN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTCR_RTSEN
// Description : RTS hardware flow control enable. If this bit is set to 1, RTS
// hardware flow control is enabled. Data is only requested when
// there is space in the receive FIFO for it to be received.
-#define UART_UARTCR_RTSEN_RESET _U(0x0)
-#define UART_UARTCR_RTSEN_BITS _U(0x00004000)
-#define UART_UARTCR_RTSEN_MSB _U(14)
-#define UART_UARTCR_RTSEN_LSB _U(14)
+#define UART_UARTCR_RTSEN_RESET _u(0x0)
+#define UART_UARTCR_RTSEN_BITS _u(0x00004000)
+#define UART_UARTCR_RTSEN_MSB _u(14)
+#define UART_UARTCR_RTSEN_LSB _u(14)
#define UART_UARTCR_RTSEN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTCR_OUT2
// Description : This bit is the complement of the UART Out2 (nUARTOut2) modem
// status output. That is, when the bit is programmed to a 1, the
// output is 0. For DTE this can be used as Ring Indicator (RI).
-#define UART_UARTCR_OUT2_RESET _U(0x0)
-#define UART_UARTCR_OUT2_BITS _U(0x00002000)
-#define UART_UARTCR_OUT2_MSB _U(13)
-#define UART_UARTCR_OUT2_LSB _U(13)
+#define UART_UARTCR_OUT2_RESET _u(0x0)
+#define UART_UARTCR_OUT2_BITS _u(0x00002000)
+#define UART_UARTCR_OUT2_MSB _u(13)
+#define UART_UARTCR_OUT2_LSB _u(13)
#define UART_UARTCR_OUT2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTCR_OUT1
@@ -413,30 +413,30 @@
// status output. That is, when the bit is programmed to a 1 the
// output is 0. For DTE this can be used as Data Carrier Detect
// (DCD).
-#define UART_UARTCR_OUT1_RESET _U(0x0)
-#define UART_UARTCR_OUT1_BITS _U(0x00001000)
-#define UART_UARTCR_OUT1_MSB _U(12)
-#define UART_UARTCR_OUT1_LSB _U(12)
+#define UART_UARTCR_OUT1_RESET _u(0x0)
+#define UART_UARTCR_OUT1_BITS _u(0x00001000)
+#define UART_UARTCR_OUT1_MSB _u(12)
+#define UART_UARTCR_OUT1_LSB _u(12)
#define UART_UARTCR_OUT1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTCR_RTS
// Description : Request to send. This bit is the complement of the UART request
// to send, nUARTRTS, modem status output. That is, when the bit
// is programmed to a 1 then nUARTRTS is LOW.
-#define UART_UARTCR_RTS_RESET _U(0x0)
-#define UART_UARTCR_RTS_BITS _U(0x00000800)
-#define UART_UARTCR_RTS_MSB _U(11)
-#define UART_UARTCR_RTS_LSB _U(11)
+#define UART_UARTCR_RTS_RESET _u(0x0)
+#define UART_UARTCR_RTS_BITS _u(0x00000800)
+#define UART_UARTCR_RTS_MSB _u(11)
+#define UART_UARTCR_RTS_LSB _u(11)
#define UART_UARTCR_RTS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTCR_DTR
// Description : Data transmit ready. This bit is the complement of the UART
// data transmit ready, nUARTDTR, modem status output. That is,
// when the bit is programmed to a 1 then nUARTDTR is LOW.
-#define UART_UARTCR_DTR_RESET _U(0x0)
-#define UART_UARTCR_DTR_BITS _U(0x00000400)
-#define UART_UARTCR_DTR_MSB _U(10)
-#define UART_UARTCR_DTR_LSB _U(10)
+#define UART_UARTCR_DTR_RESET _u(0x0)
+#define UART_UARTCR_DTR_BITS _u(0x00000400)
+#define UART_UARTCR_DTR_MSB _u(10)
+#define UART_UARTCR_DTR_LSB _u(10)
#define UART_UARTCR_DTR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTCR_RXE
@@ -445,10 +445,10 @@
// signals or SIR signals depending on the setting of the SIREN
// bit. When the UART is disabled in the middle of reception, it
// completes the current character before stopping.
-#define UART_UARTCR_RXE_RESET _U(0x1)
-#define UART_UARTCR_RXE_BITS _U(0x00000200)
-#define UART_UARTCR_RXE_MSB _U(9)
-#define UART_UARTCR_RXE_LSB _U(9)
+#define UART_UARTCR_RXE_RESET _u(0x1)
+#define UART_UARTCR_RXE_BITS _u(0x00000200)
+#define UART_UARTCR_RXE_MSB _u(9)
+#define UART_UARTCR_RXE_LSB _u(9)
#define UART_UARTCR_RXE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTCR_TXE
@@ -458,10 +458,10 @@
// SIREN bit. When the UART is disabled in the middle of
// transmission, it completes the current character before
// stopping.
-#define UART_UARTCR_TXE_RESET _U(0x1)
-#define UART_UARTCR_TXE_BITS _U(0x00000100)
-#define UART_UARTCR_TXE_MSB _U(8)
-#define UART_UARTCR_TXE_LSB _U(8)
+#define UART_UARTCR_TXE_RESET _u(0x1)
+#define UART_UARTCR_TXE_BITS _u(0x00000100)
+#define UART_UARTCR_TXE_MSB _u(8)
+#define UART_UARTCR_TXE_LSB _u(8)
#define UART_UARTCR_TXE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTCR_LBE
@@ -479,10 +479,10 @@
// mode or UART mode, when this bit is set, the modem outputs are
// also fed through to the modem inputs. This bit is cleared to 0
// on reset, to disable loopback.
-#define UART_UARTCR_LBE_RESET _U(0x0)
-#define UART_UARTCR_LBE_BITS _U(0x00000080)
-#define UART_UARTCR_LBE_MSB _U(7)
-#define UART_UARTCR_LBE_LSB _U(7)
+#define UART_UARTCR_LBE_RESET _u(0x0)
+#define UART_UARTCR_LBE_BITS _u(0x00000080)
+#define UART_UARTCR_LBE_MSB _u(7)
+#define UART_UARTCR_LBE_LSB _u(7)
#define UART_UARTCR_LBE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTCR_SIRLP
@@ -494,10 +494,10 @@
// the IrLPBaud16 input signal, regardless of the selected bit
// rate. Setting this bit uses less power, but might reduce
// transmission distances.
-#define UART_UARTCR_SIRLP_RESET _U(0x0)
-#define UART_UARTCR_SIRLP_BITS _U(0x00000004)
-#define UART_UARTCR_SIRLP_MSB _U(2)
-#define UART_UARTCR_SIRLP_LSB _U(2)
+#define UART_UARTCR_SIRLP_RESET _u(0x0)
+#define UART_UARTCR_SIRLP_BITS _u(0x00000004)
+#define UART_UARTCR_SIRLP_MSB _u(2)
+#define UART_UARTCR_SIRLP_LSB _u(2)
#define UART_UARTCR_SIRLP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTCR_SIREN
@@ -508,10 +508,10 @@
// HIGH, in the marking state. Signal transitions on UARTRXD or
// modem status inputs have no effect. This bit has no effect if
// the UARTEN bit disables the UART.
-#define UART_UARTCR_SIREN_RESET _U(0x0)
-#define UART_UARTCR_SIREN_BITS _U(0x00000002)
-#define UART_UARTCR_SIREN_MSB _U(1)
-#define UART_UARTCR_SIREN_LSB _U(1)
+#define UART_UARTCR_SIREN_RESET _u(0x0)
+#define UART_UARTCR_SIREN_BITS _u(0x00000002)
+#define UART_UARTCR_SIREN_MSB _u(1)
+#define UART_UARTCR_SIREN_LSB _u(1)
#define UART_UARTCR_SIREN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTCR_UARTEN
@@ -520,17 +520,17 @@
// current character before stopping. 1 = the UART is enabled.
// Data transmission and reception occurs for either UART signals
// or SIR signals depending on the setting of the SIREN bit.
-#define UART_UARTCR_UARTEN_RESET _U(0x0)
-#define UART_UARTCR_UARTEN_BITS _U(0x00000001)
-#define UART_UARTCR_UARTEN_MSB _U(0)
-#define UART_UARTCR_UARTEN_LSB _U(0)
+#define UART_UARTCR_UARTEN_RESET _u(0x0)
+#define UART_UARTCR_UARTEN_BITS _u(0x00000001)
+#define UART_UARTCR_UARTEN_MSB _u(0)
+#define UART_UARTCR_UARTEN_LSB _u(0)
#define UART_UARTCR_UARTEN_ACCESS "RW"
// =============================================================================
// Register : UART_UARTIFLS
// Description : Interrupt FIFO Level Select Register, UARTIFLS
-#define UART_UARTIFLS_OFFSET _U(0x00000034)
-#define UART_UARTIFLS_BITS _U(0x0000003f)
-#define UART_UARTIFLS_RESET _U(0x00000012)
+#define UART_UARTIFLS_OFFSET _u(0x00000034)
+#define UART_UARTIFLS_BITS _u(0x0000003f)
+#define UART_UARTIFLS_RESET _u(0x00000012)
// -----------------------------------------------------------------------------
// Field : UART_UARTIFLS_RXIFLSEL
// Description : Receive interrupt FIFO level select. The trigger points for the
@@ -539,10 +539,10 @@
// Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes
// >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full
// b101-b111 = reserved.
-#define UART_UARTIFLS_RXIFLSEL_RESET _U(0x2)
-#define UART_UARTIFLS_RXIFLSEL_BITS _U(0x00000038)
-#define UART_UARTIFLS_RXIFLSEL_MSB _U(5)
-#define UART_UARTIFLS_RXIFLSEL_LSB _U(3)
+#define UART_UARTIFLS_RXIFLSEL_RESET _u(0x2)
+#define UART_UARTIFLS_RXIFLSEL_BITS _u(0x00000038)
+#define UART_UARTIFLS_RXIFLSEL_MSB _u(5)
+#define UART_UARTIFLS_RXIFLSEL_LSB _u(3)
#define UART_UARTIFLS_RXIFLSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTIFLS_TXIFLSEL
@@ -552,597 +552,597 @@
// full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit
// FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 /
// 8 full b101-b111 = reserved.
-#define UART_UARTIFLS_TXIFLSEL_RESET _U(0x2)
-#define UART_UARTIFLS_TXIFLSEL_BITS _U(0x00000007)
-#define UART_UARTIFLS_TXIFLSEL_MSB _U(2)
-#define UART_UARTIFLS_TXIFLSEL_LSB _U(0)
+#define UART_UARTIFLS_TXIFLSEL_RESET _u(0x2)
+#define UART_UARTIFLS_TXIFLSEL_BITS _u(0x00000007)
+#define UART_UARTIFLS_TXIFLSEL_MSB _u(2)
+#define UART_UARTIFLS_TXIFLSEL_LSB _u(0)
#define UART_UARTIFLS_TXIFLSEL_ACCESS "RW"
// =============================================================================
// Register : UART_UARTIMSC
// Description : Interrupt Mask Set/Clear Register, UARTIMSC
-#define UART_UARTIMSC_OFFSET _U(0x00000038)
-#define UART_UARTIMSC_BITS _U(0x000007ff)
-#define UART_UARTIMSC_RESET _U(0x00000000)
+#define UART_UARTIMSC_OFFSET _u(0x00000038)
+#define UART_UARTIMSC_BITS _u(0x000007ff)
+#define UART_UARTIMSC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : UART_UARTIMSC_OEIM
// Description : Overrun error interrupt mask. A read returns the current mask
// for the UARTOEINTR interrupt. On a write of 1, the mask of the
// UARTOEINTR interrupt is set. A write of 0 clears the mask.
-#define UART_UARTIMSC_OEIM_RESET _U(0x0)
-#define UART_UARTIMSC_OEIM_BITS _U(0x00000400)
-#define UART_UARTIMSC_OEIM_MSB _U(10)
-#define UART_UARTIMSC_OEIM_LSB _U(10)
+#define UART_UARTIMSC_OEIM_RESET _u(0x0)
+#define UART_UARTIMSC_OEIM_BITS _u(0x00000400)
+#define UART_UARTIMSC_OEIM_MSB _u(10)
+#define UART_UARTIMSC_OEIM_LSB _u(10)
#define UART_UARTIMSC_OEIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTIMSC_BEIM
// Description : Break error interrupt mask. A read returns the current mask for
// the UARTBEINTR interrupt. On a write of 1, the mask of the
// UARTBEINTR interrupt is set. A write of 0 clears the mask.
-#define UART_UARTIMSC_BEIM_RESET _U(0x0)
-#define UART_UARTIMSC_BEIM_BITS _U(0x00000200)
-#define UART_UARTIMSC_BEIM_MSB _U(9)
-#define UART_UARTIMSC_BEIM_LSB _U(9)
+#define UART_UARTIMSC_BEIM_RESET _u(0x0)
+#define UART_UARTIMSC_BEIM_BITS _u(0x00000200)
+#define UART_UARTIMSC_BEIM_MSB _u(9)
+#define UART_UARTIMSC_BEIM_LSB _u(9)
#define UART_UARTIMSC_BEIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTIMSC_PEIM
// Description : Parity error interrupt mask. A read returns the current mask
// for the UARTPEINTR interrupt. On a write of 1, the mask of the
// UARTPEINTR interrupt is set. A write of 0 clears the mask.
-#define UART_UARTIMSC_PEIM_RESET _U(0x0)
-#define UART_UARTIMSC_PEIM_BITS _U(0x00000100)
-#define UART_UARTIMSC_PEIM_MSB _U(8)
-#define UART_UARTIMSC_PEIM_LSB _U(8)
+#define UART_UARTIMSC_PEIM_RESET _u(0x0)
+#define UART_UARTIMSC_PEIM_BITS _u(0x00000100)
+#define UART_UARTIMSC_PEIM_MSB _u(8)
+#define UART_UARTIMSC_PEIM_LSB _u(8)
#define UART_UARTIMSC_PEIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTIMSC_FEIM
// Description : Framing error interrupt mask. A read returns the current mask
// for the UARTFEINTR interrupt. On a write of 1, the mask of the
// UARTFEINTR interrupt is set. A write of 0 clears the mask.
-#define UART_UARTIMSC_FEIM_RESET _U(0x0)
-#define UART_UARTIMSC_FEIM_BITS _U(0x00000080)
-#define UART_UARTIMSC_FEIM_MSB _U(7)
-#define UART_UARTIMSC_FEIM_LSB _U(7)
+#define UART_UARTIMSC_FEIM_RESET _u(0x0)
+#define UART_UARTIMSC_FEIM_BITS _u(0x00000080)
+#define UART_UARTIMSC_FEIM_MSB _u(7)
+#define UART_UARTIMSC_FEIM_LSB _u(7)
#define UART_UARTIMSC_FEIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTIMSC_RTIM
// Description : Receive timeout interrupt mask. A read returns the current mask
// for the UARTRTINTR interrupt. On a write of 1, the mask of the
// UARTRTINTR interrupt is set. A write of 0 clears the mask.
-#define UART_UARTIMSC_RTIM_RESET _U(0x0)
-#define UART_UARTIMSC_RTIM_BITS _U(0x00000040)
-#define UART_UARTIMSC_RTIM_MSB _U(6)
-#define UART_UARTIMSC_RTIM_LSB _U(6)
+#define UART_UARTIMSC_RTIM_RESET _u(0x0)
+#define UART_UARTIMSC_RTIM_BITS _u(0x00000040)
+#define UART_UARTIMSC_RTIM_MSB _u(6)
+#define UART_UARTIMSC_RTIM_LSB _u(6)
#define UART_UARTIMSC_RTIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTIMSC_TXIM
// Description : Transmit interrupt mask. A read returns the current mask for
// the UARTTXINTR interrupt. On a write of 1, the mask of the
// UARTTXINTR interrupt is set. A write of 0 clears the mask.
-#define UART_UARTIMSC_TXIM_RESET _U(0x0)
-#define UART_UARTIMSC_TXIM_BITS _U(0x00000020)
-#define UART_UARTIMSC_TXIM_MSB _U(5)
-#define UART_UARTIMSC_TXIM_LSB _U(5)
+#define UART_UARTIMSC_TXIM_RESET _u(0x0)
+#define UART_UARTIMSC_TXIM_BITS _u(0x00000020)
+#define UART_UARTIMSC_TXIM_MSB _u(5)
+#define UART_UARTIMSC_TXIM_LSB _u(5)
#define UART_UARTIMSC_TXIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTIMSC_RXIM
// Description : Receive interrupt mask. A read returns the current mask for the
// UARTRXINTR interrupt. On a write of 1, the mask of the
// UARTRXINTR interrupt is set. A write of 0 clears the mask.
-#define UART_UARTIMSC_RXIM_RESET _U(0x0)
-#define UART_UARTIMSC_RXIM_BITS _U(0x00000010)
-#define UART_UARTIMSC_RXIM_MSB _U(4)
-#define UART_UARTIMSC_RXIM_LSB _U(4)
+#define UART_UARTIMSC_RXIM_RESET _u(0x0)
+#define UART_UARTIMSC_RXIM_BITS _u(0x00000010)
+#define UART_UARTIMSC_RXIM_MSB _u(4)
+#define UART_UARTIMSC_RXIM_LSB _u(4)
#define UART_UARTIMSC_RXIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTIMSC_DSRMIM
// Description : nUARTDSR modem interrupt mask. A read returns the current mask
// for the UARTDSRINTR interrupt. On a write of 1, the mask of the
// UARTDSRINTR interrupt is set. A write of 0 clears the mask.
-#define UART_UARTIMSC_DSRMIM_RESET _U(0x0)
-#define UART_UARTIMSC_DSRMIM_BITS _U(0x00000008)
-#define UART_UARTIMSC_DSRMIM_MSB _U(3)
-#define UART_UARTIMSC_DSRMIM_LSB _U(3)
+#define UART_UARTIMSC_DSRMIM_RESET _u(0x0)
+#define UART_UARTIMSC_DSRMIM_BITS _u(0x00000008)
+#define UART_UARTIMSC_DSRMIM_MSB _u(3)
+#define UART_UARTIMSC_DSRMIM_LSB _u(3)
#define UART_UARTIMSC_DSRMIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTIMSC_DCDMIM
// Description : nUARTDCD modem interrupt mask. A read returns the current mask
// for the UARTDCDINTR interrupt. On a write of 1, the mask of the
// UARTDCDINTR interrupt is set. A write of 0 clears the mask.
-#define UART_UARTIMSC_DCDMIM_RESET _U(0x0)
-#define UART_UARTIMSC_DCDMIM_BITS _U(0x00000004)
-#define UART_UARTIMSC_DCDMIM_MSB _U(2)
-#define UART_UARTIMSC_DCDMIM_LSB _U(2)
+#define UART_UARTIMSC_DCDMIM_RESET _u(0x0)
+#define UART_UARTIMSC_DCDMIM_BITS _u(0x00000004)
+#define UART_UARTIMSC_DCDMIM_MSB _u(2)
+#define UART_UARTIMSC_DCDMIM_LSB _u(2)
#define UART_UARTIMSC_DCDMIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTIMSC_CTSMIM
// Description : nUARTCTS modem interrupt mask. A read returns the current mask
// for the UARTCTSINTR interrupt. On a write of 1, the mask of the
// UARTCTSINTR interrupt is set. A write of 0 clears the mask.
-#define UART_UARTIMSC_CTSMIM_RESET _U(0x0)
-#define UART_UARTIMSC_CTSMIM_BITS _U(0x00000002)
-#define UART_UARTIMSC_CTSMIM_MSB _U(1)
-#define UART_UARTIMSC_CTSMIM_LSB _U(1)
+#define UART_UARTIMSC_CTSMIM_RESET _u(0x0)
+#define UART_UARTIMSC_CTSMIM_BITS _u(0x00000002)
+#define UART_UARTIMSC_CTSMIM_MSB _u(1)
+#define UART_UARTIMSC_CTSMIM_LSB _u(1)
#define UART_UARTIMSC_CTSMIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTIMSC_RIMIM
// Description : nUARTRI modem interrupt mask. A read returns the current mask
// for the UARTRIINTR interrupt. On a write of 1, the mask of the
// UARTRIINTR interrupt is set. A write of 0 clears the mask.
-#define UART_UARTIMSC_RIMIM_RESET _U(0x0)
-#define UART_UARTIMSC_RIMIM_BITS _U(0x00000001)
-#define UART_UARTIMSC_RIMIM_MSB _U(0)
-#define UART_UARTIMSC_RIMIM_LSB _U(0)
+#define UART_UARTIMSC_RIMIM_RESET _u(0x0)
+#define UART_UARTIMSC_RIMIM_BITS _u(0x00000001)
+#define UART_UARTIMSC_RIMIM_MSB _u(0)
+#define UART_UARTIMSC_RIMIM_LSB _u(0)
#define UART_UARTIMSC_RIMIM_ACCESS "RW"
// =============================================================================
// Register : UART_UARTRIS
// Description : Raw Interrupt Status Register, UARTRIS
-#define UART_UARTRIS_OFFSET _U(0x0000003c)
-#define UART_UARTRIS_BITS _U(0x000007ff)
-#define UART_UARTRIS_RESET _U(0x00000000)
+#define UART_UARTRIS_OFFSET _u(0x0000003c)
+#define UART_UARTRIS_BITS _u(0x000007ff)
+#define UART_UARTRIS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : UART_UARTRIS_OERIS
// Description : Overrun error interrupt status. Returns the raw interrupt state
// of the UARTOEINTR interrupt.
-#define UART_UARTRIS_OERIS_RESET _U(0x0)
-#define UART_UARTRIS_OERIS_BITS _U(0x00000400)
-#define UART_UARTRIS_OERIS_MSB _U(10)
-#define UART_UARTRIS_OERIS_LSB _U(10)
+#define UART_UARTRIS_OERIS_RESET _u(0x0)
+#define UART_UARTRIS_OERIS_BITS _u(0x00000400)
+#define UART_UARTRIS_OERIS_MSB _u(10)
+#define UART_UARTRIS_OERIS_LSB _u(10)
#define UART_UARTRIS_OERIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTRIS_BERIS
// Description : Break error interrupt status. Returns the raw interrupt state
// of the UARTBEINTR interrupt.
-#define UART_UARTRIS_BERIS_RESET _U(0x0)
-#define UART_UARTRIS_BERIS_BITS _U(0x00000200)
-#define UART_UARTRIS_BERIS_MSB _U(9)
-#define UART_UARTRIS_BERIS_LSB _U(9)
+#define UART_UARTRIS_BERIS_RESET _u(0x0)
+#define UART_UARTRIS_BERIS_BITS _u(0x00000200)
+#define UART_UARTRIS_BERIS_MSB _u(9)
+#define UART_UARTRIS_BERIS_LSB _u(9)
#define UART_UARTRIS_BERIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTRIS_PERIS
// Description : Parity error interrupt status. Returns the raw interrupt state
// of the UARTPEINTR interrupt.
-#define UART_UARTRIS_PERIS_RESET _U(0x0)
-#define UART_UARTRIS_PERIS_BITS _U(0x00000100)
-#define UART_UARTRIS_PERIS_MSB _U(8)
-#define UART_UARTRIS_PERIS_LSB _U(8)
+#define UART_UARTRIS_PERIS_RESET _u(0x0)
+#define UART_UARTRIS_PERIS_BITS _u(0x00000100)
+#define UART_UARTRIS_PERIS_MSB _u(8)
+#define UART_UARTRIS_PERIS_LSB _u(8)
#define UART_UARTRIS_PERIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTRIS_FERIS
// Description : Framing error interrupt status. Returns the raw interrupt state
// of the UARTFEINTR interrupt.
-#define UART_UARTRIS_FERIS_RESET _U(0x0)
-#define UART_UARTRIS_FERIS_BITS _U(0x00000080)
-#define UART_UARTRIS_FERIS_MSB _U(7)
-#define UART_UARTRIS_FERIS_LSB _U(7)
+#define UART_UARTRIS_FERIS_RESET _u(0x0)
+#define UART_UARTRIS_FERIS_BITS _u(0x00000080)
+#define UART_UARTRIS_FERIS_MSB _u(7)
+#define UART_UARTRIS_FERIS_LSB _u(7)
#define UART_UARTRIS_FERIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTRIS_RTRIS
// Description : Receive timeout interrupt status. Returns the raw interrupt
// state of the UARTRTINTR interrupt. a
-#define UART_UARTRIS_RTRIS_RESET _U(0x0)
-#define UART_UARTRIS_RTRIS_BITS _U(0x00000040)
-#define UART_UARTRIS_RTRIS_MSB _U(6)
-#define UART_UARTRIS_RTRIS_LSB _U(6)
+#define UART_UARTRIS_RTRIS_RESET _u(0x0)
+#define UART_UARTRIS_RTRIS_BITS _u(0x00000040)
+#define UART_UARTRIS_RTRIS_MSB _u(6)
+#define UART_UARTRIS_RTRIS_LSB _u(6)
#define UART_UARTRIS_RTRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTRIS_TXRIS
// Description : Transmit interrupt status. Returns the raw interrupt state of
// the UARTTXINTR interrupt.
-#define UART_UARTRIS_TXRIS_RESET _U(0x0)
-#define UART_UARTRIS_TXRIS_BITS _U(0x00000020)
-#define UART_UARTRIS_TXRIS_MSB _U(5)
-#define UART_UARTRIS_TXRIS_LSB _U(5)
+#define UART_UARTRIS_TXRIS_RESET _u(0x0)
+#define UART_UARTRIS_TXRIS_BITS _u(0x00000020)
+#define UART_UARTRIS_TXRIS_MSB _u(5)
+#define UART_UARTRIS_TXRIS_LSB _u(5)
#define UART_UARTRIS_TXRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTRIS_RXRIS
// Description : Receive interrupt status. Returns the raw interrupt state of
// the UARTRXINTR interrupt.
-#define UART_UARTRIS_RXRIS_RESET _U(0x0)
-#define UART_UARTRIS_RXRIS_BITS _U(0x00000010)
-#define UART_UARTRIS_RXRIS_MSB _U(4)
-#define UART_UARTRIS_RXRIS_LSB _U(4)
+#define UART_UARTRIS_RXRIS_RESET _u(0x0)
+#define UART_UARTRIS_RXRIS_BITS _u(0x00000010)
+#define UART_UARTRIS_RXRIS_MSB _u(4)
+#define UART_UARTRIS_RXRIS_LSB _u(4)
#define UART_UARTRIS_RXRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTRIS_DSRRMIS
// Description : nUARTDSR modem interrupt status. Returns the raw interrupt
// state of the UARTDSRINTR interrupt.
#define UART_UARTRIS_DSRRMIS_RESET "-"
-#define UART_UARTRIS_DSRRMIS_BITS _U(0x00000008)
-#define UART_UARTRIS_DSRRMIS_MSB _U(3)
-#define UART_UARTRIS_DSRRMIS_LSB _U(3)
+#define UART_UARTRIS_DSRRMIS_BITS _u(0x00000008)
+#define UART_UARTRIS_DSRRMIS_MSB _u(3)
+#define UART_UARTRIS_DSRRMIS_LSB _u(3)
#define UART_UARTRIS_DSRRMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTRIS_DCDRMIS
// Description : nUARTDCD modem interrupt status. Returns the raw interrupt
// state of the UARTDCDINTR interrupt.
#define UART_UARTRIS_DCDRMIS_RESET "-"
-#define UART_UARTRIS_DCDRMIS_BITS _U(0x00000004)
-#define UART_UARTRIS_DCDRMIS_MSB _U(2)
-#define UART_UARTRIS_DCDRMIS_LSB _U(2)
+#define UART_UARTRIS_DCDRMIS_BITS _u(0x00000004)
+#define UART_UARTRIS_DCDRMIS_MSB _u(2)
+#define UART_UARTRIS_DCDRMIS_LSB _u(2)
#define UART_UARTRIS_DCDRMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTRIS_CTSRMIS
// Description : nUARTCTS modem interrupt status. Returns the raw interrupt
// state of the UARTCTSINTR interrupt.
#define UART_UARTRIS_CTSRMIS_RESET "-"
-#define UART_UARTRIS_CTSRMIS_BITS _U(0x00000002)
-#define UART_UARTRIS_CTSRMIS_MSB _U(1)
-#define UART_UARTRIS_CTSRMIS_LSB _U(1)
+#define UART_UARTRIS_CTSRMIS_BITS _u(0x00000002)
+#define UART_UARTRIS_CTSRMIS_MSB _u(1)
+#define UART_UARTRIS_CTSRMIS_LSB _u(1)
#define UART_UARTRIS_CTSRMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTRIS_RIRMIS
// Description : nUARTRI modem interrupt status. Returns the raw interrupt state
// of the UARTRIINTR interrupt.
#define UART_UARTRIS_RIRMIS_RESET "-"
-#define UART_UARTRIS_RIRMIS_BITS _U(0x00000001)
-#define UART_UARTRIS_RIRMIS_MSB _U(0)
-#define UART_UARTRIS_RIRMIS_LSB _U(0)
+#define UART_UARTRIS_RIRMIS_BITS _u(0x00000001)
+#define UART_UARTRIS_RIRMIS_MSB _u(0)
+#define UART_UARTRIS_RIRMIS_LSB _u(0)
#define UART_UARTRIS_RIRMIS_ACCESS "RO"
// =============================================================================
// Register : UART_UARTMIS
// Description : Masked Interrupt Status Register, UARTMIS
-#define UART_UARTMIS_OFFSET _U(0x00000040)
-#define UART_UARTMIS_BITS _U(0x000007ff)
-#define UART_UARTMIS_RESET _U(0x00000000)
+#define UART_UARTMIS_OFFSET _u(0x00000040)
+#define UART_UARTMIS_BITS _u(0x000007ff)
+#define UART_UARTMIS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : UART_UARTMIS_OEMIS
// Description : Overrun error masked interrupt status. Returns the masked
// interrupt state of the UARTOEINTR interrupt.
-#define UART_UARTMIS_OEMIS_RESET _U(0x0)
-#define UART_UARTMIS_OEMIS_BITS _U(0x00000400)
-#define UART_UARTMIS_OEMIS_MSB _U(10)
-#define UART_UARTMIS_OEMIS_LSB _U(10)
+#define UART_UARTMIS_OEMIS_RESET _u(0x0)
+#define UART_UARTMIS_OEMIS_BITS _u(0x00000400)
+#define UART_UARTMIS_OEMIS_MSB _u(10)
+#define UART_UARTMIS_OEMIS_LSB _u(10)
#define UART_UARTMIS_OEMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTMIS_BEMIS
// Description : Break error masked interrupt status. Returns the masked
// interrupt state of the UARTBEINTR interrupt.
-#define UART_UARTMIS_BEMIS_RESET _U(0x0)
-#define UART_UARTMIS_BEMIS_BITS _U(0x00000200)
-#define UART_UARTMIS_BEMIS_MSB _U(9)
-#define UART_UARTMIS_BEMIS_LSB _U(9)
+#define UART_UARTMIS_BEMIS_RESET _u(0x0)
+#define UART_UARTMIS_BEMIS_BITS _u(0x00000200)
+#define UART_UARTMIS_BEMIS_MSB _u(9)
+#define UART_UARTMIS_BEMIS_LSB _u(9)
#define UART_UARTMIS_BEMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTMIS_PEMIS
// Description : Parity error masked interrupt status. Returns the masked
// interrupt state of the UARTPEINTR interrupt.
-#define UART_UARTMIS_PEMIS_RESET _U(0x0)
-#define UART_UARTMIS_PEMIS_BITS _U(0x00000100)
-#define UART_UARTMIS_PEMIS_MSB _U(8)
-#define UART_UARTMIS_PEMIS_LSB _U(8)
+#define UART_UARTMIS_PEMIS_RESET _u(0x0)
+#define UART_UARTMIS_PEMIS_BITS _u(0x00000100)
+#define UART_UARTMIS_PEMIS_MSB _u(8)
+#define UART_UARTMIS_PEMIS_LSB _u(8)
#define UART_UARTMIS_PEMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTMIS_FEMIS
// Description : Framing error masked interrupt status. Returns the masked
// interrupt state of the UARTFEINTR interrupt.
-#define UART_UARTMIS_FEMIS_RESET _U(0x0)
-#define UART_UARTMIS_FEMIS_BITS _U(0x00000080)
-#define UART_UARTMIS_FEMIS_MSB _U(7)
-#define UART_UARTMIS_FEMIS_LSB _U(7)
+#define UART_UARTMIS_FEMIS_RESET _u(0x0)
+#define UART_UARTMIS_FEMIS_BITS _u(0x00000080)
+#define UART_UARTMIS_FEMIS_MSB _u(7)
+#define UART_UARTMIS_FEMIS_LSB _u(7)
#define UART_UARTMIS_FEMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTMIS_RTMIS
// Description : Receive timeout masked interrupt status. Returns the masked
// interrupt state of the UARTRTINTR interrupt.
-#define UART_UARTMIS_RTMIS_RESET _U(0x0)
-#define UART_UARTMIS_RTMIS_BITS _U(0x00000040)
-#define UART_UARTMIS_RTMIS_MSB _U(6)
-#define UART_UARTMIS_RTMIS_LSB _U(6)
+#define UART_UARTMIS_RTMIS_RESET _u(0x0)
+#define UART_UARTMIS_RTMIS_BITS _u(0x00000040)
+#define UART_UARTMIS_RTMIS_MSB _u(6)
+#define UART_UARTMIS_RTMIS_LSB _u(6)
#define UART_UARTMIS_RTMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTMIS_TXMIS
// Description : Transmit masked interrupt status. Returns the masked interrupt
// state of the UARTTXINTR interrupt.
-#define UART_UARTMIS_TXMIS_RESET _U(0x0)
-#define UART_UARTMIS_TXMIS_BITS _U(0x00000020)
-#define UART_UARTMIS_TXMIS_MSB _U(5)
-#define UART_UARTMIS_TXMIS_LSB _U(5)
+#define UART_UARTMIS_TXMIS_RESET _u(0x0)
+#define UART_UARTMIS_TXMIS_BITS _u(0x00000020)
+#define UART_UARTMIS_TXMIS_MSB _u(5)
+#define UART_UARTMIS_TXMIS_LSB _u(5)
#define UART_UARTMIS_TXMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTMIS_RXMIS
// Description : Receive masked interrupt status. Returns the masked interrupt
// state of the UARTRXINTR interrupt.
-#define UART_UARTMIS_RXMIS_RESET _U(0x0)
-#define UART_UARTMIS_RXMIS_BITS _U(0x00000010)
-#define UART_UARTMIS_RXMIS_MSB _U(4)
-#define UART_UARTMIS_RXMIS_LSB _U(4)
+#define UART_UARTMIS_RXMIS_RESET _u(0x0)
+#define UART_UARTMIS_RXMIS_BITS _u(0x00000010)
+#define UART_UARTMIS_RXMIS_MSB _u(4)
+#define UART_UARTMIS_RXMIS_LSB _u(4)
#define UART_UARTMIS_RXMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTMIS_DSRMMIS
// Description : nUARTDSR modem masked interrupt status. Returns the masked
// interrupt state of the UARTDSRINTR interrupt.
#define UART_UARTMIS_DSRMMIS_RESET "-"
-#define UART_UARTMIS_DSRMMIS_BITS _U(0x00000008)
-#define UART_UARTMIS_DSRMMIS_MSB _U(3)
-#define UART_UARTMIS_DSRMMIS_LSB _U(3)
+#define UART_UARTMIS_DSRMMIS_BITS _u(0x00000008)
+#define UART_UARTMIS_DSRMMIS_MSB _u(3)
+#define UART_UARTMIS_DSRMMIS_LSB _u(3)
#define UART_UARTMIS_DSRMMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTMIS_DCDMMIS
// Description : nUARTDCD modem masked interrupt status. Returns the masked
// interrupt state of the UARTDCDINTR interrupt.
#define UART_UARTMIS_DCDMMIS_RESET "-"
-#define UART_UARTMIS_DCDMMIS_BITS _U(0x00000004)
-#define UART_UARTMIS_DCDMMIS_MSB _U(2)
-#define UART_UARTMIS_DCDMMIS_LSB _U(2)
+#define UART_UARTMIS_DCDMMIS_BITS _u(0x00000004)
+#define UART_UARTMIS_DCDMMIS_MSB _u(2)
+#define UART_UARTMIS_DCDMMIS_LSB _u(2)
#define UART_UARTMIS_DCDMMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTMIS_CTSMMIS
// Description : nUARTCTS modem masked interrupt status. Returns the masked
// interrupt state of the UARTCTSINTR interrupt.
#define UART_UARTMIS_CTSMMIS_RESET "-"
-#define UART_UARTMIS_CTSMMIS_BITS _U(0x00000002)
-#define UART_UARTMIS_CTSMMIS_MSB _U(1)
-#define UART_UARTMIS_CTSMMIS_LSB _U(1)
+#define UART_UARTMIS_CTSMMIS_BITS _u(0x00000002)
+#define UART_UARTMIS_CTSMMIS_MSB _u(1)
+#define UART_UARTMIS_CTSMMIS_LSB _u(1)
#define UART_UARTMIS_CTSMMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTMIS_RIMMIS
// Description : nUARTRI modem masked interrupt status. Returns the masked
// interrupt state of the UARTRIINTR interrupt.
#define UART_UARTMIS_RIMMIS_RESET "-"
-#define UART_UARTMIS_RIMMIS_BITS _U(0x00000001)
-#define UART_UARTMIS_RIMMIS_MSB _U(0)
-#define UART_UARTMIS_RIMMIS_LSB _U(0)
+#define UART_UARTMIS_RIMMIS_BITS _u(0x00000001)
+#define UART_UARTMIS_RIMMIS_MSB _u(0)
+#define UART_UARTMIS_RIMMIS_LSB _u(0)
#define UART_UARTMIS_RIMMIS_ACCESS "RO"
// =============================================================================
// Register : UART_UARTICR
// Description : Interrupt Clear Register, UARTICR
-#define UART_UARTICR_OFFSET _U(0x00000044)
-#define UART_UARTICR_BITS _U(0x000007ff)
-#define UART_UARTICR_RESET _U(0x00000000)
+#define UART_UARTICR_OFFSET _u(0x00000044)
+#define UART_UARTICR_BITS _u(0x000007ff)
+#define UART_UARTICR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : UART_UARTICR_OEIC
// Description : Overrun error interrupt clear. Clears the UARTOEINTR interrupt.
#define UART_UARTICR_OEIC_RESET "-"
-#define UART_UARTICR_OEIC_BITS _U(0x00000400)
-#define UART_UARTICR_OEIC_MSB _U(10)
-#define UART_UARTICR_OEIC_LSB _U(10)
+#define UART_UARTICR_OEIC_BITS _u(0x00000400)
+#define UART_UARTICR_OEIC_MSB _u(10)
+#define UART_UARTICR_OEIC_LSB _u(10)
#define UART_UARTICR_OEIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : UART_UARTICR_BEIC
// Description : Break error interrupt clear. Clears the UARTBEINTR interrupt.
#define UART_UARTICR_BEIC_RESET "-"
-#define UART_UARTICR_BEIC_BITS _U(0x00000200)
-#define UART_UARTICR_BEIC_MSB _U(9)
-#define UART_UARTICR_BEIC_LSB _U(9)
+#define UART_UARTICR_BEIC_BITS _u(0x00000200)
+#define UART_UARTICR_BEIC_MSB _u(9)
+#define UART_UARTICR_BEIC_LSB _u(9)
#define UART_UARTICR_BEIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : UART_UARTICR_PEIC
// Description : Parity error interrupt clear. Clears the UARTPEINTR interrupt.
#define UART_UARTICR_PEIC_RESET "-"
-#define UART_UARTICR_PEIC_BITS _U(0x00000100)
-#define UART_UARTICR_PEIC_MSB _U(8)
-#define UART_UARTICR_PEIC_LSB _U(8)
+#define UART_UARTICR_PEIC_BITS _u(0x00000100)
+#define UART_UARTICR_PEIC_MSB _u(8)
+#define UART_UARTICR_PEIC_LSB _u(8)
#define UART_UARTICR_PEIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : UART_UARTICR_FEIC
// Description : Framing error interrupt clear. Clears the UARTFEINTR interrupt.
#define UART_UARTICR_FEIC_RESET "-"
-#define UART_UARTICR_FEIC_BITS _U(0x00000080)
-#define UART_UARTICR_FEIC_MSB _U(7)
-#define UART_UARTICR_FEIC_LSB _U(7)
+#define UART_UARTICR_FEIC_BITS _u(0x00000080)
+#define UART_UARTICR_FEIC_MSB _u(7)
+#define UART_UARTICR_FEIC_LSB _u(7)
#define UART_UARTICR_FEIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : UART_UARTICR_RTIC
// Description : Receive timeout interrupt clear. Clears the UARTRTINTR
// interrupt.
#define UART_UARTICR_RTIC_RESET "-"
-#define UART_UARTICR_RTIC_BITS _U(0x00000040)
-#define UART_UARTICR_RTIC_MSB _U(6)
-#define UART_UARTICR_RTIC_LSB _U(6)
+#define UART_UARTICR_RTIC_BITS _u(0x00000040)
+#define UART_UARTICR_RTIC_MSB _u(6)
+#define UART_UARTICR_RTIC_LSB _u(6)
#define UART_UARTICR_RTIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : UART_UARTICR_TXIC
// Description : Transmit interrupt clear. Clears the UARTTXINTR interrupt.
#define UART_UARTICR_TXIC_RESET "-"
-#define UART_UARTICR_TXIC_BITS _U(0x00000020)
-#define UART_UARTICR_TXIC_MSB _U(5)
-#define UART_UARTICR_TXIC_LSB _U(5)
+#define UART_UARTICR_TXIC_BITS _u(0x00000020)
+#define UART_UARTICR_TXIC_MSB _u(5)
+#define UART_UARTICR_TXIC_LSB _u(5)
#define UART_UARTICR_TXIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : UART_UARTICR_RXIC
// Description : Receive interrupt clear. Clears the UARTRXINTR interrupt.
#define UART_UARTICR_RXIC_RESET "-"
-#define UART_UARTICR_RXIC_BITS _U(0x00000010)
-#define UART_UARTICR_RXIC_MSB _U(4)
-#define UART_UARTICR_RXIC_LSB _U(4)
+#define UART_UARTICR_RXIC_BITS _u(0x00000010)
+#define UART_UARTICR_RXIC_MSB _u(4)
+#define UART_UARTICR_RXIC_LSB _u(4)
#define UART_UARTICR_RXIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : UART_UARTICR_DSRMIC
// Description : nUARTDSR modem interrupt clear. Clears the UARTDSRINTR
// interrupt.
#define UART_UARTICR_DSRMIC_RESET "-"
-#define UART_UARTICR_DSRMIC_BITS _U(0x00000008)
-#define UART_UARTICR_DSRMIC_MSB _U(3)
-#define UART_UARTICR_DSRMIC_LSB _U(3)
+#define UART_UARTICR_DSRMIC_BITS _u(0x00000008)
+#define UART_UARTICR_DSRMIC_MSB _u(3)
+#define UART_UARTICR_DSRMIC_LSB _u(3)
#define UART_UARTICR_DSRMIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : UART_UARTICR_DCDMIC
// Description : nUARTDCD modem interrupt clear. Clears the UARTDCDINTR
// interrupt.
#define UART_UARTICR_DCDMIC_RESET "-"
-#define UART_UARTICR_DCDMIC_BITS _U(0x00000004)
-#define UART_UARTICR_DCDMIC_MSB _U(2)
-#define UART_UARTICR_DCDMIC_LSB _U(2)
+#define UART_UARTICR_DCDMIC_BITS _u(0x00000004)
+#define UART_UARTICR_DCDMIC_MSB _u(2)
+#define UART_UARTICR_DCDMIC_LSB _u(2)
#define UART_UARTICR_DCDMIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : UART_UARTICR_CTSMIC
// Description : nUARTCTS modem interrupt clear. Clears the UARTCTSINTR
// interrupt.
#define UART_UARTICR_CTSMIC_RESET "-"
-#define UART_UARTICR_CTSMIC_BITS _U(0x00000002)
-#define UART_UARTICR_CTSMIC_MSB _U(1)
-#define UART_UARTICR_CTSMIC_LSB _U(1)
+#define UART_UARTICR_CTSMIC_BITS _u(0x00000002)
+#define UART_UARTICR_CTSMIC_MSB _u(1)
+#define UART_UARTICR_CTSMIC_LSB _u(1)
#define UART_UARTICR_CTSMIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : UART_UARTICR_RIMIC
// Description : nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.
#define UART_UARTICR_RIMIC_RESET "-"
-#define UART_UARTICR_RIMIC_BITS _U(0x00000001)
-#define UART_UARTICR_RIMIC_MSB _U(0)
-#define UART_UARTICR_RIMIC_LSB _U(0)
+#define UART_UARTICR_RIMIC_BITS _u(0x00000001)
+#define UART_UARTICR_RIMIC_MSB _u(0)
+#define UART_UARTICR_RIMIC_LSB _u(0)
#define UART_UARTICR_RIMIC_ACCESS "WC"
// =============================================================================
// Register : UART_UARTDMACR
// Description : DMA Control Register, UARTDMACR
-#define UART_UARTDMACR_OFFSET _U(0x00000048)
-#define UART_UARTDMACR_BITS _U(0x00000007)
-#define UART_UARTDMACR_RESET _U(0x00000000)
+#define UART_UARTDMACR_OFFSET _u(0x00000048)
+#define UART_UARTDMACR_BITS _u(0x00000007)
+#define UART_UARTDMACR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : UART_UARTDMACR_DMAONERR
// Description : DMA on error. If this bit is set to 1, the DMA receive request
// outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the
// UART error interrupt is asserted.
-#define UART_UARTDMACR_DMAONERR_RESET _U(0x0)
-#define UART_UARTDMACR_DMAONERR_BITS _U(0x00000004)
-#define UART_UARTDMACR_DMAONERR_MSB _U(2)
-#define UART_UARTDMACR_DMAONERR_LSB _U(2)
+#define UART_UARTDMACR_DMAONERR_RESET _u(0x0)
+#define UART_UARTDMACR_DMAONERR_BITS _u(0x00000004)
+#define UART_UARTDMACR_DMAONERR_MSB _u(2)
+#define UART_UARTDMACR_DMAONERR_LSB _u(2)
#define UART_UARTDMACR_DMAONERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTDMACR_TXDMAE
// Description : Transmit DMA enable. If this bit is set to 1, DMA for the
// transmit FIFO is enabled.
-#define UART_UARTDMACR_TXDMAE_RESET _U(0x0)
-#define UART_UARTDMACR_TXDMAE_BITS _U(0x00000002)
-#define UART_UARTDMACR_TXDMAE_MSB _U(1)
-#define UART_UARTDMACR_TXDMAE_LSB _U(1)
+#define UART_UARTDMACR_TXDMAE_RESET _u(0x0)
+#define UART_UARTDMACR_TXDMAE_BITS _u(0x00000002)
+#define UART_UARTDMACR_TXDMAE_MSB _u(1)
+#define UART_UARTDMACR_TXDMAE_LSB _u(1)
#define UART_UARTDMACR_TXDMAE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : UART_UARTDMACR_RXDMAE
// Description : Receive DMA enable. If this bit is set to 1, DMA for the
// receive FIFO is enabled.
-#define UART_UARTDMACR_RXDMAE_RESET _U(0x0)
-#define UART_UARTDMACR_RXDMAE_BITS _U(0x00000001)
-#define UART_UARTDMACR_RXDMAE_MSB _U(0)
-#define UART_UARTDMACR_RXDMAE_LSB _U(0)
+#define UART_UARTDMACR_RXDMAE_RESET _u(0x0)
+#define UART_UARTDMACR_RXDMAE_BITS _u(0x00000001)
+#define UART_UARTDMACR_RXDMAE_MSB _u(0)
+#define UART_UARTDMACR_RXDMAE_LSB _u(0)
#define UART_UARTDMACR_RXDMAE_ACCESS "RW"
// =============================================================================
// Register : UART_UARTPERIPHID0
// Description : UARTPeriphID0 Register
-#define UART_UARTPERIPHID0_OFFSET _U(0x00000fe0)
-#define UART_UARTPERIPHID0_BITS _U(0x000000ff)
-#define UART_UARTPERIPHID0_RESET _U(0x00000011)
+#define UART_UARTPERIPHID0_OFFSET _u(0x00000fe0)
+#define UART_UARTPERIPHID0_BITS _u(0x000000ff)
+#define UART_UARTPERIPHID0_RESET _u(0x00000011)
// -----------------------------------------------------------------------------
// Field : UART_UARTPERIPHID0_PARTNUMBER0
// Description : These bits read back as 0x11
-#define UART_UARTPERIPHID0_PARTNUMBER0_RESET _U(0x11)
-#define UART_UARTPERIPHID0_PARTNUMBER0_BITS _U(0x000000ff)
-#define UART_UARTPERIPHID0_PARTNUMBER0_MSB _U(7)
-#define UART_UARTPERIPHID0_PARTNUMBER0_LSB _U(0)
+#define UART_UARTPERIPHID0_PARTNUMBER0_RESET _u(0x11)
+#define UART_UARTPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff)
+#define UART_UARTPERIPHID0_PARTNUMBER0_MSB _u(7)
+#define UART_UARTPERIPHID0_PARTNUMBER0_LSB _u(0)
#define UART_UARTPERIPHID0_PARTNUMBER0_ACCESS "RO"
// =============================================================================
// Register : UART_UARTPERIPHID1
// Description : UARTPeriphID1 Register
-#define UART_UARTPERIPHID1_OFFSET _U(0x00000fe4)
-#define UART_UARTPERIPHID1_BITS _U(0x000000ff)
-#define UART_UARTPERIPHID1_RESET _U(0x00000010)
+#define UART_UARTPERIPHID1_OFFSET _u(0x00000fe4)
+#define UART_UARTPERIPHID1_BITS _u(0x000000ff)
+#define UART_UARTPERIPHID1_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : UART_UARTPERIPHID1_DESIGNER0
// Description : These bits read back as 0x1
-#define UART_UARTPERIPHID1_DESIGNER0_RESET _U(0x1)
-#define UART_UARTPERIPHID1_DESIGNER0_BITS _U(0x000000f0)
-#define UART_UARTPERIPHID1_DESIGNER0_MSB _U(7)
-#define UART_UARTPERIPHID1_DESIGNER0_LSB _U(4)
+#define UART_UARTPERIPHID1_DESIGNER0_RESET _u(0x1)
+#define UART_UARTPERIPHID1_DESIGNER0_BITS _u(0x000000f0)
+#define UART_UARTPERIPHID1_DESIGNER0_MSB _u(7)
+#define UART_UARTPERIPHID1_DESIGNER0_LSB _u(4)
#define UART_UARTPERIPHID1_DESIGNER0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTPERIPHID1_PARTNUMBER1
// Description : These bits read back as 0x0
-#define UART_UARTPERIPHID1_PARTNUMBER1_RESET _U(0x0)
-#define UART_UARTPERIPHID1_PARTNUMBER1_BITS _U(0x0000000f)
-#define UART_UARTPERIPHID1_PARTNUMBER1_MSB _U(3)
-#define UART_UARTPERIPHID1_PARTNUMBER1_LSB _U(0)
+#define UART_UARTPERIPHID1_PARTNUMBER1_RESET _u(0x0)
+#define UART_UARTPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f)
+#define UART_UARTPERIPHID1_PARTNUMBER1_MSB _u(3)
+#define UART_UARTPERIPHID1_PARTNUMBER1_LSB _u(0)
#define UART_UARTPERIPHID1_PARTNUMBER1_ACCESS "RO"
// =============================================================================
// Register : UART_UARTPERIPHID2
// Description : UARTPeriphID2 Register
-#define UART_UARTPERIPHID2_OFFSET _U(0x00000fe8)
-#define UART_UARTPERIPHID2_BITS _U(0x000000ff)
-#define UART_UARTPERIPHID2_RESET _U(0x00000034)
+#define UART_UARTPERIPHID2_OFFSET _u(0x00000fe8)
+#define UART_UARTPERIPHID2_BITS _u(0x000000ff)
+#define UART_UARTPERIPHID2_RESET _u(0x00000034)
// -----------------------------------------------------------------------------
// Field : UART_UARTPERIPHID2_REVISION
// Description : This field depends on the revision of the UART: r1p0 0x0 r1p1
// 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3
-#define UART_UARTPERIPHID2_REVISION_RESET _U(0x3)
-#define UART_UARTPERIPHID2_REVISION_BITS _U(0x000000f0)
-#define UART_UARTPERIPHID2_REVISION_MSB _U(7)
-#define UART_UARTPERIPHID2_REVISION_LSB _U(4)
+#define UART_UARTPERIPHID2_REVISION_RESET _u(0x3)
+#define UART_UARTPERIPHID2_REVISION_BITS _u(0x000000f0)
+#define UART_UARTPERIPHID2_REVISION_MSB _u(7)
+#define UART_UARTPERIPHID2_REVISION_LSB _u(4)
#define UART_UARTPERIPHID2_REVISION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : UART_UARTPERIPHID2_DESIGNER1
// Description : These bits read back as 0x4
-#define UART_UARTPERIPHID2_DESIGNER1_RESET _U(0x4)
-#define UART_UARTPERIPHID2_DESIGNER1_BITS _U(0x0000000f)
-#define UART_UARTPERIPHID2_DESIGNER1_MSB _U(3)
-#define UART_UARTPERIPHID2_DESIGNER1_LSB _U(0)
+#define UART_UARTPERIPHID2_DESIGNER1_RESET _u(0x4)
+#define UART_UARTPERIPHID2_DESIGNER1_BITS _u(0x0000000f)
+#define UART_UARTPERIPHID2_DESIGNER1_MSB _u(3)
+#define UART_UARTPERIPHID2_DESIGNER1_LSB _u(0)
#define UART_UARTPERIPHID2_DESIGNER1_ACCESS "RO"
// =============================================================================
// Register : UART_UARTPERIPHID3
// Description : UARTPeriphID3 Register
-#define UART_UARTPERIPHID3_OFFSET _U(0x00000fec)
-#define UART_UARTPERIPHID3_BITS _U(0x000000ff)
-#define UART_UARTPERIPHID3_RESET _U(0x00000000)
+#define UART_UARTPERIPHID3_OFFSET _u(0x00000fec)
+#define UART_UARTPERIPHID3_BITS _u(0x000000ff)
+#define UART_UARTPERIPHID3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : UART_UARTPERIPHID3_CONFIGURATION
// Description : These bits read back as 0x00
-#define UART_UARTPERIPHID3_CONFIGURATION_RESET _U(0x00)
-#define UART_UARTPERIPHID3_CONFIGURATION_BITS _U(0x000000ff)
-#define UART_UARTPERIPHID3_CONFIGURATION_MSB _U(7)
-#define UART_UARTPERIPHID3_CONFIGURATION_LSB _U(0)
+#define UART_UARTPERIPHID3_CONFIGURATION_RESET _u(0x00)
+#define UART_UARTPERIPHID3_CONFIGURATION_BITS _u(0x000000ff)
+#define UART_UARTPERIPHID3_CONFIGURATION_MSB _u(7)
+#define UART_UARTPERIPHID3_CONFIGURATION_LSB _u(0)
#define UART_UARTPERIPHID3_CONFIGURATION_ACCESS "RO"
// =============================================================================
// Register : UART_UARTPCELLID0
// Description : UARTPCellID0 Register
-#define UART_UARTPCELLID0_OFFSET _U(0x00000ff0)
-#define UART_UARTPCELLID0_BITS _U(0x000000ff)
-#define UART_UARTPCELLID0_RESET _U(0x0000000d)
+#define UART_UARTPCELLID0_OFFSET _u(0x00000ff0)
+#define UART_UARTPCELLID0_BITS _u(0x000000ff)
+#define UART_UARTPCELLID0_RESET _u(0x0000000d)
// -----------------------------------------------------------------------------
// Field : UART_UARTPCELLID0_UARTPCELLID0
// Description : These bits read back as 0x0D
-#define UART_UARTPCELLID0_UARTPCELLID0_RESET _U(0x0d)
-#define UART_UARTPCELLID0_UARTPCELLID0_BITS _U(0x000000ff)
-#define UART_UARTPCELLID0_UARTPCELLID0_MSB _U(7)
-#define UART_UARTPCELLID0_UARTPCELLID0_LSB _U(0)
+#define UART_UARTPCELLID0_UARTPCELLID0_RESET _u(0x0d)
+#define UART_UARTPCELLID0_UARTPCELLID0_BITS _u(0x000000ff)
+#define UART_UARTPCELLID0_UARTPCELLID0_MSB _u(7)
+#define UART_UARTPCELLID0_UARTPCELLID0_LSB _u(0)
#define UART_UARTPCELLID0_UARTPCELLID0_ACCESS "RO"
// =============================================================================
// Register : UART_UARTPCELLID1
// Description : UARTPCellID1 Register
-#define UART_UARTPCELLID1_OFFSET _U(0x00000ff4)
-#define UART_UARTPCELLID1_BITS _U(0x000000ff)
-#define UART_UARTPCELLID1_RESET _U(0x000000f0)
+#define UART_UARTPCELLID1_OFFSET _u(0x00000ff4)
+#define UART_UARTPCELLID1_BITS _u(0x000000ff)
+#define UART_UARTPCELLID1_RESET _u(0x000000f0)
// -----------------------------------------------------------------------------
// Field : UART_UARTPCELLID1_UARTPCELLID1
// Description : These bits read back as 0xF0
-#define UART_UARTPCELLID1_UARTPCELLID1_RESET _U(0xf0)
-#define UART_UARTPCELLID1_UARTPCELLID1_BITS _U(0x000000ff)
-#define UART_UARTPCELLID1_UARTPCELLID1_MSB _U(7)
-#define UART_UARTPCELLID1_UARTPCELLID1_LSB _U(0)
+#define UART_UARTPCELLID1_UARTPCELLID1_RESET _u(0xf0)
+#define UART_UARTPCELLID1_UARTPCELLID1_BITS _u(0x000000ff)
+#define UART_UARTPCELLID1_UARTPCELLID1_MSB _u(7)
+#define UART_UARTPCELLID1_UARTPCELLID1_LSB _u(0)
#define UART_UARTPCELLID1_UARTPCELLID1_ACCESS "RO"
// =============================================================================
// Register : UART_UARTPCELLID2
// Description : UARTPCellID2 Register
-#define UART_UARTPCELLID2_OFFSET _U(0x00000ff8)
-#define UART_UARTPCELLID2_BITS _U(0x000000ff)
-#define UART_UARTPCELLID2_RESET _U(0x00000005)
+#define UART_UARTPCELLID2_OFFSET _u(0x00000ff8)
+#define UART_UARTPCELLID2_BITS _u(0x000000ff)
+#define UART_UARTPCELLID2_RESET _u(0x00000005)
// -----------------------------------------------------------------------------
// Field : UART_UARTPCELLID2_UARTPCELLID2
// Description : These bits read back as 0x05
-#define UART_UARTPCELLID2_UARTPCELLID2_RESET _U(0x05)
-#define UART_UARTPCELLID2_UARTPCELLID2_BITS _U(0x000000ff)
-#define UART_UARTPCELLID2_UARTPCELLID2_MSB _U(7)
-#define UART_UARTPCELLID2_UARTPCELLID2_LSB _U(0)
+#define UART_UARTPCELLID2_UARTPCELLID2_RESET _u(0x05)
+#define UART_UARTPCELLID2_UARTPCELLID2_BITS _u(0x000000ff)
+#define UART_UARTPCELLID2_UARTPCELLID2_MSB _u(7)
+#define UART_UARTPCELLID2_UARTPCELLID2_LSB _u(0)
#define UART_UARTPCELLID2_UARTPCELLID2_ACCESS "RO"
// =============================================================================
// Register : UART_UARTPCELLID3
// Description : UARTPCellID3 Register
-#define UART_UARTPCELLID3_OFFSET _U(0x00000ffc)
-#define UART_UARTPCELLID3_BITS _U(0x000000ff)
-#define UART_UARTPCELLID3_RESET _U(0x000000b1)
+#define UART_UARTPCELLID3_OFFSET _u(0x00000ffc)
+#define UART_UARTPCELLID3_BITS _u(0x000000ff)
+#define UART_UARTPCELLID3_RESET _u(0x000000b1)
// -----------------------------------------------------------------------------
// Field : UART_UARTPCELLID3_UARTPCELLID3
// Description : These bits read back as 0xB1
-#define UART_UARTPCELLID3_UARTPCELLID3_RESET _U(0xb1)
-#define UART_UARTPCELLID3_UARTPCELLID3_BITS _U(0x000000ff)
-#define UART_UARTPCELLID3_UARTPCELLID3_MSB _U(7)
-#define UART_UARTPCELLID3_UARTPCELLID3_LSB _U(0)
+#define UART_UARTPCELLID3_UARTPCELLID3_RESET _u(0xb1)
+#define UART_UARTPCELLID3_UARTPCELLID3_BITS _u(0x000000ff)
+#define UART_UARTPCELLID3_UARTPCELLID3_MSB _u(7)
+#define UART_UARTPCELLID3_UARTPCELLID3_LSB _u(0)
#define UART_UARTPCELLID3_UARTPCELLID3_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_UART_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/usb.h b/src/rp2040/hardware_regs/include/hardware/regs/usb.h
index a82510e..5461c29 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/usb.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/usb.h
@@ -14,881 +14,881 @@
// =============================================================================
// Register : USB_ADDR_ENDP
// Description : Device address and endpoint control
-#define USB_ADDR_ENDP_OFFSET _U(0x00000000)
-#define USB_ADDR_ENDP_BITS _U(0x000f007f)
-#define USB_ADDR_ENDP_RESET _U(0x00000000)
+#define USB_ADDR_ENDP_OFFSET _u(0x00000000)
+#define USB_ADDR_ENDP_BITS _u(0x000f007f)
+#define USB_ADDR_ENDP_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP_ENDPOINT
// Description : Device endpoint to send data to. Only valid for HOST mode.
-#define USB_ADDR_ENDP_ENDPOINT_RESET _U(0x0)
-#define USB_ADDR_ENDP_ENDPOINT_BITS _U(0x000f0000)
-#define USB_ADDR_ENDP_ENDPOINT_MSB _U(19)
-#define USB_ADDR_ENDP_ENDPOINT_LSB _U(16)
+#define USB_ADDR_ENDP_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP_ENDPOINT_LSB _u(16)
#define USB_ADDR_ENDP_ENDPOINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP_ADDRESS
// Description : In device mode, the address that the device should respond to.
// Set in response to a SET_ADDR setup packet from the host. In
// host mode set to the address of the device to communicate with.
-#define USB_ADDR_ENDP_ADDRESS_RESET _U(0x00)
-#define USB_ADDR_ENDP_ADDRESS_BITS _U(0x0000007f)
-#define USB_ADDR_ENDP_ADDRESS_MSB _U(6)
-#define USB_ADDR_ENDP_ADDRESS_LSB _U(0)
+#define USB_ADDR_ENDP_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP_ADDRESS_LSB _u(0)
#define USB_ADDR_ENDP_ADDRESS_ACCESS "RW"
// =============================================================================
// Register : USB_ADDR_ENDP1
// Description : Interrupt endpoint 1. Only valid for HOST mode.
-#define USB_ADDR_ENDP1_OFFSET _U(0x00000004)
-#define USB_ADDR_ENDP1_BITS _U(0x060f007f)
-#define USB_ADDR_ENDP1_RESET _U(0x00000000)
+#define USB_ADDR_ENDP1_OFFSET _u(0x00000004)
+#define USB_ADDR_ENDP1_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP1_INTEP_PREAMBLE
// Description : Interrupt EP requires preamble (is a low speed device on a full
// speed hub)
-#define USB_ADDR_ENDP1_INTEP_PREAMBLE_RESET _U(0x0)
-#define USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS _U(0x04000000)
-#define USB_ADDR_ENDP1_INTEP_PREAMBLE_MSB _U(26)
-#define USB_ADDR_ENDP1_INTEP_PREAMBLE_LSB _U(26)
+#define USB_ADDR_ENDP1_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP1_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP1_INTEP_PREAMBLE_LSB _u(26)
#define USB_ADDR_ENDP1_INTEP_PREAMBLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP1_INTEP_DIR
// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP1_INTEP_DIR_RESET _U(0x0)
-#define USB_ADDR_ENDP1_INTEP_DIR_BITS _U(0x02000000)
-#define USB_ADDR_ENDP1_INTEP_DIR_MSB _U(25)
-#define USB_ADDR_ENDP1_INTEP_DIR_LSB _U(25)
+#define USB_ADDR_ENDP1_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP1_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP1_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP1_INTEP_DIR_LSB _u(25)
#define USB_ADDR_ENDP1_INTEP_DIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP1_ENDPOINT
// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP1_ENDPOINT_RESET _U(0x0)
-#define USB_ADDR_ENDP1_ENDPOINT_BITS _U(0x000f0000)
-#define USB_ADDR_ENDP1_ENDPOINT_MSB _U(19)
-#define USB_ADDR_ENDP1_ENDPOINT_LSB _U(16)
+#define USB_ADDR_ENDP1_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP1_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP1_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP1_ENDPOINT_LSB _u(16)
#define USB_ADDR_ENDP1_ENDPOINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP1_ADDRESS
// Description : Device address
-#define USB_ADDR_ENDP1_ADDRESS_RESET _U(0x00)
-#define USB_ADDR_ENDP1_ADDRESS_BITS _U(0x0000007f)
-#define USB_ADDR_ENDP1_ADDRESS_MSB _U(6)
-#define USB_ADDR_ENDP1_ADDRESS_LSB _U(0)
+#define USB_ADDR_ENDP1_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP1_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP1_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP1_ADDRESS_LSB _u(0)
#define USB_ADDR_ENDP1_ADDRESS_ACCESS "RW"
// =============================================================================
// Register : USB_ADDR_ENDP2
// Description : Interrupt endpoint 2. Only valid for HOST mode.
-#define USB_ADDR_ENDP2_OFFSET _U(0x00000008)
-#define USB_ADDR_ENDP2_BITS _U(0x060f007f)
-#define USB_ADDR_ENDP2_RESET _U(0x00000000)
+#define USB_ADDR_ENDP2_OFFSET _u(0x00000008)
+#define USB_ADDR_ENDP2_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP2_INTEP_PREAMBLE
// Description : Interrupt EP requires preamble (is a low speed device on a full
// speed hub)
-#define USB_ADDR_ENDP2_INTEP_PREAMBLE_RESET _U(0x0)
-#define USB_ADDR_ENDP2_INTEP_PREAMBLE_BITS _U(0x04000000)
-#define USB_ADDR_ENDP2_INTEP_PREAMBLE_MSB _U(26)
-#define USB_ADDR_ENDP2_INTEP_PREAMBLE_LSB _U(26)
+#define USB_ADDR_ENDP2_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP2_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP2_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP2_INTEP_PREAMBLE_LSB _u(26)
#define USB_ADDR_ENDP2_INTEP_PREAMBLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP2_INTEP_DIR
// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP2_INTEP_DIR_RESET _U(0x0)
-#define USB_ADDR_ENDP2_INTEP_DIR_BITS _U(0x02000000)
-#define USB_ADDR_ENDP2_INTEP_DIR_MSB _U(25)
-#define USB_ADDR_ENDP2_INTEP_DIR_LSB _U(25)
+#define USB_ADDR_ENDP2_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP2_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP2_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP2_INTEP_DIR_LSB _u(25)
#define USB_ADDR_ENDP2_INTEP_DIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP2_ENDPOINT
// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP2_ENDPOINT_RESET _U(0x0)
-#define USB_ADDR_ENDP2_ENDPOINT_BITS _U(0x000f0000)
-#define USB_ADDR_ENDP2_ENDPOINT_MSB _U(19)
-#define USB_ADDR_ENDP2_ENDPOINT_LSB _U(16)
+#define USB_ADDR_ENDP2_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP2_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP2_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP2_ENDPOINT_LSB _u(16)
#define USB_ADDR_ENDP2_ENDPOINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP2_ADDRESS
// Description : Device address
-#define USB_ADDR_ENDP2_ADDRESS_RESET _U(0x00)
-#define USB_ADDR_ENDP2_ADDRESS_BITS _U(0x0000007f)
-#define USB_ADDR_ENDP2_ADDRESS_MSB _U(6)
-#define USB_ADDR_ENDP2_ADDRESS_LSB _U(0)
+#define USB_ADDR_ENDP2_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP2_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP2_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP2_ADDRESS_LSB _u(0)
#define USB_ADDR_ENDP2_ADDRESS_ACCESS "RW"
// =============================================================================
// Register : USB_ADDR_ENDP3
// Description : Interrupt endpoint 3. Only valid for HOST mode.
-#define USB_ADDR_ENDP3_OFFSET _U(0x0000000c)
-#define USB_ADDR_ENDP3_BITS _U(0x060f007f)
-#define USB_ADDR_ENDP3_RESET _U(0x00000000)
+#define USB_ADDR_ENDP3_OFFSET _u(0x0000000c)
+#define USB_ADDR_ENDP3_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP3_INTEP_PREAMBLE
// Description : Interrupt EP requires preamble (is a low speed device on a full
// speed hub)
-#define USB_ADDR_ENDP3_INTEP_PREAMBLE_RESET _U(0x0)
-#define USB_ADDR_ENDP3_INTEP_PREAMBLE_BITS _U(0x04000000)
-#define USB_ADDR_ENDP3_INTEP_PREAMBLE_MSB _U(26)
-#define USB_ADDR_ENDP3_INTEP_PREAMBLE_LSB _U(26)
+#define USB_ADDR_ENDP3_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP3_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP3_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP3_INTEP_PREAMBLE_LSB _u(26)
#define USB_ADDR_ENDP3_INTEP_PREAMBLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP3_INTEP_DIR
// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP3_INTEP_DIR_RESET _U(0x0)
-#define USB_ADDR_ENDP3_INTEP_DIR_BITS _U(0x02000000)
-#define USB_ADDR_ENDP3_INTEP_DIR_MSB _U(25)
-#define USB_ADDR_ENDP3_INTEP_DIR_LSB _U(25)
+#define USB_ADDR_ENDP3_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP3_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP3_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP3_INTEP_DIR_LSB _u(25)
#define USB_ADDR_ENDP3_INTEP_DIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP3_ENDPOINT
// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP3_ENDPOINT_RESET _U(0x0)
-#define USB_ADDR_ENDP3_ENDPOINT_BITS _U(0x000f0000)
-#define USB_ADDR_ENDP3_ENDPOINT_MSB _U(19)
-#define USB_ADDR_ENDP3_ENDPOINT_LSB _U(16)
+#define USB_ADDR_ENDP3_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP3_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP3_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP3_ENDPOINT_LSB _u(16)
#define USB_ADDR_ENDP3_ENDPOINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP3_ADDRESS
// Description : Device address
-#define USB_ADDR_ENDP3_ADDRESS_RESET _U(0x00)
-#define USB_ADDR_ENDP3_ADDRESS_BITS _U(0x0000007f)
-#define USB_ADDR_ENDP3_ADDRESS_MSB _U(6)
-#define USB_ADDR_ENDP3_ADDRESS_LSB _U(0)
+#define USB_ADDR_ENDP3_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP3_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP3_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP3_ADDRESS_LSB _u(0)
#define USB_ADDR_ENDP3_ADDRESS_ACCESS "RW"
// =============================================================================
// Register : USB_ADDR_ENDP4
// Description : Interrupt endpoint 4. Only valid for HOST mode.
-#define USB_ADDR_ENDP4_OFFSET _U(0x00000010)
-#define USB_ADDR_ENDP4_BITS _U(0x060f007f)
-#define USB_ADDR_ENDP4_RESET _U(0x00000000)
+#define USB_ADDR_ENDP4_OFFSET _u(0x00000010)
+#define USB_ADDR_ENDP4_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP4_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP4_INTEP_PREAMBLE
// Description : Interrupt EP requires preamble (is a low speed device on a full
// speed hub)
-#define USB_ADDR_ENDP4_INTEP_PREAMBLE_RESET _U(0x0)
-#define USB_ADDR_ENDP4_INTEP_PREAMBLE_BITS _U(0x04000000)
-#define USB_ADDR_ENDP4_INTEP_PREAMBLE_MSB _U(26)
-#define USB_ADDR_ENDP4_INTEP_PREAMBLE_LSB _U(26)
+#define USB_ADDR_ENDP4_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP4_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP4_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP4_INTEP_PREAMBLE_LSB _u(26)
#define USB_ADDR_ENDP4_INTEP_PREAMBLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP4_INTEP_DIR
// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP4_INTEP_DIR_RESET _U(0x0)
-#define USB_ADDR_ENDP4_INTEP_DIR_BITS _U(0x02000000)
-#define USB_ADDR_ENDP4_INTEP_DIR_MSB _U(25)
-#define USB_ADDR_ENDP4_INTEP_DIR_LSB _U(25)
+#define USB_ADDR_ENDP4_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP4_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP4_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP4_INTEP_DIR_LSB _u(25)
#define USB_ADDR_ENDP4_INTEP_DIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP4_ENDPOINT
// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP4_ENDPOINT_RESET _U(0x0)
-#define USB_ADDR_ENDP4_ENDPOINT_BITS _U(0x000f0000)
-#define USB_ADDR_ENDP4_ENDPOINT_MSB _U(19)
-#define USB_ADDR_ENDP4_ENDPOINT_LSB _U(16)
+#define USB_ADDR_ENDP4_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP4_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP4_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP4_ENDPOINT_LSB _u(16)
#define USB_ADDR_ENDP4_ENDPOINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP4_ADDRESS
// Description : Device address
-#define USB_ADDR_ENDP4_ADDRESS_RESET _U(0x00)
-#define USB_ADDR_ENDP4_ADDRESS_BITS _U(0x0000007f)
-#define USB_ADDR_ENDP4_ADDRESS_MSB _U(6)
-#define USB_ADDR_ENDP4_ADDRESS_LSB _U(0)
+#define USB_ADDR_ENDP4_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP4_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP4_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP4_ADDRESS_LSB _u(0)
#define USB_ADDR_ENDP4_ADDRESS_ACCESS "RW"
// =============================================================================
// Register : USB_ADDR_ENDP5
// Description : Interrupt endpoint 5. Only valid for HOST mode.
-#define USB_ADDR_ENDP5_OFFSET _U(0x00000014)
-#define USB_ADDR_ENDP5_BITS _U(0x060f007f)
-#define USB_ADDR_ENDP5_RESET _U(0x00000000)
+#define USB_ADDR_ENDP5_OFFSET _u(0x00000014)
+#define USB_ADDR_ENDP5_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP5_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP5_INTEP_PREAMBLE
// Description : Interrupt EP requires preamble (is a low speed device on a full
// speed hub)
-#define USB_ADDR_ENDP5_INTEP_PREAMBLE_RESET _U(0x0)
-#define USB_ADDR_ENDP5_INTEP_PREAMBLE_BITS _U(0x04000000)
-#define USB_ADDR_ENDP5_INTEP_PREAMBLE_MSB _U(26)
-#define USB_ADDR_ENDP5_INTEP_PREAMBLE_LSB _U(26)
+#define USB_ADDR_ENDP5_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP5_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP5_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP5_INTEP_PREAMBLE_LSB _u(26)
#define USB_ADDR_ENDP5_INTEP_PREAMBLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP5_INTEP_DIR
// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP5_INTEP_DIR_RESET _U(0x0)
-#define USB_ADDR_ENDP5_INTEP_DIR_BITS _U(0x02000000)
-#define USB_ADDR_ENDP5_INTEP_DIR_MSB _U(25)
-#define USB_ADDR_ENDP5_INTEP_DIR_LSB _U(25)
+#define USB_ADDR_ENDP5_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP5_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP5_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP5_INTEP_DIR_LSB _u(25)
#define USB_ADDR_ENDP5_INTEP_DIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP5_ENDPOINT
// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP5_ENDPOINT_RESET _U(0x0)
-#define USB_ADDR_ENDP5_ENDPOINT_BITS _U(0x000f0000)
-#define USB_ADDR_ENDP5_ENDPOINT_MSB _U(19)
-#define USB_ADDR_ENDP5_ENDPOINT_LSB _U(16)
+#define USB_ADDR_ENDP5_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP5_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP5_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP5_ENDPOINT_LSB _u(16)
#define USB_ADDR_ENDP5_ENDPOINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP5_ADDRESS
// Description : Device address
-#define USB_ADDR_ENDP5_ADDRESS_RESET _U(0x00)
-#define USB_ADDR_ENDP5_ADDRESS_BITS _U(0x0000007f)
-#define USB_ADDR_ENDP5_ADDRESS_MSB _U(6)
-#define USB_ADDR_ENDP5_ADDRESS_LSB _U(0)
+#define USB_ADDR_ENDP5_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP5_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP5_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP5_ADDRESS_LSB _u(0)
#define USB_ADDR_ENDP5_ADDRESS_ACCESS "RW"
// =============================================================================
// Register : USB_ADDR_ENDP6
// Description : Interrupt endpoint 6. Only valid for HOST mode.
-#define USB_ADDR_ENDP6_OFFSET _U(0x00000018)
-#define USB_ADDR_ENDP6_BITS _U(0x060f007f)
-#define USB_ADDR_ENDP6_RESET _U(0x00000000)
+#define USB_ADDR_ENDP6_OFFSET _u(0x00000018)
+#define USB_ADDR_ENDP6_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP6_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP6_INTEP_PREAMBLE
// Description : Interrupt EP requires preamble (is a low speed device on a full
// speed hub)
-#define USB_ADDR_ENDP6_INTEP_PREAMBLE_RESET _U(0x0)
-#define USB_ADDR_ENDP6_INTEP_PREAMBLE_BITS _U(0x04000000)
-#define USB_ADDR_ENDP6_INTEP_PREAMBLE_MSB _U(26)
-#define USB_ADDR_ENDP6_INTEP_PREAMBLE_LSB _U(26)
+#define USB_ADDR_ENDP6_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP6_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP6_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP6_INTEP_PREAMBLE_LSB _u(26)
#define USB_ADDR_ENDP6_INTEP_PREAMBLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP6_INTEP_DIR
// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP6_INTEP_DIR_RESET _U(0x0)
-#define USB_ADDR_ENDP6_INTEP_DIR_BITS _U(0x02000000)
-#define USB_ADDR_ENDP6_INTEP_DIR_MSB _U(25)
-#define USB_ADDR_ENDP6_INTEP_DIR_LSB _U(25)
+#define USB_ADDR_ENDP6_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP6_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP6_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP6_INTEP_DIR_LSB _u(25)
#define USB_ADDR_ENDP6_INTEP_DIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP6_ENDPOINT
// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP6_ENDPOINT_RESET _U(0x0)
-#define USB_ADDR_ENDP6_ENDPOINT_BITS _U(0x000f0000)
-#define USB_ADDR_ENDP6_ENDPOINT_MSB _U(19)
-#define USB_ADDR_ENDP6_ENDPOINT_LSB _U(16)
+#define USB_ADDR_ENDP6_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP6_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP6_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP6_ENDPOINT_LSB _u(16)
#define USB_ADDR_ENDP6_ENDPOINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP6_ADDRESS
// Description : Device address
-#define USB_ADDR_ENDP6_ADDRESS_RESET _U(0x00)
-#define USB_ADDR_ENDP6_ADDRESS_BITS _U(0x0000007f)
-#define USB_ADDR_ENDP6_ADDRESS_MSB _U(6)
-#define USB_ADDR_ENDP6_ADDRESS_LSB _U(0)
+#define USB_ADDR_ENDP6_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP6_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP6_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP6_ADDRESS_LSB _u(0)
#define USB_ADDR_ENDP6_ADDRESS_ACCESS "RW"
// =============================================================================
// Register : USB_ADDR_ENDP7
// Description : Interrupt endpoint 7. Only valid for HOST mode.
-#define USB_ADDR_ENDP7_OFFSET _U(0x0000001c)
-#define USB_ADDR_ENDP7_BITS _U(0x060f007f)
-#define USB_ADDR_ENDP7_RESET _U(0x00000000)
+#define USB_ADDR_ENDP7_OFFSET _u(0x0000001c)
+#define USB_ADDR_ENDP7_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP7_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP7_INTEP_PREAMBLE
// Description : Interrupt EP requires preamble (is a low speed device on a full
// speed hub)
-#define USB_ADDR_ENDP7_INTEP_PREAMBLE_RESET _U(0x0)
-#define USB_ADDR_ENDP7_INTEP_PREAMBLE_BITS _U(0x04000000)
-#define USB_ADDR_ENDP7_INTEP_PREAMBLE_MSB _U(26)
-#define USB_ADDR_ENDP7_INTEP_PREAMBLE_LSB _U(26)
+#define USB_ADDR_ENDP7_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP7_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP7_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP7_INTEP_PREAMBLE_LSB _u(26)
#define USB_ADDR_ENDP7_INTEP_PREAMBLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP7_INTEP_DIR
// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP7_INTEP_DIR_RESET _U(0x0)
-#define USB_ADDR_ENDP7_INTEP_DIR_BITS _U(0x02000000)
-#define USB_ADDR_ENDP7_INTEP_DIR_MSB _U(25)
-#define USB_ADDR_ENDP7_INTEP_DIR_LSB _U(25)
+#define USB_ADDR_ENDP7_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP7_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP7_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP7_INTEP_DIR_LSB _u(25)
#define USB_ADDR_ENDP7_INTEP_DIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP7_ENDPOINT
// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP7_ENDPOINT_RESET _U(0x0)
-#define USB_ADDR_ENDP7_ENDPOINT_BITS _U(0x000f0000)
-#define USB_ADDR_ENDP7_ENDPOINT_MSB _U(19)
-#define USB_ADDR_ENDP7_ENDPOINT_LSB _U(16)
+#define USB_ADDR_ENDP7_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP7_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP7_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP7_ENDPOINT_LSB _u(16)
#define USB_ADDR_ENDP7_ENDPOINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP7_ADDRESS
// Description : Device address
-#define USB_ADDR_ENDP7_ADDRESS_RESET _U(0x00)
-#define USB_ADDR_ENDP7_ADDRESS_BITS _U(0x0000007f)
-#define USB_ADDR_ENDP7_ADDRESS_MSB _U(6)
-#define USB_ADDR_ENDP7_ADDRESS_LSB _U(0)
+#define USB_ADDR_ENDP7_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP7_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP7_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP7_ADDRESS_LSB _u(0)
#define USB_ADDR_ENDP7_ADDRESS_ACCESS "RW"
// =============================================================================
// Register : USB_ADDR_ENDP8
// Description : Interrupt endpoint 8. Only valid for HOST mode.
-#define USB_ADDR_ENDP8_OFFSET _U(0x00000020)
-#define USB_ADDR_ENDP8_BITS _U(0x060f007f)
-#define USB_ADDR_ENDP8_RESET _U(0x00000000)
+#define USB_ADDR_ENDP8_OFFSET _u(0x00000020)
+#define USB_ADDR_ENDP8_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP8_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP8_INTEP_PREAMBLE
// Description : Interrupt EP requires preamble (is a low speed device on a full
// speed hub)
-#define USB_ADDR_ENDP8_INTEP_PREAMBLE_RESET _U(0x0)
-#define USB_ADDR_ENDP8_INTEP_PREAMBLE_BITS _U(0x04000000)
-#define USB_ADDR_ENDP8_INTEP_PREAMBLE_MSB _U(26)
-#define USB_ADDR_ENDP8_INTEP_PREAMBLE_LSB _U(26)
+#define USB_ADDR_ENDP8_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP8_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP8_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP8_INTEP_PREAMBLE_LSB _u(26)
#define USB_ADDR_ENDP8_INTEP_PREAMBLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP8_INTEP_DIR
// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP8_INTEP_DIR_RESET _U(0x0)
-#define USB_ADDR_ENDP8_INTEP_DIR_BITS _U(0x02000000)
-#define USB_ADDR_ENDP8_INTEP_DIR_MSB _U(25)
-#define USB_ADDR_ENDP8_INTEP_DIR_LSB _U(25)
+#define USB_ADDR_ENDP8_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP8_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP8_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP8_INTEP_DIR_LSB _u(25)
#define USB_ADDR_ENDP8_INTEP_DIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP8_ENDPOINT
// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP8_ENDPOINT_RESET _U(0x0)
-#define USB_ADDR_ENDP8_ENDPOINT_BITS _U(0x000f0000)
-#define USB_ADDR_ENDP8_ENDPOINT_MSB _U(19)
-#define USB_ADDR_ENDP8_ENDPOINT_LSB _U(16)
+#define USB_ADDR_ENDP8_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP8_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP8_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP8_ENDPOINT_LSB _u(16)
#define USB_ADDR_ENDP8_ENDPOINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP8_ADDRESS
// Description : Device address
-#define USB_ADDR_ENDP8_ADDRESS_RESET _U(0x00)
-#define USB_ADDR_ENDP8_ADDRESS_BITS _U(0x0000007f)
-#define USB_ADDR_ENDP8_ADDRESS_MSB _U(6)
-#define USB_ADDR_ENDP8_ADDRESS_LSB _U(0)
+#define USB_ADDR_ENDP8_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP8_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP8_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP8_ADDRESS_LSB _u(0)
#define USB_ADDR_ENDP8_ADDRESS_ACCESS "RW"
// =============================================================================
// Register : USB_ADDR_ENDP9
// Description : Interrupt endpoint 9. Only valid for HOST mode.
-#define USB_ADDR_ENDP9_OFFSET _U(0x00000024)
-#define USB_ADDR_ENDP9_BITS _U(0x060f007f)
-#define USB_ADDR_ENDP9_RESET _U(0x00000000)
+#define USB_ADDR_ENDP9_OFFSET _u(0x00000024)
+#define USB_ADDR_ENDP9_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP9_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP9_INTEP_PREAMBLE
// Description : Interrupt EP requires preamble (is a low speed device on a full
// speed hub)
-#define USB_ADDR_ENDP9_INTEP_PREAMBLE_RESET _U(0x0)
-#define USB_ADDR_ENDP9_INTEP_PREAMBLE_BITS _U(0x04000000)
-#define USB_ADDR_ENDP9_INTEP_PREAMBLE_MSB _U(26)
-#define USB_ADDR_ENDP9_INTEP_PREAMBLE_LSB _U(26)
+#define USB_ADDR_ENDP9_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP9_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP9_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP9_INTEP_PREAMBLE_LSB _u(26)
#define USB_ADDR_ENDP9_INTEP_PREAMBLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP9_INTEP_DIR
// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP9_INTEP_DIR_RESET _U(0x0)
-#define USB_ADDR_ENDP9_INTEP_DIR_BITS _U(0x02000000)
-#define USB_ADDR_ENDP9_INTEP_DIR_MSB _U(25)
-#define USB_ADDR_ENDP9_INTEP_DIR_LSB _U(25)
+#define USB_ADDR_ENDP9_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP9_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP9_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP9_INTEP_DIR_LSB _u(25)
#define USB_ADDR_ENDP9_INTEP_DIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP9_ENDPOINT
// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP9_ENDPOINT_RESET _U(0x0)
-#define USB_ADDR_ENDP9_ENDPOINT_BITS _U(0x000f0000)
-#define USB_ADDR_ENDP9_ENDPOINT_MSB _U(19)
-#define USB_ADDR_ENDP9_ENDPOINT_LSB _U(16)
+#define USB_ADDR_ENDP9_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP9_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP9_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP9_ENDPOINT_LSB _u(16)
#define USB_ADDR_ENDP9_ENDPOINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP9_ADDRESS
// Description : Device address
-#define USB_ADDR_ENDP9_ADDRESS_RESET _U(0x00)
-#define USB_ADDR_ENDP9_ADDRESS_BITS _U(0x0000007f)
-#define USB_ADDR_ENDP9_ADDRESS_MSB _U(6)
-#define USB_ADDR_ENDP9_ADDRESS_LSB _U(0)
+#define USB_ADDR_ENDP9_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP9_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP9_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP9_ADDRESS_LSB _u(0)
#define USB_ADDR_ENDP9_ADDRESS_ACCESS "RW"
// =============================================================================
// Register : USB_ADDR_ENDP10
// Description : Interrupt endpoint 10. Only valid for HOST mode.
-#define USB_ADDR_ENDP10_OFFSET _U(0x00000028)
-#define USB_ADDR_ENDP10_BITS _U(0x060f007f)
-#define USB_ADDR_ENDP10_RESET _U(0x00000000)
+#define USB_ADDR_ENDP10_OFFSET _u(0x00000028)
+#define USB_ADDR_ENDP10_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP10_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP10_INTEP_PREAMBLE
// Description : Interrupt EP requires preamble (is a low speed device on a full
// speed hub)
-#define USB_ADDR_ENDP10_INTEP_PREAMBLE_RESET _U(0x0)
-#define USB_ADDR_ENDP10_INTEP_PREAMBLE_BITS _U(0x04000000)
-#define USB_ADDR_ENDP10_INTEP_PREAMBLE_MSB _U(26)
-#define USB_ADDR_ENDP10_INTEP_PREAMBLE_LSB _U(26)
+#define USB_ADDR_ENDP10_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP10_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP10_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP10_INTEP_PREAMBLE_LSB _u(26)
#define USB_ADDR_ENDP10_INTEP_PREAMBLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP10_INTEP_DIR
// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP10_INTEP_DIR_RESET _U(0x0)
-#define USB_ADDR_ENDP10_INTEP_DIR_BITS _U(0x02000000)
-#define USB_ADDR_ENDP10_INTEP_DIR_MSB _U(25)
-#define USB_ADDR_ENDP10_INTEP_DIR_LSB _U(25)
+#define USB_ADDR_ENDP10_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP10_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP10_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP10_INTEP_DIR_LSB _u(25)
#define USB_ADDR_ENDP10_INTEP_DIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP10_ENDPOINT
// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP10_ENDPOINT_RESET _U(0x0)
-#define USB_ADDR_ENDP10_ENDPOINT_BITS _U(0x000f0000)
-#define USB_ADDR_ENDP10_ENDPOINT_MSB _U(19)
-#define USB_ADDR_ENDP10_ENDPOINT_LSB _U(16)
+#define USB_ADDR_ENDP10_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP10_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP10_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP10_ENDPOINT_LSB _u(16)
#define USB_ADDR_ENDP10_ENDPOINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP10_ADDRESS
// Description : Device address
-#define USB_ADDR_ENDP10_ADDRESS_RESET _U(0x00)
-#define USB_ADDR_ENDP10_ADDRESS_BITS _U(0x0000007f)
-#define USB_ADDR_ENDP10_ADDRESS_MSB _U(6)
-#define USB_ADDR_ENDP10_ADDRESS_LSB _U(0)
+#define USB_ADDR_ENDP10_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP10_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP10_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP10_ADDRESS_LSB _u(0)
#define USB_ADDR_ENDP10_ADDRESS_ACCESS "RW"
// =============================================================================
// Register : USB_ADDR_ENDP11
// Description : Interrupt endpoint 11. Only valid for HOST mode.
-#define USB_ADDR_ENDP11_OFFSET _U(0x0000002c)
-#define USB_ADDR_ENDP11_BITS _U(0x060f007f)
-#define USB_ADDR_ENDP11_RESET _U(0x00000000)
+#define USB_ADDR_ENDP11_OFFSET _u(0x0000002c)
+#define USB_ADDR_ENDP11_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP11_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP11_INTEP_PREAMBLE
// Description : Interrupt EP requires preamble (is a low speed device on a full
// speed hub)
-#define USB_ADDR_ENDP11_INTEP_PREAMBLE_RESET _U(0x0)
-#define USB_ADDR_ENDP11_INTEP_PREAMBLE_BITS _U(0x04000000)
-#define USB_ADDR_ENDP11_INTEP_PREAMBLE_MSB _U(26)
-#define USB_ADDR_ENDP11_INTEP_PREAMBLE_LSB _U(26)
+#define USB_ADDR_ENDP11_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP11_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP11_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP11_INTEP_PREAMBLE_LSB _u(26)
#define USB_ADDR_ENDP11_INTEP_PREAMBLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP11_INTEP_DIR
// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP11_INTEP_DIR_RESET _U(0x0)
-#define USB_ADDR_ENDP11_INTEP_DIR_BITS _U(0x02000000)
-#define USB_ADDR_ENDP11_INTEP_DIR_MSB _U(25)
-#define USB_ADDR_ENDP11_INTEP_DIR_LSB _U(25)
+#define USB_ADDR_ENDP11_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP11_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP11_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP11_INTEP_DIR_LSB _u(25)
#define USB_ADDR_ENDP11_INTEP_DIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP11_ENDPOINT
// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP11_ENDPOINT_RESET _U(0x0)
-#define USB_ADDR_ENDP11_ENDPOINT_BITS _U(0x000f0000)
-#define USB_ADDR_ENDP11_ENDPOINT_MSB _U(19)
-#define USB_ADDR_ENDP11_ENDPOINT_LSB _U(16)
+#define USB_ADDR_ENDP11_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP11_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP11_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP11_ENDPOINT_LSB _u(16)
#define USB_ADDR_ENDP11_ENDPOINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP11_ADDRESS
// Description : Device address
-#define USB_ADDR_ENDP11_ADDRESS_RESET _U(0x00)
-#define USB_ADDR_ENDP11_ADDRESS_BITS _U(0x0000007f)
-#define USB_ADDR_ENDP11_ADDRESS_MSB _U(6)
-#define USB_ADDR_ENDP11_ADDRESS_LSB _U(0)
+#define USB_ADDR_ENDP11_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP11_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP11_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP11_ADDRESS_LSB _u(0)
#define USB_ADDR_ENDP11_ADDRESS_ACCESS "RW"
// =============================================================================
// Register : USB_ADDR_ENDP12
// Description : Interrupt endpoint 12. Only valid for HOST mode.
-#define USB_ADDR_ENDP12_OFFSET _U(0x00000030)
-#define USB_ADDR_ENDP12_BITS _U(0x060f007f)
-#define USB_ADDR_ENDP12_RESET _U(0x00000000)
+#define USB_ADDR_ENDP12_OFFSET _u(0x00000030)
+#define USB_ADDR_ENDP12_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP12_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP12_INTEP_PREAMBLE
// Description : Interrupt EP requires preamble (is a low speed device on a full
// speed hub)
-#define USB_ADDR_ENDP12_INTEP_PREAMBLE_RESET _U(0x0)
-#define USB_ADDR_ENDP12_INTEP_PREAMBLE_BITS _U(0x04000000)
-#define USB_ADDR_ENDP12_INTEP_PREAMBLE_MSB _U(26)
-#define USB_ADDR_ENDP12_INTEP_PREAMBLE_LSB _U(26)
+#define USB_ADDR_ENDP12_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP12_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP12_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP12_INTEP_PREAMBLE_LSB _u(26)
#define USB_ADDR_ENDP12_INTEP_PREAMBLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP12_INTEP_DIR
// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP12_INTEP_DIR_RESET _U(0x0)
-#define USB_ADDR_ENDP12_INTEP_DIR_BITS _U(0x02000000)
-#define USB_ADDR_ENDP12_INTEP_DIR_MSB _U(25)
-#define USB_ADDR_ENDP12_INTEP_DIR_LSB _U(25)
+#define USB_ADDR_ENDP12_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP12_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP12_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP12_INTEP_DIR_LSB _u(25)
#define USB_ADDR_ENDP12_INTEP_DIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP12_ENDPOINT
// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP12_ENDPOINT_RESET _U(0x0)
-#define USB_ADDR_ENDP12_ENDPOINT_BITS _U(0x000f0000)
-#define USB_ADDR_ENDP12_ENDPOINT_MSB _U(19)
-#define USB_ADDR_ENDP12_ENDPOINT_LSB _U(16)
+#define USB_ADDR_ENDP12_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP12_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP12_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP12_ENDPOINT_LSB _u(16)
#define USB_ADDR_ENDP12_ENDPOINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP12_ADDRESS
// Description : Device address
-#define USB_ADDR_ENDP12_ADDRESS_RESET _U(0x00)
-#define USB_ADDR_ENDP12_ADDRESS_BITS _U(0x0000007f)
-#define USB_ADDR_ENDP12_ADDRESS_MSB _U(6)
-#define USB_ADDR_ENDP12_ADDRESS_LSB _U(0)
+#define USB_ADDR_ENDP12_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP12_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP12_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP12_ADDRESS_LSB _u(0)
#define USB_ADDR_ENDP12_ADDRESS_ACCESS "RW"
// =============================================================================
// Register : USB_ADDR_ENDP13
// Description : Interrupt endpoint 13. Only valid for HOST mode.
-#define USB_ADDR_ENDP13_OFFSET _U(0x00000034)
-#define USB_ADDR_ENDP13_BITS _U(0x060f007f)
-#define USB_ADDR_ENDP13_RESET _U(0x00000000)
+#define USB_ADDR_ENDP13_OFFSET _u(0x00000034)
+#define USB_ADDR_ENDP13_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP13_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP13_INTEP_PREAMBLE
// Description : Interrupt EP requires preamble (is a low speed device on a full
// speed hub)
-#define USB_ADDR_ENDP13_INTEP_PREAMBLE_RESET _U(0x0)
-#define USB_ADDR_ENDP13_INTEP_PREAMBLE_BITS _U(0x04000000)
-#define USB_ADDR_ENDP13_INTEP_PREAMBLE_MSB _U(26)
-#define USB_ADDR_ENDP13_INTEP_PREAMBLE_LSB _U(26)
+#define USB_ADDR_ENDP13_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP13_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP13_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP13_INTEP_PREAMBLE_LSB _u(26)
#define USB_ADDR_ENDP13_INTEP_PREAMBLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP13_INTEP_DIR
// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP13_INTEP_DIR_RESET _U(0x0)
-#define USB_ADDR_ENDP13_INTEP_DIR_BITS _U(0x02000000)
-#define USB_ADDR_ENDP13_INTEP_DIR_MSB _U(25)
-#define USB_ADDR_ENDP13_INTEP_DIR_LSB _U(25)
+#define USB_ADDR_ENDP13_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP13_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP13_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP13_INTEP_DIR_LSB _u(25)
#define USB_ADDR_ENDP13_INTEP_DIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP13_ENDPOINT
// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP13_ENDPOINT_RESET _U(0x0)
-#define USB_ADDR_ENDP13_ENDPOINT_BITS _U(0x000f0000)
-#define USB_ADDR_ENDP13_ENDPOINT_MSB _U(19)
-#define USB_ADDR_ENDP13_ENDPOINT_LSB _U(16)
+#define USB_ADDR_ENDP13_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP13_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP13_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP13_ENDPOINT_LSB _u(16)
#define USB_ADDR_ENDP13_ENDPOINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP13_ADDRESS
// Description : Device address
-#define USB_ADDR_ENDP13_ADDRESS_RESET _U(0x00)
-#define USB_ADDR_ENDP13_ADDRESS_BITS _U(0x0000007f)
-#define USB_ADDR_ENDP13_ADDRESS_MSB _U(6)
-#define USB_ADDR_ENDP13_ADDRESS_LSB _U(0)
+#define USB_ADDR_ENDP13_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP13_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP13_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP13_ADDRESS_LSB _u(0)
#define USB_ADDR_ENDP13_ADDRESS_ACCESS "RW"
// =============================================================================
// Register : USB_ADDR_ENDP14
// Description : Interrupt endpoint 14. Only valid for HOST mode.
-#define USB_ADDR_ENDP14_OFFSET _U(0x00000038)
-#define USB_ADDR_ENDP14_BITS _U(0x060f007f)
-#define USB_ADDR_ENDP14_RESET _U(0x00000000)
+#define USB_ADDR_ENDP14_OFFSET _u(0x00000038)
+#define USB_ADDR_ENDP14_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP14_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP14_INTEP_PREAMBLE
// Description : Interrupt EP requires preamble (is a low speed device on a full
// speed hub)
-#define USB_ADDR_ENDP14_INTEP_PREAMBLE_RESET _U(0x0)
-#define USB_ADDR_ENDP14_INTEP_PREAMBLE_BITS _U(0x04000000)
-#define USB_ADDR_ENDP14_INTEP_PREAMBLE_MSB _U(26)
-#define USB_ADDR_ENDP14_INTEP_PREAMBLE_LSB _U(26)
+#define USB_ADDR_ENDP14_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP14_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP14_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP14_INTEP_PREAMBLE_LSB _u(26)
#define USB_ADDR_ENDP14_INTEP_PREAMBLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP14_INTEP_DIR
// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP14_INTEP_DIR_RESET _U(0x0)
-#define USB_ADDR_ENDP14_INTEP_DIR_BITS _U(0x02000000)
-#define USB_ADDR_ENDP14_INTEP_DIR_MSB _U(25)
-#define USB_ADDR_ENDP14_INTEP_DIR_LSB _U(25)
+#define USB_ADDR_ENDP14_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP14_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP14_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP14_INTEP_DIR_LSB _u(25)
#define USB_ADDR_ENDP14_INTEP_DIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP14_ENDPOINT
// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP14_ENDPOINT_RESET _U(0x0)
-#define USB_ADDR_ENDP14_ENDPOINT_BITS _U(0x000f0000)
-#define USB_ADDR_ENDP14_ENDPOINT_MSB _U(19)
-#define USB_ADDR_ENDP14_ENDPOINT_LSB _U(16)
+#define USB_ADDR_ENDP14_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP14_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP14_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP14_ENDPOINT_LSB _u(16)
#define USB_ADDR_ENDP14_ENDPOINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP14_ADDRESS
// Description : Device address
-#define USB_ADDR_ENDP14_ADDRESS_RESET _U(0x00)
-#define USB_ADDR_ENDP14_ADDRESS_BITS _U(0x0000007f)
-#define USB_ADDR_ENDP14_ADDRESS_MSB _U(6)
-#define USB_ADDR_ENDP14_ADDRESS_LSB _U(0)
+#define USB_ADDR_ENDP14_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP14_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP14_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP14_ADDRESS_LSB _u(0)
#define USB_ADDR_ENDP14_ADDRESS_ACCESS "RW"
// =============================================================================
// Register : USB_ADDR_ENDP15
// Description : Interrupt endpoint 15. Only valid for HOST mode.
-#define USB_ADDR_ENDP15_OFFSET _U(0x0000003c)
-#define USB_ADDR_ENDP15_BITS _U(0x060f007f)
-#define USB_ADDR_ENDP15_RESET _U(0x00000000)
+#define USB_ADDR_ENDP15_OFFSET _u(0x0000003c)
+#define USB_ADDR_ENDP15_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP15_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP15_INTEP_PREAMBLE
// Description : Interrupt EP requires preamble (is a low speed device on a full
// speed hub)
-#define USB_ADDR_ENDP15_INTEP_PREAMBLE_RESET _U(0x0)
-#define USB_ADDR_ENDP15_INTEP_PREAMBLE_BITS _U(0x04000000)
-#define USB_ADDR_ENDP15_INTEP_PREAMBLE_MSB _U(26)
-#define USB_ADDR_ENDP15_INTEP_PREAMBLE_LSB _U(26)
+#define USB_ADDR_ENDP15_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP15_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP15_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP15_INTEP_PREAMBLE_LSB _u(26)
#define USB_ADDR_ENDP15_INTEP_PREAMBLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP15_INTEP_DIR
// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP15_INTEP_DIR_RESET _U(0x0)
-#define USB_ADDR_ENDP15_INTEP_DIR_BITS _U(0x02000000)
-#define USB_ADDR_ENDP15_INTEP_DIR_MSB _U(25)
-#define USB_ADDR_ENDP15_INTEP_DIR_LSB _U(25)
+#define USB_ADDR_ENDP15_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP15_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP15_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP15_INTEP_DIR_LSB _u(25)
#define USB_ADDR_ENDP15_INTEP_DIR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP15_ENDPOINT
// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP15_ENDPOINT_RESET _U(0x0)
-#define USB_ADDR_ENDP15_ENDPOINT_BITS _U(0x000f0000)
-#define USB_ADDR_ENDP15_ENDPOINT_MSB _U(19)
-#define USB_ADDR_ENDP15_ENDPOINT_LSB _U(16)
+#define USB_ADDR_ENDP15_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP15_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP15_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP15_ENDPOINT_LSB _u(16)
#define USB_ADDR_ENDP15_ENDPOINT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_ADDR_ENDP15_ADDRESS
// Description : Device address
-#define USB_ADDR_ENDP15_ADDRESS_RESET _U(0x00)
-#define USB_ADDR_ENDP15_ADDRESS_BITS _U(0x0000007f)
-#define USB_ADDR_ENDP15_ADDRESS_MSB _U(6)
-#define USB_ADDR_ENDP15_ADDRESS_LSB _U(0)
+#define USB_ADDR_ENDP15_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP15_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP15_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP15_ADDRESS_LSB _u(0)
#define USB_ADDR_ENDP15_ADDRESS_ACCESS "RW"
// =============================================================================
// Register : USB_MAIN_CTRL
// Description : Main control register
-#define USB_MAIN_CTRL_OFFSET _U(0x00000040)
-#define USB_MAIN_CTRL_BITS _U(0x80000003)
-#define USB_MAIN_CTRL_RESET _U(0x00000000)
+#define USB_MAIN_CTRL_OFFSET _u(0x00000040)
+#define USB_MAIN_CTRL_BITS _u(0x80000003)
+#define USB_MAIN_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_MAIN_CTRL_SIM_TIMING
// Description : Reduced timings for simulation
-#define USB_MAIN_CTRL_SIM_TIMING_RESET _U(0x0)
-#define USB_MAIN_CTRL_SIM_TIMING_BITS _U(0x80000000)
-#define USB_MAIN_CTRL_SIM_TIMING_MSB _U(31)
-#define USB_MAIN_CTRL_SIM_TIMING_LSB _U(31)
+#define USB_MAIN_CTRL_SIM_TIMING_RESET _u(0x0)
+#define USB_MAIN_CTRL_SIM_TIMING_BITS _u(0x80000000)
+#define USB_MAIN_CTRL_SIM_TIMING_MSB _u(31)
+#define USB_MAIN_CTRL_SIM_TIMING_LSB _u(31)
#define USB_MAIN_CTRL_SIM_TIMING_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_MAIN_CTRL_HOST_NDEVICE
// Description : Device mode = 0, Host mode = 1
-#define USB_MAIN_CTRL_HOST_NDEVICE_RESET _U(0x0)
-#define USB_MAIN_CTRL_HOST_NDEVICE_BITS _U(0x00000002)
-#define USB_MAIN_CTRL_HOST_NDEVICE_MSB _U(1)
-#define USB_MAIN_CTRL_HOST_NDEVICE_LSB _U(1)
+#define USB_MAIN_CTRL_HOST_NDEVICE_RESET _u(0x0)
+#define USB_MAIN_CTRL_HOST_NDEVICE_BITS _u(0x00000002)
+#define USB_MAIN_CTRL_HOST_NDEVICE_MSB _u(1)
+#define USB_MAIN_CTRL_HOST_NDEVICE_LSB _u(1)
#define USB_MAIN_CTRL_HOST_NDEVICE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_MAIN_CTRL_CONTROLLER_EN
// Description : Enable controller
-#define USB_MAIN_CTRL_CONTROLLER_EN_RESET _U(0x0)
-#define USB_MAIN_CTRL_CONTROLLER_EN_BITS _U(0x00000001)
-#define USB_MAIN_CTRL_CONTROLLER_EN_MSB _U(0)
-#define USB_MAIN_CTRL_CONTROLLER_EN_LSB _U(0)
+#define USB_MAIN_CTRL_CONTROLLER_EN_RESET _u(0x0)
+#define USB_MAIN_CTRL_CONTROLLER_EN_BITS _u(0x00000001)
+#define USB_MAIN_CTRL_CONTROLLER_EN_MSB _u(0)
+#define USB_MAIN_CTRL_CONTROLLER_EN_LSB _u(0)
#define USB_MAIN_CTRL_CONTROLLER_EN_ACCESS "RW"
// =============================================================================
// Register : USB_SOF_WR
// Description : Set the SOF (Start of Frame) frame number in the host
// controller. The SOF packet is sent every 1ms and the host will
// increment the frame number by 1 each time.
-#define USB_SOF_WR_OFFSET _U(0x00000044)
-#define USB_SOF_WR_BITS _U(0x000007ff)
-#define USB_SOF_WR_RESET _U(0x00000000)
+#define USB_SOF_WR_OFFSET _u(0x00000044)
+#define USB_SOF_WR_BITS _u(0x000007ff)
+#define USB_SOF_WR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_SOF_WR_COUNT
// Description : None
-#define USB_SOF_WR_COUNT_RESET _U(0x000)
-#define USB_SOF_WR_COUNT_BITS _U(0x000007ff)
-#define USB_SOF_WR_COUNT_MSB _U(10)
-#define USB_SOF_WR_COUNT_LSB _U(0)
+#define USB_SOF_WR_COUNT_RESET _u(0x000)
+#define USB_SOF_WR_COUNT_BITS _u(0x000007ff)
+#define USB_SOF_WR_COUNT_MSB _u(10)
+#define USB_SOF_WR_COUNT_LSB _u(0)
#define USB_SOF_WR_COUNT_ACCESS "WF"
// =============================================================================
// Register : USB_SOF_RD
// Description : Read the last SOF (Start of Frame) frame number seen. In device
// mode the last SOF received from the host. In host mode the last
// SOF sent by the host.
-#define USB_SOF_RD_OFFSET _U(0x00000048)
-#define USB_SOF_RD_BITS _U(0x000007ff)
-#define USB_SOF_RD_RESET _U(0x00000000)
+#define USB_SOF_RD_OFFSET _u(0x00000048)
+#define USB_SOF_RD_BITS _u(0x000007ff)
+#define USB_SOF_RD_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_SOF_RD_COUNT
// Description : None
-#define USB_SOF_RD_COUNT_RESET _U(0x000)
-#define USB_SOF_RD_COUNT_BITS _U(0x000007ff)
-#define USB_SOF_RD_COUNT_MSB _U(10)
-#define USB_SOF_RD_COUNT_LSB _U(0)
+#define USB_SOF_RD_COUNT_RESET _u(0x000)
+#define USB_SOF_RD_COUNT_BITS _u(0x000007ff)
+#define USB_SOF_RD_COUNT_MSB _u(10)
+#define USB_SOF_RD_COUNT_LSB _u(0)
#define USB_SOF_RD_COUNT_ACCESS "RO"
// =============================================================================
// Register : USB_SIE_CTRL
// Description : SIE control register
-#define USB_SIE_CTRL_OFFSET _U(0x0000004c)
-#define USB_SIE_CTRL_BITS _U(0xff07bf5f)
-#define USB_SIE_CTRL_RESET _U(0x00000000)
+#define USB_SIE_CTRL_OFFSET _u(0x0000004c)
+#define USB_SIE_CTRL_BITS _u(0xff07bf5f)
+#define USB_SIE_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_EP0_INT_STALL
// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
-#define USB_SIE_CTRL_EP0_INT_STALL_RESET _U(0x0)
-#define USB_SIE_CTRL_EP0_INT_STALL_BITS _U(0x80000000)
-#define USB_SIE_CTRL_EP0_INT_STALL_MSB _U(31)
-#define USB_SIE_CTRL_EP0_INT_STALL_LSB _U(31)
+#define USB_SIE_CTRL_EP0_INT_STALL_RESET _u(0x0)
+#define USB_SIE_CTRL_EP0_INT_STALL_BITS _u(0x80000000)
+#define USB_SIE_CTRL_EP0_INT_STALL_MSB _u(31)
+#define USB_SIE_CTRL_EP0_INT_STALL_LSB _u(31)
#define USB_SIE_CTRL_EP0_INT_STALL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_EP0_DOUBLE_BUF
// Description : Device: EP0 single buffered = 0, double buffered = 1
-#define USB_SIE_CTRL_EP0_DOUBLE_BUF_RESET _U(0x0)
-#define USB_SIE_CTRL_EP0_DOUBLE_BUF_BITS _U(0x40000000)
-#define USB_SIE_CTRL_EP0_DOUBLE_BUF_MSB _U(30)
-#define USB_SIE_CTRL_EP0_DOUBLE_BUF_LSB _U(30)
+#define USB_SIE_CTRL_EP0_DOUBLE_BUF_RESET _u(0x0)
+#define USB_SIE_CTRL_EP0_DOUBLE_BUF_BITS _u(0x40000000)
+#define USB_SIE_CTRL_EP0_DOUBLE_BUF_MSB _u(30)
+#define USB_SIE_CTRL_EP0_DOUBLE_BUF_LSB _u(30)
#define USB_SIE_CTRL_EP0_DOUBLE_BUF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_EP0_INT_1BUF
// Description : Device: Set bit in BUFF_STATUS for every buffer completed on
// EP0
-#define USB_SIE_CTRL_EP0_INT_1BUF_RESET _U(0x0)
-#define USB_SIE_CTRL_EP0_INT_1BUF_BITS _U(0x20000000)
-#define USB_SIE_CTRL_EP0_INT_1BUF_MSB _U(29)
-#define USB_SIE_CTRL_EP0_INT_1BUF_LSB _U(29)
+#define USB_SIE_CTRL_EP0_INT_1BUF_RESET _u(0x0)
+#define USB_SIE_CTRL_EP0_INT_1BUF_BITS _u(0x20000000)
+#define USB_SIE_CTRL_EP0_INT_1BUF_MSB _u(29)
+#define USB_SIE_CTRL_EP0_INT_1BUF_LSB _u(29)
#define USB_SIE_CTRL_EP0_INT_1BUF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_EP0_INT_2BUF
// Description : Device: Set bit in BUFF_STATUS for every 2 buffers completed on
// EP0
-#define USB_SIE_CTRL_EP0_INT_2BUF_RESET _U(0x0)
-#define USB_SIE_CTRL_EP0_INT_2BUF_BITS _U(0x10000000)
-#define USB_SIE_CTRL_EP0_INT_2BUF_MSB _U(28)
-#define USB_SIE_CTRL_EP0_INT_2BUF_LSB _U(28)
+#define USB_SIE_CTRL_EP0_INT_2BUF_RESET _u(0x0)
+#define USB_SIE_CTRL_EP0_INT_2BUF_BITS _u(0x10000000)
+#define USB_SIE_CTRL_EP0_INT_2BUF_MSB _u(28)
+#define USB_SIE_CTRL_EP0_INT_2BUF_LSB _u(28)
#define USB_SIE_CTRL_EP0_INT_2BUF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_EP0_INT_NAK
// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
-#define USB_SIE_CTRL_EP0_INT_NAK_RESET _U(0x0)
-#define USB_SIE_CTRL_EP0_INT_NAK_BITS _U(0x08000000)
-#define USB_SIE_CTRL_EP0_INT_NAK_MSB _U(27)
-#define USB_SIE_CTRL_EP0_INT_NAK_LSB _U(27)
+#define USB_SIE_CTRL_EP0_INT_NAK_RESET _u(0x0)
+#define USB_SIE_CTRL_EP0_INT_NAK_BITS _u(0x08000000)
+#define USB_SIE_CTRL_EP0_INT_NAK_MSB _u(27)
+#define USB_SIE_CTRL_EP0_INT_NAK_LSB _u(27)
#define USB_SIE_CTRL_EP0_INT_NAK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_DIRECT_EN
// Description : Direct bus drive enable
-#define USB_SIE_CTRL_DIRECT_EN_RESET _U(0x0)
-#define USB_SIE_CTRL_DIRECT_EN_BITS _U(0x04000000)
-#define USB_SIE_CTRL_DIRECT_EN_MSB _U(26)
-#define USB_SIE_CTRL_DIRECT_EN_LSB _U(26)
+#define USB_SIE_CTRL_DIRECT_EN_RESET _u(0x0)
+#define USB_SIE_CTRL_DIRECT_EN_BITS _u(0x04000000)
+#define USB_SIE_CTRL_DIRECT_EN_MSB _u(26)
+#define USB_SIE_CTRL_DIRECT_EN_LSB _u(26)
#define USB_SIE_CTRL_DIRECT_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_DIRECT_DP
// Description : Direct control of DP
-#define USB_SIE_CTRL_DIRECT_DP_RESET _U(0x0)
-#define USB_SIE_CTRL_DIRECT_DP_BITS _U(0x02000000)
-#define USB_SIE_CTRL_DIRECT_DP_MSB _U(25)
-#define USB_SIE_CTRL_DIRECT_DP_LSB _U(25)
+#define USB_SIE_CTRL_DIRECT_DP_RESET _u(0x0)
+#define USB_SIE_CTRL_DIRECT_DP_BITS _u(0x02000000)
+#define USB_SIE_CTRL_DIRECT_DP_MSB _u(25)
+#define USB_SIE_CTRL_DIRECT_DP_LSB _u(25)
#define USB_SIE_CTRL_DIRECT_DP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_DIRECT_DM
// Description : Direct control of DM
-#define USB_SIE_CTRL_DIRECT_DM_RESET _U(0x0)
-#define USB_SIE_CTRL_DIRECT_DM_BITS _U(0x01000000)
-#define USB_SIE_CTRL_DIRECT_DM_MSB _U(24)
-#define USB_SIE_CTRL_DIRECT_DM_LSB _U(24)
+#define USB_SIE_CTRL_DIRECT_DM_RESET _u(0x0)
+#define USB_SIE_CTRL_DIRECT_DM_BITS _u(0x01000000)
+#define USB_SIE_CTRL_DIRECT_DM_MSB _u(24)
+#define USB_SIE_CTRL_DIRECT_DM_LSB _u(24)
#define USB_SIE_CTRL_DIRECT_DM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_TRANSCEIVER_PD
// Description : Power down bus transceiver
-#define USB_SIE_CTRL_TRANSCEIVER_PD_RESET _U(0x0)
-#define USB_SIE_CTRL_TRANSCEIVER_PD_BITS _U(0x00040000)
-#define USB_SIE_CTRL_TRANSCEIVER_PD_MSB _U(18)
-#define USB_SIE_CTRL_TRANSCEIVER_PD_LSB _U(18)
+#define USB_SIE_CTRL_TRANSCEIVER_PD_RESET _u(0x0)
+#define USB_SIE_CTRL_TRANSCEIVER_PD_BITS _u(0x00040000)
+#define USB_SIE_CTRL_TRANSCEIVER_PD_MSB _u(18)
+#define USB_SIE_CTRL_TRANSCEIVER_PD_LSB _u(18)
#define USB_SIE_CTRL_TRANSCEIVER_PD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_RPU_OPT
// Description : Device: Pull-up strength (0=1K2, 1=2k3)
-#define USB_SIE_CTRL_RPU_OPT_RESET _U(0x0)
-#define USB_SIE_CTRL_RPU_OPT_BITS _U(0x00020000)
-#define USB_SIE_CTRL_RPU_OPT_MSB _U(17)
-#define USB_SIE_CTRL_RPU_OPT_LSB _U(17)
+#define USB_SIE_CTRL_RPU_OPT_RESET _u(0x0)
+#define USB_SIE_CTRL_RPU_OPT_BITS _u(0x00020000)
+#define USB_SIE_CTRL_RPU_OPT_MSB _u(17)
+#define USB_SIE_CTRL_RPU_OPT_LSB _u(17)
#define USB_SIE_CTRL_RPU_OPT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_PULLUP_EN
// Description : Device: Enable pull up resistor
-#define USB_SIE_CTRL_PULLUP_EN_RESET _U(0x0)
-#define USB_SIE_CTRL_PULLUP_EN_BITS _U(0x00010000)
-#define USB_SIE_CTRL_PULLUP_EN_MSB _U(16)
-#define USB_SIE_CTRL_PULLUP_EN_LSB _U(16)
+#define USB_SIE_CTRL_PULLUP_EN_RESET _u(0x0)
+#define USB_SIE_CTRL_PULLUP_EN_BITS _u(0x00010000)
+#define USB_SIE_CTRL_PULLUP_EN_MSB _u(16)
+#define USB_SIE_CTRL_PULLUP_EN_LSB _u(16)
#define USB_SIE_CTRL_PULLUP_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_PULLDOWN_EN
// Description : Host: Enable pull down resistors
-#define USB_SIE_CTRL_PULLDOWN_EN_RESET _U(0x0)
-#define USB_SIE_CTRL_PULLDOWN_EN_BITS _U(0x00008000)
-#define USB_SIE_CTRL_PULLDOWN_EN_MSB _U(15)
-#define USB_SIE_CTRL_PULLDOWN_EN_LSB _U(15)
+#define USB_SIE_CTRL_PULLDOWN_EN_RESET _u(0x0)
+#define USB_SIE_CTRL_PULLDOWN_EN_BITS _u(0x00008000)
+#define USB_SIE_CTRL_PULLDOWN_EN_MSB _u(15)
+#define USB_SIE_CTRL_PULLDOWN_EN_LSB _u(15)
#define USB_SIE_CTRL_PULLDOWN_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_RESET_BUS
// Description : Host: Reset bus
-#define USB_SIE_CTRL_RESET_BUS_RESET _U(0x0)
-#define USB_SIE_CTRL_RESET_BUS_BITS _U(0x00002000)
-#define USB_SIE_CTRL_RESET_BUS_MSB _U(13)
-#define USB_SIE_CTRL_RESET_BUS_LSB _U(13)
+#define USB_SIE_CTRL_RESET_BUS_RESET _u(0x0)
+#define USB_SIE_CTRL_RESET_BUS_BITS _u(0x00002000)
+#define USB_SIE_CTRL_RESET_BUS_MSB _u(13)
+#define USB_SIE_CTRL_RESET_BUS_LSB _u(13)
#define USB_SIE_CTRL_RESET_BUS_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_RESUME
// Description : Device: Remote wakeup. Device can initiate its own resume after
// suspend.
-#define USB_SIE_CTRL_RESUME_RESET _U(0x0)
-#define USB_SIE_CTRL_RESUME_BITS _U(0x00001000)
-#define USB_SIE_CTRL_RESUME_MSB _U(12)
-#define USB_SIE_CTRL_RESUME_LSB _U(12)
+#define USB_SIE_CTRL_RESUME_RESET _u(0x0)
+#define USB_SIE_CTRL_RESUME_BITS _u(0x00001000)
+#define USB_SIE_CTRL_RESUME_MSB _u(12)
+#define USB_SIE_CTRL_RESUME_LSB _u(12)
#define USB_SIE_CTRL_RESUME_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_VBUS_EN
// Description : Host: Enable VBUS
-#define USB_SIE_CTRL_VBUS_EN_RESET _U(0x0)
-#define USB_SIE_CTRL_VBUS_EN_BITS _U(0x00000800)
-#define USB_SIE_CTRL_VBUS_EN_MSB _U(11)
-#define USB_SIE_CTRL_VBUS_EN_LSB _U(11)
+#define USB_SIE_CTRL_VBUS_EN_RESET _u(0x0)
+#define USB_SIE_CTRL_VBUS_EN_BITS _u(0x00000800)
+#define USB_SIE_CTRL_VBUS_EN_MSB _u(11)
+#define USB_SIE_CTRL_VBUS_EN_LSB _u(11)
#define USB_SIE_CTRL_VBUS_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_KEEP_ALIVE_EN
// Description : Host: Enable keep alive packet (for low speed bus)
-#define USB_SIE_CTRL_KEEP_ALIVE_EN_RESET _U(0x0)
-#define USB_SIE_CTRL_KEEP_ALIVE_EN_BITS _U(0x00000400)
-#define USB_SIE_CTRL_KEEP_ALIVE_EN_MSB _U(10)
-#define USB_SIE_CTRL_KEEP_ALIVE_EN_LSB _U(10)
+#define USB_SIE_CTRL_KEEP_ALIVE_EN_RESET _u(0x0)
+#define USB_SIE_CTRL_KEEP_ALIVE_EN_BITS _u(0x00000400)
+#define USB_SIE_CTRL_KEEP_ALIVE_EN_MSB _u(10)
+#define USB_SIE_CTRL_KEEP_ALIVE_EN_LSB _u(10)
#define USB_SIE_CTRL_KEEP_ALIVE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_SOF_EN
// Description : Host: Enable SOF generation (for full speed bus)
-#define USB_SIE_CTRL_SOF_EN_RESET _U(0x0)
-#define USB_SIE_CTRL_SOF_EN_BITS _U(0x00000200)
-#define USB_SIE_CTRL_SOF_EN_MSB _U(9)
-#define USB_SIE_CTRL_SOF_EN_LSB _U(9)
+#define USB_SIE_CTRL_SOF_EN_RESET _u(0x0)
+#define USB_SIE_CTRL_SOF_EN_BITS _u(0x00000200)
+#define USB_SIE_CTRL_SOF_EN_MSB _u(9)
+#define USB_SIE_CTRL_SOF_EN_LSB _u(9)
#define USB_SIE_CTRL_SOF_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_SOF_SYNC
// Description : Host: Delay packet(s) until after SOF
-#define USB_SIE_CTRL_SOF_SYNC_RESET _U(0x0)
-#define USB_SIE_CTRL_SOF_SYNC_BITS _U(0x00000100)
-#define USB_SIE_CTRL_SOF_SYNC_MSB _U(8)
-#define USB_SIE_CTRL_SOF_SYNC_LSB _U(8)
+#define USB_SIE_CTRL_SOF_SYNC_RESET _u(0x0)
+#define USB_SIE_CTRL_SOF_SYNC_BITS _u(0x00000100)
+#define USB_SIE_CTRL_SOF_SYNC_MSB _u(8)
+#define USB_SIE_CTRL_SOF_SYNC_LSB _u(8)
#define USB_SIE_CTRL_SOF_SYNC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_PREAMBLE_EN
// Description : Host: Preable enable for LS device on FS hub
-#define USB_SIE_CTRL_PREAMBLE_EN_RESET _U(0x0)
-#define USB_SIE_CTRL_PREAMBLE_EN_BITS _U(0x00000040)
-#define USB_SIE_CTRL_PREAMBLE_EN_MSB _U(6)
-#define USB_SIE_CTRL_PREAMBLE_EN_LSB _U(6)
+#define USB_SIE_CTRL_PREAMBLE_EN_RESET _u(0x0)
+#define USB_SIE_CTRL_PREAMBLE_EN_BITS _u(0x00000040)
+#define USB_SIE_CTRL_PREAMBLE_EN_MSB _u(6)
+#define USB_SIE_CTRL_PREAMBLE_EN_LSB _u(6)
#define USB_SIE_CTRL_PREAMBLE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_STOP_TRANS
// Description : Host: Stop transaction
-#define USB_SIE_CTRL_STOP_TRANS_RESET _U(0x0)
-#define USB_SIE_CTRL_STOP_TRANS_BITS _U(0x00000010)
-#define USB_SIE_CTRL_STOP_TRANS_MSB _U(4)
-#define USB_SIE_CTRL_STOP_TRANS_LSB _U(4)
+#define USB_SIE_CTRL_STOP_TRANS_RESET _u(0x0)
+#define USB_SIE_CTRL_STOP_TRANS_BITS _u(0x00000010)
+#define USB_SIE_CTRL_STOP_TRANS_MSB _u(4)
+#define USB_SIE_CTRL_STOP_TRANS_LSB _u(4)
#define USB_SIE_CTRL_STOP_TRANS_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_RECEIVE_DATA
// Description : Host: Receive transaction (IN to host)
-#define USB_SIE_CTRL_RECEIVE_DATA_RESET _U(0x0)
-#define USB_SIE_CTRL_RECEIVE_DATA_BITS _U(0x00000008)
-#define USB_SIE_CTRL_RECEIVE_DATA_MSB _U(3)
-#define USB_SIE_CTRL_RECEIVE_DATA_LSB _U(3)
+#define USB_SIE_CTRL_RECEIVE_DATA_RESET _u(0x0)
+#define USB_SIE_CTRL_RECEIVE_DATA_BITS _u(0x00000008)
+#define USB_SIE_CTRL_RECEIVE_DATA_MSB _u(3)
+#define USB_SIE_CTRL_RECEIVE_DATA_LSB _u(3)
#define USB_SIE_CTRL_RECEIVE_DATA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_SEND_DATA
// Description : Host: Send transaction (OUT from host)
-#define USB_SIE_CTRL_SEND_DATA_RESET _U(0x0)
-#define USB_SIE_CTRL_SEND_DATA_BITS _U(0x00000004)
-#define USB_SIE_CTRL_SEND_DATA_MSB _U(2)
-#define USB_SIE_CTRL_SEND_DATA_LSB _U(2)
+#define USB_SIE_CTRL_SEND_DATA_RESET _u(0x0)
+#define USB_SIE_CTRL_SEND_DATA_BITS _u(0x00000004)
+#define USB_SIE_CTRL_SEND_DATA_MSB _u(2)
+#define USB_SIE_CTRL_SEND_DATA_LSB _u(2)
#define USB_SIE_CTRL_SEND_DATA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_SEND_SETUP
// Description : Host: Send Setup packet
-#define USB_SIE_CTRL_SEND_SETUP_RESET _U(0x0)
-#define USB_SIE_CTRL_SEND_SETUP_BITS _U(0x00000002)
-#define USB_SIE_CTRL_SEND_SETUP_MSB _U(1)
-#define USB_SIE_CTRL_SEND_SETUP_LSB _U(1)
+#define USB_SIE_CTRL_SEND_SETUP_RESET _u(0x0)
+#define USB_SIE_CTRL_SEND_SETUP_BITS _u(0x00000002)
+#define USB_SIE_CTRL_SEND_SETUP_MSB _u(1)
+#define USB_SIE_CTRL_SEND_SETUP_LSB _u(1)
#define USB_SIE_CTRL_SEND_SETUP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_SIE_CTRL_START_TRANS
// Description : Host: Start transaction
-#define USB_SIE_CTRL_START_TRANS_RESET _U(0x0)
-#define USB_SIE_CTRL_START_TRANS_BITS _U(0x00000001)
-#define USB_SIE_CTRL_START_TRANS_MSB _U(0)
-#define USB_SIE_CTRL_START_TRANS_LSB _U(0)
+#define USB_SIE_CTRL_START_TRANS_RESET _u(0x0)
+#define USB_SIE_CTRL_START_TRANS_BITS _u(0x00000001)
+#define USB_SIE_CTRL_START_TRANS_MSB _u(0)
+#define USB_SIE_CTRL_START_TRANS_LSB _u(0)
#define USB_SIE_CTRL_START_TRANS_ACCESS "SC"
// =============================================================================
// Register : USB_SIE_STATUS
// Description : SIE status register
-#define USB_SIE_STATUS_OFFSET _U(0x00000050)
-#define USB_SIE_STATUS_BITS _U(0xff0f0f1d)
-#define USB_SIE_STATUS_RESET _U(0x00000000)
+#define USB_SIE_STATUS_OFFSET _u(0x00000050)
+#define USB_SIE_STATUS_BITS _u(0xff0f0f1d)
+#define USB_SIE_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_DATA_SEQ_ERROR
// Description : Data Sequence Error.
@@ -905,76 +905,76 @@
// conditions:
//
// * An IN packet from the device has the wrong data PID
-#define USB_SIE_STATUS_DATA_SEQ_ERROR_RESET _U(0x0)
-#define USB_SIE_STATUS_DATA_SEQ_ERROR_BITS _U(0x80000000)
-#define USB_SIE_STATUS_DATA_SEQ_ERROR_MSB _U(31)
-#define USB_SIE_STATUS_DATA_SEQ_ERROR_LSB _U(31)
+#define USB_SIE_STATUS_DATA_SEQ_ERROR_RESET _u(0x0)
+#define USB_SIE_STATUS_DATA_SEQ_ERROR_BITS _u(0x80000000)
+#define USB_SIE_STATUS_DATA_SEQ_ERROR_MSB _u(31)
+#define USB_SIE_STATUS_DATA_SEQ_ERROR_LSB _u(31)
#define USB_SIE_STATUS_DATA_SEQ_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_ACK_REC
// Description : ACK received. Raised by both host and device.
-#define USB_SIE_STATUS_ACK_REC_RESET _U(0x0)
-#define USB_SIE_STATUS_ACK_REC_BITS _U(0x40000000)
-#define USB_SIE_STATUS_ACK_REC_MSB _U(30)
-#define USB_SIE_STATUS_ACK_REC_LSB _U(30)
+#define USB_SIE_STATUS_ACK_REC_RESET _u(0x0)
+#define USB_SIE_STATUS_ACK_REC_BITS _u(0x40000000)
+#define USB_SIE_STATUS_ACK_REC_MSB _u(30)
+#define USB_SIE_STATUS_ACK_REC_LSB _u(30)
#define USB_SIE_STATUS_ACK_REC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_STALL_REC
// Description : Host: STALL received
-#define USB_SIE_STATUS_STALL_REC_RESET _U(0x0)
-#define USB_SIE_STATUS_STALL_REC_BITS _U(0x20000000)
-#define USB_SIE_STATUS_STALL_REC_MSB _U(29)
-#define USB_SIE_STATUS_STALL_REC_LSB _U(29)
+#define USB_SIE_STATUS_STALL_REC_RESET _u(0x0)
+#define USB_SIE_STATUS_STALL_REC_BITS _u(0x20000000)
+#define USB_SIE_STATUS_STALL_REC_MSB _u(29)
+#define USB_SIE_STATUS_STALL_REC_LSB _u(29)
#define USB_SIE_STATUS_STALL_REC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_NAK_REC
// Description : Host: NAK received
-#define USB_SIE_STATUS_NAK_REC_RESET _U(0x0)
-#define USB_SIE_STATUS_NAK_REC_BITS _U(0x10000000)
-#define USB_SIE_STATUS_NAK_REC_MSB _U(28)
-#define USB_SIE_STATUS_NAK_REC_LSB _U(28)
+#define USB_SIE_STATUS_NAK_REC_RESET _u(0x0)
+#define USB_SIE_STATUS_NAK_REC_BITS _u(0x10000000)
+#define USB_SIE_STATUS_NAK_REC_MSB _u(28)
+#define USB_SIE_STATUS_NAK_REC_LSB _u(28)
#define USB_SIE_STATUS_NAK_REC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_RX_TIMEOUT
// Description : RX timeout is raised by both the host and device if an ACK is
// not received in the maximum time specified by the USB spec.
-#define USB_SIE_STATUS_RX_TIMEOUT_RESET _U(0x0)
-#define USB_SIE_STATUS_RX_TIMEOUT_BITS _U(0x08000000)
-#define USB_SIE_STATUS_RX_TIMEOUT_MSB _U(27)
-#define USB_SIE_STATUS_RX_TIMEOUT_LSB _U(27)
+#define USB_SIE_STATUS_RX_TIMEOUT_RESET _u(0x0)
+#define USB_SIE_STATUS_RX_TIMEOUT_BITS _u(0x08000000)
+#define USB_SIE_STATUS_RX_TIMEOUT_MSB _u(27)
+#define USB_SIE_STATUS_RX_TIMEOUT_LSB _u(27)
#define USB_SIE_STATUS_RX_TIMEOUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_RX_OVERFLOW
// Description : RX overflow is raised by the Serial RX engine if the incoming
// data is too fast.
-#define USB_SIE_STATUS_RX_OVERFLOW_RESET _U(0x0)
-#define USB_SIE_STATUS_RX_OVERFLOW_BITS _U(0x04000000)
-#define USB_SIE_STATUS_RX_OVERFLOW_MSB _U(26)
-#define USB_SIE_STATUS_RX_OVERFLOW_LSB _U(26)
+#define USB_SIE_STATUS_RX_OVERFLOW_RESET _u(0x0)
+#define USB_SIE_STATUS_RX_OVERFLOW_BITS _u(0x04000000)
+#define USB_SIE_STATUS_RX_OVERFLOW_MSB _u(26)
+#define USB_SIE_STATUS_RX_OVERFLOW_LSB _u(26)
#define USB_SIE_STATUS_RX_OVERFLOW_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_BIT_STUFF_ERROR
// Description : Bit Stuff Error. Raised by the Serial RX engine.
-#define USB_SIE_STATUS_BIT_STUFF_ERROR_RESET _U(0x0)
-#define USB_SIE_STATUS_BIT_STUFF_ERROR_BITS _U(0x02000000)
-#define USB_SIE_STATUS_BIT_STUFF_ERROR_MSB _U(25)
-#define USB_SIE_STATUS_BIT_STUFF_ERROR_LSB _U(25)
+#define USB_SIE_STATUS_BIT_STUFF_ERROR_RESET _u(0x0)
+#define USB_SIE_STATUS_BIT_STUFF_ERROR_BITS _u(0x02000000)
+#define USB_SIE_STATUS_BIT_STUFF_ERROR_MSB _u(25)
+#define USB_SIE_STATUS_BIT_STUFF_ERROR_LSB _u(25)
#define USB_SIE_STATUS_BIT_STUFF_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_CRC_ERROR
// Description : CRC Error. Raised by the Serial RX engine.
-#define USB_SIE_STATUS_CRC_ERROR_RESET _U(0x0)
-#define USB_SIE_STATUS_CRC_ERROR_BITS _U(0x01000000)
-#define USB_SIE_STATUS_CRC_ERROR_MSB _U(24)
-#define USB_SIE_STATUS_CRC_ERROR_LSB _U(24)
+#define USB_SIE_STATUS_CRC_ERROR_RESET _u(0x0)
+#define USB_SIE_STATUS_CRC_ERROR_BITS _u(0x01000000)
+#define USB_SIE_STATUS_CRC_ERROR_MSB _u(24)
+#define USB_SIE_STATUS_CRC_ERROR_LSB _u(24)
#define USB_SIE_STATUS_CRC_ERROR_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_BUS_RESET
// Description : Device: bus reset received
-#define USB_SIE_STATUS_BUS_RESET_RESET _U(0x0)
-#define USB_SIE_STATUS_BUS_RESET_BITS _U(0x00080000)
-#define USB_SIE_STATUS_BUS_RESET_MSB _U(19)
-#define USB_SIE_STATUS_BUS_RESET_LSB _U(19)
+#define USB_SIE_STATUS_BUS_RESET_RESET _u(0x0)
+#define USB_SIE_STATUS_BUS_RESET_BITS _u(0x00080000)
+#define USB_SIE_STATUS_BUS_RESET_MSB _u(19)
+#define USB_SIE_STATUS_BUS_RESET_LSB _u(19)
#define USB_SIE_STATUS_BUS_RESET_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_TRANS_COMPLETE
@@ -992,91 +992,91 @@
// `LAST_BUFF` bit is set in the buffer control register * An IN
// packet is received with zero length * An OUT packet is sent and
// the `LAST_BUFF` bit is set
-#define USB_SIE_STATUS_TRANS_COMPLETE_RESET _U(0x0)
-#define USB_SIE_STATUS_TRANS_COMPLETE_BITS _U(0x00040000)
-#define USB_SIE_STATUS_TRANS_COMPLETE_MSB _U(18)
-#define USB_SIE_STATUS_TRANS_COMPLETE_LSB _U(18)
+#define USB_SIE_STATUS_TRANS_COMPLETE_RESET _u(0x0)
+#define USB_SIE_STATUS_TRANS_COMPLETE_BITS _u(0x00040000)
+#define USB_SIE_STATUS_TRANS_COMPLETE_MSB _u(18)
+#define USB_SIE_STATUS_TRANS_COMPLETE_LSB _u(18)
#define USB_SIE_STATUS_TRANS_COMPLETE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_SETUP_REC
// Description : Device: Setup packet received
-#define USB_SIE_STATUS_SETUP_REC_RESET _U(0x0)
-#define USB_SIE_STATUS_SETUP_REC_BITS _U(0x00020000)
-#define USB_SIE_STATUS_SETUP_REC_MSB _U(17)
-#define USB_SIE_STATUS_SETUP_REC_LSB _U(17)
+#define USB_SIE_STATUS_SETUP_REC_RESET _u(0x0)
+#define USB_SIE_STATUS_SETUP_REC_BITS _u(0x00020000)
+#define USB_SIE_STATUS_SETUP_REC_MSB _u(17)
+#define USB_SIE_STATUS_SETUP_REC_LSB _u(17)
#define USB_SIE_STATUS_SETUP_REC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_CONNECTED
// Description : Device: connected
-#define USB_SIE_STATUS_CONNECTED_RESET _U(0x0)
-#define USB_SIE_STATUS_CONNECTED_BITS _U(0x00010000)
-#define USB_SIE_STATUS_CONNECTED_MSB _U(16)
-#define USB_SIE_STATUS_CONNECTED_LSB _U(16)
+#define USB_SIE_STATUS_CONNECTED_RESET _u(0x0)
+#define USB_SIE_STATUS_CONNECTED_BITS _u(0x00010000)
+#define USB_SIE_STATUS_CONNECTED_MSB _u(16)
+#define USB_SIE_STATUS_CONNECTED_LSB _u(16)
#define USB_SIE_STATUS_CONNECTED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_RESUME
// Description : Host: Device has initiated a remote resume. Device: host has
// initiated a resume.
-#define USB_SIE_STATUS_RESUME_RESET _U(0x0)
-#define USB_SIE_STATUS_RESUME_BITS _U(0x00000800)
-#define USB_SIE_STATUS_RESUME_MSB _U(11)
-#define USB_SIE_STATUS_RESUME_LSB _U(11)
+#define USB_SIE_STATUS_RESUME_RESET _u(0x0)
+#define USB_SIE_STATUS_RESUME_BITS _u(0x00000800)
+#define USB_SIE_STATUS_RESUME_MSB _u(11)
+#define USB_SIE_STATUS_RESUME_LSB _u(11)
#define USB_SIE_STATUS_RESUME_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_VBUS_OVER_CURR
// Description : VBUS over current detected
-#define USB_SIE_STATUS_VBUS_OVER_CURR_RESET _U(0x0)
-#define USB_SIE_STATUS_VBUS_OVER_CURR_BITS _U(0x00000400)
-#define USB_SIE_STATUS_VBUS_OVER_CURR_MSB _U(10)
-#define USB_SIE_STATUS_VBUS_OVER_CURR_LSB _U(10)
+#define USB_SIE_STATUS_VBUS_OVER_CURR_RESET _u(0x0)
+#define USB_SIE_STATUS_VBUS_OVER_CURR_BITS _u(0x00000400)
+#define USB_SIE_STATUS_VBUS_OVER_CURR_MSB _u(10)
+#define USB_SIE_STATUS_VBUS_OVER_CURR_LSB _u(10)
#define USB_SIE_STATUS_VBUS_OVER_CURR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_SPEED
// Description : Host: device speed. Disconnected = 00, LS = 01, FS = 10
-#define USB_SIE_STATUS_SPEED_RESET _U(0x0)
-#define USB_SIE_STATUS_SPEED_BITS _U(0x00000300)
-#define USB_SIE_STATUS_SPEED_MSB _U(9)
-#define USB_SIE_STATUS_SPEED_LSB _U(8)
+#define USB_SIE_STATUS_SPEED_RESET _u(0x0)
+#define USB_SIE_STATUS_SPEED_BITS _u(0x00000300)
+#define USB_SIE_STATUS_SPEED_MSB _u(9)
+#define USB_SIE_STATUS_SPEED_LSB _u(8)
#define USB_SIE_STATUS_SPEED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_SUSPENDED
// Description : Bus in suspended state. Valid for device and host. Host and
// device will go into suspend if neither Keep Alive / SOF frames
// are enabled.
-#define USB_SIE_STATUS_SUSPENDED_RESET _U(0x0)
-#define USB_SIE_STATUS_SUSPENDED_BITS _U(0x00000010)
-#define USB_SIE_STATUS_SUSPENDED_MSB _U(4)
-#define USB_SIE_STATUS_SUSPENDED_LSB _U(4)
+#define USB_SIE_STATUS_SUSPENDED_RESET _u(0x0)
+#define USB_SIE_STATUS_SUSPENDED_BITS _u(0x00000010)
+#define USB_SIE_STATUS_SUSPENDED_MSB _u(4)
+#define USB_SIE_STATUS_SUSPENDED_LSB _u(4)
#define USB_SIE_STATUS_SUSPENDED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_LINE_STATE
// Description : USB bus line state
-#define USB_SIE_STATUS_LINE_STATE_RESET _U(0x0)
-#define USB_SIE_STATUS_LINE_STATE_BITS _U(0x0000000c)
-#define USB_SIE_STATUS_LINE_STATE_MSB _U(3)
-#define USB_SIE_STATUS_LINE_STATE_LSB _U(2)
+#define USB_SIE_STATUS_LINE_STATE_RESET _u(0x0)
+#define USB_SIE_STATUS_LINE_STATE_BITS _u(0x0000000c)
+#define USB_SIE_STATUS_LINE_STATE_MSB _u(3)
+#define USB_SIE_STATUS_LINE_STATE_LSB _u(2)
#define USB_SIE_STATUS_LINE_STATE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_VBUS_DETECTED
// Description : Device: VBUS Detected
-#define USB_SIE_STATUS_VBUS_DETECTED_RESET _U(0x0)
-#define USB_SIE_STATUS_VBUS_DETECTED_BITS _U(0x00000001)
-#define USB_SIE_STATUS_VBUS_DETECTED_MSB _U(0)
-#define USB_SIE_STATUS_VBUS_DETECTED_LSB _U(0)
+#define USB_SIE_STATUS_VBUS_DETECTED_RESET _u(0x0)
+#define USB_SIE_STATUS_VBUS_DETECTED_BITS _u(0x00000001)
+#define USB_SIE_STATUS_VBUS_DETECTED_MSB _u(0)
+#define USB_SIE_STATUS_VBUS_DETECTED_LSB _u(0)
#define USB_SIE_STATUS_VBUS_DETECTED_ACCESS "RO"
// =============================================================================
// Register : USB_INT_EP_CTRL
// Description : interrupt endpoint control register
-#define USB_INT_EP_CTRL_OFFSET _U(0x00000054)
-#define USB_INT_EP_CTRL_BITS _U(0x0000fffe)
-#define USB_INT_EP_CTRL_RESET _U(0x00000000)
+#define USB_INT_EP_CTRL_OFFSET _u(0x00000054)
+#define USB_INT_EP_CTRL_BITS _u(0x0000fffe)
+#define USB_INT_EP_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_INT_EP_CTRL_INT_EP_ACTIVE
// Description : Host: Enable interrupt endpoint 1 -> 15
-#define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET _U(0x0000)
-#define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS _U(0x0000fffe)
-#define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB _U(15)
-#define USB_INT_EP_CTRL_INT_EP_ACTIVE_LSB _U(1)
+#define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET _u(0x0000)
+#define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS _u(0x0000fffe)
+#define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB _u(15)
+#define USB_INT_EP_CTRL_INT_EP_ACTIVE_LSB _u(1)
#define USB_INT_EP_CTRL_INT_EP_ACTIVE_ACCESS "RW"
// =============================================================================
// Register : USB_BUFF_STATUS
@@ -1085,264 +1085,264 @@
// enabled). It is possible for 2 buffers to be completed, so
// clearing the buffer status bit may instantly re set it on the
// next clock cycle.
-#define USB_BUFF_STATUS_OFFSET _U(0x00000058)
-#define USB_BUFF_STATUS_BITS _U(0xffffffff)
-#define USB_BUFF_STATUS_RESET _U(0x00000000)
+#define USB_BUFF_STATUS_OFFSET _u(0x00000058)
+#define USB_BUFF_STATUS_BITS _u(0xffffffff)
+#define USB_BUFF_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP15_OUT
// Description : None
-#define USB_BUFF_STATUS_EP15_OUT_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP15_OUT_BITS _U(0x80000000)
-#define USB_BUFF_STATUS_EP15_OUT_MSB _U(31)
-#define USB_BUFF_STATUS_EP15_OUT_LSB _U(31)
+#define USB_BUFF_STATUS_EP15_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP15_OUT_BITS _u(0x80000000)
+#define USB_BUFF_STATUS_EP15_OUT_MSB _u(31)
+#define USB_BUFF_STATUS_EP15_OUT_LSB _u(31)
#define USB_BUFF_STATUS_EP15_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP15_IN
// Description : None
-#define USB_BUFF_STATUS_EP15_IN_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP15_IN_BITS _U(0x40000000)
-#define USB_BUFF_STATUS_EP15_IN_MSB _U(30)
-#define USB_BUFF_STATUS_EP15_IN_LSB _U(30)
+#define USB_BUFF_STATUS_EP15_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP15_IN_BITS _u(0x40000000)
+#define USB_BUFF_STATUS_EP15_IN_MSB _u(30)
+#define USB_BUFF_STATUS_EP15_IN_LSB _u(30)
#define USB_BUFF_STATUS_EP15_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP14_OUT
// Description : None
-#define USB_BUFF_STATUS_EP14_OUT_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP14_OUT_BITS _U(0x20000000)
-#define USB_BUFF_STATUS_EP14_OUT_MSB _U(29)
-#define USB_BUFF_STATUS_EP14_OUT_LSB _U(29)
+#define USB_BUFF_STATUS_EP14_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP14_OUT_BITS _u(0x20000000)
+#define USB_BUFF_STATUS_EP14_OUT_MSB _u(29)
+#define USB_BUFF_STATUS_EP14_OUT_LSB _u(29)
#define USB_BUFF_STATUS_EP14_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP14_IN
// Description : None
-#define USB_BUFF_STATUS_EP14_IN_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP14_IN_BITS _U(0x10000000)
-#define USB_BUFF_STATUS_EP14_IN_MSB _U(28)
-#define USB_BUFF_STATUS_EP14_IN_LSB _U(28)
+#define USB_BUFF_STATUS_EP14_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP14_IN_BITS _u(0x10000000)
+#define USB_BUFF_STATUS_EP14_IN_MSB _u(28)
+#define USB_BUFF_STATUS_EP14_IN_LSB _u(28)
#define USB_BUFF_STATUS_EP14_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP13_OUT
// Description : None
-#define USB_BUFF_STATUS_EP13_OUT_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP13_OUT_BITS _U(0x08000000)
-#define USB_BUFF_STATUS_EP13_OUT_MSB _U(27)
-#define USB_BUFF_STATUS_EP13_OUT_LSB _U(27)
+#define USB_BUFF_STATUS_EP13_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP13_OUT_BITS _u(0x08000000)
+#define USB_BUFF_STATUS_EP13_OUT_MSB _u(27)
+#define USB_BUFF_STATUS_EP13_OUT_LSB _u(27)
#define USB_BUFF_STATUS_EP13_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP13_IN
// Description : None
-#define USB_BUFF_STATUS_EP13_IN_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP13_IN_BITS _U(0x04000000)
-#define USB_BUFF_STATUS_EP13_IN_MSB _U(26)
-#define USB_BUFF_STATUS_EP13_IN_LSB _U(26)
+#define USB_BUFF_STATUS_EP13_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP13_IN_BITS _u(0x04000000)
+#define USB_BUFF_STATUS_EP13_IN_MSB _u(26)
+#define USB_BUFF_STATUS_EP13_IN_LSB _u(26)
#define USB_BUFF_STATUS_EP13_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP12_OUT
// Description : None
-#define USB_BUFF_STATUS_EP12_OUT_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP12_OUT_BITS _U(0x02000000)
-#define USB_BUFF_STATUS_EP12_OUT_MSB _U(25)
-#define USB_BUFF_STATUS_EP12_OUT_LSB _U(25)
+#define USB_BUFF_STATUS_EP12_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP12_OUT_BITS _u(0x02000000)
+#define USB_BUFF_STATUS_EP12_OUT_MSB _u(25)
+#define USB_BUFF_STATUS_EP12_OUT_LSB _u(25)
#define USB_BUFF_STATUS_EP12_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP12_IN
// Description : None
-#define USB_BUFF_STATUS_EP12_IN_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP12_IN_BITS _U(0x01000000)
-#define USB_BUFF_STATUS_EP12_IN_MSB _U(24)
-#define USB_BUFF_STATUS_EP12_IN_LSB _U(24)
+#define USB_BUFF_STATUS_EP12_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP12_IN_BITS _u(0x01000000)
+#define USB_BUFF_STATUS_EP12_IN_MSB _u(24)
+#define USB_BUFF_STATUS_EP12_IN_LSB _u(24)
#define USB_BUFF_STATUS_EP12_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP11_OUT
// Description : None
-#define USB_BUFF_STATUS_EP11_OUT_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP11_OUT_BITS _U(0x00800000)
-#define USB_BUFF_STATUS_EP11_OUT_MSB _U(23)
-#define USB_BUFF_STATUS_EP11_OUT_LSB _U(23)
+#define USB_BUFF_STATUS_EP11_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP11_OUT_BITS _u(0x00800000)
+#define USB_BUFF_STATUS_EP11_OUT_MSB _u(23)
+#define USB_BUFF_STATUS_EP11_OUT_LSB _u(23)
#define USB_BUFF_STATUS_EP11_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP11_IN
// Description : None
-#define USB_BUFF_STATUS_EP11_IN_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP11_IN_BITS _U(0x00400000)
-#define USB_BUFF_STATUS_EP11_IN_MSB _U(22)
-#define USB_BUFF_STATUS_EP11_IN_LSB _U(22)
+#define USB_BUFF_STATUS_EP11_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP11_IN_BITS _u(0x00400000)
+#define USB_BUFF_STATUS_EP11_IN_MSB _u(22)
+#define USB_BUFF_STATUS_EP11_IN_LSB _u(22)
#define USB_BUFF_STATUS_EP11_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP10_OUT
// Description : None
-#define USB_BUFF_STATUS_EP10_OUT_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP10_OUT_BITS _U(0x00200000)
-#define USB_BUFF_STATUS_EP10_OUT_MSB _U(21)
-#define USB_BUFF_STATUS_EP10_OUT_LSB _U(21)
+#define USB_BUFF_STATUS_EP10_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP10_OUT_BITS _u(0x00200000)
+#define USB_BUFF_STATUS_EP10_OUT_MSB _u(21)
+#define USB_BUFF_STATUS_EP10_OUT_LSB _u(21)
#define USB_BUFF_STATUS_EP10_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP10_IN
// Description : None
-#define USB_BUFF_STATUS_EP10_IN_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP10_IN_BITS _U(0x00100000)
-#define USB_BUFF_STATUS_EP10_IN_MSB _U(20)
-#define USB_BUFF_STATUS_EP10_IN_LSB _U(20)
+#define USB_BUFF_STATUS_EP10_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP10_IN_BITS _u(0x00100000)
+#define USB_BUFF_STATUS_EP10_IN_MSB _u(20)
+#define USB_BUFF_STATUS_EP10_IN_LSB _u(20)
#define USB_BUFF_STATUS_EP10_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP9_OUT
// Description : None
-#define USB_BUFF_STATUS_EP9_OUT_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP9_OUT_BITS _U(0x00080000)
-#define USB_BUFF_STATUS_EP9_OUT_MSB _U(19)
-#define USB_BUFF_STATUS_EP9_OUT_LSB _U(19)
+#define USB_BUFF_STATUS_EP9_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP9_OUT_BITS _u(0x00080000)
+#define USB_BUFF_STATUS_EP9_OUT_MSB _u(19)
+#define USB_BUFF_STATUS_EP9_OUT_LSB _u(19)
#define USB_BUFF_STATUS_EP9_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP9_IN
// Description : None
-#define USB_BUFF_STATUS_EP9_IN_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP9_IN_BITS _U(0x00040000)
-#define USB_BUFF_STATUS_EP9_IN_MSB _U(18)
-#define USB_BUFF_STATUS_EP9_IN_LSB _U(18)
+#define USB_BUFF_STATUS_EP9_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP9_IN_BITS _u(0x00040000)
+#define USB_BUFF_STATUS_EP9_IN_MSB _u(18)
+#define USB_BUFF_STATUS_EP9_IN_LSB _u(18)
#define USB_BUFF_STATUS_EP9_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP8_OUT
// Description : None
-#define USB_BUFF_STATUS_EP8_OUT_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP8_OUT_BITS _U(0x00020000)
-#define USB_BUFF_STATUS_EP8_OUT_MSB _U(17)
-#define USB_BUFF_STATUS_EP8_OUT_LSB _U(17)
+#define USB_BUFF_STATUS_EP8_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP8_OUT_BITS _u(0x00020000)
+#define USB_BUFF_STATUS_EP8_OUT_MSB _u(17)
+#define USB_BUFF_STATUS_EP8_OUT_LSB _u(17)
#define USB_BUFF_STATUS_EP8_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP8_IN
// Description : None
-#define USB_BUFF_STATUS_EP8_IN_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP8_IN_BITS _U(0x00010000)
-#define USB_BUFF_STATUS_EP8_IN_MSB _U(16)
-#define USB_BUFF_STATUS_EP8_IN_LSB _U(16)
+#define USB_BUFF_STATUS_EP8_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP8_IN_BITS _u(0x00010000)
+#define USB_BUFF_STATUS_EP8_IN_MSB _u(16)
+#define USB_BUFF_STATUS_EP8_IN_LSB _u(16)
#define USB_BUFF_STATUS_EP8_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP7_OUT
// Description : None
-#define USB_BUFF_STATUS_EP7_OUT_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP7_OUT_BITS _U(0x00008000)
-#define USB_BUFF_STATUS_EP7_OUT_MSB _U(15)
-#define USB_BUFF_STATUS_EP7_OUT_LSB _U(15)
+#define USB_BUFF_STATUS_EP7_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP7_OUT_BITS _u(0x00008000)
+#define USB_BUFF_STATUS_EP7_OUT_MSB _u(15)
+#define USB_BUFF_STATUS_EP7_OUT_LSB _u(15)
#define USB_BUFF_STATUS_EP7_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP7_IN
// Description : None
-#define USB_BUFF_STATUS_EP7_IN_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP7_IN_BITS _U(0x00004000)
-#define USB_BUFF_STATUS_EP7_IN_MSB _U(14)
-#define USB_BUFF_STATUS_EP7_IN_LSB _U(14)
+#define USB_BUFF_STATUS_EP7_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP7_IN_BITS _u(0x00004000)
+#define USB_BUFF_STATUS_EP7_IN_MSB _u(14)
+#define USB_BUFF_STATUS_EP7_IN_LSB _u(14)
#define USB_BUFF_STATUS_EP7_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP6_OUT
// Description : None
-#define USB_BUFF_STATUS_EP6_OUT_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP6_OUT_BITS _U(0x00002000)
-#define USB_BUFF_STATUS_EP6_OUT_MSB _U(13)
-#define USB_BUFF_STATUS_EP6_OUT_LSB _U(13)
+#define USB_BUFF_STATUS_EP6_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP6_OUT_BITS _u(0x00002000)
+#define USB_BUFF_STATUS_EP6_OUT_MSB _u(13)
+#define USB_BUFF_STATUS_EP6_OUT_LSB _u(13)
#define USB_BUFF_STATUS_EP6_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP6_IN
// Description : None
-#define USB_BUFF_STATUS_EP6_IN_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP6_IN_BITS _U(0x00001000)
-#define USB_BUFF_STATUS_EP6_IN_MSB _U(12)
-#define USB_BUFF_STATUS_EP6_IN_LSB _U(12)
+#define USB_BUFF_STATUS_EP6_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP6_IN_BITS _u(0x00001000)
+#define USB_BUFF_STATUS_EP6_IN_MSB _u(12)
+#define USB_BUFF_STATUS_EP6_IN_LSB _u(12)
#define USB_BUFF_STATUS_EP6_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP5_OUT
// Description : None
-#define USB_BUFF_STATUS_EP5_OUT_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP5_OUT_BITS _U(0x00000800)
-#define USB_BUFF_STATUS_EP5_OUT_MSB _U(11)
-#define USB_BUFF_STATUS_EP5_OUT_LSB _U(11)
+#define USB_BUFF_STATUS_EP5_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP5_OUT_BITS _u(0x00000800)
+#define USB_BUFF_STATUS_EP5_OUT_MSB _u(11)
+#define USB_BUFF_STATUS_EP5_OUT_LSB _u(11)
#define USB_BUFF_STATUS_EP5_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP5_IN
// Description : None
-#define USB_BUFF_STATUS_EP5_IN_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP5_IN_BITS _U(0x00000400)
-#define USB_BUFF_STATUS_EP5_IN_MSB _U(10)
-#define USB_BUFF_STATUS_EP5_IN_LSB _U(10)
+#define USB_BUFF_STATUS_EP5_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP5_IN_BITS _u(0x00000400)
+#define USB_BUFF_STATUS_EP5_IN_MSB _u(10)
+#define USB_BUFF_STATUS_EP5_IN_LSB _u(10)
#define USB_BUFF_STATUS_EP5_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP4_OUT
// Description : None
-#define USB_BUFF_STATUS_EP4_OUT_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP4_OUT_BITS _U(0x00000200)
-#define USB_BUFF_STATUS_EP4_OUT_MSB _U(9)
-#define USB_BUFF_STATUS_EP4_OUT_LSB _U(9)
+#define USB_BUFF_STATUS_EP4_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP4_OUT_BITS _u(0x00000200)
+#define USB_BUFF_STATUS_EP4_OUT_MSB _u(9)
+#define USB_BUFF_STATUS_EP4_OUT_LSB _u(9)
#define USB_BUFF_STATUS_EP4_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP4_IN
// Description : None
-#define USB_BUFF_STATUS_EP4_IN_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP4_IN_BITS _U(0x00000100)
-#define USB_BUFF_STATUS_EP4_IN_MSB _U(8)
-#define USB_BUFF_STATUS_EP4_IN_LSB _U(8)
+#define USB_BUFF_STATUS_EP4_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP4_IN_BITS _u(0x00000100)
+#define USB_BUFF_STATUS_EP4_IN_MSB _u(8)
+#define USB_BUFF_STATUS_EP4_IN_LSB _u(8)
#define USB_BUFF_STATUS_EP4_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP3_OUT
// Description : None
-#define USB_BUFF_STATUS_EP3_OUT_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP3_OUT_BITS _U(0x00000080)
-#define USB_BUFF_STATUS_EP3_OUT_MSB _U(7)
-#define USB_BUFF_STATUS_EP3_OUT_LSB _U(7)
+#define USB_BUFF_STATUS_EP3_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP3_OUT_BITS _u(0x00000080)
+#define USB_BUFF_STATUS_EP3_OUT_MSB _u(7)
+#define USB_BUFF_STATUS_EP3_OUT_LSB _u(7)
#define USB_BUFF_STATUS_EP3_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP3_IN
// Description : None
-#define USB_BUFF_STATUS_EP3_IN_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP3_IN_BITS _U(0x00000040)
-#define USB_BUFF_STATUS_EP3_IN_MSB _U(6)
-#define USB_BUFF_STATUS_EP3_IN_LSB _U(6)
+#define USB_BUFF_STATUS_EP3_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP3_IN_BITS _u(0x00000040)
+#define USB_BUFF_STATUS_EP3_IN_MSB _u(6)
+#define USB_BUFF_STATUS_EP3_IN_LSB _u(6)
#define USB_BUFF_STATUS_EP3_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP2_OUT
// Description : None
-#define USB_BUFF_STATUS_EP2_OUT_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP2_OUT_BITS _U(0x00000020)
-#define USB_BUFF_STATUS_EP2_OUT_MSB _U(5)
-#define USB_BUFF_STATUS_EP2_OUT_LSB _U(5)
+#define USB_BUFF_STATUS_EP2_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP2_OUT_BITS _u(0x00000020)
+#define USB_BUFF_STATUS_EP2_OUT_MSB _u(5)
+#define USB_BUFF_STATUS_EP2_OUT_LSB _u(5)
#define USB_BUFF_STATUS_EP2_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP2_IN
// Description : None
-#define USB_BUFF_STATUS_EP2_IN_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP2_IN_BITS _U(0x00000010)
-#define USB_BUFF_STATUS_EP2_IN_MSB _U(4)
-#define USB_BUFF_STATUS_EP2_IN_LSB _U(4)
+#define USB_BUFF_STATUS_EP2_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP2_IN_BITS _u(0x00000010)
+#define USB_BUFF_STATUS_EP2_IN_MSB _u(4)
+#define USB_BUFF_STATUS_EP2_IN_LSB _u(4)
#define USB_BUFF_STATUS_EP2_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP1_OUT
// Description : None
-#define USB_BUFF_STATUS_EP1_OUT_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP1_OUT_BITS _U(0x00000008)
-#define USB_BUFF_STATUS_EP1_OUT_MSB _U(3)
-#define USB_BUFF_STATUS_EP1_OUT_LSB _U(3)
+#define USB_BUFF_STATUS_EP1_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP1_OUT_BITS _u(0x00000008)
+#define USB_BUFF_STATUS_EP1_OUT_MSB _u(3)
+#define USB_BUFF_STATUS_EP1_OUT_LSB _u(3)
#define USB_BUFF_STATUS_EP1_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP1_IN
// Description : None
-#define USB_BUFF_STATUS_EP1_IN_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP1_IN_BITS _U(0x00000004)
-#define USB_BUFF_STATUS_EP1_IN_MSB _U(2)
-#define USB_BUFF_STATUS_EP1_IN_LSB _U(2)
+#define USB_BUFF_STATUS_EP1_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP1_IN_BITS _u(0x00000004)
+#define USB_BUFF_STATUS_EP1_IN_MSB _u(2)
+#define USB_BUFF_STATUS_EP1_IN_LSB _u(2)
#define USB_BUFF_STATUS_EP1_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP0_OUT
// Description : None
-#define USB_BUFF_STATUS_EP0_OUT_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP0_OUT_BITS _U(0x00000002)
-#define USB_BUFF_STATUS_EP0_OUT_MSB _U(1)
-#define USB_BUFF_STATUS_EP0_OUT_LSB _U(1)
+#define USB_BUFF_STATUS_EP0_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP0_OUT_BITS _u(0x00000002)
+#define USB_BUFF_STATUS_EP0_OUT_MSB _u(1)
+#define USB_BUFF_STATUS_EP0_OUT_LSB _u(1)
#define USB_BUFF_STATUS_EP0_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_STATUS_EP0_IN
// Description : None
-#define USB_BUFF_STATUS_EP0_IN_RESET _U(0x0)
-#define USB_BUFF_STATUS_EP0_IN_BITS _U(0x00000001)
-#define USB_BUFF_STATUS_EP0_IN_MSB _U(0)
-#define USB_BUFF_STATUS_EP0_IN_LSB _U(0)
+#define USB_BUFF_STATUS_EP0_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP0_IN_BITS _u(0x00000001)
+#define USB_BUFF_STATUS_EP0_IN_MSB _u(0)
+#define USB_BUFF_STATUS_EP0_IN_LSB _u(0)
#define USB_BUFF_STATUS_EP0_IN_ACCESS "WC"
// =============================================================================
// Register : USB_BUFF_CPU_SHOULD_HANDLE
@@ -1350,264 +1350,264 @@
// using an interrupt per buffer (i.e. not per 2 buffers). Not
// valid for host interrupt endpoint polling because they are only
// single buffered.
-#define USB_BUFF_CPU_SHOULD_HANDLE_OFFSET _U(0x0000005c)
-#define USB_BUFF_CPU_SHOULD_HANDLE_BITS _U(0xffffffff)
-#define USB_BUFF_CPU_SHOULD_HANDLE_RESET _U(0x00000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_OFFSET _u(0x0000005c)
+#define USB_BUFF_CPU_SHOULD_HANDLE_BITS _u(0xffffffff)
+#define USB_BUFF_CPU_SHOULD_HANDLE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS _U(0x80000000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB _U(31)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_LSB _U(31)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS _u(0x80000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB _u(31)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_LSB _u(31)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS _U(0x40000000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB _U(30)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_LSB _U(30)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS _u(0x40000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB _u(30)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_LSB _u(30)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS _U(0x20000000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB _U(29)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_LSB _U(29)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS _u(0x20000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB _u(29)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_LSB _u(29)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS _U(0x10000000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB _U(28)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_LSB _U(28)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS _u(0x10000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB _u(28)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_LSB _u(28)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS _U(0x08000000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB _U(27)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_LSB _U(27)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS _u(0x08000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB _u(27)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_LSB _u(27)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS _U(0x04000000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB _U(26)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_LSB _U(26)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS _u(0x04000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB _u(26)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_LSB _u(26)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS _U(0x02000000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB _U(25)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_LSB _U(25)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS _u(0x02000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB _u(25)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_LSB _u(25)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS _U(0x01000000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB _U(24)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_LSB _U(24)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS _u(0x01000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB _u(24)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_LSB _u(24)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS _U(0x00800000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB _U(23)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_LSB _U(23)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS _u(0x00800000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB _u(23)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_LSB _u(23)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS _U(0x00400000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB _U(22)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_LSB _U(22)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS _u(0x00400000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB _u(22)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_LSB _u(22)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS _U(0x00200000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB _U(21)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_LSB _U(21)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS _u(0x00200000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB _u(21)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_LSB _u(21)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS _U(0x00100000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB _U(20)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_LSB _U(20)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS _u(0x00100000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB _u(20)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_LSB _u(20)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS _U(0x00080000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB _U(19)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_LSB _U(19)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS _u(0x00080000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB _u(19)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_LSB _u(19)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS _U(0x00040000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB _U(18)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_LSB _U(18)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS _u(0x00040000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB _u(18)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_LSB _u(18)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS _U(0x00020000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB _U(17)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_LSB _U(17)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS _u(0x00020000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB _u(17)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_LSB _u(17)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS _U(0x00010000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB _U(16)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_LSB _U(16)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS _u(0x00010000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB _u(16)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_LSB _u(16)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS _U(0x00008000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB _U(15)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_LSB _U(15)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS _u(0x00008000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB _u(15)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_LSB _u(15)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS _U(0x00004000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB _U(14)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_LSB _U(14)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS _u(0x00004000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB _u(14)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_LSB _u(14)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS _U(0x00002000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB _U(13)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_LSB _U(13)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS _u(0x00002000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB _u(13)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_LSB _u(13)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS _U(0x00001000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB _U(12)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_LSB _U(12)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS _u(0x00001000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB _u(12)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_LSB _u(12)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS _U(0x00000800)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB _U(11)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_LSB _U(11)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS _u(0x00000800)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB _u(11)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_LSB _u(11)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS _U(0x00000400)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB _U(10)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_LSB _U(10)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS _u(0x00000400)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB _u(10)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_LSB _u(10)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS _U(0x00000200)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB _U(9)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_LSB _U(9)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS _u(0x00000200)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB _u(9)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_LSB _u(9)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS _U(0x00000100)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB _U(8)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_LSB _U(8)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS _u(0x00000100)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB _u(8)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_LSB _u(8)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS _U(0x00000080)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB _U(7)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_LSB _U(7)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS _u(0x00000080)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB _u(7)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_LSB _u(7)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS _U(0x00000040)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB _U(6)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_LSB _U(6)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS _u(0x00000040)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB _u(6)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_LSB _u(6)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS _U(0x00000020)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB _U(5)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_LSB _U(5)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS _u(0x00000020)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB _u(5)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_LSB _u(5)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS _U(0x00000010)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB _U(4)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_LSB _U(4)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS _u(0x00000010)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB _u(4)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_LSB _u(4)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS _U(0x00000008)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB _U(3)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_LSB _U(3)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS _u(0x00000008)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB _u(3)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_LSB _u(3)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS _U(0x00000004)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB _U(2)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_LSB _U(2)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS _u(0x00000004)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB _u(2)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_LSB _u(2)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS _U(0x00000002)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB _U(1)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_LSB _U(1)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS _u(0x00000002)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB _u(1)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_LSB _u(1)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN
// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET _U(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS _U(0x00000001)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB _U(0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_LSB _U(0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS _u(0x00000001)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB _u(0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_LSB _u(0)
#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_ACCESS "RO"
// =============================================================================
// Register : USB_EP_ABORT
@@ -1616,528 +1616,528 @@
// NAK will be sent for every access to the endpoint until this
// bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set
// when it is safe to modify the buffer control register.
-#define USB_EP_ABORT_OFFSET _U(0x00000060)
-#define USB_EP_ABORT_BITS _U(0xffffffff)
-#define USB_EP_ABORT_RESET _U(0x00000000)
+#define USB_EP_ABORT_OFFSET _u(0x00000060)
+#define USB_EP_ABORT_BITS _u(0xffffffff)
+#define USB_EP_ABORT_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP15_OUT
// Description : None
-#define USB_EP_ABORT_EP15_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_EP15_OUT_BITS _U(0x80000000)
-#define USB_EP_ABORT_EP15_OUT_MSB _U(31)
-#define USB_EP_ABORT_EP15_OUT_LSB _U(31)
+#define USB_EP_ABORT_EP15_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP15_OUT_BITS _u(0x80000000)
+#define USB_EP_ABORT_EP15_OUT_MSB _u(31)
+#define USB_EP_ABORT_EP15_OUT_LSB _u(31)
#define USB_EP_ABORT_EP15_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP15_IN
// Description : None
-#define USB_EP_ABORT_EP15_IN_RESET _U(0x0)
-#define USB_EP_ABORT_EP15_IN_BITS _U(0x40000000)
-#define USB_EP_ABORT_EP15_IN_MSB _U(30)
-#define USB_EP_ABORT_EP15_IN_LSB _U(30)
+#define USB_EP_ABORT_EP15_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP15_IN_BITS _u(0x40000000)
+#define USB_EP_ABORT_EP15_IN_MSB _u(30)
+#define USB_EP_ABORT_EP15_IN_LSB _u(30)
#define USB_EP_ABORT_EP15_IN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP14_OUT
// Description : None
-#define USB_EP_ABORT_EP14_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_EP14_OUT_BITS _U(0x20000000)
-#define USB_EP_ABORT_EP14_OUT_MSB _U(29)
-#define USB_EP_ABORT_EP14_OUT_LSB _U(29)
+#define USB_EP_ABORT_EP14_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP14_OUT_BITS _u(0x20000000)
+#define USB_EP_ABORT_EP14_OUT_MSB _u(29)
+#define USB_EP_ABORT_EP14_OUT_LSB _u(29)
#define USB_EP_ABORT_EP14_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP14_IN
// Description : None
-#define USB_EP_ABORT_EP14_IN_RESET _U(0x0)
-#define USB_EP_ABORT_EP14_IN_BITS _U(0x10000000)
-#define USB_EP_ABORT_EP14_IN_MSB _U(28)
-#define USB_EP_ABORT_EP14_IN_LSB _U(28)
+#define USB_EP_ABORT_EP14_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP14_IN_BITS _u(0x10000000)
+#define USB_EP_ABORT_EP14_IN_MSB _u(28)
+#define USB_EP_ABORT_EP14_IN_LSB _u(28)
#define USB_EP_ABORT_EP14_IN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP13_OUT
// Description : None
-#define USB_EP_ABORT_EP13_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_EP13_OUT_BITS _U(0x08000000)
-#define USB_EP_ABORT_EP13_OUT_MSB _U(27)
-#define USB_EP_ABORT_EP13_OUT_LSB _U(27)
+#define USB_EP_ABORT_EP13_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP13_OUT_BITS _u(0x08000000)
+#define USB_EP_ABORT_EP13_OUT_MSB _u(27)
+#define USB_EP_ABORT_EP13_OUT_LSB _u(27)
#define USB_EP_ABORT_EP13_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP13_IN
// Description : None
-#define USB_EP_ABORT_EP13_IN_RESET _U(0x0)
-#define USB_EP_ABORT_EP13_IN_BITS _U(0x04000000)
-#define USB_EP_ABORT_EP13_IN_MSB _U(26)
-#define USB_EP_ABORT_EP13_IN_LSB _U(26)
+#define USB_EP_ABORT_EP13_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP13_IN_BITS _u(0x04000000)
+#define USB_EP_ABORT_EP13_IN_MSB _u(26)
+#define USB_EP_ABORT_EP13_IN_LSB _u(26)
#define USB_EP_ABORT_EP13_IN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP12_OUT
// Description : None
-#define USB_EP_ABORT_EP12_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_EP12_OUT_BITS _U(0x02000000)
-#define USB_EP_ABORT_EP12_OUT_MSB _U(25)
-#define USB_EP_ABORT_EP12_OUT_LSB _U(25)
+#define USB_EP_ABORT_EP12_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP12_OUT_BITS _u(0x02000000)
+#define USB_EP_ABORT_EP12_OUT_MSB _u(25)
+#define USB_EP_ABORT_EP12_OUT_LSB _u(25)
#define USB_EP_ABORT_EP12_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP12_IN
// Description : None
-#define USB_EP_ABORT_EP12_IN_RESET _U(0x0)
-#define USB_EP_ABORT_EP12_IN_BITS _U(0x01000000)
-#define USB_EP_ABORT_EP12_IN_MSB _U(24)
-#define USB_EP_ABORT_EP12_IN_LSB _U(24)
+#define USB_EP_ABORT_EP12_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP12_IN_BITS _u(0x01000000)
+#define USB_EP_ABORT_EP12_IN_MSB _u(24)
+#define USB_EP_ABORT_EP12_IN_LSB _u(24)
#define USB_EP_ABORT_EP12_IN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP11_OUT
// Description : None
-#define USB_EP_ABORT_EP11_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_EP11_OUT_BITS _U(0x00800000)
-#define USB_EP_ABORT_EP11_OUT_MSB _U(23)
-#define USB_EP_ABORT_EP11_OUT_LSB _U(23)
+#define USB_EP_ABORT_EP11_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP11_OUT_BITS _u(0x00800000)
+#define USB_EP_ABORT_EP11_OUT_MSB _u(23)
+#define USB_EP_ABORT_EP11_OUT_LSB _u(23)
#define USB_EP_ABORT_EP11_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP11_IN
// Description : None
-#define USB_EP_ABORT_EP11_IN_RESET _U(0x0)
-#define USB_EP_ABORT_EP11_IN_BITS _U(0x00400000)
-#define USB_EP_ABORT_EP11_IN_MSB _U(22)
-#define USB_EP_ABORT_EP11_IN_LSB _U(22)
+#define USB_EP_ABORT_EP11_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP11_IN_BITS _u(0x00400000)
+#define USB_EP_ABORT_EP11_IN_MSB _u(22)
+#define USB_EP_ABORT_EP11_IN_LSB _u(22)
#define USB_EP_ABORT_EP11_IN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP10_OUT
// Description : None
-#define USB_EP_ABORT_EP10_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_EP10_OUT_BITS _U(0x00200000)
-#define USB_EP_ABORT_EP10_OUT_MSB _U(21)
-#define USB_EP_ABORT_EP10_OUT_LSB _U(21)
+#define USB_EP_ABORT_EP10_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP10_OUT_BITS _u(0x00200000)
+#define USB_EP_ABORT_EP10_OUT_MSB _u(21)
+#define USB_EP_ABORT_EP10_OUT_LSB _u(21)
#define USB_EP_ABORT_EP10_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP10_IN
// Description : None
-#define USB_EP_ABORT_EP10_IN_RESET _U(0x0)
-#define USB_EP_ABORT_EP10_IN_BITS _U(0x00100000)
-#define USB_EP_ABORT_EP10_IN_MSB _U(20)
-#define USB_EP_ABORT_EP10_IN_LSB _U(20)
+#define USB_EP_ABORT_EP10_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP10_IN_BITS _u(0x00100000)
+#define USB_EP_ABORT_EP10_IN_MSB _u(20)
+#define USB_EP_ABORT_EP10_IN_LSB _u(20)
#define USB_EP_ABORT_EP10_IN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP9_OUT
// Description : None
-#define USB_EP_ABORT_EP9_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_EP9_OUT_BITS _U(0x00080000)
-#define USB_EP_ABORT_EP9_OUT_MSB _U(19)
-#define USB_EP_ABORT_EP9_OUT_LSB _U(19)
+#define USB_EP_ABORT_EP9_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP9_OUT_BITS _u(0x00080000)
+#define USB_EP_ABORT_EP9_OUT_MSB _u(19)
+#define USB_EP_ABORT_EP9_OUT_LSB _u(19)
#define USB_EP_ABORT_EP9_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP9_IN
// Description : None
-#define USB_EP_ABORT_EP9_IN_RESET _U(0x0)
-#define USB_EP_ABORT_EP9_IN_BITS _U(0x00040000)
-#define USB_EP_ABORT_EP9_IN_MSB _U(18)
-#define USB_EP_ABORT_EP9_IN_LSB _U(18)
+#define USB_EP_ABORT_EP9_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP9_IN_BITS _u(0x00040000)
+#define USB_EP_ABORT_EP9_IN_MSB _u(18)
+#define USB_EP_ABORT_EP9_IN_LSB _u(18)
#define USB_EP_ABORT_EP9_IN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP8_OUT
// Description : None
-#define USB_EP_ABORT_EP8_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_EP8_OUT_BITS _U(0x00020000)
-#define USB_EP_ABORT_EP8_OUT_MSB _U(17)
-#define USB_EP_ABORT_EP8_OUT_LSB _U(17)
+#define USB_EP_ABORT_EP8_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP8_OUT_BITS _u(0x00020000)
+#define USB_EP_ABORT_EP8_OUT_MSB _u(17)
+#define USB_EP_ABORT_EP8_OUT_LSB _u(17)
#define USB_EP_ABORT_EP8_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP8_IN
// Description : None
-#define USB_EP_ABORT_EP8_IN_RESET _U(0x0)
-#define USB_EP_ABORT_EP8_IN_BITS _U(0x00010000)
-#define USB_EP_ABORT_EP8_IN_MSB _U(16)
-#define USB_EP_ABORT_EP8_IN_LSB _U(16)
+#define USB_EP_ABORT_EP8_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP8_IN_BITS _u(0x00010000)
+#define USB_EP_ABORT_EP8_IN_MSB _u(16)
+#define USB_EP_ABORT_EP8_IN_LSB _u(16)
#define USB_EP_ABORT_EP8_IN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP7_OUT
// Description : None
-#define USB_EP_ABORT_EP7_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_EP7_OUT_BITS _U(0x00008000)
-#define USB_EP_ABORT_EP7_OUT_MSB _U(15)
-#define USB_EP_ABORT_EP7_OUT_LSB _U(15)
+#define USB_EP_ABORT_EP7_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP7_OUT_BITS _u(0x00008000)
+#define USB_EP_ABORT_EP7_OUT_MSB _u(15)
+#define USB_EP_ABORT_EP7_OUT_LSB _u(15)
#define USB_EP_ABORT_EP7_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP7_IN
// Description : None
-#define USB_EP_ABORT_EP7_IN_RESET _U(0x0)
-#define USB_EP_ABORT_EP7_IN_BITS _U(0x00004000)
-#define USB_EP_ABORT_EP7_IN_MSB _U(14)
-#define USB_EP_ABORT_EP7_IN_LSB _U(14)
+#define USB_EP_ABORT_EP7_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP7_IN_BITS _u(0x00004000)
+#define USB_EP_ABORT_EP7_IN_MSB _u(14)
+#define USB_EP_ABORT_EP7_IN_LSB _u(14)
#define USB_EP_ABORT_EP7_IN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP6_OUT
// Description : None
-#define USB_EP_ABORT_EP6_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_EP6_OUT_BITS _U(0x00002000)
-#define USB_EP_ABORT_EP6_OUT_MSB _U(13)
-#define USB_EP_ABORT_EP6_OUT_LSB _U(13)
+#define USB_EP_ABORT_EP6_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP6_OUT_BITS _u(0x00002000)
+#define USB_EP_ABORT_EP6_OUT_MSB _u(13)
+#define USB_EP_ABORT_EP6_OUT_LSB _u(13)
#define USB_EP_ABORT_EP6_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP6_IN
// Description : None
-#define USB_EP_ABORT_EP6_IN_RESET _U(0x0)
-#define USB_EP_ABORT_EP6_IN_BITS _U(0x00001000)
-#define USB_EP_ABORT_EP6_IN_MSB _U(12)
-#define USB_EP_ABORT_EP6_IN_LSB _U(12)
+#define USB_EP_ABORT_EP6_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP6_IN_BITS _u(0x00001000)
+#define USB_EP_ABORT_EP6_IN_MSB _u(12)
+#define USB_EP_ABORT_EP6_IN_LSB _u(12)
#define USB_EP_ABORT_EP6_IN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP5_OUT
// Description : None
-#define USB_EP_ABORT_EP5_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_EP5_OUT_BITS _U(0x00000800)
-#define USB_EP_ABORT_EP5_OUT_MSB _U(11)
-#define USB_EP_ABORT_EP5_OUT_LSB _U(11)
+#define USB_EP_ABORT_EP5_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP5_OUT_BITS _u(0x00000800)
+#define USB_EP_ABORT_EP5_OUT_MSB _u(11)
+#define USB_EP_ABORT_EP5_OUT_LSB _u(11)
#define USB_EP_ABORT_EP5_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP5_IN
// Description : None
-#define USB_EP_ABORT_EP5_IN_RESET _U(0x0)
-#define USB_EP_ABORT_EP5_IN_BITS _U(0x00000400)
-#define USB_EP_ABORT_EP5_IN_MSB _U(10)
-#define USB_EP_ABORT_EP5_IN_LSB _U(10)
+#define USB_EP_ABORT_EP5_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP5_IN_BITS _u(0x00000400)
+#define USB_EP_ABORT_EP5_IN_MSB _u(10)
+#define USB_EP_ABORT_EP5_IN_LSB _u(10)
#define USB_EP_ABORT_EP5_IN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP4_OUT
// Description : None
-#define USB_EP_ABORT_EP4_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_EP4_OUT_BITS _U(0x00000200)
-#define USB_EP_ABORT_EP4_OUT_MSB _U(9)
-#define USB_EP_ABORT_EP4_OUT_LSB _U(9)
+#define USB_EP_ABORT_EP4_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP4_OUT_BITS _u(0x00000200)
+#define USB_EP_ABORT_EP4_OUT_MSB _u(9)
+#define USB_EP_ABORT_EP4_OUT_LSB _u(9)
#define USB_EP_ABORT_EP4_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP4_IN
// Description : None
-#define USB_EP_ABORT_EP4_IN_RESET _U(0x0)
-#define USB_EP_ABORT_EP4_IN_BITS _U(0x00000100)
-#define USB_EP_ABORT_EP4_IN_MSB _U(8)
-#define USB_EP_ABORT_EP4_IN_LSB _U(8)
+#define USB_EP_ABORT_EP4_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP4_IN_BITS _u(0x00000100)
+#define USB_EP_ABORT_EP4_IN_MSB _u(8)
+#define USB_EP_ABORT_EP4_IN_LSB _u(8)
#define USB_EP_ABORT_EP4_IN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP3_OUT
// Description : None
-#define USB_EP_ABORT_EP3_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_EP3_OUT_BITS _U(0x00000080)
-#define USB_EP_ABORT_EP3_OUT_MSB _U(7)
-#define USB_EP_ABORT_EP3_OUT_LSB _U(7)
+#define USB_EP_ABORT_EP3_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP3_OUT_BITS _u(0x00000080)
+#define USB_EP_ABORT_EP3_OUT_MSB _u(7)
+#define USB_EP_ABORT_EP3_OUT_LSB _u(7)
#define USB_EP_ABORT_EP3_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP3_IN
// Description : None
-#define USB_EP_ABORT_EP3_IN_RESET _U(0x0)
-#define USB_EP_ABORT_EP3_IN_BITS _U(0x00000040)
-#define USB_EP_ABORT_EP3_IN_MSB _U(6)
-#define USB_EP_ABORT_EP3_IN_LSB _U(6)
+#define USB_EP_ABORT_EP3_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP3_IN_BITS _u(0x00000040)
+#define USB_EP_ABORT_EP3_IN_MSB _u(6)
+#define USB_EP_ABORT_EP3_IN_LSB _u(6)
#define USB_EP_ABORT_EP3_IN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP2_OUT
// Description : None
-#define USB_EP_ABORT_EP2_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_EP2_OUT_BITS _U(0x00000020)
-#define USB_EP_ABORT_EP2_OUT_MSB _U(5)
-#define USB_EP_ABORT_EP2_OUT_LSB _U(5)
+#define USB_EP_ABORT_EP2_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP2_OUT_BITS _u(0x00000020)
+#define USB_EP_ABORT_EP2_OUT_MSB _u(5)
+#define USB_EP_ABORT_EP2_OUT_LSB _u(5)
#define USB_EP_ABORT_EP2_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP2_IN
// Description : None
-#define USB_EP_ABORT_EP2_IN_RESET _U(0x0)
-#define USB_EP_ABORT_EP2_IN_BITS _U(0x00000010)
-#define USB_EP_ABORT_EP2_IN_MSB _U(4)
-#define USB_EP_ABORT_EP2_IN_LSB _U(4)
+#define USB_EP_ABORT_EP2_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP2_IN_BITS _u(0x00000010)
+#define USB_EP_ABORT_EP2_IN_MSB _u(4)
+#define USB_EP_ABORT_EP2_IN_LSB _u(4)
#define USB_EP_ABORT_EP2_IN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP1_OUT
// Description : None
-#define USB_EP_ABORT_EP1_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_EP1_OUT_BITS _U(0x00000008)
-#define USB_EP_ABORT_EP1_OUT_MSB _U(3)
-#define USB_EP_ABORT_EP1_OUT_LSB _U(3)
+#define USB_EP_ABORT_EP1_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP1_OUT_BITS _u(0x00000008)
+#define USB_EP_ABORT_EP1_OUT_MSB _u(3)
+#define USB_EP_ABORT_EP1_OUT_LSB _u(3)
#define USB_EP_ABORT_EP1_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP1_IN
// Description : None
-#define USB_EP_ABORT_EP1_IN_RESET _U(0x0)
-#define USB_EP_ABORT_EP1_IN_BITS _U(0x00000004)
-#define USB_EP_ABORT_EP1_IN_MSB _U(2)
-#define USB_EP_ABORT_EP1_IN_LSB _U(2)
+#define USB_EP_ABORT_EP1_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP1_IN_BITS _u(0x00000004)
+#define USB_EP_ABORT_EP1_IN_MSB _u(2)
+#define USB_EP_ABORT_EP1_IN_LSB _u(2)
#define USB_EP_ABORT_EP1_IN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP0_OUT
// Description : None
-#define USB_EP_ABORT_EP0_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_EP0_OUT_BITS _U(0x00000002)
-#define USB_EP_ABORT_EP0_OUT_MSB _U(1)
-#define USB_EP_ABORT_EP0_OUT_LSB _U(1)
+#define USB_EP_ABORT_EP0_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP0_OUT_BITS _u(0x00000002)
+#define USB_EP_ABORT_EP0_OUT_MSB _u(1)
+#define USB_EP_ABORT_EP0_OUT_LSB _u(1)
#define USB_EP_ABORT_EP0_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_EP0_IN
// Description : None
-#define USB_EP_ABORT_EP0_IN_RESET _U(0x0)
-#define USB_EP_ABORT_EP0_IN_BITS _U(0x00000001)
-#define USB_EP_ABORT_EP0_IN_MSB _U(0)
-#define USB_EP_ABORT_EP0_IN_LSB _U(0)
+#define USB_EP_ABORT_EP0_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP0_IN_BITS _u(0x00000001)
+#define USB_EP_ABORT_EP0_IN_MSB _u(0)
+#define USB_EP_ABORT_EP0_IN_LSB _u(0)
#define USB_EP_ABORT_EP0_IN_ACCESS "RW"
// =============================================================================
// Register : USB_EP_ABORT_DONE
// Description : Device only: Used in conjunction with `EP_ABORT`. Set once an
// endpoint is idle so the programmer knows it is safe to modify
// the buffer control register.
-#define USB_EP_ABORT_DONE_OFFSET _U(0x00000064)
-#define USB_EP_ABORT_DONE_BITS _U(0xffffffff)
-#define USB_EP_ABORT_DONE_RESET _U(0x00000000)
+#define USB_EP_ABORT_DONE_OFFSET _u(0x00000064)
+#define USB_EP_ABORT_DONE_BITS _u(0xffffffff)
+#define USB_EP_ABORT_DONE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP15_OUT
// Description : None
-#define USB_EP_ABORT_DONE_EP15_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP15_OUT_BITS _U(0x80000000)
-#define USB_EP_ABORT_DONE_EP15_OUT_MSB _U(31)
-#define USB_EP_ABORT_DONE_EP15_OUT_LSB _U(31)
+#define USB_EP_ABORT_DONE_EP15_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP15_OUT_BITS _u(0x80000000)
+#define USB_EP_ABORT_DONE_EP15_OUT_MSB _u(31)
+#define USB_EP_ABORT_DONE_EP15_OUT_LSB _u(31)
#define USB_EP_ABORT_DONE_EP15_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP15_IN
// Description : None
-#define USB_EP_ABORT_DONE_EP15_IN_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP15_IN_BITS _U(0x40000000)
-#define USB_EP_ABORT_DONE_EP15_IN_MSB _U(30)
-#define USB_EP_ABORT_DONE_EP15_IN_LSB _U(30)
+#define USB_EP_ABORT_DONE_EP15_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP15_IN_BITS _u(0x40000000)
+#define USB_EP_ABORT_DONE_EP15_IN_MSB _u(30)
+#define USB_EP_ABORT_DONE_EP15_IN_LSB _u(30)
#define USB_EP_ABORT_DONE_EP15_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP14_OUT
// Description : None
-#define USB_EP_ABORT_DONE_EP14_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP14_OUT_BITS _U(0x20000000)
-#define USB_EP_ABORT_DONE_EP14_OUT_MSB _U(29)
-#define USB_EP_ABORT_DONE_EP14_OUT_LSB _U(29)
+#define USB_EP_ABORT_DONE_EP14_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP14_OUT_BITS _u(0x20000000)
+#define USB_EP_ABORT_DONE_EP14_OUT_MSB _u(29)
+#define USB_EP_ABORT_DONE_EP14_OUT_LSB _u(29)
#define USB_EP_ABORT_DONE_EP14_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP14_IN
// Description : None
-#define USB_EP_ABORT_DONE_EP14_IN_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP14_IN_BITS _U(0x10000000)
-#define USB_EP_ABORT_DONE_EP14_IN_MSB _U(28)
-#define USB_EP_ABORT_DONE_EP14_IN_LSB _U(28)
+#define USB_EP_ABORT_DONE_EP14_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP14_IN_BITS _u(0x10000000)
+#define USB_EP_ABORT_DONE_EP14_IN_MSB _u(28)
+#define USB_EP_ABORT_DONE_EP14_IN_LSB _u(28)
#define USB_EP_ABORT_DONE_EP14_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP13_OUT
// Description : None
-#define USB_EP_ABORT_DONE_EP13_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP13_OUT_BITS _U(0x08000000)
-#define USB_EP_ABORT_DONE_EP13_OUT_MSB _U(27)
-#define USB_EP_ABORT_DONE_EP13_OUT_LSB _U(27)
+#define USB_EP_ABORT_DONE_EP13_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP13_OUT_BITS _u(0x08000000)
+#define USB_EP_ABORT_DONE_EP13_OUT_MSB _u(27)
+#define USB_EP_ABORT_DONE_EP13_OUT_LSB _u(27)
#define USB_EP_ABORT_DONE_EP13_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP13_IN
// Description : None
-#define USB_EP_ABORT_DONE_EP13_IN_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP13_IN_BITS _U(0x04000000)
-#define USB_EP_ABORT_DONE_EP13_IN_MSB _U(26)
-#define USB_EP_ABORT_DONE_EP13_IN_LSB _U(26)
+#define USB_EP_ABORT_DONE_EP13_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP13_IN_BITS _u(0x04000000)
+#define USB_EP_ABORT_DONE_EP13_IN_MSB _u(26)
+#define USB_EP_ABORT_DONE_EP13_IN_LSB _u(26)
#define USB_EP_ABORT_DONE_EP13_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP12_OUT
// Description : None
-#define USB_EP_ABORT_DONE_EP12_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP12_OUT_BITS _U(0x02000000)
-#define USB_EP_ABORT_DONE_EP12_OUT_MSB _U(25)
-#define USB_EP_ABORT_DONE_EP12_OUT_LSB _U(25)
+#define USB_EP_ABORT_DONE_EP12_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP12_OUT_BITS _u(0x02000000)
+#define USB_EP_ABORT_DONE_EP12_OUT_MSB _u(25)
+#define USB_EP_ABORT_DONE_EP12_OUT_LSB _u(25)
#define USB_EP_ABORT_DONE_EP12_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP12_IN
// Description : None
-#define USB_EP_ABORT_DONE_EP12_IN_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP12_IN_BITS _U(0x01000000)
-#define USB_EP_ABORT_DONE_EP12_IN_MSB _U(24)
-#define USB_EP_ABORT_DONE_EP12_IN_LSB _U(24)
+#define USB_EP_ABORT_DONE_EP12_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP12_IN_BITS _u(0x01000000)
+#define USB_EP_ABORT_DONE_EP12_IN_MSB _u(24)
+#define USB_EP_ABORT_DONE_EP12_IN_LSB _u(24)
#define USB_EP_ABORT_DONE_EP12_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP11_OUT
// Description : None
-#define USB_EP_ABORT_DONE_EP11_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP11_OUT_BITS _U(0x00800000)
-#define USB_EP_ABORT_DONE_EP11_OUT_MSB _U(23)
-#define USB_EP_ABORT_DONE_EP11_OUT_LSB _U(23)
+#define USB_EP_ABORT_DONE_EP11_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP11_OUT_BITS _u(0x00800000)
+#define USB_EP_ABORT_DONE_EP11_OUT_MSB _u(23)
+#define USB_EP_ABORT_DONE_EP11_OUT_LSB _u(23)
#define USB_EP_ABORT_DONE_EP11_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP11_IN
// Description : None
-#define USB_EP_ABORT_DONE_EP11_IN_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP11_IN_BITS _U(0x00400000)
-#define USB_EP_ABORT_DONE_EP11_IN_MSB _U(22)
-#define USB_EP_ABORT_DONE_EP11_IN_LSB _U(22)
+#define USB_EP_ABORT_DONE_EP11_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP11_IN_BITS _u(0x00400000)
+#define USB_EP_ABORT_DONE_EP11_IN_MSB _u(22)
+#define USB_EP_ABORT_DONE_EP11_IN_LSB _u(22)
#define USB_EP_ABORT_DONE_EP11_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP10_OUT
// Description : None
-#define USB_EP_ABORT_DONE_EP10_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP10_OUT_BITS _U(0x00200000)
-#define USB_EP_ABORT_DONE_EP10_OUT_MSB _U(21)
-#define USB_EP_ABORT_DONE_EP10_OUT_LSB _U(21)
+#define USB_EP_ABORT_DONE_EP10_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP10_OUT_BITS _u(0x00200000)
+#define USB_EP_ABORT_DONE_EP10_OUT_MSB _u(21)
+#define USB_EP_ABORT_DONE_EP10_OUT_LSB _u(21)
#define USB_EP_ABORT_DONE_EP10_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP10_IN
// Description : None
-#define USB_EP_ABORT_DONE_EP10_IN_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP10_IN_BITS _U(0x00100000)
-#define USB_EP_ABORT_DONE_EP10_IN_MSB _U(20)
-#define USB_EP_ABORT_DONE_EP10_IN_LSB _U(20)
+#define USB_EP_ABORT_DONE_EP10_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP10_IN_BITS _u(0x00100000)
+#define USB_EP_ABORT_DONE_EP10_IN_MSB _u(20)
+#define USB_EP_ABORT_DONE_EP10_IN_LSB _u(20)
#define USB_EP_ABORT_DONE_EP10_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP9_OUT
// Description : None
-#define USB_EP_ABORT_DONE_EP9_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP9_OUT_BITS _U(0x00080000)
-#define USB_EP_ABORT_DONE_EP9_OUT_MSB _U(19)
-#define USB_EP_ABORT_DONE_EP9_OUT_LSB _U(19)
+#define USB_EP_ABORT_DONE_EP9_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP9_OUT_BITS _u(0x00080000)
+#define USB_EP_ABORT_DONE_EP9_OUT_MSB _u(19)
+#define USB_EP_ABORT_DONE_EP9_OUT_LSB _u(19)
#define USB_EP_ABORT_DONE_EP9_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP9_IN
// Description : None
-#define USB_EP_ABORT_DONE_EP9_IN_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP9_IN_BITS _U(0x00040000)
-#define USB_EP_ABORT_DONE_EP9_IN_MSB _U(18)
-#define USB_EP_ABORT_DONE_EP9_IN_LSB _U(18)
+#define USB_EP_ABORT_DONE_EP9_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP9_IN_BITS _u(0x00040000)
+#define USB_EP_ABORT_DONE_EP9_IN_MSB _u(18)
+#define USB_EP_ABORT_DONE_EP9_IN_LSB _u(18)
#define USB_EP_ABORT_DONE_EP9_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP8_OUT
// Description : None
-#define USB_EP_ABORT_DONE_EP8_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP8_OUT_BITS _U(0x00020000)
-#define USB_EP_ABORT_DONE_EP8_OUT_MSB _U(17)
-#define USB_EP_ABORT_DONE_EP8_OUT_LSB _U(17)
+#define USB_EP_ABORT_DONE_EP8_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP8_OUT_BITS _u(0x00020000)
+#define USB_EP_ABORT_DONE_EP8_OUT_MSB _u(17)
+#define USB_EP_ABORT_DONE_EP8_OUT_LSB _u(17)
#define USB_EP_ABORT_DONE_EP8_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP8_IN
// Description : None
-#define USB_EP_ABORT_DONE_EP8_IN_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP8_IN_BITS _U(0x00010000)
-#define USB_EP_ABORT_DONE_EP8_IN_MSB _U(16)
-#define USB_EP_ABORT_DONE_EP8_IN_LSB _U(16)
+#define USB_EP_ABORT_DONE_EP8_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP8_IN_BITS _u(0x00010000)
+#define USB_EP_ABORT_DONE_EP8_IN_MSB _u(16)
+#define USB_EP_ABORT_DONE_EP8_IN_LSB _u(16)
#define USB_EP_ABORT_DONE_EP8_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP7_OUT
// Description : None
-#define USB_EP_ABORT_DONE_EP7_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP7_OUT_BITS _U(0x00008000)
-#define USB_EP_ABORT_DONE_EP7_OUT_MSB _U(15)
-#define USB_EP_ABORT_DONE_EP7_OUT_LSB _U(15)
+#define USB_EP_ABORT_DONE_EP7_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP7_OUT_BITS _u(0x00008000)
+#define USB_EP_ABORT_DONE_EP7_OUT_MSB _u(15)
+#define USB_EP_ABORT_DONE_EP7_OUT_LSB _u(15)
#define USB_EP_ABORT_DONE_EP7_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP7_IN
// Description : None
-#define USB_EP_ABORT_DONE_EP7_IN_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP7_IN_BITS _U(0x00004000)
-#define USB_EP_ABORT_DONE_EP7_IN_MSB _U(14)
-#define USB_EP_ABORT_DONE_EP7_IN_LSB _U(14)
+#define USB_EP_ABORT_DONE_EP7_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP7_IN_BITS _u(0x00004000)
+#define USB_EP_ABORT_DONE_EP7_IN_MSB _u(14)
+#define USB_EP_ABORT_DONE_EP7_IN_LSB _u(14)
#define USB_EP_ABORT_DONE_EP7_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP6_OUT
// Description : None
-#define USB_EP_ABORT_DONE_EP6_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP6_OUT_BITS _U(0x00002000)
-#define USB_EP_ABORT_DONE_EP6_OUT_MSB _U(13)
-#define USB_EP_ABORT_DONE_EP6_OUT_LSB _U(13)
+#define USB_EP_ABORT_DONE_EP6_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP6_OUT_BITS _u(0x00002000)
+#define USB_EP_ABORT_DONE_EP6_OUT_MSB _u(13)
+#define USB_EP_ABORT_DONE_EP6_OUT_LSB _u(13)
#define USB_EP_ABORT_DONE_EP6_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP6_IN
// Description : None
-#define USB_EP_ABORT_DONE_EP6_IN_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP6_IN_BITS _U(0x00001000)
-#define USB_EP_ABORT_DONE_EP6_IN_MSB _U(12)
-#define USB_EP_ABORT_DONE_EP6_IN_LSB _U(12)
+#define USB_EP_ABORT_DONE_EP6_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP6_IN_BITS _u(0x00001000)
+#define USB_EP_ABORT_DONE_EP6_IN_MSB _u(12)
+#define USB_EP_ABORT_DONE_EP6_IN_LSB _u(12)
#define USB_EP_ABORT_DONE_EP6_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP5_OUT
// Description : None
-#define USB_EP_ABORT_DONE_EP5_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP5_OUT_BITS _U(0x00000800)
-#define USB_EP_ABORT_DONE_EP5_OUT_MSB _U(11)
-#define USB_EP_ABORT_DONE_EP5_OUT_LSB _U(11)
+#define USB_EP_ABORT_DONE_EP5_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP5_OUT_BITS _u(0x00000800)
+#define USB_EP_ABORT_DONE_EP5_OUT_MSB _u(11)
+#define USB_EP_ABORT_DONE_EP5_OUT_LSB _u(11)
#define USB_EP_ABORT_DONE_EP5_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP5_IN
// Description : None
-#define USB_EP_ABORT_DONE_EP5_IN_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP5_IN_BITS _U(0x00000400)
-#define USB_EP_ABORT_DONE_EP5_IN_MSB _U(10)
-#define USB_EP_ABORT_DONE_EP5_IN_LSB _U(10)
+#define USB_EP_ABORT_DONE_EP5_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP5_IN_BITS _u(0x00000400)
+#define USB_EP_ABORT_DONE_EP5_IN_MSB _u(10)
+#define USB_EP_ABORT_DONE_EP5_IN_LSB _u(10)
#define USB_EP_ABORT_DONE_EP5_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP4_OUT
// Description : None
-#define USB_EP_ABORT_DONE_EP4_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP4_OUT_BITS _U(0x00000200)
-#define USB_EP_ABORT_DONE_EP4_OUT_MSB _U(9)
-#define USB_EP_ABORT_DONE_EP4_OUT_LSB _U(9)
+#define USB_EP_ABORT_DONE_EP4_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP4_OUT_BITS _u(0x00000200)
+#define USB_EP_ABORT_DONE_EP4_OUT_MSB _u(9)
+#define USB_EP_ABORT_DONE_EP4_OUT_LSB _u(9)
#define USB_EP_ABORT_DONE_EP4_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP4_IN
// Description : None
-#define USB_EP_ABORT_DONE_EP4_IN_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP4_IN_BITS _U(0x00000100)
-#define USB_EP_ABORT_DONE_EP4_IN_MSB _U(8)
-#define USB_EP_ABORT_DONE_EP4_IN_LSB _U(8)
+#define USB_EP_ABORT_DONE_EP4_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP4_IN_BITS _u(0x00000100)
+#define USB_EP_ABORT_DONE_EP4_IN_MSB _u(8)
+#define USB_EP_ABORT_DONE_EP4_IN_LSB _u(8)
#define USB_EP_ABORT_DONE_EP4_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP3_OUT
// Description : None
-#define USB_EP_ABORT_DONE_EP3_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP3_OUT_BITS _U(0x00000080)
-#define USB_EP_ABORT_DONE_EP3_OUT_MSB _U(7)
-#define USB_EP_ABORT_DONE_EP3_OUT_LSB _U(7)
+#define USB_EP_ABORT_DONE_EP3_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP3_OUT_BITS _u(0x00000080)
+#define USB_EP_ABORT_DONE_EP3_OUT_MSB _u(7)
+#define USB_EP_ABORT_DONE_EP3_OUT_LSB _u(7)
#define USB_EP_ABORT_DONE_EP3_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP3_IN
// Description : None
-#define USB_EP_ABORT_DONE_EP3_IN_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP3_IN_BITS _U(0x00000040)
-#define USB_EP_ABORT_DONE_EP3_IN_MSB _U(6)
-#define USB_EP_ABORT_DONE_EP3_IN_LSB _U(6)
+#define USB_EP_ABORT_DONE_EP3_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP3_IN_BITS _u(0x00000040)
+#define USB_EP_ABORT_DONE_EP3_IN_MSB _u(6)
+#define USB_EP_ABORT_DONE_EP3_IN_LSB _u(6)
#define USB_EP_ABORT_DONE_EP3_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP2_OUT
// Description : None
-#define USB_EP_ABORT_DONE_EP2_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP2_OUT_BITS _U(0x00000020)
-#define USB_EP_ABORT_DONE_EP2_OUT_MSB _U(5)
-#define USB_EP_ABORT_DONE_EP2_OUT_LSB _U(5)
+#define USB_EP_ABORT_DONE_EP2_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP2_OUT_BITS _u(0x00000020)
+#define USB_EP_ABORT_DONE_EP2_OUT_MSB _u(5)
+#define USB_EP_ABORT_DONE_EP2_OUT_LSB _u(5)
#define USB_EP_ABORT_DONE_EP2_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP2_IN
// Description : None
-#define USB_EP_ABORT_DONE_EP2_IN_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP2_IN_BITS _U(0x00000010)
-#define USB_EP_ABORT_DONE_EP2_IN_MSB _U(4)
-#define USB_EP_ABORT_DONE_EP2_IN_LSB _U(4)
+#define USB_EP_ABORT_DONE_EP2_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP2_IN_BITS _u(0x00000010)
+#define USB_EP_ABORT_DONE_EP2_IN_MSB _u(4)
+#define USB_EP_ABORT_DONE_EP2_IN_LSB _u(4)
#define USB_EP_ABORT_DONE_EP2_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP1_OUT
// Description : None
-#define USB_EP_ABORT_DONE_EP1_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP1_OUT_BITS _U(0x00000008)
-#define USB_EP_ABORT_DONE_EP1_OUT_MSB _U(3)
-#define USB_EP_ABORT_DONE_EP1_OUT_LSB _U(3)
+#define USB_EP_ABORT_DONE_EP1_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP1_OUT_BITS _u(0x00000008)
+#define USB_EP_ABORT_DONE_EP1_OUT_MSB _u(3)
+#define USB_EP_ABORT_DONE_EP1_OUT_LSB _u(3)
#define USB_EP_ABORT_DONE_EP1_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP1_IN
// Description : None
-#define USB_EP_ABORT_DONE_EP1_IN_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP1_IN_BITS _U(0x00000004)
-#define USB_EP_ABORT_DONE_EP1_IN_MSB _U(2)
-#define USB_EP_ABORT_DONE_EP1_IN_LSB _U(2)
+#define USB_EP_ABORT_DONE_EP1_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP1_IN_BITS _u(0x00000004)
+#define USB_EP_ABORT_DONE_EP1_IN_MSB _u(2)
+#define USB_EP_ABORT_DONE_EP1_IN_LSB _u(2)
#define USB_EP_ABORT_DONE_EP1_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP0_OUT
// Description : None
-#define USB_EP_ABORT_DONE_EP0_OUT_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP0_OUT_BITS _U(0x00000002)
-#define USB_EP_ABORT_DONE_EP0_OUT_MSB _U(1)
-#define USB_EP_ABORT_DONE_EP0_OUT_LSB _U(1)
+#define USB_EP_ABORT_DONE_EP0_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP0_OUT_BITS _u(0x00000002)
+#define USB_EP_ABORT_DONE_EP0_OUT_MSB _u(1)
+#define USB_EP_ABORT_DONE_EP0_OUT_LSB _u(1)
#define USB_EP_ABORT_DONE_EP0_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_ABORT_DONE_EP0_IN
// Description : None
-#define USB_EP_ABORT_DONE_EP0_IN_RESET _U(0x0)
-#define USB_EP_ABORT_DONE_EP0_IN_BITS _U(0x00000001)
-#define USB_EP_ABORT_DONE_EP0_IN_MSB _U(0)
-#define USB_EP_ABORT_DONE_EP0_IN_LSB _U(0)
+#define USB_EP_ABORT_DONE_EP0_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP0_IN_BITS _u(0x00000001)
+#define USB_EP_ABORT_DONE_EP0_IN_MSB _u(0)
+#define USB_EP_ABORT_DONE_EP0_IN_LSB _u(0)
#define USB_EP_ABORT_DONE_EP0_IN_ACCESS "WC"
// =============================================================================
// Register : USB_EP_STALL_ARM
@@ -2146,350 +2146,350 @@
// device controller clears these bits when a SETUP packet is
// received because the USB spec requires that a STALL condition
// is cleared when a SETUP packet is received.
-#define USB_EP_STALL_ARM_OFFSET _U(0x00000068)
-#define USB_EP_STALL_ARM_BITS _U(0x00000003)
-#define USB_EP_STALL_ARM_RESET _U(0x00000000)
+#define USB_EP_STALL_ARM_OFFSET _u(0x00000068)
+#define USB_EP_STALL_ARM_BITS _u(0x00000003)
+#define USB_EP_STALL_ARM_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_EP_STALL_ARM_EP0_OUT
// Description : None
-#define USB_EP_STALL_ARM_EP0_OUT_RESET _U(0x0)
-#define USB_EP_STALL_ARM_EP0_OUT_BITS _U(0x00000002)
-#define USB_EP_STALL_ARM_EP0_OUT_MSB _U(1)
-#define USB_EP_STALL_ARM_EP0_OUT_LSB _U(1)
+#define USB_EP_STALL_ARM_EP0_OUT_RESET _u(0x0)
+#define USB_EP_STALL_ARM_EP0_OUT_BITS _u(0x00000002)
+#define USB_EP_STALL_ARM_EP0_OUT_MSB _u(1)
+#define USB_EP_STALL_ARM_EP0_OUT_LSB _u(1)
#define USB_EP_STALL_ARM_EP0_OUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_EP_STALL_ARM_EP0_IN
// Description : None
-#define USB_EP_STALL_ARM_EP0_IN_RESET _U(0x0)
-#define USB_EP_STALL_ARM_EP0_IN_BITS _U(0x00000001)
-#define USB_EP_STALL_ARM_EP0_IN_MSB _U(0)
-#define USB_EP_STALL_ARM_EP0_IN_LSB _U(0)
+#define USB_EP_STALL_ARM_EP0_IN_RESET _u(0x0)
+#define USB_EP_STALL_ARM_EP0_IN_BITS _u(0x00000001)
+#define USB_EP_STALL_ARM_EP0_IN_MSB _u(0)
+#define USB_EP_STALL_ARM_EP0_IN_LSB _u(0)
#define USB_EP_STALL_ARM_EP0_IN_ACCESS "RW"
// =============================================================================
// Register : USB_NAK_POLL
// Description : Used by the host controller. Sets the wait time in microseconds
// before trying again if the device replies with a NAK.
-#define USB_NAK_POLL_OFFSET _U(0x0000006c)
-#define USB_NAK_POLL_BITS _U(0x03ff03ff)
-#define USB_NAK_POLL_RESET _U(0x00100010)
+#define USB_NAK_POLL_OFFSET _u(0x0000006c)
+#define USB_NAK_POLL_BITS _u(0x03ff03ff)
+#define USB_NAK_POLL_RESET _u(0x00100010)
// -----------------------------------------------------------------------------
// Field : USB_NAK_POLL_DELAY_FS
// Description : NAK polling interval for a full speed device
-#define USB_NAK_POLL_DELAY_FS_RESET _U(0x010)
-#define USB_NAK_POLL_DELAY_FS_BITS _U(0x03ff0000)
-#define USB_NAK_POLL_DELAY_FS_MSB _U(25)
-#define USB_NAK_POLL_DELAY_FS_LSB _U(16)
+#define USB_NAK_POLL_DELAY_FS_RESET _u(0x010)
+#define USB_NAK_POLL_DELAY_FS_BITS _u(0x03ff0000)
+#define USB_NAK_POLL_DELAY_FS_MSB _u(25)
+#define USB_NAK_POLL_DELAY_FS_LSB _u(16)
#define USB_NAK_POLL_DELAY_FS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_NAK_POLL_DELAY_LS
// Description : NAK polling interval for a low speed device
-#define USB_NAK_POLL_DELAY_LS_RESET _U(0x010)
-#define USB_NAK_POLL_DELAY_LS_BITS _U(0x000003ff)
-#define USB_NAK_POLL_DELAY_LS_MSB _U(9)
-#define USB_NAK_POLL_DELAY_LS_LSB _U(0)
+#define USB_NAK_POLL_DELAY_LS_RESET _u(0x010)
+#define USB_NAK_POLL_DELAY_LS_BITS _u(0x000003ff)
+#define USB_NAK_POLL_DELAY_LS_MSB _u(9)
+#define USB_NAK_POLL_DELAY_LS_LSB _u(0)
#define USB_NAK_POLL_DELAY_LS_ACCESS "RW"
// =============================================================================
// Register : USB_EP_STATUS_STALL_NAK
// Description : Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL`
// bits are set. For EP0 this comes from `SIE_CTRL`. For all other
// endpoints it comes from the endpoint control register.
-#define USB_EP_STATUS_STALL_NAK_OFFSET _U(0x00000070)
-#define USB_EP_STATUS_STALL_NAK_BITS _U(0xffffffff)
-#define USB_EP_STATUS_STALL_NAK_RESET _U(0x00000000)
+#define USB_EP_STATUS_STALL_NAK_OFFSET _u(0x00000070)
+#define USB_EP_STATUS_STALL_NAK_BITS _u(0xffffffff)
+#define USB_EP_STATUS_STALL_NAK_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP15_OUT
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS _U(0x80000000)
-#define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB _U(31)
-#define USB_EP_STATUS_STALL_NAK_EP15_OUT_LSB _U(31)
+#define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS _u(0x80000000)
+#define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB _u(31)
+#define USB_EP_STATUS_STALL_NAK_EP15_OUT_LSB _u(31)
#define USB_EP_STATUS_STALL_NAK_EP15_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP15_IN
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS _U(0x40000000)
-#define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB _U(30)
-#define USB_EP_STATUS_STALL_NAK_EP15_IN_LSB _U(30)
+#define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS _u(0x40000000)
+#define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB _u(30)
+#define USB_EP_STATUS_STALL_NAK_EP15_IN_LSB _u(30)
#define USB_EP_STATUS_STALL_NAK_EP15_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP14_OUT
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS _U(0x20000000)
-#define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB _U(29)
-#define USB_EP_STATUS_STALL_NAK_EP14_OUT_LSB _U(29)
+#define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS _u(0x20000000)
+#define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB _u(29)
+#define USB_EP_STATUS_STALL_NAK_EP14_OUT_LSB _u(29)
#define USB_EP_STATUS_STALL_NAK_EP14_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP14_IN
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS _U(0x10000000)
-#define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB _U(28)
-#define USB_EP_STATUS_STALL_NAK_EP14_IN_LSB _U(28)
+#define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS _u(0x10000000)
+#define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB _u(28)
+#define USB_EP_STATUS_STALL_NAK_EP14_IN_LSB _u(28)
#define USB_EP_STATUS_STALL_NAK_EP14_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP13_OUT
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS _U(0x08000000)
-#define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB _U(27)
-#define USB_EP_STATUS_STALL_NAK_EP13_OUT_LSB _U(27)
+#define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS _u(0x08000000)
+#define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB _u(27)
+#define USB_EP_STATUS_STALL_NAK_EP13_OUT_LSB _u(27)
#define USB_EP_STATUS_STALL_NAK_EP13_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP13_IN
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS _U(0x04000000)
-#define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB _U(26)
-#define USB_EP_STATUS_STALL_NAK_EP13_IN_LSB _U(26)
+#define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS _u(0x04000000)
+#define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB _u(26)
+#define USB_EP_STATUS_STALL_NAK_EP13_IN_LSB _u(26)
#define USB_EP_STATUS_STALL_NAK_EP13_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP12_OUT
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS _U(0x02000000)
-#define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB _U(25)
-#define USB_EP_STATUS_STALL_NAK_EP12_OUT_LSB _U(25)
+#define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS _u(0x02000000)
+#define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB _u(25)
+#define USB_EP_STATUS_STALL_NAK_EP12_OUT_LSB _u(25)
#define USB_EP_STATUS_STALL_NAK_EP12_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP12_IN
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS _U(0x01000000)
-#define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB _U(24)
-#define USB_EP_STATUS_STALL_NAK_EP12_IN_LSB _U(24)
+#define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS _u(0x01000000)
+#define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB _u(24)
+#define USB_EP_STATUS_STALL_NAK_EP12_IN_LSB _u(24)
#define USB_EP_STATUS_STALL_NAK_EP12_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP11_OUT
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS _U(0x00800000)
-#define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB _U(23)
-#define USB_EP_STATUS_STALL_NAK_EP11_OUT_LSB _U(23)
+#define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS _u(0x00800000)
+#define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB _u(23)
+#define USB_EP_STATUS_STALL_NAK_EP11_OUT_LSB _u(23)
#define USB_EP_STATUS_STALL_NAK_EP11_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP11_IN
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS _U(0x00400000)
-#define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB _U(22)
-#define USB_EP_STATUS_STALL_NAK_EP11_IN_LSB _U(22)
+#define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS _u(0x00400000)
+#define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB _u(22)
+#define USB_EP_STATUS_STALL_NAK_EP11_IN_LSB _u(22)
#define USB_EP_STATUS_STALL_NAK_EP11_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP10_OUT
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS _U(0x00200000)
-#define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB _U(21)
-#define USB_EP_STATUS_STALL_NAK_EP10_OUT_LSB _U(21)
+#define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS _u(0x00200000)
+#define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB _u(21)
+#define USB_EP_STATUS_STALL_NAK_EP10_OUT_LSB _u(21)
#define USB_EP_STATUS_STALL_NAK_EP10_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP10_IN
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS _U(0x00100000)
-#define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB _U(20)
-#define USB_EP_STATUS_STALL_NAK_EP10_IN_LSB _U(20)
+#define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS _u(0x00100000)
+#define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB _u(20)
+#define USB_EP_STATUS_STALL_NAK_EP10_IN_LSB _u(20)
#define USB_EP_STATUS_STALL_NAK_EP10_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP9_OUT
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS _U(0x00080000)
-#define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB _U(19)
-#define USB_EP_STATUS_STALL_NAK_EP9_OUT_LSB _U(19)
+#define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS _u(0x00080000)
+#define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB _u(19)
+#define USB_EP_STATUS_STALL_NAK_EP9_OUT_LSB _u(19)
#define USB_EP_STATUS_STALL_NAK_EP9_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP9_IN
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS _U(0x00040000)
-#define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB _U(18)
-#define USB_EP_STATUS_STALL_NAK_EP9_IN_LSB _U(18)
+#define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS _u(0x00040000)
+#define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB _u(18)
+#define USB_EP_STATUS_STALL_NAK_EP9_IN_LSB _u(18)
#define USB_EP_STATUS_STALL_NAK_EP9_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP8_OUT
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS _U(0x00020000)
-#define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB _U(17)
-#define USB_EP_STATUS_STALL_NAK_EP8_OUT_LSB _U(17)
+#define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS _u(0x00020000)
+#define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB _u(17)
+#define USB_EP_STATUS_STALL_NAK_EP8_OUT_LSB _u(17)
#define USB_EP_STATUS_STALL_NAK_EP8_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP8_IN
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS _U(0x00010000)
-#define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB _U(16)
-#define USB_EP_STATUS_STALL_NAK_EP8_IN_LSB _U(16)
+#define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS _u(0x00010000)
+#define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB _u(16)
+#define USB_EP_STATUS_STALL_NAK_EP8_IN_LSB _u(16)
#define USB_EP_STATUS_STALL_NAK_EP8_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP7_OUT
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS _U(0x00008000)
-#define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB _U(15)
-#define USB_EP_STATUS_STALL_NAK_EP7_OUT_LSB _U(15)
+#define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS _u(0x00008000)
+#define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB _u(15)
+#define USB_EP_STATUS_STALL_NAK_EP7_OUT_LSB _u(15)
#define USB_EP_STATUS_STALL_NAK_EP7_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP7_IN
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS _U(0x00004000)
-#define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB _U(14)
-#define USB_EP_STATUS_STALL_NAK_EP7_IN_LSB _U(14)
+#define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS _u(0x00004000)
+#define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB _u(14)
+#define USB_EP_STATUS_STALL_NAK_EP7_IN_LSB _u(14)
#define USB_EP_STATUS_STALL_NAK_EP7_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP6_OUT
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS _U(0x00002000)
-#define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB _U(13)
-#define USB_EP_STATUS_STALL_NAK_EP6_OUT_LSB _U(13)
+#define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS _u(0x00002000)
+#define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB _u(13)
+#define USB_EP_STATUS_STALL_NAK_EP6_OUT_LSB _u(13)
#define USB_EP_STATUS_STALL_NAK_EP6_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP6_IN
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS _U(0x00001000)
-#define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB _U(12)
-#define USB_EP_STATUS_STALL_NAK_EP6_IN_LSB _U(12)
+#define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS _u(0x00001000)
+#define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB _u(12)
+#define USB_EP_STATUS_STALL_NAK_EP6_IN_LSB _u(12)
#define USB_EP_STATUS_STALL_NAK_EP6_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP5_OUT
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS _U(0x00000800)
-#define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB _U(11)
-#define USB_EP_STATUS_STALL_NAK_EP5_OUT_LSB _U(11)
+#define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS _u(0x00000800)
+#define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB _u(11)
+#define USB_EP_STATUS_STALL_NAK_EP5_OUT_LSB _u(11)
#define USB_EP_STATUS_STALL_NAK_EP5_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP5_IN
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS _U(0x00000400)
-#define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB _U(10)
-#define USB_EP_STATUS_STALL_NAK_EP5_IN_LSB _U(10)
+#define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS _u(0x00000400)
+#define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB _u(10)
+#define USB_EP_STATUS_STALL_NAK_EP5_IN_LSB _u(10)
#define USB_EP_STATUS_STALL_NAK_EP5_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP4_OUT
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS _U(0x00000200)
-#define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB _U(9)
-#define USB_EP_STATUS_STALL_NAK_EP4_OUT_LSB _U(9)
+#define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS _u(0x00000200)
+#define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB _u(9)
+#define USB_EP_STATUS_STALL_NAK_EP4_OUT_LSB _u(9)
#define USB_EP_STATUS_STALL_NAK_EP4_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP4_IN
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS _U(0x00000100)
-#define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB _U(8)
-#define USB_EP_STATUS_STALL_NAK_EP4_IN_LSB _U(8)
+#define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS _u(0x00000100)
+#define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB _u(8)
+#define USB_EP_STATUS_STALL_NAK_EP4_IN_LSB _u(8)
#define USB_EP_STATUS_STALL_NAK_EP4_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP3_OUT
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS _U(0x00000080)
-#define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB _U(7)
-#define USB_EP_STATUS_STALL_NAK_EP3_OUT_LSB _U(7)
+#define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS _u(0x00000080)
+#define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB _u(7)
+#define USB_EP_STATUS_STALL_NAK_EP3_OUT_LSB _u(7)
#define USB_EP_STATUS_STALL_NAK_EP3_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP3_IN
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS _U(0x00000040)
-#define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB _U(6)
-#define USB_EP_STATUS_STALL_NAK_EP3_IN_LSB _U(6)
+#define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS _u(0x00000040)
+#define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB _u(6)
+#define USB_EP_STATUS_STALL_NAK_EP3_IN_LSB _u(6)
#define USB_EP_STATUS_STALL_NAK_EP3_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP2_OUT
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS _U(0x00000020)
-#define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB _U(5)
-#define USB_EP_STATUS_STALL_NAK_EP2_OUT_LSB _U(5)
+#define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS _u(0x00000020)
+#define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB _u(5)
+#define USB_EP_STATUS_STALL_NAK_EP2_OUT_LSB _u(5)
#define USB_EP_STATUS_STALL_NAK_EP2_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP2_IN
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS _U(0x00000010)
-#define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB _U(4)
-#define USB_EP_STATUS_STALL_NAK_EP2_IN_LSB _U(4)
+#define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS _u(0x00000010)
+#define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB _u(4)
+#define USB_EP_STATUS_STALL_NAK_EP2_IN_LSB _u(4)
#define USB_EP_STATUS_STALL_NAK_EP2_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP1_OUT
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS _U(0x00000008)
-#define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB _U(3)
-#define USB_EP_STATUS_STALL_NAK_EP1_OUT_LSB _U(3)
+#define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS _u(0x00000008)
+#define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB _u(3)
+#define USB_EP_STATUS_STALL_NAK_EP1_OUT_LSB _u(3)
#define USB_EP_STATUS_STALL_NAK_EP1_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP1_IN
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS _U(0x00000004)
-#define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB _U(2)
-#define USB_EP_STATUS_STALL_NAK_EP1_IN_LSB _U(2)
+#define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS _u(0x00000004)
+#define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB _u(2)
+#define USB_EP_STATUS_STALL_NAK_EP1_IN_LSB _u(2)
#define USB_EP_STATUS_STALL_NAK_EP1_IN_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP0_OUT
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS _U(0x00000002)
-#define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB _U(1)
-#define USB_EP_STATUS_STALL_NAK_EP0_OUT_LSB _U(1)
+#define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS _u(0x00000002)
+#define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB _u(1)
+#define USB_EP_STATUS_STALL_NAK_EP0_OUT_LSB _u(1)
#define USB_EP_STATUS_STALL_NAK_EP0_OUT_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : USB_EP_STATUS_STALL_NAK_EP0_IN
// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET _U(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS _U(0x00000001)
-#define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB _U(0)
-#define USB_EP_STATUS_STALL_NAK_EP0_IN_LSB _U(0)
+#define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS _u(0x00000001)
+#define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB _u(0)
+#define USB_EP_STATUS_STALL_NAK_EP0_IN_LSB _u(0)
#define USB_EP_STATUS_STALL_NAK_EP0_IN_ACCESS "WC"
// =============================================================================
// Register : USB_USB_MUXING
// Description : Where to connect the USB controller. Should be to_phy by
// default.
-#define USB_USB_MUXING_OFFSET _U(0x00000074)
-#define USB_USB_MUXING_BITS _U(0x0000000f)
-#define USB_USB_MUXING_RESET _U(0x00000000)
+#define USB_USB_MUXING_OFFSET _u(0x00000074)
+#define USB_USB_MUXING_BITS _u(0x0000000f)
+#define USB_USB_MUXING_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_USB_MUXING_SOFTCON
// Description : None
-#define USB_USB_MUXING_SOFTCON_RESET _U(0x0)
-#define USB_USB_MUXING_SOFTCON_BITS _U(0x00000008)
-#define USB_USB_MUXING_SOFTCON_MSB _U(3)
-#define USB_USB_MUXING_SOFTCON_LSB _U(3)
+#define USB_USB_MUXING_SOFTCON_RESET _u(0x0)
+#define USB_USB_MUXING_SOFTCON_BITS _u(0x00000008)
+#define USB_USB_MUXING_SOFTCON_MSB _u(3)
+#define USB_USB_MUXING_SOFTCON_LSB _u(3)
#define USB_USB_MUXING_SOFTCON_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USB_MUXING_TO_DIGITAL_PAD
// Description : None
-#define USB_USB_MUXING_TO_DIGITAL_PAD_RESET _U(0x0)
-#define USB_USB_MUXING_TO_DIGITAL_PAD_BITS _U(0x00000004)
-#define USB_USB_MUXING_TO_DIGITAL_PAD_MSB _U(2)
-#define USB_USB_MUXING_TO_DIGITAL_PAD_LSB _U(2)
+#define USB_USB_MUXING_TO_DIGITAL_PAD_RESET _u(0x0)
+#define USB_USB_MUXING_TO_DIGITAL_PAD_BITS _u(0x00000004)
+#define USB_USB_MUXING_TO_DIGITAL_PAD_MSB _u(2)
+#define USB_USB_MUXING_TO_DIGITAL_PAD_LSB _u(2)
#define USB_USB_MUXING_TO_DIGITAL_PAD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USB_MUXING_TO_EXTPHY
// Description : None
-#define USB_USB_MUXING_TO_EXTPHY_RESET _U(0x0)
-#define USB_USB_MUXING_TO_EXTPHY_BITS _U(0x00000002)
-#define USB_USB_MUXING_TO_EXTPHY_MSB _U(1)
-#define USB_USB_MUXING_TO_EXTPHY_LSB _U(1)
+#define USB_USB_MUXING_TO_EXTPHY_RESET _u(0x0)
+#define USB_USB_MUXING_TO_EXTPHY_BITS _u(0x00000002)
+#define USB_USB_MUXING_TO_EXTPHY_MSB _u(1)
+#define USB_USB_MUXING_TO_EXTPHY_LSB _u(1)
#define USB_USB_MUXING_TO_EXTPHY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USB_MUXING_TO_PHY
// Description : None
-#define USB_USB_MUXING_TO_PHY_RESET _U(0x0)
-#define USB_USB_MUXING_TO_PHY_BITS _U(0x00000001)
-#define USB_USB_MUXING_TO_PHY_MSB _U(0)
-#define USB_USB_MUXING_TO_PHY_LSB _U(0)
+#define USB_USB_MUXING_TO_PHY_RESET _u(0x0)
+#define USB_USB_MUXING_TO_PHY_BITS _u(0x00000001)
+#define USB_USB_MUXING_TO_PHY_MSB _u(0)
+#define USB_USB_MUXING_TO_PHY_LSB _u(0)
#define USB_USB_MUXING_TO_PHY_ACCESS "RW"
// =============================================================================
// Register : USB_USB_PWR
@@ -2497,167 +2497,167 @@
// signals are not hooked up to GPIO. Set the value of the
// override and then the override enable to switch over to the
// override value.
-#define USB_USB_PWR_OFFSET _U(0x00000078)
-#define USB_USB_PWR_BITS _U(0x0000003f)
-#define USB_USB_PWR_RESET _U(0x00000000)
+#define USB_USB_PWR_OFFSET _u(0x00000078)
+#define USB_USB_PWR_BITS _u(0x0000003f)
+#define USB_USB_PWR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_USB_PWR_OVERCURR_DETECT_EN
// Description : None
-#define USB_USB_PWR_OVERCURR_DETECT_EN_RESET _U(0x0)
-#define USB_USB_PWR_OVERCURR_DETECT_EN_BITS _U(0x00000020)
-#define USB_USB_PWR_OVERCURR_DETECT_EN_MSB _U(5)
-#define USB_USB_PWR_OVERCURR_DETECT_EN_LSB _U(5)
+#define USB_USB_PWR_OVERCURR_DETECT_EN_RESET _u(0x0)
+#define USB_USB_PWR_OVERCURR_DETECT_EN_BITS _u(0x00000020)
+#define USB_USB_PWR_OVERCURR_DETECT_EN_MSB _u(5)
+#define USB_USB_PWR_OVERCURR_DETECT_EN_LSB _u(5)
#define USB_USB_PWR_OVERCURR_DETECT_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USB_PWR_OVERCURR_DETECT
// Description : None
-#define USB_USB_PWR_OVERCURR_DETECT_RESET _U(0x0)
-#define USB_USB_PWR_OVERCURR_DETECT_BITS _U(0x00000010)
-#define USB_USB_PWR_OVERCURR_DETECT_MSB _U(4)
-#define USB_USB_PWR_OVERCURR_DETECT_LSB _U(4)
+#define USB_USB_PWR_OVERCURR_DETECT_RESET _u(0x0)
+#define USB_USB_PWR_OVERCURR_DETECT_BITS _u(0x00000010)
+#define USB_USB_PWR_OVERCURR_DETECT_MSB _u(4)
+#define USB_USB_PWR_OVERCURR_DETECT_LSB _u(4)
#define USB_USB_PWR_OVERCURR_DETECT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN
// Description : None
-#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET _U(0x0)
-#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS _U(0x00000008)
-#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB _U(3)
-#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_LSB _U(3)
+#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS _u(0x00000008)
+#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB _u(3)
+#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_LSB _u(3)
#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USB_PWR_VBUS_DETECT
// Description : None
-#define USB_USB_PWR_VBUS_DETECT_RESET _U(0x0)
-#define USB_USB_PWR_VBUS_DETECT_BITS _U(0x00000004)
-#define USB_USB_PWR_VBUS_DETECT_MSB _U(2)
-#define USB_USB_PWR_VBUS_DETECT_LSB _U(2)
+#define USB_USB_PWR_VBUS_DETECT_RESET _u(0x0)
+#define USB_USB_PWR_VBUS_DETECT_BITS _u(0x00000004)
+#define USB_USB_PWR_VBUS_DETECT_MSB _u(2)
+#define USB_USB_PWR_VBUS_DETECT_LSB _u(2)
#define USB_USB_PWR_VBUS_DETECT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USB_PWR_VBUS_EN_OVERRIDE_EN
// Description : None
-#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET _U(0x0)
-#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS _U(0x00000002)
-#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB _U(1)
-#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_LSB _U(1)
+#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS _u(0x00000002)
+#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB _u(1)
+#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_LSB _u(1)
#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USB_PWR_VBUS_EN
// Description : None
-#define USB_USB_PWR_VBUS_EN_RESET _U(0x0)
-#define USB_USB_PWR_VBUS_EN_BITS _U(0x00000001)
-#define USB_USB_PWR_VBUS_EN_MSB _U(0)
-#define USB_USB_PWR_VBUS_EN_LSB _U(0)
+#define USB_USB_PWR_VBUS_EN_RESET _u(0x0)
+#define USB_USB_PWR_VBUS_EN_BITS _u(0x00000001)
+#define USB_USB_PWR_VBUS_EN_MSB _u(0)
+#define USB_USB_PWR_VBUS_EN_LSB _u(0)
#define USB_USB_PWR_VBUS_EN_ACCESS "RW"
// =============================================================================
// Register : USB_USBPHY_DIRECT
// Description : This register allows for direct control of the USB phy. Use in
// conjunction with usbphy_direct_override register to enable each
// override bit.
-#define USB_USBPHY_DIRECT_OFFSET _U(0x0000007c)
-#define USB_USBPHY_DIRECT_BITS _U(0x007fff77)
-#define USB_USBPHY_DIRECT_RESET _U(0x00000000)
+#define USB_USBPHY_DIRECT_OFFSET _u(0x0000007c)
+#define USB_USBPHY_DIRECT_BITS _u(0x007fff77)
+#define USB_USBPHY_DIRECT_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_DM_OVV
// Description : DM over voltage
-#define USB_USBPHY_DIRECT_DM_OVV_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_DM_OVV_BITS _U(0x00400000)
-#define USB_USBPHY_DIRECT_DM_OVV_MSB _U(22)
-#define USB_USBPHY_DIRECT_DM_OVV_LSB _U(22)
+#define USB_USBPHY_DIRECT_DM_OVV_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DM_OVV_BITS _u(0x00400000)
+#define USB_USBPHY_DIRECT_DM_OVV_MSB _u(22)
+#define USB_USBPHY_DIRECT_DM_OVV_LSB _u(22)
#define USB_USBPHY_DIRECT_DM_OVV_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_DP_OVV
// Description : DP over voltage
-#define USB_USBPHY_DIRECT_DP_OVV_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_DP_OVV_BITS _U(0x00200000)
-#define USB_USBPHY_DIRECT_DP_OVV_MSB _U(21)
-#define USB_USBPHY_DIRECT_DP_OVV_LSB _U(21)
+#define USB_USBPHY_DIRECT_DP_OVV_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DP_OVV_BITS _u(0x00200000)
+#define USB_USBPHY_DIRECT_DP_OVV_MSB _u(21)
+#define USB_USBPHY_DIRECT_DP_OVV_LSB _u(21)
#define USB_USBPHY_DIRECT_DP_OVV_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_DM_OVCN
// Description : DM overcurrent
-#define USB_USBPHY_DIRECT_DM_OVCN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_DM_OVCN_BITS _U(0x00100000)
-#define USB_USBPHY_DIRECT_DM_OVCN_MSB _U(20)
-#define USB_USBPHY_DIRECT_DM_OVCN_LSB _U(20)
+#define USB_USBPHY_DIRECT_DM_OVCN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DM_OVCN_BITS _u(0x00100000)
+#define USB_USBPHY_DIRECT_DM_OVCN_MSB _u(20)
+#define USB_USBPHY_DIRECT_DM_OVCN_LSB _u(20)
#define USB_USBPHY_DIRECT_DM_OVCN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_DP_OVCN
// Description : DP overcurrent
-#define USB_USBPHY_DIRECT_DP_OVCN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_DP_OVCN_BITS _U(0x00080000)
-#define USB_USBPHY_DIRECT_DP_OVCN_MSB _U(19)
-#define USB_USBPHY_DIRECT_DP_OVCN_LSB _U(19)
+#define USB_USBPHY_DIRECT_DP_OVCN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DP_OVCN_BITS _u(0x00080000)
+#define USB_USBPHY_DIRECT_DP_OVCN_MSB _u(19)
+#define USB_USBPHY_DIRECT_DP_OVCN_LSB _u(19)
#define USB_USBPHY_DIRECT_DP_OVCN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_RX_DM
// Description : DPM pin state
-#define USB_USBPHY_DIRECT_RX_DM_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_RX_DM_BITS _U(0x00040000)
-#define USB_USBPHY_DIRECT_RX_DM_MSB _U(18)
-#define USB_USBPHY_DIRECT_RX_DM_LSB _U(18)
+#define USB_USBPHY_DIRECT_RX_DM_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_RX_DM_BITS _u(0x00040000)
+#define USB_USBPHY_DIRECT_RX_DM_MSB _u(18)
+#define USB_USBPHY_DIRECT_RX_DM_LSB _u(18)
#define USB_USBPHY_DIRECT_RX_DM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_RX_DP
// Description : DPP pin state
-#define USB_USBPHY_DIRECT_RX_DP_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_RX_DP_BITS _U(0x00020000)
-#define USB_USBPHY_DIRECT_RX_DP_MSB _U(17)
-#define USB_USBPHY_DIRECT_RX_DP_LSB _U(17)
+#define USB_USBPHY_DIRECT_RX_DP_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_RX_DP_BITS _u(0x00020000)
+#define USB_USBPHY_DIRECT_RX_DP_MSB _u(17)
+#define USB_USBPHY_DIRECT_RX_DP_LSB _u(17)
#define USB_USBPHY_DIRECT_RX_DP_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_RX_DD
// Description : Differential RX
-#define USB_USBPHY_DIRECT_RX_DD_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_RX_DD_BITS _U(0x00010000)
-#define USB_USBPHY_DIRECT_RX_DD_MSB _U(16)
-#define USB_USBPHY_DIRECT_RX_DD_LSB _U(16)
+#define USB_USBPHY_DIRECT_RX_DD_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_RX_DD_BITS _u(0x00010000)
+#define USB_USBPHY_DIRECT_RX_DD_MSB _u(16)
+#define USB_USBPHY_DIRECT_RX_DD_LSB _u(16)
#define USB_USBPHY_DIRECT_RX_DD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_TX_DIFFMODE
// Description : TX_DIFFMODE=0: Single ended mode
// TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE
// ignored)
-#define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS _U(0x00008000)
-#define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB _U(15)
-#define USB_USBPHY_DIRECT_TX_DIFFMODE_LSB _U(15)
+#define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS _u(0x00008000)
+#define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB _u(15)
+#define USB_USBPHY_DIRECT_TX_DIFFMODE_LSB _u(15)
#define USB_USBPHY_DIRECT_TX_DIFFMODE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_TX_FSSLEW
// Description : TX_FSSLEW=0: Low speed slew rate
// TX_FSSLEW=1: Full speed slew rate
-#define USB_USBPHY_DIRECT_TX_FSSLEW_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_TX_FSSLEW_BITS _U(0x00004000)
-#define USB_USBPHY_DIRECT_TX_FSSLEW_MSB _U(14)
-#define USB_USBPHY_DIRECT_TX_FSSLEW_LSB _U(14)
+#define USB_USBPHY_DIRECT_TX_FSSLEW_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_TX_FSSLEW_BITS _u(0x00004000)
+#define USB_USBPHY_DIRECT_TX_FSSLEW_MSB _u(14)
+#define USB_USBPHY_DIRECT_TX_FSSLEW_LSB _u(14)
#define USB_USBPHY_DIRECT_TX_FSSLEW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_TX_PD
// Description : TX power down override (if override enable is set). 1 = powered
// down.
-#define USB_USBPHY_DIRECT_TX_PD_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_TX_PD_BITS _U(0x00002000)
-#define USB_USBPHY_DIRECT_TX_PD_MSB _U(13)
-#define USB_USBPHY_DIRECT_TX_PD_LSB _U(13)
+#define USB_USBPHY_DIRECT_TX_PD_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_TX_PD_BITS _u(0x00002000)
+#define USB_USBPHY_DIRECT_TX_PD_MSB _u(13)
+#define USB_USBPHY_DIRECT_TX_PD_LSB _u(13)
#define USB_USBPHY_DIRECT_TX_PD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_RX_PD
// Description : RX power down override (if override enable is set). 1 = powered
// down.
-#define USB_USBPHY_DIRECT_RX_PD_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_RX_PD_BITS _U(0x00001000)
-#define USB_USBPHY_DIRECT_RX_PD_MSB _U(12)
-#define USB_USBPHY_DIRECT_RX_PD_LSB _U(12)
+#define USB_USBPHY_DIRECT_RX_PD_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_RX_PD_BITS _u(0x00001000)
+#define USB_USBPHY_DIRECT_RX_PD_MSB _u(12)
+#define USB_USBPHY_DIRECT_RX_PD_LSB _u(12)
#define USB_USBPHY_DIRECT_RX_PD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_TX_DM
// Description : Output data. TX_DIFFMODE=1, Ignored
// TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive.
// DPM=TX_DM
-#define USB_USBPHY_DIRECT_TX_DM_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_TX_DM_BITS _U(0x00000800)
-#define USB_USBPHY_DIRECT_TX_DM_MSB _U(11)
-#define USB_USBPHY_DIRECT_TX_DM_LSB _U(11)
+#define USB_USBPHY_DIRECT_TX_DM_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_TX_DM_BITS _u(0x00000800)
+#define USB_USBPHY_DIRECT_TX_DM_MSB _u(11)
+#define USB_USBPHY_DIRECT_TX_DM_LSB _u(11)
#define USB_USBPHY_DIRECT_TX_DM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_TX_DP
@@ -2665,20 +2665,20 @@
// TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP
// If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive.
// DPP=TX_DP
-#define USB_USBPHY_DIRECT_TX_DP_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_TX_DP_BITS _U(0x00000400)
-#define USB_USBPHY_DIRECT_TX_DP_MSB _U(10)
-#define USB_USBPHY_DIRECT_TX_DP_LSB _U(10)
+#define USB_USBPHY_DIRECT_TX_DP_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_TX_DP_BITS _u(0x00000400)
+#define USB_USBPHY_DIRECT_TX_DP_MSB _u(10)
+#define USB_USBPHY_DIRECT_TX_DP_LSB _u(10)
#define USB_USBPHY_DIRECT_TX_DP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_TX_DM_OE
// Description : Output enable. If TX_DIFFMODE=1, Ignored.
// If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 -
// DPM driving
-#define USB_USBPHY_DIRECT_TX_DM_OE_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_TX_DM_OE_BITS _U(0x00000200)
-#define USB_USBPHY_DIRECT_TX_DM_OE_MSB _U(9)
-#define USB_USBPHY_DIRECT_TX_DM_OE_LSB _U(9)
+#define USB_USBPHY_DIRECT_TX_DM_OE_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_TX_DM_OE_BITS _u(0x00000200)
+#define USB_USBPHY_DIRECT_TX_DM_OE_MSB _u(9)
+#define USB_USBPHY_DIRECT_TX_DM_OE_LSB _u(9)
#define USB_USBPHY_DIRECT_TX_DM_OE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_TX_DP_OE
@@ -2686,195 +2686,195 @@
// DPP/DPM in Hi-Z state; 1 - DPP/DPM driving
// If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 -
// DPP driving
-#define USB_USBPHY_DIRECT_TX_DP_OE_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_TX_DP_OE_BITS _U(0x00000100)
-#define USB_USBPHY_DIRECT_TX_DP_OE_MSB _U(8)
-#define USB_USBPHY_DIRECT_TX_DP_OE_LSB _U(8)
+#define USB_USBPHY_DIRECT_TX_DP_OE_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_TX_DP_OE_BITS _u(0x00000100)
+#define USB_USBPHY_DIRECT_TX_DP_OE_MSB _u(8)
+#define USB_USBPHY_DIRECT_TX_DP_OE_LSB _u(8)
#define USB_USBPHY_DIRECT_TX_DP_OE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_DM_PULLDN_EN
// Description : DM pull down enable
-#define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS _U(0x00000040)
-#define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB _U(6)
-#define USB_USBPHY_DIRECT_DM_PULLDN_EN_LSB _U(6)
+#define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS _u(0x00000040)
+#define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB _u(6)
+#define USB_USBPHY_DIRECT_DM_PULLDN_EN_LSB _u(6)
#define USB_USBPHY_DIRECT_DM_PULLDN_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_DM_PULLUP_EN
// Description : DM pull up enable
-#define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS _U(0x00000020)
-#define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB _U(5)
-#define USB_USBPHY_DIRECT_DM_PULLUP_EN_LSB _U(5)
+#define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS _u(0x00000020)
+#define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB _u(5)
+#define USB_USBPHY_DIRECT_DM_PULLUP_EN_LSB _u(5)
#define USB_USBPHY_DIRECT_DM_PULLUP_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_DM_PULLUP_HISEL
// Description : Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 -
// Pull = Rpu1 + Rpu2
-#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS _U(0x00000010)
-#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB _U(4)
-#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_LSB _U(4)
+#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS _u(0x00000010)
+#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB _u(4)
+#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_LSB _u(4)
#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_DP_PULLDN_EN
// Description : DP pull down enable
-#define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS _U(0x00000004)
-#define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB _U(2)
-#define USB_USBPHY_DIRECT_DP_PULLDN_EN_LSB _U(2)
+#define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS _u(0x00000004)
+#define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB _u(2)
+#define USB_USBPHY_DIRECT_DP_PULLDN_EN_LSB _u(2)
#define USB_USBPHY_DIRECT_DP_PULLDN_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_DP_PULLUP_EN
// Description : DP pull up enable
-#define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS _U(0x00000002)
-#define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB _U(1)
-#define USB_USBPHY_DIRECT_DP_PULLUP_EN_LSB _U(1)
+#define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS _u(0x00000002)
+#define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB _u(1)
+#define USB_USBPHY_DIRECT_DP_PULLUP_EN_LSB _u(1)
#define USB_USBPHY_DIRECT_DP_PULLUP_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_DP_PULLUP_HISEL
// Description : Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 -
// Pull = Rpu1 + Rpu2
-#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS _U(0x00000001)
-#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB _U(0)
-#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_LSB _U(0)
+#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS _u(0x00000001)
+#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB _u(0)
+#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_LSB _u(0)
#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_ACCESS "RW"
// =============================================================================
// Register : USB_USBPHY_DIRECT_OVERRIDE
// Description : Override enable for each control in usbphy_direct
-#define USB_USBPHY_DIRECT_OVERRIDE_OFFSET _U(0x00000080)
-#define USB_USBPHY_DIRECT_OVERRIDE_BITS _U(0x00009fff)
-#define USB_USBPHY_DIRECT_OVERRIDE_RESET _U(0x00000000)
+#define USB_USBPHY_DIRECT_OVERRIDE_OFFSET _u(0x00000080)
+#define USB_USBPHY_DIRECT_OVERRIDE_BITS _u(0x00009fff)
+#define USB_USBPHY_DIRECT_OVERRIDE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN
// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS _U(0x00008000)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB _U(15)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_LSB _U(15)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS _u(0x00008000)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB _u(15)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_LSB _u(15)
#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN
// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS _U(0x00001000)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB _U(12)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_LSB _U(12)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS _u(0x00001000)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB _u(12)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_LSB _u(12)
#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN
// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS _U(0x00000800)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB _U(11)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_LSB _U(11)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS _u(0x00000800)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB _u(11)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_LSB _u(11)
#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN
// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS _U(0x00000400)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB _U(10)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_LSB _U(10)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS _u(0x00000400)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB _u(10)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_LSB _u(10)
#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN
// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS _U(0x00000200)
-#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB _U(9)
-#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_LSB _U(9)
+#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS _u(0x00000200)
+#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB _u(9)
+#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_LSB _u(9)
#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN
// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS _U(0x00000100)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB _U(8)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_LSB _U(8)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS _u(0x00000100)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB _u(8)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_LSB _u(8)
#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN
// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS _U(0x00000080)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB _U(7)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_LSB _U(7)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS _u(0x00000080)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB _u(7)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_LSB _u(7)
#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN
// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS _U(0x00000040)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB _U(6)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_LSB _U(6)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS _u(0x00000040)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB _u(6)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_LSB _u(6)
#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN
// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS _U(0x00000020)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB _U(5)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_LSB _U(5)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS _u(0x00000020)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB _u(5)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_LSB _u(5)
#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN
// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS _U(0x00000010)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB _U(4)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_LSB _U(4)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000010)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB _u(4)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_LSB _u(4)
#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN
// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS _U(0x00000008)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB _U(3)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_LSB _U(3)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000008)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB _u(3)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_LSB _u(3)
#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN
// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS _U(0x00000004)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB _U(2)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_LSB _U(2)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS _u(0x00000004)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB _u(2)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_LSB _u(2)
#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN
// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS _U(0x00000002)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB _U(1)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_LSB _U(1)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000002)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB _u(1)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_LSB _u(1)
#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN
// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET _U(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS _U(0x00000001)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB _U(0)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_LSB _U(0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000001)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB _u(0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_LSB _u(0)
#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW"
// =============================================================================
// Register : USB_USBPHY_TRIM
// Description : Used to adjust trim values of USB phy pull down resistors.
-#define USB_USBPHY_TRIM_OFFSET _U(0x00000084)
-#define USB_USBPHY_TRIM_BITS _U(0x00001f1f)
-#define USB_USBPHY_TRIM_RESET _U(0x00001f1f)
+#define USB_USBPHY_TRIM_OFFSET _u(0x00000084)
+#define USB_USBPHY_TRIM_BITS _u(0x00001f1f)
+#define USB_USBPHY_TRIM_RESET _u(0x00001f1f)
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_TRIM_DM_PULLDN_TRIM
// Description : Value to drive to USB PHY
// DM pulldown resistor trim control
// Experimental data suggests that the reset value will work, but
// this register allows adjustment if required
-#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_RESET _U(0x1f)
-#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_BITS _U(0x00001f00)
-#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_MSB _U(12)
-#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_LSB _U(8)
+#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_RESET _u(0x1f)
+#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_BITS _u(0x00001f00)
+#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_MSB _u(12)
+#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_LSB _u(8)
#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_USBPHY_TRIM_DP_PULLDN_TRIM
@@ -2882,722 +2882,722 @@
// DP pulldown resistor trim control
// Experimental data suggests that the reset value will work, but
// this register allows adjustment if required
-#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_RESET _U(0x1f)
-#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_BITS _U(0x0000001f)
-#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_MSB _U(4)
-#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_LSB _U(0)
+#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_RESET _u(0x1f)
+#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_BITS _u(0x0000001f)
+#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_MSB _u(4)
+#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_LSB _u(0)
#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_ACCESS "RW"
// =============================================================================
// Register : USB_INTR
// Description : Raw Interrupts
-#define USB_INTR_OFFSET _U(0x0000008c)
-#define USB_INTR_BITS _U(0x000fffff)
-#define USB_INTR_RESET _U(0x00000000)
+#define USB_INTR_OFFSET _u(0x0000008c)
+#define USB_INTR_BITS _u(0x000fffff)
+#define USB_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_INTR_EP_STALL_NAK
// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
// clearing all bits in EP_STATUS_STALL_NAK.
-#define USB_INTR_EP_STALL_NAK_RESET _U(0x0)
-#define USB_INTR_EP_STALL_NAK_BITS _U(0x00080000)
-#define USB_INTR_EP_STALL_NAK_MSB _U(19)
-#define USB_INTR_EP_STALL_NAK_LSB _U(19)
+#define USB_INTR_EP_STALL_NAK_RESET _u(0x0)
+#define USB_INTR_EP_STALL_NAK_BITS _u(0x00080000)
+#define USB_INTR_EP_STALL_NAK_MSB _u(19)
+#define USB_INTR_EP_STALL_NAK_LSB _u(19)
#define USB_INTR_EP_STALL_NAK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_ABORT_DONE
// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
// bits in ABORT_DONE.
-#define USB_INTR_ABORT_DONE_RESET _U(0x0)
-#define USB_INTR_ABORT_DONE_BITS _U(0x00040000)
-#define USB_INTR_ABORT_DONE_MSB _U(18)
-#define USB_INTR_ABORT_DONE_LSB _U(18)
+#define USB_INTR_ABORT_DONE_RESET _u(0x0)
+#define USB_INTR_ABORT_DONE_BITS _u(0x00040000)
+#define USB_INTR_ABORT_DONE_MSB _u(18)
+#define USB_INTR_ABORT_DONE_LSB _u(18)
#define USB_INTR_ABORT_DONE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_DEV_SOF
// Description : Set every time the device receives a SOF (Start of Frame)
// packet. Cleared by reading SOF_RD
-#define USB_INTR_DEV_SOF_RESET _U(0x0)
-#define USB_INTR_DEV_SOF_BITS _U(0x00020000)
-#define USB_INTR_DEV_SOF_MSB _U(17)
-#define USB_INTR_DEV_SOF_LSB _U(17)
+#define USB_INTR_DEV_SOF_RESET _u(0x0)
+#define USB_INTR_DEV_SOF_BITS _u(0x00020000)
+#define USB_INTR_DEV_SOF_MSB _u(17)
+#define USB_INTR_DEV_SOF_LSB _u(17)
#define USB_INTR_DEV_SOF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_SETUP_REQ
// Description : Device. Source: SIE_STATUS.SETUP_REC
-#define USB_INTR_SETUP_REQ_RESET _U(0x0)
-#define USB_INTR_SETUP_REQ_BITS _U(0x00010000)
-#define USB_INTR_SETUP_REQ_MSB _U(16)
-#define USB_INTR_SETUP_REQ_LSB _U(16)
+#define USB_INTR_SETUP_REQ_RESET _u(0x0)
+#define USB_INTR_SETUP_REQ_BITS _u(0x00010000)
+#define USB_INTR_SETUP_REQ_MSB _u(16)
+#define USB_INTR_SETUP_REQ_LSB _u(16)
#define USB_INTR_SETUP_REQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_DEV_RESUME_FROM_HOST
// Description : Set when the device receives a resume from the host. Cleared by
// writing to SIE_STATUS.RESUME
-#define USB_INTR_DEV_RESUME_FROM_HOST_RESET _U(0x0)
-#define USB_INTR_DEV_RESUME_FROM_HOST_BITS _U(0x00008000)
-#define USB_INTR_DEV_RESUME_FROM_HOST_MSB _U(15)
-#define USB_INTR_DEV_RESUME_FROM_HOST_LSB _U(15)
+#define USB_INTR_DEV_RESUME_FROM_HOST_RESET _u(0x0)
+#define USB_INTR_DEV_RESUME_FROM_HOST_BITS _u(0x00008000)
+#define USB_INTR_DEV_RESUME_FROM_HOST_MSB _u(15)
+#define USB_INTR_DEV_RESUME_FROM_HOST_LSB _u(15)
#define USB_INTR_DEV_RESUME_FROM_HOST_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_DEV_SUSPEND
// Description : Set when the device suspend state changes. Cleared by writing
// to SIE_STATUS.SUSPENDED
-#define USB_INTR_DEV_SUSPEND_RESET _U(0x0)
-#define USB_INTR_DEV_SUSPEND_BITS _U(0x00004000)
-#define USB_INTR_DEV_SUSPEND_MSB _U(14)
-#define USB_INTR_DEV_SUSPEND_LSB _U(14)
+#define USB_INTR_DEV_SUSPEND_RESET _u(0x0)
+#define USB_INTR_DEV_SUSPEND_BITS _u(0x00004000)
+#define USB_INTR_DEV_SUSPEND_MSB _u(14)
+#define USB_INTR_DEV_SUSPEND_LSB _u(14)
#define USB_INTR_DEV_SUSPEND_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_DEV_CONN_DIS
// Description : Set when the device connection state changes. Cleared by
// writing to SIE_STATUS.CONNECTED
-#define USB_INTR_DEV_CONN_DIS_RESET _U(0x0)
-#define USB_INTR_DEV_CONN_DIS_BITS _U(0x00002000)
-#define USB_INTR_DEV_CONN_DIS_MSB _U(13)
-#define USB_INTR_DEV_CONN_DIS_LSB _U(13)
+#define USB_INTR_DEV_CONN_DIS_RESET _u(0x0)
+#define USB_INTR_DEV_CONN_DIS_BITS _u(0x00002000)
+#define USB_INTR_DEV_CONN_DIS_MSB _u(13)
+#define USB_INTR_DEV_CONN_DIS_LSB _u(13)
#define USB_INTR_DEV_CONN_DIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_BUS_RESET
// Description : Source: SIE_STATUS.BUS_RESET
-#define USB_INTR_BUS_RESET_RESET _U(0x0)
-#define USB_INTR_BUS_RESET_BITS _U(0x00001000)
-#define USB_INTR_BUS_RESET_MSB _U(12)
-#define USB_INTR_BUS_RESET_LSB _U(12)
+#define USB_INTR_BUS_RESET_RESET _u(0x0)
+#define USB_INTR_BUS_RESET_BITS _u(0x00001000)
+#define USB_INTR_BUS_RESET_MSB _u(12)
+#define USB_INTR_BUS_RESET_LSB _u(12)
#define USB_INTR_BUS_RESET_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_VBUS_DETECT
// Description : Source: SIE_STATUS.VBUS_DETECT
-#define USB_INTR_VBUS_DETECT_RESET _U(0x0)
-#define USB_INTR_VBUS_DETECT_BITS _U(0x00000800)
-#define USB_INTR_VBUS_DETECT_MSB _U(11)
-#define USB_INTR_VBUS_DETECT_LSB _U(11)
+#define USB_INTR_VBUS_DETECT_RESET _u(0x0)
+#define USB_INTR_VBUS_DETECT_BITS _u(0x00000800)
+#define USB_INTR_VBUS_DETECT_MSB _u(11)
+#define USB_INTR_VBUS_DETECT_LSB _u(11)
#define USB_INTR_VBUS_DETECT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_STALL
// Description : Source: SIE_STATUS.STALL_REC
-#define USB_INTR_STALL_RESET _U(0x0)
-#define USB_INTR_STALL_BITS _U(0x00000400)
-#define USB_INTR_STALL_MSB _U(10)
-#define USB_INTR_STALL_LSB _U(10)
+#define USB_INTR_STALL_RESET _u(0x0)
+#define USB_INTR_STALL_BITS _u(0x00000400)
+#define USB_INTR_STALL_MSB _u(10)
+#define USB_INTR_STALL_LSB _u(10)
#define USB_INTR_STALL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_ERROR_CRC
// Description : Source: SIE_STATUS.CRC_ERROR
-#define USB_INTR_ERROR_CRC_RESET _U(0x0)
-#define USB_INTR_ERROR_CRC_BITS _U(0x00000200)
-#define USB_INTR_ERROR_CRC_MSB _U(9)
-#define USB_INTR_ERROR_CRC_LSB _U(9)
+#define USB_INTR_ERROR_CRC_RESET _u(0x0)
+#define USB_INTR_ERROR_CRC_BITS _u(0x00000200)
+#define USB_INTR_ERROR_CRC_MSB _u(9)
+#define USB_INTR_ERROR_CRC_LSB _u(9)
#define USB_INTR_ERROR_CRC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_ERROR_BIT_STUFF
// Description : Source: SIE_STATUS.BIT_STUFF_ERROR
-#define USB_INTR_ERROR_BIT_STUFF_RESET _U(0x0)
-#define USB_INTR_ERROR_BIT_STUFF_BITS _U(0x00000100)
-#define USB_INTR_ERROR_BIT_STUFF_MSB _U(8)
-#define USB_INTR_ERROR_BIT_STUFF_LSB _U(8)
+#define USB_INTR_ERROR_BIT_STUFF_RESET _u(0x0)
+#define USB_INTR_ERROR_BIT_STUFF_BITS _u(0x00000100)
+#define USB_INTR_ERROR_BIT_STUFF_MSB _u(8)
+#define USB_INTR_ERROR_BIT_STUFF_LSB _u(8)
#define USB_INTR_ERROR_BIT_STUFF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_ERROR_RX_OVERFLOW
// Description : Source: SIE_STATUS.RX_OVERFLOW
-#define USB_INTR_ERROR_RX_OVERFLOW_RESET _U(0x0)
-#define USB_INTR_ERROR_RX_OVERFLOW_BITS _U(0x00000080)
-#define USB_INTR_ERROR_RX_OVERFLOW_MSB _U(7)
-#define USB_INTR_ERROR_RX_OVERFLOW_LSB _U(7)
+#define USB_INTR_ERROR_RX_OVERFLOW_RESET _u(0x0)
+#define USB_INTR_ERROR_RX_OVERFLOW_BITS _u(0x00000080)
+#define USB_INTR_ERROR_RX_OVERFLOW_MSB _u(7)
+#define USB_INTR_ERROR_RX_OVERFLOW_LSB _u(7)
#define USB_INTR_ERROR_RX_OVERFLOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_ERROR_RX_TIMEOUT
// Description : Source: SIE_STATUS.RX_TIMEOUT
-#define USB_INTR_ERROR_RX_TIMEOUT_RESET _U(0x0)
-#define USB_INTR_ERROR_RX_TIMEOUT_BITS _U(0x00000040)
-#define USB_INTR_ERROR_RX_TIMEOUT_MSB _U(6)
-#define USB_INTR_ERROR_RX_TIMEOUT_LSB _U(6)
+#define USB_INTR_ERROR_RX_TIMEOUT_RESET _u(0x0)
+#define USB_INTR_ERROR_RX_TIMEOUT_BITS _u(0x00000040)
+#define USB_INTR_ERROR_RX_TIMEOUT_MSB _u(6)
+#define USB_INTR_ERROR_RX_TIMEOUT_LSB _u(6)
#define USB_INTR_ERROR_RX_TIMEOUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_ERROR_DATA_SEQ
// Description : Source: SIE_STATUS.DATA_SEQ_ERROR
-#define USB_INTR_ERROR_DATA_SEQ_RESET _U(0x0)
-#define USB_INTR_ERROR_DATA_SEQ_BITS _U(0x00000020)
-#define USB_INTR_ERROR_DATA_SEQ_MSB _U(5)
-#define USB_INTR_ERROR_DATA_SEQ_LSB _U(5)
+#define USB_INTR_ERROR_DATA_SEQ_RESET _u(0x0)
+#define USB_INTR_ERROR_DATA_SEQ_BITS _u(0x00000020)
+#define USB_INTR_ERROR_DATA_SEQ_MSB _u(5)
+#define USB_INTR_ERROR_DATA_SEQ_LSB _u(5)
#define USB_INTR_ERROR_DATA_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_BUFF_STATUS
// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
// all bits in BUFF_STATUS.
-#define USB_INTR_BUFF_STATUS_RESET _U(0x0)
-#define USB_INTR_BUFF_STATUS_BITS _U(0x00000010)
-#define USB_INTR_BUFF_STATUS_MSB _U(4)
-#define USB_INTR_BUFF_STATUS_LSB _U(4)
+#define USB_INTR_BUFF_STATUS_RESET _u(0x0)
+#define USB_INTR_BUFF_STATUS_BITS _u(0x00000010)
+#define USB_INTR_BUFF_STATUS_MSB _u(4)
+#define USB_INTR_BUFF_STATUS_LSB _u(4)
#define USB_INTR_BUFF_STATUS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_TRANS_COMPLETE
// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
// writing to this bit.
-#define USB_INTR_TRANS_COMPLETE_RESET _U(0x0)
-#define USB_INTR_TRANS_COMPLETE_BITS _U(0x00000008)
-#define USB_INTR_TRANS_COMPLETE_MSB _U(3)
-#define USB_INTR_TRANS_COMPLETE_LSB _U(3)
+#define USB_INTR_TRANS_COMPLETE_RESET _u(0x0)
+#define USB_INTR_TRANS_COMPLETE_BITS _u(0x00000008)
+#define USB_INTR_TRANS_COMPLETE_MSB _u(3)
+#define USB_INTR_TRANS_COMPLETE_LSB _u(3)
#define USB_INTR_TRANS_COMPLETE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_HOST_SOF
// Description : Host: raised every time the host sends a SOF (Start of Frame).
// Cleared by reading SOF_RD
-#define USB_INTR_HOST_SOF_RESET _U(0x0)
-#define USB_INTR_HOST_SOF_BITS _U(0x00000004)
-#define USB_INTR_HOST_SOF_MSB _U(2)
-#define USB_INTR_HOST_SOF_LSB _U(2)
+#define USB_INTR_HOST_SOF_RESET _u(0x0)
+#define USB_INTR_HOST_SOF_BITS _u(0x00000004)
+#define USB_INTR_HOST_SOF_MSB _u(2)
+#define USB_INTR_HOST_SOF_LSB _u(2)
#define USB_INTR_HOST_SOF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_HOST_RESUME
// Description : Host: raised when a device wakes up the host. Cleared by
// writing to SIE_STATUS.RESUME
-#define USB_INTR_HOST_RESUME_RESET _U(0x0)
-#define USB_INTR_HOST_RESUME_BITS _U(0x00000002)
-#define USB_INTR_HOST_RESUME_MSB _U(1)
-#define USB_INTR_HOST_RESUME_LSB _U(1)
+#define USB_INTR_HOST_RESUME_RESET _u(0x0)
+#define USB_INTR_HOST_RESUME_BITS _u(0x00000002)
+#define USB_INTR_HOST_RESUME_MSB _u(1)
+#define USB_INTR_HOST_RESUME_LSB _u(1)
#define USB_INTR_HOST_RESUME_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTR_HOST_CONN_DIS
// Description : Host: raised when a device is connected or disconnected (i.e.
// when SIE_STATUS.SPEED changes). Cleared by writing to
// SIE_STATUS.SPEED
-#define USB_INTR_HOST_CONN_DIS_RESET _U(0x0)
-#define USB_INTR_HOST_CONN_DIS_BITS _U(0x00000001)
-#define USB_INTR_HOST_CONN_DIS_MSB _U(0)
-#define USB_INTR_HOST_CONN_DIS_LSB _U(0)
+#define USB_INTR_HOST_CONN_DIS_RESET _u(0x0)
+#define USB_INTR_HOST_CONN_DIS_BITS _u(0x00000001)
+#define USB_INTR_HOST_CONN_DIS_MSB _u(0)
+#define USB_INTR_HOST_CONN_DIS_LSB _u(0)
#define USB_INTR_HOST_CONN_DIS_ACCESS "RO"
// =============================================================================
// Register : USB_INTE
// Description : Interrupt Enable
-#define USB_INTE_OFFSET _U(0x00000090)
-#define USB_INTE_BITS _U(0x000fffff)
-#define USB_INTE_RESET _U(0x00000000)
+#define USB_INTE_OFFSET _u(0x00000090)
+#define USB_INTE_BITS _u(0x000fffff)
+#define USB_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_INTE_EP_STALL_NAK
// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
// clearing all bits in EP_STATUS_STALL_NAK.
-#define USB_INTE_EP_STALL_NAK_RESET _U(0x0)
-#define USB_INTE_EP_STALL_NAK_BITS _U(0x00080000)
-#define USB_INTE_EP_STALL_NAK_MSB _U(19)
-#define USB_INTE_EP_STALL_NAK_LSB _U(19)
+#define USB_INTE_EP_STALL_NAK_RESET _u(0x0)
+#define USB_INTE_EP_STALL_NAK_BITS _u(0x00080000)
+#define USB_INTE_EP_STALL_NAK_MSB _u(19)
+#define USB_INTE_EP_STALL_NAK_LSB _u(19)
#define USB_INTE_EP_STALL_NAK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_ABORT_DONE
// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
// bits in ABORT_DONE.
-#define USB_INTE_ABORT_DONE_RESET _U(0x0)
-#define USB_INTE_ABORT_DONE_BITS _U(0x00040000)
-#define USB_INTE_ABORT_DONE_MSB _U(18)
-#define USB_INTE_ABORT_DONE_LSB _U(18)
+#define USB_INTE_ABORT_DONE_RESET _u(0x0)
+#define USB_INTE_ABORT_DONE_BITS _u(0x00040000)
+#define USB_INTE_ABORT_DONE_MSB _u(18)
+#define USB_INTE_ABORT_DONE_LSB _u(18)
#define USB_INTE_ABORT_DONE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_DEV_SOF
// Description : Set every time the device receives a SOF (Start of Frame)
// packet. Cleared by reading SOF_RD
-#define USB_INTE_DEV_SOF_RESET _U(0x0)
-#define USB_INTE_DEV_SOF_BITS _U(0x00020000)
-#define USB_INTE_DEV_SOF_MSB _U(17)
-#define USB_INTE_DEV_SOF_LSB _U(17)
+#define USB_INTE_DEV_SOF_RESET _u(0x0)
+#define USB_INTE_DEV_SOF_BITS _u(0x00020000)
+#define USB_INTE_DEV_SOF_MSB _u(17)
+#define USB_INTE_DEV_SOF_LSB _u(17)
#define USB_INTE_DEV_SOF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_SETUP_REQ
// Description : Device. Source: SIE_STATUS.SETUP_REC
-#define USB_INTE_SETUP_REQ_RESET _U(0x0)
-#define USB_INTE_SETUP_REQ_BITS _U(0x00010000)
-#define USB_INTE_SETUP_REQ_MSB _U(16)
-#define USB_INTE_SETUP_REQ_LSB _U(16)
+#define USB_INTE_SETUP_REQ_RESET _u(0x0)
+#define USB_INTE_SETUP_REQ_BITS _u(0x00010000)
+#define USB_INTE_SETUP_REQ_MSB _u(16)
+#define USB_INTE_SETUP_REQ_LSB _u(16)
#define USB_INTE_SETUP_REQ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_DEV_RESUME_FROM_HOST
// Description : Set when the device receives a resume from the host. Cleared by
// writing to SIE_STATUS.RESUME
-#define USB_INTE_DEV_RESUME_FROM_HOST_RESET _U(0x0)
-#define USB_INTE_DEV_RESUME_FROM_HOST_BITS _U(0x00008000)
-#define USB_INTE_DEV_RESUME_FROM_HOST_MSB _U(15)
-#define USB_INTE_DEV_RESUME_FROM_HOST_LSB _U(15)
+#define USB_INTE_DEV_RESUME_FROM_HOST_RESET _u(0x0)
+#define USB_INTE_DEV_RESUME_FROM_HOST_BITS _u(0x00008000)
+#define USB_INTE_DEV_RESUME_FROM_HOST_MSB _u(15)
+#define USB_INTE_DEV_RESUME_FROM_HOST_LSB _u(15)
#define USB_INTE_DEV_RESUME_FROM_HOST_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_DEV_SUSPEND
// Description : Set when the device suspend state changes. Cleared by writing
// to SIE_STATUS.SUSPENDED
-#define USB_INTE_DEV_SUSPEND_RESET _U(0x0)
-#define USB_INTE_DEV_SUSPEND_BITS _U(0x00004000)
-#define USB_INTE_DEV_SUSPEND_MSB _U(14)
-#define USB_INTE_DEV_SUSPEND_LSB _U(14)
+#define USB_INTE_DEV_SUSPEND_RESET _u(0x0)
+#define USB_INTE_DEV_SUSPEND_BITS _u(0x00004000)
+#define USB_INTE_DEV_SUSPEND_MSB _u(14)
+#define USB_INTE_DEV_SUSPEND_LSB _u(14)
#define USB_INTE_DEV_SUSPEND_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_DEV_CONN_DIS
// Description : Set when the device connection state changes. Cleared by
// writing to SIE_STATUS.CONNECTED
-#define USB_INTE_DEV_CONN_DIS_RESET _U(0x0)
-#define USB_INTE_DEV_CONN_DIS_BITS _U(0x00002000)
-#define USB_INTE_DEV_CONN_DIS_MSB _U(13)
-#define USB_INTE_DEV_CONN_DIS_LSB _U(13)
+#define USB_INTE_DEV_CONN_DIS_RESET _u(0x0)
+#define USB_INTE_DEV_CONN_DIS_BITS _u(0x00002000)
+#define USB_INTE_DEV_CONN_DIS_MSB _u(13)
+#define USB_INTE_DEV_CONN_DIS_LSB _u(13)
#define USB_INTE_DEV_CONN_DIS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_BUS_RESET
// Description : Source: SIE_STATUS.BUS_RESET
-#define USB_INTE_BUS_RESET_RESET _U(0x0)
-#define USB_INTE_BUS_RESET_BITS _U(0x00001000)
-#define USB_INTE_BUS_RESET_MSB _U(12)
-#define USB_INTE_BUS_RESET_LSB _U(12)
+#define USB_INTE_BUS_RESET_RESET _u(0x0)
+#define USB_INTE_BUS_RESET_BITS _u(0x00001000)
+#define USB_INTE_BUS_RESET_MSB _u(12)
+#define USB_INTE_BUS_RESET_LSB _u(12)
#define USB_INTE_BUS_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_VBUS_DETECT
// Description : Source: SIE_STATUS.VBUS_DETECT
-#define USB_INTE_VBUS_DETECT_RESET _U(0x0)
-#define USB_INTE_VBUS_DETECT_BITS _U(0x00000800)
-#define USB_INTE_VBUS_DETECT_MSB _U(11)
-#define USB_INTE_VBUS_DETECT_LSB _U(11)
+#define USB_INTE_VBUS_DETECT_RESET _u(0x0)
+#define USB_INTE_VBUS_DETECT_BITS _u(0x00000800)
+#define USB_INTE_VBUS_DETECT_MSB _u(11)
+#define USB_INTE_VBUS_DETECT_LSB _u(11)
#define USB_INTE_VBUS_DETECT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_STALL
// Description : Source: SIE_STATUS.STALL_REC
-#define USB_INTE_STALL_RESET _U(0x0)
-#define USB_INTE_STALL_BITS _U(0x00000400)
-#define USB_INTE_STALL_MSB _U(10)
-#define USB_INTE_STALL_LSB _U(10)
+#define USB_INTE_STALL_RESET _u(0x0)
+#define USB_INTE_STALL_BITS _u(0x00000400)
+#define USB_INTE_STALL_MSB _u(10)
+#define USB_INTE_STALL_LSB _u(10)
#define USB_INTE_STALL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_ERROR_CRC
// Description : Source: SIE_STATUS.CRC_ERROR
-#define USB_INTE_ERROR_CRC_RESET _U(0x0)
-#define USB_INTE_ERROR_CRC_BITS _U(0x00000200)
-#define USB_INTE_ERROR_CRC_MSB _U(9)
-#define USB_INTE_ERROR_CRC_LSB _U(9)
+#define USB_INTE_ERROR_CRC_RESET _u(0x0)
+#define USB_INTE_ERROR_CRC_BITS _u(0x00000200)
+#define USB_INTE_ERROR_CRC_MSB _u(9)
+#define USB_INTE_ERROR_CRC_LSB _u(9)
#define USB_INTE_ERROR_CRC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_ERROR_BIT_STUFF
// Description : Source: SIE_STATUS.BIT_STUFF_ERROR
-#define USB_INTE_ERROR_BIT_STUFF_RESET _U(0x0)
-#define USB_INTE_ERROR_BIT_STUFF_BITS _U(0x00000100)
-#define USB_INTE_ERROR_BIT_STUFF_MSB _U(8)
-#define USB_INTE_ERROR_BIT_STUFF_LSB _U(8)
+#define USB_INTE_ERROR_BIT_STUFF_RESET _u(0x0)
+#define USB_INTE_ERROR_BIT_STUFF_BITS _u(0x00000100)
+#define USB_INTE_ERROR_BIT_STUFF_MSB _u(8)
+#define USB_INTE_ERROR_BIT_STUFF_LSB _u(8)
#define USB_INTE_ERROR_BIT_STUFF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_ERROR_RX_OVERFLOW
// Description : Source: SIE_STATUS.RX_OVERFLOW
-#define USB_INTE_ERROR_RX_OVERFLOW_RESET _U(0x0)
-#define USB_INTE_ERROR_RX_OVERFLOW_BITS _U(0x00000080)
-#define USB_INTE_ERROR_RX_OVERFLOW_MSB _U(7)
-#define USB_INTE_ERROR_RX_OVERFLOW_LSB _U(7)
+#define USB_INTE_ERROR_RX_OVERFLOW_RESET _u(0x0)
+#define USB_INTE_ERROR_RX_OVERFLOW_BITS _u(0x00000080)
+#define USB_INTE_ERROR_RX_OVERFLOW_MSB _u(7)
+#define USB_INTE_ERROR_RX_OVERFLOW_LSB _u(7)
#define USB_INTE_ERROR_RX_OVERFLOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_ERROR_RX_TIMEOUT
// Description : Source: SIE_STATUS.RX_TIMEOUT
-#define USB_INTE_ERROR_RX_TIMEOUT_RESET _U(0x0)
-#define USB_INTE_ERROR_RX_TIMEOUT_BITS _U(0x00000040)
-#define USB_INTE_ERROR_RX_TIMEOUT_MSB _U(6)
-#define USB_INTE_ERROR_RX_TIMEOUT_LSB _U(6)
+#define USB_INTE_ERROR_RX_TIMEOUT_RESET _u(0x0)
+#define USB_INTE_ERROR_RX_TIMEOUT_BITS _u(0x00000040)
+#define USB_INTE_ERROR_RX_TIMEOUT_MSB _u(6)
+#define USB_INTE_ERROR_RX_TIMEOUT_LSB _u(6)
#define USB_INTE_ERROR_RX_TIMEOUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_ERROR_DATA_SEQ
// Description : Source: SIE_STATUS.DATA_SEQ_ERROR
-#define USB_INTE_ERROR_DATA_SEQ_RESET _U(0x0)
-#define USB_INTE_ERROR_DATA_SEQ_BITS _U(0x00000020)
-#define USB_INTE_ERROR_DATA_SEQ_MSB _U(5)
-#define USB_INTE_ERROR_DATA_SEQ_LSB _U(5)
+#define USB_INTE_ERROR_DATA_SEQ_RESET _u(0x0)
+#define USB_INTE_ERROR_DATA_SEQ_BITS _u(0x00000020)
+#define USB_INTE_ERROR_DATA_SEQ_MSB _u(5)
+#define USB_INTE_ERROR_DATA_SEQ_LSB _u(5)
#define USB_INTE_ERROR_DATA_SEQ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_BUFF_STATUS
// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
// all bits in BUFF_STATUS.
-#define USB_INTE_BUFF_STATUS_RESET _U(0x0)
-#define USB_INTE_BUFF_STATUS_BITS _U(0x00000010)
-#define USB_INTE_BUFF_STATUS_MSB _U(4)
-#define USB_INTE_BUFF_STATUS_LSB _U(4)
+#define USB_INTE_BUFF_STATUS_RESET _u(0x0)
+#define USB_INTE_BUFF_STATUS_BITS _u(0x00000010)
+#define USB_INTE_BUFF_STATUS_MSB _u(4)
+#define USB_INTE_BUFF_STATUS_LSB _u(4)
#define USB_INTE_BUFF_STATUS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_TRANS_COMPLETE
// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
// writing to this bit.
-#define USB_INTE_TRANS_COMPLETE_RESET _U(0x0)
-#define USB_INTE_TRANS_COMPLETE_BITS _U(0x00000008)
-#define USB_INTE_TRANS_COMPLETE_MSB _U(3)
-#define USB_INTE_TRANS_COMPLETE_LSB _U(3)
+#define USB_INTE_TRANS_COMPLETE_RESET _u(0x0)
+#define USB_INTE_TRANS_COMPLETE_BITS _u(0x00000008)
+#define USB_INTE_TRANS_COMPLETE_MSB _u(3)
+#define USB_INTE_TRANS_COMPLETE_LSB _u(3)
#define USB_INTE_TRANS_COMPLETE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_HOST_SOF
// Description : Host: raised every time the host sends a SOF (Start of Frame).
// Cleared by reading SOF_RD
-#define USB_INTE_HOST_SOF_RESET _U(0x0)
-#define USB_INTE_HOST_SOF_BITS _U(0x00000004)
-#define USB_INTE_HOST_SOF_MSB _U(2)
-#define USB_INTE_HOST_SOF_LSB _U(2)
+#define USB_INTE_HOST_SOF_RESET _u(0x0)
+#define USB_INTE_HOST_SOF_BITS _u(0x00000004)
+#define USB_INTE_HOST_SOF_MSB _u(2)
+#define USB_INTE_HOST_SOF_LSB _u(2)
#define USB_INTE_HOST_SOF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_HOST_RESUME
// Description : Host: raised when a device wakes up the host. Cleared by
// writing to SIE_STATUS.RESUME
-#define USB_INTE_HOST_RESUME_RESET _U(0x0)
-#define USB_INTE_HOST_RESUME_BITS _U(0x00000002)
-#define USB_INTE_HOST_RESUME_MSB _U(1)
-#define USB_INTE_HOST_RESUME_LSB _U(1)
+#define USB_INTE_HOST_RESUME_RESET _u(0x0)
+#define USB_INTE_HOST_RESUME_BITS _u(0x00000002)
+#define USB_INTE_HOST_RESUME_MSB _u(1)
+#define USB_INTE_HOST_RESUME_LSB _u(1)
#define USB_INTE_HOST_RESUME_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTE_HOST_CONN_DIS
// Description : Host: raised when a device is connected or disconnected (i.e.
// when SIE_STATUS.SPEED changes). Cleared by writing to
// SIE_STATUS.SPEED
-#define USB_INTE_HOST_CONN_DIS_RESET _U(0x0)
-#define USB_INTE_HOST_CONN_DIS_BITS _U(0x00000001)
-#define USB_INTE_HOST_CONN_DIS_MSB _U(0)
-#define USB_INTE_HOST_CONN_DIS_LSB _U(0)
+#define USB_INTE_HOST_CONN_DIS_RESET _u(0x0)
+#define USB_INTE_HOST_CONN_DIS_BITS _u(0x00000001)
+#define USB_INTE_HOST_CONN_DIS_MSB _u(0)
+#define USB_INTE_HOST_CONN_DIS_LSB _u(0)
#define USB_INTE_HOST_CONN_DIS_ACCESS "RW"
// =============================================================================
// Register : USB_INTF
// Description : Interrupt Force
-#define USB_INTF_OFFSET _U(0x00000094)
-#define USB_INTF_BITS _U(0x000fffff)
-#define USB_INTF_RESET _U(0x00000000)
+#define USB_INTF_OFFSET _u(0x00000094)
+#define USB_INTF_BITS _u(0x000fffff)
+#define USB_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_INTF_EP_STALL_NAK
// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
// clearing all bits in EP_STATUS_STALL_NAK.
-#define USB_INTF_EP_STALL_NAK_RESET _U(0x0)
-#define USB_INTF_EP_STALL_NAK_BITS _U(0x00080000)
-#define USB_INTF_EP_STALL_NAK_MSB _U(19)
-#define USB_INTF_EP_STALL_NAK_LSB _U(19)
+#define USB_INTF_EP_STALL_NAK_RESET _u(0x0)
+#define USB_INTF_EP_STALL_NAK_BITS _u(0x00080000)
+#define USB_INTF_EP_STALL_NAK_MSB _u(19)
+#define USB_INTF_EP_STALL_NAK_LSB _u(19)
#define USB_INTF_EP_STALL_NAK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_ABORT_DONE
// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
// bits in ABORT_DONE.
-#define USB_INTF_ABORT_DONE_RESET _U(0x0)
-#define USB_INTF_ABORT_DONE_BITS _U(0x00040000)
-#define USB_INTF_ABORT_DONE_MSB _U(18)
-#define USB_INTF_ABORT_DONE_LSB _U(18)
+#define USB_INTF_ABORT_DONE_RESET _u(0x0)
+#define USB_INTF_ABORT_DONE_BITS _u(0x00040000)
+#define USB_INTF_ABORT_DONE_MSB _u(18)
+#define USB_INTF_ABORT_DONE_LSB _u(18)
#define USB_INTF_ABORT_DONE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_DEV_SOF
// Description : Set every time the device receives a SOF (Start of Frame)
// packet. Cleared by reading SOF_RD
-#define USB_INTF_DEV_SOF_RESET _U(0x0)
-#define USB_INTF_DEV_SOF_BITS _U(0x00020000)
-#define USB_INTF_DEV_SOF_MSB _U(17)
-#define USB_INTF_DEV_SOF_LSB _U(17)
+#define USB_INTF_DEV_SOF_RESET _u(0x0)
+#define USB_INTF_DEV_SOF_BITS _u(0x00020000)
+#define USB_INTF_DEV_SOF_MSB _u(17)
+#define USB_INTF_DEV_SOF_LSB _u(17)
#define USB_INTF_DEV_SOF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_SETUP_REQ
// Description : Device. Source: SIE_STATUS.SETUP_REC
-#define USB_INTF_SETUP_REQ_RESET _U(0x0)
-#define USB_INTF_SETUP_REQ_BITS _U(0x00010000)
-#define USB_INTF_SETUP_REQ_MSB _U(16)
-#define USB_INTF_SETUP_REQ_LSB _U(16)
+#define USB_INTF_SETUP_REQ_RESET _u(0x0)
+#define USB_INTF_SETUP_REQ_BITS _u(0x00010000)
+#define USB_INTF_SETUP_REQ_MSB _u(16)
+#define USB_INTF_SETUP_REQ_LSB _u(16)
#define USB_INTF_SETUP_REQ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_DEV_RESUME_FROM_HOST
// Description : Set when the device receives a resume from the host. Cleared by
// writing to SIE_STATUS.RESUME
-#define USB_INTF_DEV_RESUME_FROM_HOST_RESET _U(0x0)
-#define USB_INTF_DEV_RESUME_FROM_HOST_BITS _U(0x00008000)
-#define USB_INTF_DEV_RESUME_FROM_HOST_MSB _U(15)
-#define USB_INTF_DEV_RESUME_FROM_HOST_LSB _U(15)
+#define USB_INTF_DEV_RESUME_FROM_HOST_RESET _u(0x0)
+#define USB_INTF_DEV_RESUME_FROM_HOST_BITS _u(0x00008000)
+#define USB_INTF_DEV_RESUME_FROM_HOST_MSB _u(15)
+#define USB_INTF_DEV_RESUME_FROM_HOST_LSB _u(15)
#define USB_INTF_DEV_RESUME_FROM_HOST_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_DEV_SUSPEND
// Description : Set when the device suspend state changes. Cleared by writing
// to SIE_STATUS.SUSPENDED
-#define USB_INTF_DEV_SUSPEND_RESET _U(0x0)
-#define USB_INTF_DEV_SUSPEND_BITS _U(0x00004000)
-#define USB_INTF_DEV_SUSPEND_MSB _U(14)
-#define USB_INTF_DEV_SUSPEND_LSB _U(14)
+#define USB_INTF_DEV_SUSPEND_RESET _u(0x0)
+#define USB_INTF_DEV_SUSPEND_BITS _u(0x00004000)
+#define USB_INTF_DEV_SUSPEND_MSB _u(14)
+#define USB_INTF_DEV_SUSPEND_LSB _u(14)
#define USB_INTF_DEV_SUSPEND_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_DEV_CONN_DIS
// Description : Set when the device connection state changes. Cleared by
// writing to SIE_STATUS.CONNECTED
-#define USB_INTF_DEV_CONN_DIS_RESET _U(0x0)
-#define USB_INTF_DEV_CONN_DIS_BITS _U(0x00002000)
-#define USB_INTF_DEV_CONN_DIS_MSB _U(13)
-#define USB_INTF_DEV_CONN_DIS_LSB _U(13)
+#define USB_INTF_DEV_CONN_DIS_RESET _u(0x0)
+#define USB_INTF_DEV_CONN_DIS_BITS _u(0x00002000)
+#define USB_INTF_DEV_CONN_DIS_MSB _u(13)
+#define USB_INTF_DEV_CONN_DIS_LSB _u(13)
#define USB_INTF_DEV_CONN_DIS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_BUS_RESET
// Description : Source: SIE_STATUS.BUS_RESET
-#define USB_INTF_BUS_RESET_RESET _U(0x0)
-#define USB_INTF_BUS_RESET_BITS _U(0x00001000)
-#define USB_INTF_BUS_RESET_MSB _U(12)
-#define USB_INTF_BUS_RESET_LSB _U(12)
+#define USB_INTF_BUS_RESET_RESET _u(0x0)
+#define USB_INTF_BUS_RESET_BITS _u(0x00001000)
+#define USB_INTF_BUS_RESET_MSB _u(12)
+#define USB_INTF_BUS_RESET_LSB _u(12)
#define USB_INTF_BUS_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_VBUS_DETECT
// Description : Source: SIE_STATUS.VBUS_DETECT
-#define USB_INTF_VBUS_DETECT_RESET _U(0x0)
-#define USB_INTF_VBUS_DETECT_BITS _U(0x00000800)
-#define USB_INTF_VBUS_DETECT_MSB _U(11)
-#define USB_INTF_VBUS_DETECT_LSB _U(11)
+#define USB_INTF_VBUS_DETECT_RESET _u(0x0)
+#define USB_INTF_VBUS_DETECT_BITS _u(0x00000800)
+#define USB_INTF_VBUS_DETECT_MSB _u(11)
+#define USB_INTF_VBUS_DETECT_LSB _u(11)
#define USB_INTF_VBUS_DETECT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_STALL
// Description : Source: SIE_STATUS.STALL_REC
-#define USB_INTF_STALL_RESET _U(0x0)
-#define USB_INTF_STALL_BITS _U(0x00000400)
-#define USB_INTF_STALL_MSB _U(10)
-#define USB_INTF_STALL_LSB _U(10)
+#define USB_INTF_STALL_RESET _u(0x0)
+#define USB_INTF_STALL_BITS _u(0x00000400)
+#define USB_INTF_STALL_MSB _u(10)
+#define USB_INTF_STALL_LSB _u(10)
#define USB_INTF_STALL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_ERROR_CRC
// Description : Source: SIE_STATUS.CRC_ERROR
-#define USB_INTF_ERROR_CRC_RESET _U(0x0)
-#define USB_INTF_ERROR_CRC_BITS _U(0x00000200)
-#define USB_INTF_ERROR_CRC_MSB _U(9)
-#define USB_INTF_ERROR_CRC_LSB _U(9)
+#define USB_INTF_ERROR_CRC_RESET _u(0x0)
+#define USB_INTF_ERROR_CRC_BITS _u(0x00000200)
+#define USB_INTF_ERROR_CRC_MSB _u(9)
+#define USB_INTF_ERROR_CRC_LSB _u(9)
#define USB_INTF_ERROR_CRC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_ERROR_BIT_STUFF
// Description : Source: SIE_STATUS.BIT_STUFF_ERROR
-#define USB_INTF_ERROR_BIT_STUFF_RESET _U(0x0)
-#define USB_INTF_ERROR_BIT_STUFF_BITS _U(0x00000100)
-#define USB_INTF_ERROR_BIT_STUFF_MSB _U(8)
-#define USB_INTF_ERROR_BIT_STUFF_LSB _U(8)
+#define USB_INTF_ERROR_BIT_STUFF_RESET _u(0x0)
+#define USB_INTF_ERROR_BIT_STUFF_BITS _u(0x00000100)
+#define USB_INTF_ERROR_BIT_STUFF_MSB _u(8)
+#define USB_INTF_ERROR_BIT_STUFF_LSB _u(8)
#define USB_INTF_ERROR_BIT_STUFF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_ERROR_RX_OVERFLOW
// Description : Source: SIE_STATUS.RX_OVERFLOW
-#define USB_INTF_ERROR_RX_OVERFLOW_RESET _U(0x0)
-#define USB_INTF_ERROR_RX_OVERFLOW_BITS _U(0x00000080)
-#define USB_INTF_ERROR_RX_OVERFLOW_MSB _U(7)
-#define USB_INTF_ERROR_RX_OVERFLOW_LSB _U(7)
+#define USB_INTF_ERROR_RX_OVERFLOW_RESET _u(0x0)
+#define USB_INTF_ERROR_RX_OVERFLOW_BITS _u(0x00000080)
+#define USB_INTF_ERROR_RX_OVERFLOW_MSB _u(7)
+#define USB_INTF_ERROR_RX_OVERFLOW_LSB _u(7)
#define USB_INTF_ERROR_RX_OVERFLOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_ERROR_RX_TIMEOUT
// Description : Source: SIE_STATUS.RX_TIMEOUT
-#define USB_INTF_ERROR_RX_TIMEOUT_RESET _U(0x0)
-#define USB_INTF_ERROR_RX_TIMEOUT_BITS _U(0x00000040)
-#define USB_INTF_ERROR_RX_TIMEOUT_MSB _U(6)
-#define USB_INTF_ERROR_RX_TIMEOUT_LSB _U(6)
+#define USB_INTF_ERROR_RX_TIMEOUT_RESET _u(0x0)
+#define USB_INTF_ERROR_RX_TIMEOUT_BITS _u(0x00000040)
+#define USB_INTF_ERROR_RX_TIMEOUT_MSB _u(6)
+#define USB_INTF_ERROR_RX_TIMEOUT_LSB _u(6)
#define USB_INTF_ERROR_RX_TIMEOUT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_ERROR_DATA_SEQ
// Description : Source: SIE_STATUS.DATA_SEQ_ERROR
-#define USB_INTF_ERROR_DATA_SEQ_RESET _U(0x0)
-#define USB_INTF_ERROR_DATA_SEQ_BITS _U(0x00000020)
-#define USB_INTF_ERROR_DATA_SEQ_MSB _U(5)
-#define USB_INTF_ERROR_DATA_SEQ_LSB _U(5)
+#define USB_INTF_ERROR_DATA_SEQ_RESET _u(0x0)
+#define USB_INTF_ERROR_DATA_SEQ_BITS _u(0x00000020)
+#define USB_INTF_ERROR_DATA_SEQ_MSB _u(5)
+#define USB_INTF_ERROR_DATA_SEQ_LSB _u(5)
#define USB_INTF_ERROR_DATA_SEQ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_BUFF_STATUS
// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
// all bits in BUFF_STATUS.
-#define USB_INTF_BUFF_STATUS_RESET _U(0x0)
-#define USB_INTF_BUFF_STATUS_BITS _U(0x00000010)
-#define USB_INTF_BUFF_STATUS_MSB _U(4)
-#define USB_INTF_BUFF_STATUS_LSB _U(4)
+#define USB_INTF_BUFF_STATUS_RESET _u(0x0)
+#define USB_INTF_BUFF_STATUS_BITS _u(0x00000010)
+#define USB_INTF_BUFF_STATUS_MSB _u(4)
+#define USB_INTF_BUFF_STATUS_LSB _u(4)
#define USB_INTF_BUFF_STATUS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_TRANS_COMPLETE
// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
// writing to this bit.
-#define USB_INTF_TRANS_COMPLETE_RESET _U(0x0)
-#define USB_INTF_TRANS_COMPLETE_BITS _U(0x00000008)
-#define USB_INTF_TRANS_COMPLETE_MSB _U(3)
-#define USB_INTF_TRANS_COMPLETE_LSB _U(3)
+#define USB_INTF_TRANS_COMPLETE_RESET _u(0x0)
+#define USB_INTF_TRANS_COMPLETE_BITS _u(0x00000008)
+#define USB_INTF_TRANS_COMPLETE_MSB _u(3)
+#define USB_INTF_TRANS_COMPLETE_LSB _u(3)
#define USB_INTF_TRANS_COMPLETE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_HOST_SOF
// Description : Host: raised every time the host sends a SOF (Start of Frame).
// Cleared by reading SOF_RD
-#define USB_INTF_HOST_SOF_RESET _U(0x0)
-#define USB_INTF_HOST_SOF_BITS _U(0x00000004)
-#define USB_INTF_HOST_SOF_MSB _U(2)
-#define USB_INTF_HOST_SOF_LSB _U(2)
+#define USB_INTF_HOST_SOF_RESET _u(0x0)
+#define USB_INTF_HOST_SOF_BITS _u(0x00000004)
+#define USB_INTF_HOST_SOF_MSB _u(2)
+#define USB_INTF_HOST_SOF_LSB _u(2)
#define USB_INTF_HOST_SOF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_HOST_RESUME
// Description : Host: raised when a device wakes up the host. Cleared by
// writing to SIE_STATUS.RESUME
-#define USB_INTF_HOST_RESUME_RESET _U(0x0)
-#define USB_INTF_HOST_RESUME_BITS _U(0x00000002)
-#define USB_INTF_HOST_RESUME_MSB _U(1)
-#define USB_INTF_HOST_RESUME_LSB _U(1)
+#define USB_INTF_HOST_RESUME_RESET _u(0x0)
+#define USB_INTF_HOST_RESUME_BITS _u(0x00000002)
+#define USB_INTF_HOST_RESUME_MSB _u(1)
+#define USB_INTF_HOST_RESUME_LSB _u(1)
#define USB_INTF_HOST_RESUME_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : USB_INTF_HOST_CONN_DIS
// Description : Host: raised when a device is connected or disconnected (i.e.
// when SIE_STATUS.SPEED changes). Cleared by writing to
// SIE_STATUS.SPEED
-#define USB_INTF_HOST_CONN_DIS_RESET _U(0x0)
-#define USB_INTF_HOST_CONN_DIS_BITS _U(0x00000001)
-#define USB_INTF_HOST_CONN_DIS_MSB _U(0)
-#define USB_INTF_HOST_CONN_DIS_LSB _U(0)
+#define USB_INTF_HOST_CONN_DIS_RESET _u(0x0)
+#define USB_INTF_HOST_CONN_DIS_BITS _u(0x00000001)
+#define USB_INTF_HOST_CONN_DIS_MSB _u(0)
+#define USB_INTF_HOST_CONN_DIS_LSB _u(0)
#define USB_INTF_HOST_CONN_DIS_ACCESS "RW"
// =============================================================================
// Register : USB_INTS
// Description : Interrupt status after masking & forcing
-#define USB_INTS_OFFSET _U(0x00000098)
-#define USB_INTS_BITS _U(0x000fffff)
-#define USB_INTS_RESET _U(0x00000000)
+#define USB_INTS_OFFSET _u(0x00000098)
+#define USB_INTS_BITS _u(0x000fffff)
+#define USB_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : USB_INTS_EP_STALL_NAK
// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
// clearing all bits in EP_STATUS_STALL_NAK.
-#define USB_INTS_EP_STALL_NAK_RESET _U(0x0)
-#define USB_INTS_EP_STALL_NAK_BITS _U(0x00080000)
-#define USB_INTS_EP_STALL_NAK_MSB _U(19)
-#define USB_INTS_EP_STALL_NAK_LSB _U(19)
+#define USB_INTS_EP_STALL_NAK_RESET _u(0x0)
+#define USB_INTS_EP_STALL_NAK_BITS _u(0x00080000)
+#define USB_INTS_EP_STALL_NAK_MSB _u(19)
+#define USB_INTS_EP_STALL_NAK_LSB _u(19)
#define USB_INTS_EP_STALL_NAK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_ABORT_DONE
// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
// bits in ABORT_DONE.
-#define USB_INTS_ABORT_DONE_RESET _U(0x0)
-#define USB_INTS_ABORT_DONE_BITS _U(0x00040000)
-#define USB_INTS_ABORT_DONE_MSB _U(18)
-#define USB_INTS_ABORT_DONE_LSB _U(18)
+#define USB_INTS_ABORT_DONE_RESET _u(0x0)
+#define USB_INTS_ABORT_DONE_BITS _u(0x00040000)
+#define USB_INTS_ABORT_DONE_MSB _u(18)
+#define USB_INTS_ABORT_DONE_LSB _u(18)
#define USB_INTS_ABORT_DONE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_DEV_SOF
// Description : Set every time the device receives a SOF (Start of Frame)
// packet. Cleared by reading SOF_RD
-#define USB_INTS_DEV_SOF_RESET _U(0x0)
-#define USB_INTS_DEV_SOF_BITS _U(0x00020000)
-#define USB_INTS_DEV_SOF_MSB _U(17)
-#define USB_INTS_DEV_SOF_LSB _U(17)
+#define USB_INTS_DEV_SOF_RESET _u(0x0)
+#define USB_INTS_DEV_SOF_BITS _u(0x00020000)
+#define USB_INTS_DEV_SOF_MSB _u(17)
+#define USB_INTS_DEV_SOF_LSB _u(17)
#define USB_INTS_DEV_SOF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_SETUP_REQ
// Description : Device. Source: SIE_STATUS.SETUP_REC
-#define USB_INTS_SETUP_REQ_RESET _U(0x0)
-#define USB_INTS_SETUP_REQ_BITS _U(0x00010000)
-#define USB_INTS_SETUP_REQ_MSB _U(16)
-#define USB_INTS_SETUP_REQ_LSB _U(16)
+#define USB_INTS_SETUP_REQ_RESET _u(0x0)
+#define USB_INTS_SETUP_REQ_BITS _u(0x00010000)
+#define USB_INTS_SETUP_REQ_MSB _u(16)
+#define USB_INTS_SETUP_REQ_LSB _u(16)
#define USB_INTS_SETUP_REQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_DEV_RESUME_FROM_HOST
// Description : Set when the device receives a resume from the host. Cleared by
// writing to SIE_STATUS.RESUME
-#define USB_INTS_DEV_RESUME_FROM_HOST_RESET _U(0x0)
-#define USB_INTS_DEV_RESUME_FROM_HOST_BITS _U(0x00008000)
-#define USB_INTS_DEV_RESUME_FROM_HOST_MSB _U(15)
-#define USB_INTS_DEV_RESUME_FROM_HOST_LSB _U(15)
+#define USB_INTS_DEV_RESUME_FROM_HOST_RESET _u(0x0)
+#define USB_INTS_DEV_RESUME_FROM_HOST_BITS _u(0x00008000)
+#define USB_INTS_DEV_RESUME_FROM_HOST_MSB _u(15)
+#define USB_INTS_DEV_RESUME_FROM_HOST_LSB _u(15)
#define USB_INTS_DEV_RESUME_FROM_HOST_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_DEV_SUSPEND
// Description : Set when the device suspend state changes. Cleared by writing
// to SIE_STATUS.SUSPENDED
-#define USB_INTS_DEV_SUSPEND_RESET _U(0x0)
-#define USB_INTS_DEV_SUSPEND_BITS _U(0x00004000)
-#define USB_INTS_DEV_SUSPEND_MSB _U(14)
-#define USB_INTS_DEV_SUSPEND_LSB _U(14)
+#define USB_INTS_DEV_SUSPEND_RESET _u(0x0)
+#define USB_INTS_DEV_SUSPEND_BITS _u(0x00004000)
+#define USB_INTS_DEV_SUSPEND_MSB _u(14)
+#define USB_INTS_DEV_SUSPEND_LSB _u(14)
#define USB_INTS_DEV_SUSPEND_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_DEV_CONN_DIS
// Description : Set when the device connection state changes. Cleared by
// writing to SIE_STATUS.CONNECTED
-#define USB_INTS_DEV_CONN_DIS_RESET _U(0x0)
-#define USB_INTS_DEV_CONN_DIS_BITS _U(0x00002000)
-#define USB_INTS_DEV_CONN_DIS_MSB _U(13)
-#define USB_INTS_DEV_CONN_DIS_LSB _U(13)
+#define USB_INTS_DEV_CONN_DIS_RESET _u(0x0)
+#define USB_INTS_DEV_CONN_DIS_BITS _u(0x00002000)
+#define USB_INTS_DEV_CONN_DIS_MSB _u(13)
+#define USB_INTS_DEV_CONN_DIS_LSB _u(13)
#define USB_INTS_DEV_CONN_DIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_BUS_RESET
// Description : Source: SIE_STATUS.BUS_RESET
-#define USB_INTS_BUS_RESET_RESET _U(0x0)
-#define USB_INTS_BUS_RESET_BITS _U(0x00001000)
-#define USB_INTS_BUS_RESET_MSB _U(12)
-#define USB_INTS_BUS_RESET_LSB _U(12)
+#define USB_INTS_BUS_RESET_RESET _u(0x0)
+#define USB_INTS_BUS_RESET_BITS _u(0x00001000)
+#define USB_INTS_BUS_RESET_MSB _u(12)
+#define USB_INTS_BUS_RESET_LSB _u(12)
#define USB_INTS_BUS_RESET_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_VBUS_DETECT
// Description : Source: SIE_STATUS.VBUS_DETECT
-#define USB_INTS_VBUS_DETECT_RESET _U(0x0)
-#define USB_INTS_VBUS_DETECT_BITS _U(0x00000800)
-#define USB_INTS_VBUS_DETECT_MSB _U(11)
-#define USB_INTS_VBUS_DETECT_LSB _U(11)
+#define USB_INTS_VBUS_DETECT_RESET _u(0x0)
+#define USB_INTS_VBUS_DETECT_BITS _u(0x00000800)
+#define USB_INTS_VBUS_DETECT_MSB _u(11)
+#define USB_INTS_VBUS_DETECT_LSB _u(11)
#define USB_INTS_VBUS_DETECT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_STALL
// Description : Source: SIE_STATUS.STALL_REC
-#define USB_INTS_STALL_RESET _U(0x0)
-#define USB_INTS_STALL_BITS _U(0x00000400)
-#define USB_INTS_STALL_MSB _U(10)
-#define USB_INTS_STALL_LSB _U(10)
+#define USB_INTS_STALL_RESET _u(0x0)
+#define USB_INTS_STALL_BITS _u(0x00000400)
+#define USB_INTS_STALL_MSB _u(10)
+#define USB_INTS_STALL_LSB _u(10)
#define USB_INTS_STALL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_ERROR_CRC
// Description : Source: SIE_STATUS.CRC_ERROR
-#define USB_INTS_ERROR_CRC_RESET _U(0x0)
-#define USB_INTS_ERROR_CRC_BITS _U(0x00000200)
-#define USB_INTS_ERROR_CRC_MSB _U(9)
-#define USB_INTS_ERROR_CRC_LSB _U(9)
+#define USB_INTS_ERROR_CRC_RESET _u(0x0)
+#define USB_INTS_ERROR_CRC_BITS _u(0x00000200)
+#define USB_INTS_ERROR_CRC_MSB _u(9)
+#define USB_INTS_ERROR_CRC_LSB _u(9)
#define USB_INTS_ERROR_CRC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_ERROR_BIT_STUFF
// Description : Source: SIE_STATUS.BIT_STUFF_ERROR
-#define USB_INTS_ERROR_BIT_STUFF_RESET _U(0x0)
-#define USB_INTS_ERROR_BIT_STUFF_BITS _U(0x00000100)
-#define USB_INTS_ERROR_BIT_STUFF_MSB _U(8)
-#define USB_INTS_ERROR_BIT_STUFF_LSB _U(8)
+#define USB_INTS_ERROR_BIT_STUFF_RESET _u(0x0)
+#define USB_INTS_ERROR_BIT_STUFF_BITS _u(0x00000100)
+#define USB_INTS_ERROR_BIT_STUFF_MSB _u(8)
+#define USB_INTS_ERROR_BIT_STUFF_LSB _u(8)
#define USB_INTS_ERROR_BIT_STUFF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_ERROR_RX_OVERFLOW
// Description : Source: SIE_STATUS.RX_OVERFLOW
-#define USB_INTS_ERROR_RX_OVERFLOW_RESET _U(0x0)
-#define USB_INTS_ERROR_RX_OVERFLOW_BITS _U(0x00000080)
-#define USB_INTS_ERROR_RX_OVERFLOW_MSB _U(7)
-#define USB_INTS_ERROR_RX_OVERFLOW_LSB _U(7)
+#define USB_INTS_ERROR_RX_OVERFLOW_RESET _u(0x0)
+#define USB_INTS_ERROR_RX_OVERFLOW_BITS _u(0x00000080)
+#define USB_INTS_ERROR_RX_OVERFLOW_MSB _u(7)
+#define USB_INTS_ERROR_RX_OVERFLOW_LSB _u(7)
#define USB_INTS_ERROR_RX_OVERFLOW_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_ERROR_RX_TIMEOUT
// Description : Source: SIE_STATUS.RX_TIMEOUT
-#define USB_INTS_ERROR_RX_TIMEOUT_RESET _U(0x0)
-#define USB_INTS_ERROR_RX_TIMEOUT_BITS _U(0x00000040)
-#define USB_INTS_ERROR_RX_TIMEOUT_MSB _U(6)
-#define USB_INTS_ERROR_RX_TIMEOUT_LSB _U(6)
+#define USB_INTS_ERROR_RX_TIMEOUT_RESET _u(0x0)
+#define USB_INTS_ERROR_RX_TIMEOUT_BITS _u(0x00000040)
+#define USB_INTS_ERROR_RX_TIMEOUT_MSB _u(6)
+#define USB_INTS_ERROR_RX_TIMEOUT_LSB _u(6)
#define USB_INTS_ERROR_RX_TIMEOUT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_ERROR_DATA_SEQ
// Description : Source: SIE_STATUS.DATA_SEQ_ERROR
-#define USB_INTS_ERROR_DATA_SEQ_RESET _U(0x0)
-#define USB_INTS_ERROR_DATA_SEQ_BITS _U(0x00000020)
-#define USB_INTS_ERROR_DATA_SEQ_MSB _U(5)
-#define USB_INTS_ERROR_DATA_SEQ_LSB _U(5)
+#define USB_INTS_ERROR_DATA_SEQ_RESET _u(0x0)
+#define USB_INTS_ERROR_DATA_SEQ_BITS _u(0x00000020)
+#define USB_INTS_ERROR_DATA_SEQ_MSB _u(5)
+#define USB_INTS_ERROR_DATA_SEQ_LSB _u(5)
#define USB_INTS_ERROR_DATA_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_BUFF_STATUS
// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
// all bits in BUFF_STATUS.
-#define USB_INTS_BUFF_STATUS_RESET _U(0x0)
-#define USB_INTS_BUFF_STATUS_BITS _U(0x00000010)
-#define USB_INTS_BUFF_STATUS_MSB _U(4)
-#define USB_INTS_BUFF_STATUS_LSB _U(4)
+#define USB_INTS_BUFF_STATUS_RESET _u(0x0)
+#define USB_INTS_BUFF_STATUS_BITS _u(0x00000010)
+#define USB_INTS_BUFF_STATUS_MSB _u(4)
+#define USB_INTS_BUFF_STATUS_LSB _u(4)
#define USB_INTS_BUFF_STATUS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_TRANS_COMPLETE
// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
// writing to this bit.
-#define USB_INTS_TRANS_COMPLETE_RESET _U(0x0)
-#define USB_INTS_TRANS_COMPLETE_BITS _U(0x00000008)
-#define USB_INTS_TRANS_COMPLETE_MSB _U(3)
-#define USB_INTS_TRANS_COMPLETE_LSB _U(3)
+#define USB_INTS_TRANS_COMPLETE_RESET _u(0x0)
+#define USB_INTS_TRANS_COMPLETE_BITS _u(0x00000008)
+#define USB_INTS_TRANS_COMPLETE_MSB _u(3)
+#define USB_INTS_TRANS_COMPLETE_LSB _u(3)
#define USB_INTS_TRANS_COMPLETE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_HOST_SOF
// Description : Host: raised every time the host sends a SOF (Start of Frame).
// Cleared by reading SOF_RD
-#define USB_INTS_HOST_SOF_RESET _U(0x0)
-#define USB_INTS_HOST_SOF_BITS _U(0x00000004)
-#define USB_INTS_HOST_SOF_MSB _U(2)
-#define USB_INTS_HOST_SOF_LSB _U(2)
+#define USB_INTS_HOST_SOF_RESET _u(0x0)
+#define USB_INTS_HOST_SOF_BITS _u(0x00000004)
+#define USB_INTS_HOST_SOF_MSB _u(2)
+#define USB_INTS_HOST_SOF_LSB _u(2)
#define USB_INTS_HOST_SOF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_HOST_RESUME
// Description : Host: raised when a device wakes up the host. Cleared by
// writing to SIE_STATUS.RESUME
-#define USB_INTS_HOST_RESUME_RESET _U(0x0)
-#define USB_INTS_HOST_RESUME_BITS _U(0x00000002)
-#define USB_INTS_HOST_RESUME_MSB _U(1)
-#define USB_INTS_HOST_RESUME_LSB _U(1)
+#define USB_INTS_HOST_RESUME_RESET _u(0x0)
+#define USB_INTS_HOST_RESUME_BITS _u(0x00000002)
+#define USB_INTS_HOST_RESUME_MSB _u(1)
+#define USB_INTS_HOST_RESUME_LSB _u(1)
#define USB_INTS_HOST_RESUME_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : USB_INTS_HOST_CONN_DIS
// Description : Host: raised when a device is connected or disconnected (i.e.
// when SIE_STATUS.SPEED changes). Cleared by writing to
// SIE_STATUS.SPEED
-#define USB_INTS_HOST_CONN_DIS_RESET _U(0x0)
-#define USB_INTS_HOST_CONN_DIS_BITS _U(0x00000001)
-#define USB_INTS_HOST_CONN_DIS_MSB _U(0)
-#define USB_INTS_HOST_CONN_DIS_LSB _U(0)
+#define USB_INTS_HOST_CONN_DIS_RESET _u(0x0)
+#define USB_INTS_HOST_CONN_DIS_BITS _u(0x00000001)
+#define USB_INTS_HOST_CONN_DIS_MSB _u(0)
+#define USB_INTS_HOST_CONN_DIS_LSB _u(0)
#define USB_INTS_HOST_CONN_DIS_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_USB_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h b/src/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h
index dca4431..356ff56 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h
@@ -15,17 +15,17 @@
// =============================================================================
// Register : VREG_AND_CHIP_RESET_VREG
// Description : Voltage regulator control and status
-#define VREG_AND_CHIP_RESET_VREG_OFFSET _U(0x00000000)
-#define VREG_AND_CHIP_RESET_VREG_BITS _U(0x000010f3)
-#define VREG_AND_CHIP_RESET_VREG_RESET _U(0x000000b1)
+#define VREG_AND_CHIP_RESET_VREG_OFFSET _u(0x00000000)
+#define VREG_AND_CHIP_RESET_VREG_BITS _u(0x000010f3)
+#define VREG_AND_CHIP_RESET_VREG_RESET _u(0x000000b1)
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_VREG_ROK
// Description : regulation status
// 0=not in regulation, 1=in regulation
-#define VREG_AND_CHIP_RESET_VREG_ROK_RESET _U(0x0)
-#define VREG_AND_CHIP_RESET_VREG_ROK_BITS _U(0x00001000)
-#define VREG_AND_CHIP_RESET_VREG_ROK_MSB _U(12)
-#define VREG_AND_CHIP_RESET_VREG_ROK_LSB _U(12)
+#define VREG_AND_CHIP_RESET_VREG_ROK_RESET _u(0x0)
+#define VREG_AND_CHIP_RESET_VREG_ROK_BITS _u(0x00001000)
+#define VREG_AND_CHIP_RESET_VREG_ROK_MSB _u(12)
+#define VREG_AND_CHIP_RESET_VREG_ROK_LSB _u(12)
#define VREG_AND_CHIP_RESET_VREG_ROK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_VREG_VSEL
@@ -41,35 +41,35 @@
// 1101 - 1.20V
// 1110 - 1.25V
// 1111 - 1.30V
-#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET _U(0xb)
-#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS _U(0x000000f0)
-#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB _U(7)
-#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB _U(4)
+#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET _u(0xb)
+#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS _u(0x000000f0)
+#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB _u(7)
+#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB _u(4)
#define VREG_AND_CHIP_RESET_VREG_VSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_VREG_HIZ
// Description : high impedance mode select
// 0=not in high impedance mode, 1=in high impedance mode
-#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET _U(0x0)
-#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS _U(0x00000002)
-#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB _U(1)
-#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB _U(1)
+#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET _u(0x0)
+#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS _u(0x00000002)
+#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB _u(1)
+#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB _u(1)
#define VREG_AND_CHIP_RESET_VREG_HIZ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_VREG_EN
// Description : enable
// 0=not enabled, 1=enabled
-#define VREG_AND_CHIP_RESET_VREG_EN_RESET _U(0x1)
-#define VREG_AND_CHIP_RESET_VREG_EN_BITS _U(0x00000001)
-#define VREG_AND_CHIP_RESET_VREG_EN_MSB _U(0)
-#define VREG_AND_CHIP_RESET_VREG_EN_LSB _U(0)
+#define VREG_AND_CHIP_RESET_VREG_EN_RESET _u(0x1)
+#define VREG_AND_CHIP_RESET_VREG_EN_BITS _u(0x00000001)
+#define VREG_AND_CHIP_RESET_VREG_EN_MSB _u(0)
+#define VREG_AND_CHIP_RESET_VREG_EN_LSB _u(0)
#define VREG_AND_CHIP_RESET_VREG_EN_ACCESS "RW"
// =============================================================================
// Register : VREG_AND_CHIP_RESET_BOD
// Description : brown-out detection control
-#define VREG_AND_CHIP_RESET_BOD_OFFSET _U(0x00000004)
-#define VREG_AND_CHIP_RESET_BOD_BITS _U(0x000000f1)
-#define VREG_AND_CHIP_RESET_BOD_RESET _U(0x00000091)
+#define VREG_AND_CHIP_RESET_BOD_OFFSET _u(0x00000004)
+#define VREG_AND_CHIP_RESET_BOD_BITS _u(0x000000f1)
+#define VREG_AND_CHIP_RESET_BOD_RESET _u(0x00000091)
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_BOD_VSEL
// Description : threshold select
@@ -89,26 +89,26 @@
// 1101 - 1.032V
// 1110 - 1.075V
// 1111 - 1.118V
-#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET _U(0x9)
-#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS _U(0x000000f0)
-#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB _U(7)
-#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB _U(4)
+#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET _u(0x9)
+#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS _u(0x000000f0)
+#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB _u(7)
+#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB _u(4)
#define VREG_AND_CHIP_RESET_BOD_VSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_BOD_EN
// Description : enable
// 0=not enabled, 1=enabled
-#define VREG_AND_CHIP_RESET_BOD_EN_RESET _U(0x1)
-#define VREG_AND_CHIP_RESET_BOD_EN_BITS _U(0x00000001)
-#define VREG_AND_CHIP_RESET_BOD_EN_MSB _U(0)
-#define VREG_AND_CHIP_RESET_BOD_EN_LSB _U(0)
+#define VREG_AND_CHIP_RESET_BOD_EN_RESET _u(0x1)
+#define VREG_AND_CHIP_RESET_BOD_EN_BITS _u(0x00000001)
+#define VREG_AND_CHIP_RESET_BOD_EN_MSB _u(0)
+#define VREG_AND_CHIP_RESET_BOD_EN_LSB _u(0)
#define VREG_AND_CHIP_RESET_BOD_EN_ACCESS "RW"
// =============================================================================
// Register : VREG_AND_CHIP_RESET_CHIP_RESET
// Description : Chip reset control and status
-#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET _U(0x00000008)
-#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS _U(0x01110100)
-#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET _U(0x00000000)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET _u(0x00000008)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS _u(0x01110100)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG
// Description : This is set by psm_restart from the debugger.
@@ -117,35 +117,35 @@
// boot lock-up.
// In the safe mode the debugger can repair the boot code, clear
// this flag then reboot the processor.
-#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET _U(0x0)
-#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS _U(0x01000000)
-#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB _U(24)
-#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB _U(24)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET _u(0x0)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS _u(0x01000000)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB _u(24)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB _u(24)
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART
// Description : Last reset was from the debug port
-#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET _U(0x0)
-#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS _U(0x00100000)
-#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB _U(20)
-#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB _U(20)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET _u(0x0)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS _u(0x00100000)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB _u(20)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB _u(20)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN
// Description : Last reset was from the RUN pin
-#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET _U(0x0)
-#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS _U(0x00010000)
-#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB _U(16)
-#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB _U(16)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET _u(0x0)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS _u(0x00010000)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB _u(16)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB _u(16)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR
// Description : Last reset was from the power-on reset or brown-out detection
// blocks
-#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET _U(0x0)
-#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS _U(0x00000100)
-#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB _U(8)
-#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB _U(8)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET _u(0x0)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS _u(0x00000100)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB _u(8)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB _u(8)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/watchdog.h b/src/rp2040/hardware_regs/include/hardware/regs/watchdog.h
index a127384..6a9853d 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/watchdog.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/watchdog.h
@@ -17,210 +17,210 @@
// The rst_wdsel register determines which subsystems are reset
// when the watchdog is triggered.
// The watchdog can be triggered in software.
-#define WATCHDOG_CTRL_OFFSET _U(0x00000000)
-#define WATCHDOG_CTRL_BITS _U(0xc7ffffff)
-#define WATCHDOG_CTRL_RESET _U(0x07000000)
+#define WATCHDOG_CTRL_OFFSET _u(0x00000000)
+#define WATCHDOG_CTRL_BITS _u(0xc7ffffff)
+#define WATCHDOG_CTRL_RESET _u(0x07000000)
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_TRIGGER
// Description : Trigger a watchdog reset
-#define WATCHDOG_CTRL_TRIGGER_RESET _U(0x0)
-#define WATCHDOG_CTRL_TRIGGER_BITS _U(0x80000000)
-#define WATCHDOG_CTRL_TRIGGER_MSB _U(31)
-#define WATCHDOG_CTRL_TRIGGER_LSB _U(31)
+#define WATCHDOG_CTRL_TRIGGER_RESET _u(0x0)
+#define WATCHDOG_CTRL_TRIGGER_BITS _u(0x80000000)
+#define WATCHDOG_CTRL_TRIGGER_MSB _u(31)
+#define WATCHDOG_CTRL_TRIGGER_LSB _u(31)
#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_ENABLE
// Description : When not enabled the watchdog timer is paused
-#define WATCHDOG_CTRL_ENABLE_RESET _U(0x0)
-#define WATCHDOG_CTRL_ENABLE_BITS _U(0x40000000)
-#define WATCHDOG_CTRL_ENABLE_MSB _U(30)
-#define WATCHDOG_CTRL_ENABLE_LSB _U(30)
+#define WATCHDOG_CTRL_ENABLE_RESET _u(0x0)
+#define WATCHDOG_CTRL_ENABLE_BITS _u(0x40000000)
+#define WATCHDOG_CTRL_ENABLE_MSB _u(30)
+#define WATCHDOG_CTRL_ENABLE_LSB _u(30)
#define WATCHDOG_CTRL_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_DBG1
// Description : Pause the watchdog timer when processor 1 is in debug mode
-#define WATCHDOG_CTRL_PAUSE_DBG1_RESET _U(0x1)
-#define WATCHDOG_CTRL_PAUSE_DBG1_BITS _U(0x04000000)
-#define WATCHDOG_CTRL_PAUSE_DBG1_MSB _U(26)
-#define WATCHDOG_CTRL_PAUSE_DBG1_LSB _U(26)
+#define WATCHDOG_CTRL_PAUSE_DBG1_RESET _u(0x1)
+#define WATCHDOG_CTRL_PAUSE_DBG1_BITS _u(0x04000000)
+#define WATCHDOG_CTRL_PAUSE_DBG1_MSB _u(26)
+#define WATCHDOG_CTRL_PAUSE_DBG1_LSB _u(26)
#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_DBG0
// Description : Pause the watchdog timer when processor 0 is in debug mode
-#define WATCHDOG_CTRL_PAUSE_DBG0_RESET _U(0x1)
-#define WATCHDOG_CTRL_PAUSE_DBG0_BITS _U(0x02000000)
-#define WATCHDOG_CTRL_PAUSE_DBG0_MSB _U(25)
-#define WATCHDOG_CTRL_PAUSE_DBG0_LSB _U(25)
+#define WATCHDOG_CTRL_PAUSE_DBG0_RESET _u(0x1)
+#define WATCHDOG_CTRL_PAUSE_DBG0_BITS _u(0x02000000)
+#define WATCHDOG_CTRL_PAUSE_DBG0_MSB _u(25)
+#define WATCHDOG_CTRL_PAUSE_DBG0_LSB _u(25)
#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_JTAG
// Description : Pause the watchdog timer when JTAG is accessing the bus fabric
-#define WATCHDOG_CTRL_PAUSE_JTAG_RESET _U(0x1)
-#define WATCHDOG_CTRL_PAUSE_JTAG_BITS _U(0x01000000)
-#define WATCHDOG_CTRL_PAUSE_JTAG_MSB _U(24)
-#define WATCHDOG_CTRL_PAUSE_JTAG_LSB _U(24)
+#define WATCHDOG_CTRL_PAUSE_JTAG_RESET _u(0x1)
+#define WATCHDOG_CTRL_PAUSE_JTAG_BITS _u(0x01000000)
+#define WATCHDOG_CTRL_PAUSE_JTAG_MSB _u(24)
+#define WATCHDOG_CTRL_PAUSE_JTAG_LSB _u(24)
#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_TIME
// Description : Indicates the number of ticks / 2 (see errata RP2040-E1) before
// a watchdog reset will be triggered
-#define WATCHDOG_CTRL_TIME_RESET _U(0x000000)
-#define WATCHDOG_CTRL_TIME_BITS _U(0x00ffffff)
-#define WATCHDOG_CTRL_TIME_MSB _U(23)
-#define WATCHDOG_CTRL_TIME_LSB _U(0)
+#define WATCHDOG_CTRL_TIME_RESET _u(0x000000)
+#define WATCHDOG_CTRL_TIME_BITS _u(0x00ffffff)
+#define WATCHDOG_CTRL_TIME_MSB _u(23)
+#define WATCHDOG_CTRL_TIME_LSB _u(0)
#define WATCHDOG_CTRL_TIME_ACCESS "RO"
// =============================================================================
// Register : WATCHDOG_LOAD
// Description : Load the watchdog timer. The maximum setting is 0xffffff which
// corresponds to 0xffffff / 2 ticks before triggering a watchdog
// reset (see errata RP2040-E1).
-#define WATCHDOG_LOAD_OFFSET _U(0x00000004)
-#define WATCHDOG_LOAD_BITS _U(0x00ffffff)
-#define WATCHDOG_LOAD_RESET _U(0x00000000)
-#define WATCHDOG_LOAD_MSB _U(23)
-#define WATCHDOG_LOAD_LSB _U(0)
+#define WATCHDOG_LOAD_OFFSET _u(0x00000004)
+#define WATCHDOG_LOAD_BITS _u(0x00ffffff)
+#define WATCHDOG_LOAD_RESET _u(0x00000000)
+#define WATCHDOG_LOAD_MSB _u(23)
+#define WATCHDOG_LOAD_LSB _u(0)
#define WATCHDOG_LOAD_ACCESS "WF"
// =============================================================================
// Register : WATCHDOG_REASON
// Description : Logs the reason for the last reset. Both bits are zero for the
// case of a hardware reset.
-#define WATCHDOG_REASON_OFFSET _U(0x00000008)
-#define WATCHDOG_REASON_BITS _U(0x00000003)
-#define WATCHDOG_REASON_RESET _U(0x00000000)
+#define WATCHDOG_REASON_OFFSET _u(0x00000008)
+#define WATCHDOG_REASON_BITS _u(0x00000003)
+#define WATCHDOG_REASON_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : WATCHDOG_REASON_FORCE
// Description : None
-#define WATCHDOG_REASON_FORCE_RESET _U(0x0)
-#define WATCHDOG_REASON_FORCE_BITS _U(0x00000002)
-#define WATCHDOG_REASON_FORCE_MSB _U(1)
-#define WATCHDOG_REASON_FORCE_LSB _U(1)
+#define WATCHDOG_REASON_FORCE_RESET _u(0x0)
+#define WATCHDOG_REASON_FORCE_BITS _u(0x00000002)
+#define WATCHDOG_REASON_FORCE_MSB _u(1)
+#define WATCHDOG_REASON_FORCE_LSB _u(1)
#define WATCHDOG_REASON_FORCE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_REASON_TIMER
// Description : None
-#define WATCHDOG_REASON_TIMER_RESET _U(0x0)
-#define WATCHDOG_REASON_TIMER_BITS _U(0x00000001)
-#define WATCHDOG_REASON_TIMER_MSB _U(0)
-#define WATCHDOG_REASON_TIMER_LSB _U(0)
+#define WATCHDOG_REASON_TIMER_RESET _u(0x0)
+#define WATCHDOG_REASON_TIMER_BITS _u(0x00000001)
+#define WATCHDOG_REASON_TIMER_MSB _u(0)
+#define WATCHDOG_REASON_TIMER_LSB _u(0)
#define WATCHDOG_REASON_TIMER_ACCESS "RO"
// =============================================================================
// Register : WATCHDOG_SCRATCH0
// Description : Scratch register. Information persists through soft reset of
// the chip.
-#define WATCHDOG_SCRATCH0_OFFSET _U(0x0000000c)
-#define WATCHDOG_SCRATCH0_BITS _U(0xffffffff)
-#define WATCHDOG_SCRATCH0_RESET _U(0x00000000)
-#define WATCHDOG_SCRATCH0_MSB _U(31)
-#define WATCHDOG_SCRATCH0_LSB _U(0)
+#define WATCHDOG_SCRATCH0_OFFSET _u(0x0000000c)
+#define WATCHDOG_SCRATCH0_BITS _u(0xffffffff)
+#define WATCHDOG_SCRATCH0_RESET _u(0x00000000)
+#define WATCHDOG_SCRATCH0_MSB _u(31)
+#define WATCHDOG_SCRATCH0_LSB _u(0)
#define WATCHDOG_SCRATCH0_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH1
// Description : Scratch register. Information persists through soft reset of
// the chip.
-#define WATCHDOG_SCRATCH1_OFFSET _U(0x00000010)
-#define WATCHDOG_SCRATCH1_BITS _U(0xffffffff)
-#define WATCHDOG_SCRATCH1_RESET _U(0x00000000)
-#define WATCHDOG_SCRATCH1_MSB _U(31)
-#define WATCHDOG_SCRATCH1_LSB _U(0)
+#define WATCHDOG_SCRATCH1_OFFSET _u(0x00000010)
+#define WATCHDOG_SCRATCH1_BITS _u(0xffffffff)
+#define WATCHDOG_SCRATCH1_RESET _u(0x00000000)
+#define WATCHDOG_SCRATCH1_MSB _u(31)
+#define WATCHDOG_SCRATCH1_LSB _u(0)
#define WATCHDOG_SCRATCH1_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH2
// Description : Scratch register. Information persists through soft reset of
// the chip.
-#define WATCHDOG_SCRATCH2_OFFSET _U(0x00000014)
-#define WATCHDOG_SCRATCH2_BITS _U(0xffffffff)
-#define WATCHDOG_SCRATCH2_RESET _U(0x00000000)
-#define WATCHDOG_SCRATCH2_MSB _U(31)
-#define WATCHDOG_SCRATCH2_LSB _U(0)
+#define WATCHDOG_SCRATCH2_OFFSET _u(0x00000014)
+#define WATCHDOG_SCRATCH2_BITS _u(0xffffffff)
+#define WATCHDOG_SCRATCH2_RESET _u(0x00000000)
+#define WATCHDOG_SCRATCH2_MSB _u(31)
+#define WATCHDOG_SCRATCH2_LSB _u(0)
#define WATCHDOG_SCRATCH2_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH3
// Description : Scratch register. Information persists through soft reset of
// the chip.
-#define WATCHDOG_SCRATCH3_OFFSET _U(0x00000018)
-#define WATCHDOG_SCRATCH3_BITS _U(0xffffffff)
-#define WATCHDOG_SCRATCH3_RESET _U(0x00000000)
-#define WATCHDOG_SCRATCH3_MSB _U(31)
-#define WATCHDOG_SCRATCH3_LSB _U(0)
+#define WATCHDOG_SCRATCH3_OFFSET _u(0x00000018)
+#define WATCHDOG_SCRATCH3_BITS _u(0xffffffff)
+#define WATCHDOG_SCRATCH3_RESET _u(0x00000000)
+#define WATCHDOG_SCRATCH3_MSB _u(31)
+#define WATCHDOG_SCRATCH3_LSB _u(0)
#define WATCHDOG_SCRATCH3_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH4
// Description : Scratch register. Information persists through soft reset of
// the chip.
-#define WATCHDOG_SCRATCH4_OFFSET _U(0x0000001c)
-#define WATCHDOG_SCRATCH4_BITS _U(0xffffffff)
-#define WATCHDOG_SCRATCH4_RESET _U(0x00000000)
-#define WATCHDOG_SCRATCH4_MSB _U(31)
-#define WATCHDOG_SCRATCH4_LSB _U(0)
+#define WATCHDOG_SCRATCH4_OFFSET _u(0x0000001c)
+#define WATCHDOG_SCRATCH4_BITS _u(0xffffffff)
+#define WATCHDOG_SCRATCH4_RESET _u(0x00000000)
+#define WATCHDOG_SCRATCH4_MSB _u(31)
+#define WATCHDOG_SCRATCH4_LSB _u(0)
#define WATCHDOG_SCRATCH4_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH5
// Description : Scratch register. Information persists through soft reset of
// the chip.
-#define WATCHDOG_SCRATCH5_OFFSET _U(0x00000020)
-#define WATCHDOG_SCRATCH5_BITS _U(0xffffffff)
-#define WATCHDOG_SCRATCH5_RESET _U(0x00000000)
-#define WATCHDOG_SCRATCH5_MSB _U(31)
-#define WATCHDOG_SCRATCH5_LSB _U(0)
+#define WATCHDOG_SCRATCH5_OFFSET _u(0x00000020)
+#define WATCHDOG_SCRATCH5_BITS _u(0xffffffff)
+#define WATCHDOG_SCRATCH5_RESET _u(0x00000000)
+#define WATCHDOG_SCRATCH5_MSB _u(31)
+#define WATCHDOG_SCRATCH5_LSB _u(0)
#define WATCHDOG_SCRATCH5_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH6
// Description : Scratch register. Information persists through soft reset of
// the chip.
-#define WATCHDOG_SCRATCH6_OFFSET _U(0x00000024)
-#define WATCHDOG_SCRATCH6_BITS _U(0xffffffff)
-#define WATCHDOG_SCRATCH6_RESET _U(0x00000000)
-#define WATCHDOG_SCRATCH6_MSB _U(31)
-#define WATCHDOG_SCRATCH6_LSB _U(0)
+#define WATCHDOG_SCRATCH6_OFFSET _u(0x00000024)
+#define WATCHDOG_SCRATCH6_BITS _u(0xffffffff)
+#define WATCHDOG_SCRATCH6_RESET _u(0x00000000)
+#define WATCHDOG_SCRATCH6_MSB _u(31)
+#define WATCHDOG_SCRATCH6_LSB _u(0)
#define WATCHDOG_SCRATCH6_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH7
// Description : Scratch register. Information persists through soft reset of
// the chip.
-#define WATCHDOG_SCRATCH7_OFFSET _U(0x00000028)
-#define WATCHDOG_SCRATCH7_BITS _U(0xffffffff)
-#define WATCHDOG_SCRATCH7_RESET _U(0x00000000)
-#define WATCHDOG_SCRATCH7_MSB _U(31)
-#define WATCHDOG_SCRATCH7_LSB _U(0)
+#define WATCHDOG_SCRATCH7_OFFSET _u(0x00000028)
+#define WATCHDOG_SCRATCH7_BITS _u(0xffffffff)
+#define WATCHDOG_SCRATCH7_RESET _u(0x00000000)
+#define WATCHDOG_SCRATCH7_MSB _u(31)
+#define WATCHDOG_SCRATCH7_LSB _u(0)
#define WATCHDOG_SCRATCH7_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_TICK
// Description : Controls the tick generator
-#define WATCHDOG_TICK_OFFSET _U(0x0000002c)
-#define WATCHDOG_TICK_BITS _U(0x000fffff)
-#define WATCHDOG_TICK_RESET _U(0x00000200)
+#define WATCHDOG_TICK_OFFSET _u(0x0000002c)
+#define WATCHDOG_TICK_BITS _u(0x000fffff)
+#define WATCHDOG_TICK_RESET _u(0x00000200)
// -----------------------------------------------------------------------------
// Field : WATCHDOG_TICK_COUNT
// Description : Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define WATCHDOG_TICK_COUNT_RESET "-"
-#define WATCHDOG_TICK_COUNT_BITS _U(0x000ff800)
-#define WATCHDOG_TICK_COUNT_MSB _U(19)
-#define WATCHDOG_TICK_COUNT_LSB _U(11)
+#define WATCHDOG_TICK_COUNT_BITS _u(0x000ff800)
+#define WATCHDOG_TICK_COUNT_MSB _u(19)
+#define WATCHDOG_TICK_COUNT_LSB _u(11)
#define WATCHDOG_TICK_COUNT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_TICK_RUNNING
// Description : Is the tick generator running?
#define WATCHDOG_TICK_RUNNING_RESET "-"
-#define WATCHDOG_TICK_RUNNING_BITS _U(0x00000400)
-#define WATCHDOG_TICK_RUNNING_MSB _U(10)
-#define WATCHDOG_TICK_RUNNING_LSB _U(10)
+#define WATCHDOG_TICK_RUNNING_BITS _u(0x00000400)
+#define WATCHDOG_TICK_RUNNING_MSB _u(10)
+#define WATCHDOG_TICK_RUNNING_LSB _u(10)
#define WATCHDOG_TICK_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_TICK_ENABLE
// Description : start / stop tick generation
-#define WATCHDOG_TICK_ENABLE_RESET _U(0x1)
-#define WATCHDOG_TICK_ENABLE_BITS _U(0x00000200)
-#define WATCHDOG_TICK_ENABLE_MSB _U(9)
-#define WATCHDOG_TICK_ENABLE_LSB _U(9)
+#define WATCHDOG_TICK_ENABLE_RESET _u(0x1)
+#define WATCHDOG_TICK_ENABLE_BITS _u(0x00000200)
+#define WATCHDOG_TICK_ENABLE_MSB _u(9)
+#define WATCHDOG_TICK_ENABLE_LSB _u(9)
#define WATCHDOG_TICK_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_TICK_CYCLES
// Description : Total number of clk_tick cycles before the next tick.
-#define WATCHDOG_TICK_CYCLES_RESET _U(0x000)
-#define WATCHDOG_TICK_CYCLES_BITS _U(0x000001ff)
-#define WATCHDOG_TICK_CYCLES_MSB _U(8)
-#define WATCHDOG_TICK_CYCLES_LSB _U(0)
+#define WATCHDOG_TICK_CYCLES_RESET _u(0x000)
+#define WATCHDOG_TICK_CYCLES_BITS _u(0x000001ff)
+#define WATCHDOG_TICK_CYCLES_MSB _u(8)
+#define WATCHDOG_TICK_CYCLES_LSB _u(0)
#define WATCHDOG_TICK_CYCLES_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_WATCHDOG_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/xip.h b/src/rp2040/hardware_regs/include/hardware/regs/xip.h
index 9bc37d1..3964f67 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/xip.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/xip.h
@@ -14,9 +14,9 @@
// =============================================================================
// Register : XIP_CTRL
// Description : Cache control
-#define XIP_CTRL_OFFSET _U(0x00000000)
-#define XIP_CTRL_BITS _U(0x0000000b)
-#define XIP_CTRL_RESET _U(0x00000003)
+#define XIP_CTRL_OFFSET _u(0x00000000)
+#define XIP_CTRL_BITS _u(0x0000000b)
+#define XIP_CTRL_RESET _u(0x00000003)
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_POWER_DOWN
// Description : When 1, the cache memories are powered down. They retain state,
@@ -26,10 +26,10 @@
// be enabled when powered down.
// Cache-as-SRAM accesses will produce a bus error response when
// the cache is powered down.
-#define XIP_CTRL_POWER_DOWN_RESET _U(0x0)
-#define XIP_CTRL_POWER_DOWN_BITS _U(0x00000008)
-#define XIP_CTRL_POWER_DOWN_MSB _U(3)
-#define XIP_CTRL_POWER_DOWN_LSB _U(3)
+#define XIP_CTRL_POWER_DOWN_RESET _u(0x0)
+#define XIP_CTRL_POWER_DOWN_BITS _u(0x00000008)
+#define XIP_CTRL_POWER_DOWN_MSB _u(3)
+#define XIP_CTRL_POWER_DOWN_LSB _u(3)
#define XIP_CTRL_POWER_DOWN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_ERR_BADWRITE
@@ -40,10 +40,10 @@
// In either case, writes to the 0x0 alias will deallocate on tag
// match,
// as usual.
-#define XIP_CTRL_ERR_BADWRITE_RESET _U(0x1)
-#define XIP_CTRL_ERR_BADWRITE_BITS _U(0x00000002)
-#define XIP_CTRL_ERR_BADWRITE_MSB _U(1)
-#define XIP_CTRL_ERR_BADWRITE_LSB _U(1)
+#define XIP_CTRL_ERR_BADWRITE_RESET _u(0x1)
+#define XIP_CTRL_ERR_BADWRITE_BITS _u(0x00000002)
+#define XIP_CTRL_ERR_BADWRITE_MSB _u(1)
+#define XIP_CTRL_ERR_BADWRITE_LSB _u(1)
#define XIP_CTRL_ERR_BADWRITE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_EN
@@ -57,10 +57,10 @@
// If the cache is enabled, cache-as-SRAM accesses have no effect
// on the
// cache data RAM, and will produce a bus error response.
-#define XIP_CTRL_EN_RESET _U(0x1)
-#define XIP_CTRL_EN_BITS _U(0x00000001)
-#define XIP_CTRL_EN_MSB _U(0)
-#define XIP_CTRL_EN_LSB _U(0)
+#define XIP_CTRL_EN_RESET _u(0x1)
+#define XIP_CTRL_EN_BITS _u(0x00000001)
+#define XIP_CTRL_EN_MSB _u(0)
+#define XIP_CTRL_EN_LSB _u(0)
#define XIP_CTRL_EN_ACCESS "RW"
// =============================================================================
// Register : XIP_FLUSH
@@ -70,45 +70,45 @@
// contents is not affected by flush or reset.)
// Reading will hold the bus (stall the processor) until the flush
// completes. Alternatively STAT can be polled until completion.
-#define XIP_FLUSH_OFFSET _U(0x00000004)
-#define XIP_FLUSH_BITS _U(0x00000001)
-#define XIP_FLUSH_RESET _U(0x00000000)
-#define XIP_FLUSH_MSB _U(0)
-#define XIP_FLUSH_LSB _U(0)
+#define XIP_FLUSH_OFFSET _u(0x00000004)
+#define XIP_FLUSH_BITS _u(0x00000001)
+#define XIP_FLUSH_RESET _u(0x00000000)
+#define XIP_FLUSH_MSB _u(0)
+#define XIP_FLUSH_LSB _u(0)
#define XIP_FLUSH_ACCESS "SC"
// =============================================================================
// Register : XIP_STAT
// Description : Cache Status
-#define XIP_STAT_OFFSET _U(0x00000008)
-#define XIP_STAT_BITS _U(0x00000007)
-#define XIP_STAT_RESET _U(0x00000002)
+#define XIP_STAT_OFFSET _u(0x00000008)
+#define XIP_STAT_BITS _u(0x00000007)
+#define XIP_STAT_RESET _u(0x00000002)
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FIFO_FULL
// Description : When 1, indicates the XIP streaming FIFO is completely full.
// The streaming FIFO is 2 entries deep, so the full and empty
// flag allow its level to be ascertained.
-#define XIP_STAT_FIFO_FULL_RESET _U(0x0)
-#define XIP_STAT_FIFO_FULL_BITS _U(0x00000004)
-#define XIP_STAT_FIFO_FULL_MSB _U(2)
-#define XIP_STAT_FIFO_FULL_LSB _U(2)
+#define XIP_STAT_FIFO_FULL_RESET _u(0x0)
+#define XIP_STAT_FIFO_FULL_BITS _u(0x00000004)
+#define XIP_STAT_FIFO_FULL_MSB _u(2)
+#define XIP_STAT_FIFO_FULL_LSB _u(2)
#define XIP_STAT_FIFO_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FIFO_EMPTY
// Description : When 1, indicates the XIP streaming FIFO is completely empty.
-#define XIP_STAT_FIFO_EMPTY_RESET _U(0x1)
-#define XIP_STAT_FIFO_EMPTY_BITS _U(0x00000002)
-#define XIP_STAT_FIFO_EMPTY_MSB _U(1)
-#define XIP_STAT_FIFO_EMPTY_LSB _U(1)
+#define XIP_STAT_FIFO_EMPTY_RESET _u(0x1)
+#define XIP_STAT_FIFO_EMPTY_BITS _u(0x00000002)
+#define XIP_STAT_FIFO_EMPTY_MSB _u(1)
+#define XIP_STAT_FIFO_EMPTY_LSB _u(1)
#define XIP_STAT_FIFO_EMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FLUSH_READY
// Description : Reads as 0 while a cache flush is in progress, and 1 otherwise.
// The cache is flushed whenever the XIP block is reset, and also
// when requested via the FLUSH register.
-#define XIP_STAT_FLUSH_READY_RESET _U(0x0)
-#define XIP_STAT_FLUSH_READY_BITS _U(0x00000001)
-#define XIP_STAT_FLUSH_READY_MSB _U(0)
-#define XIP_STAT_FLUSH_READY_LSB _U(0)
+#define XIP_STAT_FLUSH_READY_RESET _u(0x0)
+#define XIP_STAT_FLUSH_READY_BITS _u(0x00000001)
+#define XIP_STAT_FLUSH_READY_MSB _u(0)
+#define XIP_STAT_FLUSH_READY_LSB _u(0)
#define XIP_STAT_FLUSH_READY_ACCESS "RO"
// =============================================================================
// Register : XIP_CTR_HIT
@@ -117,11 +117,11 @@
// hit,
// i.e. when an XIP access is serviced directly from cached data.
// Write any value to clear.
-#define XIP_CTR_HIT_OFFSET _U(0x0000000c)
-#define XIP_CTR_HIT_BITS _U(0xffffffff)
-#define XIP_CTR_HIT_RESET _U(0x00000000)
-#define XIP_CTR_HIT_MSB _U(31)
-#define XIP_CTR_HIT_LSB _U(0)
+#define XIP_CTR_HIT_OFFSET _u(0x0000000c)
+#define XIP_CTR_HIT_BITS _u(0xffffffff)
+#define XIP_CTR_HIT_RESET _u(0x00000000)
+#define XIP_CTR_HIT_MSB _u(31)
+#define XIP_CTR_HIT_LSB _u(0)
#define XIP_CTR_HIT_ACCESS "WC"
// =============================================================================
// Register : XIP_CTR_ACC
@@ -131,11 +131,11 @@
// whether the cache is hit or not. This includes noncacheable
// accesses.
// Write any value to clear.
-#define XIP_CTR_ACC_OFFSET _U(0x00000010)
-#define XIP_CTR_ACC_BITS _U(0xffffffff)
-#define XIP_CTR_ACC_RESET _U(0x00000000)
-#define XIP_CTR_ACC_MSB _U(31)
-#define XIP_CTR_ACC_LSB _U(0)
+#define XIP_CTR_ACC_OFFSET _u(0x00000010)
+#define XIP_CTR_ACC_BITS _u(0xffffffff)
+#define XIP_CTR_ACC_RESET _u(0x00000000)
+#define XIP_CTR_ACC_MSB _u(31)
+#define XIP_CTR_ACC_LSB _u(0)
#define XIP_CTR_ACC_ACCESS "WC"
// =============================================================================
// Register : XIP_STREAM_ADDR
@@ -145,11 +145,11 @@
// Increments automatically after each flash access.
// Write the initial access address here before starting a
// streaming read.
-#define XIP_STREAM_ADDR_OFFSET _U(0x00000014)
-#define XIP_STREAM_ADDR_BITS _U(0xfffffffc)
-#define XIP_STREAM_ADDR_RESET _U(0x00000000)
-#define XIP_STREAM_ADDR_MSB _U(31)
-#define XIP_STREAM_ADDR_LSB _U(2)
+#define XIP_STREAM_ADDR_OFFSET _u(0x00000014)
+#define XIP_STREAM_ADDR_BITS _u(0xfffffffc)
+#define XIP_STREAM_ADDR_RESET _u(0x00000000)
+#define XIP_STREAM_ADDR_MSB _u(31)
+#define XIP_STREAM_ADDR_LSB _u(2)
#define XIP_STREAM_ADDR_ACCESS "RW"
// =============================================================================
// Register : XIP_STREAM_CTR
@@ -163,11 +163,11 @@
// in-flight
// read, so that a new stream can immediately be started (after
// draining the FIFO and reinitialising STREAM_ADDR)
-#define XIP_STREAM_CTR_OFFSET _U(0x00000018)
-#define XIP_STREAM_CTR_BITS _U(0x003fffff)
-#define XIP_STREAM_CTR_RESET _U(0x00000000)
-#define XIP_STREAM_CTR_MSB _U(21)
-#define XIP_STREAM_CTR_LSB _U(0)
+#define XIP_STREAM_CTR_OFFSET _u(0x00000018)
+#define XIP_STREAM_CTR_BITS _u(0x003fffff)
+#define XIP_STREAM_CTR_RESET _u(0x00000000)
+#define XIP_STREAM_CTR_MSB _u(21)
+#define XIP_STREAM_CTR_LSB _u(0)
#define XIP_STREAM_CTR_ACCESS "RW"
// =============================================================================
// Register : XIP_STREAM_FIFO
@@ -177,11 +177,11 @@
// This FIFO can also be accessed via the XIP_AUX slave, to avoid
// exposing
// the DMA to bus stalls caused by other XIP traffic.
-#define XIP_STREAM_FIFO_OFFSET _U(0x0000001c)
-#define XIP_STREAM_FIFO_BITS _U(0xffffffff)
-#define XIP_STREAM_FIFO_RESET _U(0x00000000)
-#define XIP_STREAM_FIFO_MSB _U(31)
-#define XIP_STREAM_FIFO_LSB _U(0)
+#define XIP_STREAM_FIFO_OFFSET _u(0x0000001c)
+#define XIP_STREAM_FIFO_BITS _u(0xffffffff)
+#define XIP_STREAM_FIFO_RESET _u(0x00000000)
+#define XIP_STREAM_FIFO_MSB _u(31)
+#define XIP_STREAM_FIFO_LSB _u(0)
#define XIP_STREAM_FIFO_ACCESS "RF"
// =============================================================================
#endif // HARDWARE_REGS_XIP_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/xosc.h b/src/rp2040/hardware_regs/include/hardware/regs/xosc.h
index 3ebf5a8..4af78b9 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/xosc.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/xosc.h
@@ -14,9 +14,9 @@
// =============================================================================
// Register : XOSC_CTRL
// Description : Crystal Oscillator Control
-#define XOSC_CTRL_OFFSET _U(0x00000000)
-#define XOSC_CTRL_BITS _U(0x00ffffff)
-#define XOSC_CTRL_RESET _U(0x00000000)
+#define XOSC_CTRL_OFFSET _u(0x00000000)
+#define XOSC_CTRL_BITS _u(0x00ffffff)
+#define XOSC_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_CTRL_ENABLE
// Description : On power-up this field is initialised to DISABLE and the chip
@@ -31,12 +31,12 @@
// 0xd1e -> DISABLE
// 0xfab -> ENABLE
#define XOSC_CTRL_ENABLE_RESET "-"
-#define XOSC_CTRL_ENABLE_BITS _U(0x00fff000)
-#define XOSC_CTRL_ENABLE_MSB _U(23)
-#define XOSC_CTRL_ENABLE_LSB _U(12)
+#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000)
+#define XOSC_CTRL_ENABLE_MSB _u(23)
+#define XOSC_CTRL_ENABLE_LSB _u(12)
#define XOSC_CTRL_ENABLE_ACCESS "RW"
-#define XOSC_CTRL_ENABLE_VALUE_DISABLE _U(0xd1e)
-#define XOSC_CTRL_ENABLE_VALUE_ENABLE _U(0xfab)
+#define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
+#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
// -----------------------------------------------------------------------------
// Field : XOSC_CTRL_FREQ_RANGE
// Description : Frequency range. This resets to 0xAA0 and cannot be changed.
@@ -45,45 +45,45 @@
// 0xaa2 -> RESERVED_2
// 0xaa3 -> RESERVED_3
#define XOSC_CTRL_FREQ_RANGE_RESET "-"
-#define XOSC_CTRL_FREQ_RANGE_BITS _U(0x00000fff)
-#define XOSC_CTRL_FREQ_RANGE_MSB _U(11)
-#define XOSC_CTRL_FREQ_RANGE_LSB _U(0)
+#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff)
+#define XOSC_CTRL_FREQ_RANGE_MSB _u(11)
+#define XOSC_CTRL_FREQ_RANGE_LSB _u(0)
#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW"
-#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _U(0xaa0)
-#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 _U(0xaa1)
-#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 _U(0xaa2)
-#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 _U(0xaa3)
+#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0)
+#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 _u(0xaa1)
+#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 _u(0xaa2)
+#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 _u(0xaa3)
// =============================================================================
// Register : XOSC_STATUS
// Description : Crystal Oscillator Status
-#define XOSC_STATUS_OFFSET _U(0x00000004)
-#define XOSC_STATUS_BITS _U(0x81001003)
-#define XOSC_STATUS_RESET _U(0x00000000)
+#define XOSC_STATUS_OFFSET _u(0x00000004)
+#define XOSC_STATUS_BITS _u(0x81001003)
+#define XOSC_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_STABLE
// Description : Oscillator is running and stable
-#define XOSC_STATUS_STABLE_RESET _U(0x0)
-#define XOSC_STATUS_STABLE_BITS _U(0x80000000)
-#define XOSC_STATUS_STABLE_MSB _U(31)
-#define XOSC_STATUS_STABLE_LSB _U(31)
+#define XOSC_STATUS_STABLE_RESET _u(0x0)
+#define XOSC_STATUS_STABLE_BITS _u(0x80000000)
+#define XOSC_STATUS_STABLE_MSB _u(31)
+#define XOSC_STATUS_STABLE_LSB _u(31)
#define XOSC_STATUS_STABLE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_BADWRITE
// Description : An invalid value has been written to CTRL_ENABLE or
// CTRL_FREQ_RANGE or DORMANT
-#define XOSC_STATUS_BADWRITE_RESET _U(0x0)
-#define XOSC_STATUS_BADWRITE_BITS _U(0x01000000)
-#define XOSC_STATUS_BADWRITE_MSB _U(24)
-#define XOSC_STATUS_BADWRITE_LSB _U(24)
+#define XOSC_STATUS_BADWRITE_RESET _u(0x0)
+#define XOSC_STATUS_BADWRITE_BITS _u(0x01000000)
+#define XOSC_STATUS_BADWRITE_MSB _u(24)
+#define XOSC_STATUS_BADWRITE_LSB _u(24)
#define XOSC_STATUS_BADWRITE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_ENABLED
// Description : Oscillator is enabled but not necessarily running and stable,
// resets to 0
#define XOSC_STATUS_ENABLED_RESET "-"
-#define XOSC_STATUS_ENABLED_BITS _U(0x00001000)
-#define XOSC_STATUS_ENABLED_MSB _U(12)
-#define XOSC_STATUS_ENABLED_LSB _U(12)
+#define XOSC_STATUS_ENABLED_BITS _u(0x00001000)
+#define XOSC_STATUS_ENABLED_MSB _u(12)
+#define XOSC_STATUS_ENABLED_LSB _u(12)
#define XOSC_STATUS_ENABLED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_FREQ_RANGE
@@ -93,14 +93,14 @@
// 0x2 -> RESERVED_2
// 0x3 -> RESERVED_3
#define XOSC_STATUS_FREQ_RANGE_RESET "-"
-#define XOSC_STATUS_FREQ_RANGE_BITS _U(0x00000003)
-#define XOSC_STATUS_FREQ_RANGE_MSB _U(1)
-#define XOSC_STATUS_FREQ_RANGE_LSB _U(0)
+#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003)
+#define XOSC_STATUS_FREQ_RANGE_MSB _u(1)
+#define XOSC_STATUS_FREQ_RANGE_LSB _u(0)
#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO"
-#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _U(0x0)
-#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 _U(0x1)
-#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 _U(0x2)
-#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 _U(0x3)
+#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0)
+#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 _u(0x1)
+#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 _u(0x2)
+#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 _u(0x3)
// =============================================================================
// Register : XOSC_DORMANT
// Description : Crystal Oscillator pause control
@@ -111,36 +111,36 @@
// WARNING: setup the irq before selecting dormant mode
// 0x636f6d61 -> DORMANT
// 0x77616b65 -> WAKE
-#define XOSC_DORMANT_OFFSET _U(0x00000008)
-#define XOSC_DORMANT_BITS _U(0xffffffff)
+#define XOSC_DORMANT_OFFSET _u(0x00000008)
+#define XOSC_DORMANT_BITS _u(0xffffffff)
#define XOSC_DORMANT_RESET "-"
-#define XOSC_DORMANT_MSB _U(31)
-#define XOSC_DORMANT_LSB _U(0)
+#define XOSC_DORMANT_MSB _u(31)
+#define XOSC_DORMANT_LSB _u(0)
#define XOSC_DORMANT_ACCESS "RW"
-#define XOSC_DORMANT_VALUE_DORMANT _U(0x636f6d61)
-#define XOSC_DORMANT_VALUE_WAKE _U(0x77616b65)
+#define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
+#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65)
// =============================================================================
// Register : XOSC_STARTUP
// Description : Controls the startup delay
-#define XOSC_STARTUP_OFFSET _U(0x0000000c)
-#define XOSC_STARTUP_BITS _U(0x00103fff)
-#define XOSC_STARTUP_RESET _U(0x00000000)
+#define XOSC_STARTUP_OFFSET _u(0x0000000c)
+#define XOSC_STARTUP_BITS _u(0x00103fff)
+#define XOSC_STARTUP_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_X4
// Description : Multiplies the startup_delay by 4. This is of little value to
// the user given that the delay can be programmed directly
#define XOSC_STARTUP_X4_RESET "-"
-#define XOSC_STARTUP_X4_BITS _U(0x00100000)
-#define XOSC_STARTUP_X4_MSB _U(20)
-#define XOSC_STARTUP_X4_LSB _U(20)
+#define XOSC_STARTUP_X4_BITS _u(0x00100000)
+#define XOSC_STARTUP_X4_MSB _u(20)
+#define XOSC_STARTUP_X4_LSB _u(20)
#define XOSC_STARTUP_X4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_DELAY
// Description : in multiples of 256*xtal_period
#define XOSC_STARTUP_DELAY_RESET "-"
-#define XOSC_STARTUP_DELAY_BITS _U(0x00003fff)
-#define XOSC_STARTUP_DELAY_MSB _U(13)
-#define XOSC_STARTUP_DELAY_LSB _U(0)
+#define XOSC_STARTUP_DELAY_BITS _u(0x00003fff)
+#define XOSC_STARTUP_DELAY_MSB _u(13)
+#define XOSC_STARTUP_DELAY_LSB _u(0)
#define XOSC_STARTUP_DELAY_ACCESS "RW"
// =============================================================================
// Register : XOSC_COUNT
@@ -149,11 +149,11 @@
// To start the counter write a non-zero value.
// Can be used for short software pauses when setting up time
// sensitive hardware.
-#define XOSC_COUNT_OFFSET _U(0x0000001c)
-#define XOSC_COUNT_BITS _U(0x000000ff)
-#define XOSC_COUNT_RESET _U(0x00000000)
-#define XOSC_COUNT_MSB _U(7)
-#define XOSC_COUNT_LSB _U(0)
+#define XOSC_COUNT_OFFSET _u(0x0000001c)
+#define XOSC_COUNT_BITS _u(0x000000ff)
+#define XOSC_COUNT_RESET _u(0x00000000)
+#define XOSC_COUNT_MSB _u(7)
+#define XOSC_COUNT_LSB _u(0)
#define XOSC_COUNT_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_XOSC_DEFINED
diff --git a/src/rp2_common/hardware_irq/include/hardware/irq.h b/src/rp2_common/hardware_irq/include/hardware/irq.h
index d999632..8711026 100644
--- a/src/rp2_common/hardware_irq/include/hardware/irq.h
+++ b/src/rp2_common/hardware_irq/include/hardware/irq.h
@@ -21,6 +21,7 @@
#ifndef __ASSEMBLER__
#include "pico.h"
+#include "hardware/address_mapped.h"
#include "hardware/regs/intctrl.h"
#include "hardware/regs/m0plus.h"
diff --git a/src/rp2_common/pico_standard_link/CMakeLists.txt b/src/rp2_common/pico_standard_link/CMakeLists.txt
index 8dc8ab8..489594c 100644
--- a/src/rp2_common/pico_standard_link/CMakeLists.txt
+++ b/src/rp2_common/pico_standard_link/CMakeLists.txt
@@ -83,7 +83,7 @@
#target_link_options(pico_standard_link INTERFACE "LINKER:--build-id=none")
# this line occasionally useful for debugging ... todo maybe make a PICO_ var
-# target_compile_options(pico_standard_link INTERFACE --save-temps) #debugging only
+ # target_compile_options(pico_standard_link INTERFACE --save-temps) #debugging only
# PICO_CMAKE_CONFIG: PICO_NO_GC_SECTIONS, Disable -ffunction-sections -fdata-sections, and --gc-sections, type=bool, default=0, advanced=true, group=pico_standard_link
if (NOT PICO_NO_GC_SECTIONS)
