| // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT |
| |
| /** |
| * Copyright (c) 2024 Raspberry Pi Ltd. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| // ============================================================================= |
| // Register block : DMA |
| // Version : 1 |
| // Bus type : apb |
| // Description : DMA with separate read and write masters |
| // ============================================================================= |
| #ifndef _HARDWARE_REGS_DMA_H |
| #define _HARDWARE_REGS_DMA_H |
| // ============================================================================= |
| // Register : DMA_CH0_READ_ADDR |
| // Description : DMA Channel 0 Read Address pointer |
| // This register updates automatically each time a read completes. |
| // The current value is the next address to be read by this |
| // channel. |
| #define DMA_CH0_READ_ADDR_OFFSET _u(0x00000000) |
| #define DMA_CH0_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH0_READ_ADDR_RESET _u(0x00000000) |
| #define DMA_CH0_READ_ADDR_MSB _u(31) |
| #define DMA_CH0_READ_ADDR_LSB _u(0) |
| #define DMA_CH0_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH0_WRITE_ADDR |
| // Description : DMA Channel 0 Write Address pointer |
| // This register updates automatically each time a write |
| // completes. The current value is the next address to be written |
| // by this channel. |
| #define DMA_CH0_WRITE_ADDR_OFFSET _u(0x00000004) |
| #define DMA_CH0_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH0_WRITE_ADDR_RESET _u(0x00000000) |
| #define DMA_CH0_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH0_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH0_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH0_TRANS_COUNT |
| // Description : DMA Channel 0 Transfer Count |
| #define DMA_CH0_TRANS_COUNT_OFFSET _u(0x00000008) |
| #define DMA_CH0_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH0_TRANS_COUNT_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_TRANS_COUNT_MODE |
| // Description : When MODE is 0x0, the transfer count decrements with each |
| // transfer until 0, and then the channel triggers the next |
| // channel indicated by CTRL_CHAIN_TO. |
| // |
| // When MODE is 0x1, the transfer count decrements with each |
| // transfer until 0, and then the channel re-triggers itself, in |
| // addition to the trigger indicated by CTRL_CHAIN_TO. This is |
| // useful for e.g. an endless ring-buffer DMA with periodic |
| // interrupts. |
| // |
| // When MODE is 0xf, the transfer count does not decrement. The |
| // DMA channel performs an endless sequence of transfers, never |
| // triggering other channels or raising interrupts, until an ABORT |
| // is raised. |
| // |
| // All other values are reserved. |
| // 0x0 -> NORMAL |
| // 0x1 -> TRIGGER_SELF |
| // 0xf -> ENDLESS |
| #define DMA_CH0_TRANS_COUNT_MODE_RESET _u(0x0) |
| #define DMA_CH0_TRANS_COUNT_MODE_BITS _u(0xf0000000) |
| #define DMA_CH0_TRANS_COUNT_MODE_MSB _u(31) |
| #define DMA_CH0_TRANS_COUNT_MODE_LSB _u(28) |
| #define DMA_CH0_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH0_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) |
| #define DMA_CH0_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) |
| #define DMA_CH0_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_TRANS_COUNT_COUNT |
| // Description : 28-bit transfer count (256 million transfers maximum). |
| // |
| // Program the number of bus transfers a channel will perform |
| // before halting. Note that, if transfers are larger than one |
| // byte in size, this is not equal to the number of bytes |
| // transferred (see CTRL_DATA_SIZE). |
| // |
| // When the channel is active, reading this register shows the |
| // number of transfers remaining, updating automatically each time |
| // a write transfer completes. |
| // |
| // Writing this register sets the RELOAD value for the transfer |
| // counter. Each time this channel is triggered, the RELOAD value |
| // is copied into the live transfer counter. The channel can be |
| // started multiple times, and will perform the same number of |
| // transfers each time, as programmed by most recent write. |
| // |
| // The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT |
| // is used as a trigger, the written value is used immediately as |
| // the length of the new transfer sequence, as well as being |
| // written to RELOAD. |
| #define DMA_CH0_TRANS_COUNT_COUNT_RESET _u(0x0000000) |
| #define DMA_CH0_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) |
| #define DMA_CH0_TRANS_COUNT_COUNT_MSB _u(27) |
| #define DMA_CH0_TRANS_COUNT_COUNT_LSB _u(0) |
| #define DMA_CH0_TRANS_COUNT_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH0_CTRL_TRIG |
| // Description : DMA Channel 0 Control and Status |
| #define DMA_CH0_CTRL_TRIG_OFFSET _u(0x0000000c) |
| #define DMA_CH0_CTRL_TRIG_BITS _u(0xe7ffffff) |
| #define DMA_CH0_CTRL_TRIG_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_AHB_ERROR |
| // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel |
| // halts when it encounters any bus error, and always raises its |
| // channel IRQ flag. |
| #define DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) |
| #define DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB _u(31) |
| #define DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB _u(31) |
| #define DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_READ_ERROR |
| // Description : If 1, the channel received a read bus error. Write one to |
| // clear. |
| // READ_ADDR shows the approximate address where the bus error was |
| // encountered (will not be earlier, or more than 3 transfers |
| // later) |
| #define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) |
| #define DMA_CH0_CTRL_TRIG_READ_ERROR_MSB _u(30) |
| #define DMA_CH0_CTRL_TRIG_READ_ERROR_LSB _u(30) |
| #define DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_WRITE_ERROR |
| // Description : If 1, the channel received a write bus error. Write one to |
| // clear. |
| // WRITE_ADDR shows the approximate address where the bus error |
| // was encountered (will not be earlier, or more than 5 transfers |
| // later) |
| #define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) |
| #define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB _u(29) |
| #define DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB _u(29) |
| #define DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_BUSY |
| // Description : This flag goes high when the channel starts a new transfer |
| // sequence, and low when the last transfer of that sequence |
| // completes. Clearing EN while BUSY is high pauses the channel, |
| // and BUSY will stay high while paused. |
| // |
| // To terminate a sequence early (and clear the BUSY flag), see |
| // CHAN_ABORT. |
| #define DMA_CH0_CTRL_TRIG_BUSY_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_BUSY_BITS _u(0x04000000) |
| #define DMA_CH0_CTRL_TRIG_BUSY_MSB _u(26) |
| #define DMA_CH0_CTRL_TRIG_BUSY_LSB _u(26) |
| #define DMA_CH0_CTRL_TRIG_BUSY_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_SNIFF_EN |
| // Description : If 1, this channel's data transfers are visible to the sniff |
| // hardware, and each transfer will advance the state of the |
| // checksum. This only applies if the sniff hardware is enabled, |
| // and has this channel selected. |
| // |
| // This allows checksum to be enabled or disabled on a per- |
| // control- block basis. |
| #define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) |
| #define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB _u(25) |
| #define DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB _u(25) |
| #define DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_BSWAP |
| // Description : Apply byte-swap transformation to DMA data. |
| // For byte data, this has no effect. For halfword data, the two |
| // bytes of each halfword are swapped. For word data, the four |
| // bytes of each word are swapped to reverse order. |
| #define DMA_CH0_CTRL_TRIG_BSWAP_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_BSWAP_BITS _u(0x01000000) |
| #define DMA_CH0_CTRL_TRIG_BSWAP_MSB _u(24) |
| #define DMA_CH0_CTRL_TRIG_BSWAP_LSB _u(24) |
| #define DMA_CH0_CTRL_TRIG_BSWAP_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_IRQ_QUIET |
| // Description : In QUIET mode, the channel does not generate IRQs at the end of |
| // every transfer block. Instead, an IRQ is raised when NULL is |
| // written to a trigger register, indicating the end of a control |
| // block chain. |
| // |
| // This reduces the number of interrupts to be serviced by the CPU |
| // when transferring a DMA chain of many small control blocks. |
| #define DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) |
| #define DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB _u(23) |
| #define DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB _u(23) |
| #define DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_TREQ_SEL |
| // Description : Select a Transfer Request signal. |
| // The channel uses the transfer request signal to pace its data |
| // transfer rate. Sources for TREQ signals are internal (TIMERS) |
| // or external (DREQ, a Data Request from the system). |
| // 0x0 to 0x3a -> select DREQ n as TREQ |
| // 0x3b -> Select Timer 0 as TREQ |
| // 0x3c -> Select Timer 1 as TREQ |
| // 0x3d -> Select Timer 2 as TREQ (Optional) |
| // 0x3e -> Select Timer 3 as TREQ (Optional) |
| // 0x3f -> Permanent request, for unpaced transfers. |
| #define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) |
| #define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) |
| #define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(22) |
| #define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB _u(17) |
| #define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) |
| #define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) |
| #define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) |
| #define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) |
| #define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_CHAIN_TO |
| // Description : When this channel completes, it will trigger the channel |
| // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this |
| // channel)_. |
| // |
| // Note this field resets to 0, so channels 1 and above will chain |
| // to channel 0 by default. Set this field to avoid this |
| // behaviour. |
| #define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) |
| #define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB _u(16) |
| #define DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB _u(13) |
| #define DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_RING_SEL |
| // Description : Select whether RING_SIZE applies to read or write addresses. |
| // If 0, read addresses are wrapped on a (1 << RING_SIZE) |
| // boundary. If 1, write addresses are wrapped. |
| #define DMA_CH0_CTRL_TRIG_RING_SEL_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) |
| #define DMA_CH0_CTRL_TRIG_RING_SEL_MSB _u(12) |
| #define DMA_CH0_CTRL_TRIG_RING_SEL_LSB _u(12) |
| #define DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_RING_SIZE |
| // Description : Size of address wrap region. If 0, don't wrap. For values n > |
| // 0, only the lower n bits of the address will change. This wraps |
| // the address on a (1 << n) byte boundary, facilitating access to |
| // naturally-aligned ring buffers. |
| // |
| // Ring sizes between 2 and 32768 bytes are possible. This can |
| // apply to either read or write addresses, based on value of |
| // RING_SEL. |
| // 0x0 -> RING_NONE |
| #define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) |
| #define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB _u(11) |
| #define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB _u(8) |
| #define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_INCR_WRITE_REV |
| // Description : If 1, and INCR_WRITE is 1, the write address is decremented |
| // rather than incremented with each transfer. |
| // |
| // If 1, and INCR_WRITE is 0, this otherwise-unused combination |
| // causes the write address to be incremented by twice the |
| // transfer size, i.e. skipping over alternate addresses. |
| #define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) |
| #define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) |
| #define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) |
| #define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_INCR_WRITE |
| // Description : If 1, the write address increments with each transfer. If 0, |
| // each write is directed to the same, initial address. |
| // |
| // Generally this should be disabled for memory-to-peripheral |
| // transfers. |
| #define DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) |
| #define DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB _u(6) |
| #define DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB _u(6) |
| #define DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_INCR_READ_REV |
| // Description : If 1, and INCR_READ is 1, the read address is decremented |
| // rather than incremented with each transfer. |
| // |
| // If 1, and INCR_READ is 0, this otherwise-unused combination |
| // causes the read address to be incremented by twice the transfer |
| // size, i.e. skipping over alternate addresses. |
| #define DMA_CH0_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) |
| #define DMA_CH0_CTRL_TRIG_INCR_READ_REV_MSB _u(5) |
| #define DMA_CH0_CTRL_TRIG_INCR_READ_REV_LSB _u(5) |
| #define DMA_CH0_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_INCR_READ |
| // Description : If 1, the read address increments with each transfer. If 0, |
| // each read is directed to the same, initial address. |
| // |
| // Generally this should be disabled for peripheral-to-memory |
| // transfers. |
| #define DMA_CH0_CTRL_TRIG_INCR_READ_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) |
| #define DMA_CH0_CTRL_TRIG_INCR_READ_MSB _u(4) |
| #define DMA_CH0_CTRL_TRIG_INCR_READ_LSB _u(4) |
| #define DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_DATA_SIZE |
| // Description : Set the size of each bus transfer (byte/halfword/word). |
| // READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) |
| // with each transfer. |
| // 0x0 -> SIZE_BYTE |
| // 0x1 -> SIZE_HALFWORD |
| // 0x2 -> SIZE_WORD |
| #define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) |
| #define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB _u(3) |
| #define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB _u(2) |
| #define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) |
| #define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_HIGH_PRIORITY |
| // Description : HIGH_PRIORITY gives a channel preferential treatment in issue |
| // scheduling: in each scheduling round, all high priority |
| // channels are considered first, and then only a single low |
| // priority channel, before returning to the high priority |
| // channels. |
| // |
| // This only affects the order in which the DMA schedules |
| // channels. The DMA's bus priority is not changed. If the DMA is |
| // not saturated then a low priority channel will see no loss of |
| // throughput. |
| #define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) |
| #define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) |
| #define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) |
| #define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH0_CTRL_TRIG_EN |
| // Description : DMA Channel Enable. |
| // When 1, the channel will respond to triggering events, which |
| // will cause it to become BUSY and start transferring data. When |
| // 0, the channel will ignore triggers, stop issuing transfers, |
| // and pause the current transfer sequence (i.e. BUSY will remain |
| // high if already high) |
| #define DMA_CH0_CTRL_TRIG_EN_RESET _u(0x0) |
| #define DMA_CH0_CTRL_TRIG_EN_BITS _u(0x00000001) |
| #define DMA_CH0_CTRL_TRIG_EN_MSB _u(0) |
| #define DMA_CH0_CTRL_TRIG_EN_LSB _u(0) |
| #define DMA_CH0_CTRL_TRIG_EN_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH0_AL1_CTRL |
| // Description : Alias for channel 0 CTRL register |
| #define DMA_CH0_AL1_CTRL_OFFSET _u(0x00000010) |
| #define DMA_CH0_AL1_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH0_AL1_CTRL_RESET "-" |
| #define DMA_CH0_AL1_CTRL_MSB _u(31) |
| #define DMA_CH0_AL1_CTRL_LSB _u(0) |
| #define DMA_CH0_AL1_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH0_AL1_READ_ADDR |
| // Description : Alias for channel 0 READ_ADDR register |
| #define DMA_CH0_AL1_READ_ADDR_OFFSET _u(0x00000014) |
| #define DMA_CH0_AL1_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH0_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH0_AL1_READ_ADDR_MSB _u(31) |
| #define DMA_CH0_AL1_READ_ADDR_LSB _u(0) |
| #define DMA_CH0_AL1_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH0_AL1_WRITE_ADDR |
| // Description : Alias for channel 0 WRITE_ADDR register |
| #define DMA_CH0_AL1_WRITE_ADDR_OFFSET _u(0x00000018) |
| #define DMA_CH0_AL1_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH0_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH0_AL1_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH0_AL1_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH0_AL1_TRANS_COUNT_TRIG |
| // Description : Alias for channel 0 TRANS_COUNT register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000001c) |
| #define DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB _u(31) |
| #define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB _u(0) |
| #define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH0_AL2_CTRL |
| // Description : Alias for channel 0 CTRL register |
| #define DMA_CH0_AL2_CTRL_OFFSET _u(0x00000020) |
| #define DMA_CH0_AL2_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH0_AL2_CTRL_RESET "-" |
| #define DMA_CH0_AL2_CTRL_MSB _u(31) |
| #define DMA_CH0_AL2_CTRL_LSB _u(0) |
| #define DMA_CH0_AL2_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH0_AL2_TRANS_COUNT |
| // Description : Alias for channel 0 TRANS_COUNT register |
| #define DMA_CH0_AL2_TRANS_COUNT_OFFSET _u(0x00000024) |
| #define DMA_CH0_AL2_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH0_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH0_AL2_TRANS_COUNT_MSB _u(31) |
| #define DMA_CH0_AL2_TRANS_COUNT_LSB _u(0) |
| #define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH0_AL2_READ_ADDR |
| // Description : Alias for channel 0 READ_ADDR register |
| #define DMA_CH0_AL2_READ_ADDR_OFFSET _u(0x00000028) |
| #define DMA_CH0_AL2_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH0_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH0_AL2_READ_ADDR_MSB _u(31) |
| #define DMA_CH0_AL2_READ_ADDR_LSB _u(0) |
| #define DMA_CH0_AL2_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH0_AL2_WRITE_ADDR_TRIG |
| // Description : Alias for channel 0 WRITE_ADDR register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000002c) |
| #define DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB _u(31) |
| #define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB _u(0) |
| #define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH0_AL3_CTRL |
| // Description : Alias for channel 0 CTRL register |
| #define DMA_CH0_AL3_CTRL_OFFSET _u(0x00000030) |
| #define DMA_CH0_AL3_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH0_AL3_CTRL_RESET "-" |
| #define DMA_CH0_AL3_CTRL_MSB _u(31) |
| #define DMA_CH0_AL3_CTRL_LSB _u(0) |
| #define DMA_CH0_AL3_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH0_AL3_WRITE_ADDR |
| // Description : Alias for channel 0 WRITE_ADDR register |
| #define DMA_CH0_AL3_WRITE_ADDR_OFFSET _u(0x00000034) |
| #define DMA_CH0_AL3_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH0_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH0_AL3_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH0_AL3_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH0_AL3_TRANS_COUNT |
| // Description : Alias for channel 0 TRANS_COUNT register |
| #define DMA_CH0_AL3_TRANS_COUNT_OFFSET _u(0x00000038) |
| #define DMA_CH0_AL3_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH0_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH0_AL3_TRANS_COUNT_MSB _u(31) |
| #define DMA_CH0_AL3_TRANS_COUNT_LSB _u(0) |
| #define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH0_AL3_READ_ADDR_TRIG |
| // Description : Alias for channel 0 READ_ADDR register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000003c) |
| #define DMA_CH0_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH0_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH0_AL3_READ_ADDR_TRIG_MSB _u(31) |
| #define DMA_CH0_AL3_READ_ADDR_TRIG_LSB _u(0) |
| #define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH1_READ_ADDR |
| // Description : DMA Channel 1 Read Address pointer |
| // This register updates automatically each time a read completes. |
| // The current value is the next address to be read by this |
| // channel. |
| #define DMA_CH1_READ_ADDR_OFFSET _u(0x00000040) |
| #define DMA_CH1_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH1_READ_ADDR_RESET _u(0x00000000) |
| #define DMA_CH1_READ_ADDR_MSB _u(31) |
| #define DMA_CH1_READ_ADDR_LSB _u(0) |
| #define DMA_CH1_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH1_WRITE_ADDR |
| // Description : DMA Channel 1 Write Address pointer |
| // This register updates automatically each time a write |
| // completes. The current value is the next address to be written |
| // by this channel. |
| #define DMA_CH1_WRITE_ADDR_OFFSET _u(0x00000044) |
| #define DMA_CH1_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH1_WRITE_ADDR_RESET _u(0x00000000) |
| #define DMA_CH1_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH1_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH1_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH1_TRANS_COUNT |
| // Description : DMA Channel 1 Transfer Count |
| #define DMA_CH1_TRANS_COUNT_OFFSET _u(0x00000048) |
| #define DMA_CH1_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH1_TRANS_COUNT_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_TRANS_COUNT_MODE |
| // Description : When MODE is 0x0, the transfer count decrements with each |
| // transfer until 0, and then the channel triggers the next |
| // channel indicated by CTRL_CHAIN_TO. |
| // |
| // When MODE is 0x1, the transfer count decrements with each |
| // transfer until 0, and then the channel re-triggers itself, in |
| // addition to the trigger indicated by CTRL_CHAIN_TO. This is |
| // useful for e.g. an endless ring-buffer DMA with periodic |
| // interrupts. |
| // |
| // When MODE is 0xf, the transfer count does not decrement. The |
| // DMA channel performs an endless sequence of transfers, never |
| // triggering other channels or raising interrupts, until an ABORT |
| // is raised. |
| // |
| // All other values are reserved. |
| // 0x0 -> NORMAL |
| // 0x1 -> TRIGGER_SELF |
| // 0xf -> ENDLESS |
| #define DMA_CH1_TRANS_COUNT_MODE_RESET _u(0x0) |
| #define DMA_CH1_TRANS_COUNT_MODE_BITS _u(0xf0000000) |
| #define DMA_CH1_TRANS_COUNT_MODE_MSB _u(31) |
| #define DMA_CH1_TRANS_COUNT_MODE_LSB _u(28) |
| #define DMA_CH1_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH1_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) |
| #define DMA_CH1_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) |
| #define DMA_CH1_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_TRANS_COUNT_COUNT |
| // Description : 28-bit transfer count (256 million transfers maximum). |
| // |
| // Program the number of bus transfers a channel will perform |
| // before halting. Note that, if transfers are larger than one |
| // byte in size, this is not equal to the number of bytes |
| // transferred (see CTRL_DATA_SIZE). |
| // |
| // When the channel is active, reading this register shows the |
| // number of transfers remaining, updating automatically each time |
| // a write transfer completes. |
| // |
| // Writing this register sets the RELOAD value for the transfer |
| // counter. Each time this channel is triggered, the RELOAD value |
| // is copied into the live transfer counter. The channel can be |
| // started multiple times, and will perform the same number of |
| // transfers each time, as programmed by most recent write. |
| // |
| // The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT |
| // is used as a trigger, the written value is used immediately as |
| // the length of the new transfer sequence, as well as being |
| // written to RELOAD. |
| #define DMA_CH1_TRANS_COUNT_COUNT_RESET _u(0x0000000) |
| #define DMA_CH1_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) |
| #define DMA_CH1_TRANS_COUNT_COUNT_MSB _u(27) |
| #define DMA_CH1_TRANS_COUNT_COUNT_LSB _u(0) |
| #define DMA_CH1_TRANS_COUNT_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH1_CTRL_TRIG |
| // Description : DMA Channel 1 Control and Status |
| #define DMA_CH1_CTRL_TRIG_OFFSET _u(0x0000004c) |
| #define DMA_CH1_CTRL_TRIG_BITS _u(0xe7ffffff) |
| #define DMA_CH1_CTRL_TRIG_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_AHB_ERROR |
| // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel |
| // halts when it encounters any bus error, and always raises its |
| // channel IRQ flag. |
| #define DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) |
| #define DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB _u(31) |
| #define DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB _u(31) |
| #define DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_READ_ERROR |
| // Description : If 1, the channel received a read bus error. Write one to |
| // clear. |
| // READ_ADDR shows the approximate address where the bus error was |
| // encountered (will not be earlier, or more than 3 transfers |
| // later) |
| #define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) |
| #define DMA_CH1_CTRL_TRIG_READ_ERROR_MSB _u(30) |
| #define DMA_CH1_CTRL_TRIG_READ_ERROR_LSB _u(30) |
| #define DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_WRITE_ERROR |
| // Description : If 1, the channel received a write bus error. Write one to |
| // clear. |
| // WRITE_ADDR shows the approximate address where the bus error |
| // was encountered (will not be earlier, or more than 5 transfers |
| // later) |
| #define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) |
| #define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB _u(29) |
| #define DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB _u(29) |
| #define DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_BUSY |
| // Description : This flag goes high when the channel starts a new transfer |
| // sequence, and low when the last transfer of that sequence |
| // completes. Clearing EN while BUSY is high pauses the channel, |
| // and BUSY will stay high while paused. |
| // |
| // To terminate a sequence early (and clear the BUSY flag), see |
| // CHAN_ABORT. |
| #define DMA_CH1_CTRL_TRIG_BUSY_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_BUSY_BITS _u(0x04000000) |
| #define DMA_CH1_CTRL_TRIG_BUSY_MSB _u(26) |
| #define DMA_CH1_CTRL_TRIG_BUSY_LSB _u(26) |
| #define DMA_CH1_CTRL_TRIG_BUSY_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_SNIFF_EN |
| // Description : If 1, this channel's data transfers are visible to the sniff |
| // hardware, and each transfer will advance the state of the |
| // checksum. This only applies if the sniff hardware is enabled, |
| // and has this channel selected. |
| // |
| // This allows checksum to be enabled or disabled on a per- |
| // control- block basis. |
| #define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) |
| #define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB _u(25) |
| #define DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB _u(25) |
| #define DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_BSWAP |
| // Description : Apply byte-swap transformation to DMA data. |
| // For byte data, this has no effect. For halfword data, the two |
| // bytes of each halfword are swapped. For word data, the four |
| // bytes of each word are swapped to reverse order. |
| #define DMA_CH1_CTRL_TRIG_BSWAP_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_BSWAP_BITS _u(0x01000000) |
| #define DMA_CH1_CTRL_TRIG_BSWAP_MSB _u(24) |
| #define DMA_CH1_CTRL_TRIG_BSWAP_LSB _u(24) |
| #define DMA_CH1_CTRL_TRIG_BSWAP_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_IRQ_QUIET |
| // Description : In QUIET mode, the channel does not generate IRQs at the end of |
| // every transfer block. Instead, an IRQ is raised when NULL is |
| // written to a trigger register, indicating the end of a control |
| // block chain. |
| // |
| // This reduces the number of interrupts to be serviced by the CPU |
| // when transferring a DMA chain of many small control blocks. |
| #define DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) |
| #define DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB _u(23) |
| #define DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB _u(23) |
| #define DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_TREQ_SEL |
| // Description : Select a Transfer Request signal. |
| // The channel uses the transfer request signal to pace its data |
| // transfer rate. Sources for TREQ signals are internal (TIMERS) |
| // or external (DREQ, a Data Request from the system). |
| // 0x0 to 0x3a -> select DREQ n as TREQ |
| // 0x3b -> Select Timer 0 as TREQ |
| // 0x3c -> Select Timer 1 as TREQ |
| // 0x3d -> Select Timer 2 as TREQ (Optional) |
| // 0x3e -> Select Timer 3 as TREQ (Optional) |
| // 0x3f -> Permanent request, for unpaced transfers. |
| #define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) |
| #define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) |
| #define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(22) |
| #define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB _u(17) |
| #define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) |
| #define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) |
| #define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) |
| #define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) |
| #define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_CHAIN_TO |
| // Description : When this channel completes, it will trigger the channel |
| // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this |
| // channel)_. |
| // |
| // Note this field resets to 0, so channels 1 and above will chain |
| // to channel 0 by default. Set this field to avoid this |
| // behaviour. |
| #define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) |
| #define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB _u(16) |
| #define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB _u(13) |
| #define DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_RING_SEL |
| // Description : Select whether RING_SIZE applies to read or write addresses. |
| // If 0, read addresses are wrapped on a (1 << RING_SIZE) |
| // boundary. If 1, write addresses are wrapped. |
| #define DMA_CH1_CTRL_TRIG_RING_SEL_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) |
| #define DMA_CH1_CTRL_TRIG_RING_SEL_MSB _u(12) |
| #define DMA_CH1_CTRL_TRIG_RING_SEL_LSB _u(12) |
| #define DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_RING_SIZE |
| // Description : Size of address wrap region. If 0, don't wrap. For values n > |
| // 0, only the lower n bits of the address will change. This wraps |
| // the address on a (1 << n) byte boundary, facilitating access to |
| // naturally-aligned ring buffers. |
| // |
| // Ring sizes between 2 and 32768 bytes are possible. This can |
| // apply to either read or write addresses, based on value of |
| // RING_SEL. |
| // 0x0 -> RING_NONE |
| #define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) |
| #define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB _u(11) |
| #define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB _u(8) |
| #define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_INCR_WRITE_REV |
| // Description : If 1, and INCR_WRITE is 1, the write address is decremented |
| // rather than incremented with each transfer. |
| // |
| // If 1, and INCR_WRITE is 0, this otherwise-unused combination |
| // causes the write address to be incremented by twice the |
| // transfer size, i.e. skipping over alternate addresses. |
| #define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) |
| #define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) |
| #define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) |
| #define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_INCR_WRITE |
| // Description : If 1, the write address increments with each transfer. If 0, |
| // each write is directed to the same, initial address. |
| // |
| // Generally this should be disabled for memory-to-peripheral |
| // transfers. |
| #define DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) |
| #define DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB _u(6) |
| #define DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB _u(6) |
| #define DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_INCR_READ_REV |
| // Description : If 1, and INCR_READ is 1, the read address is decremented |
| // rather than incremented with each transfer. |
| // |
| // If 1, and INCR_READ is 0, this otherwise-unused combination |
| // causes the read address to be incremented by twice the transfer |
| // size, i.e. skipping over alternate addresses. |
| #define DMA_CH1_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) |
| #define DMA_CH1_CTRL_TRIG_INCR_READ_REV_MSB _u(5) |
| #define DMA_CH1_CTRL_TRIG_INCR_READ_REV_LSB _u(5) |
| #define DMA_CH1_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_INCR_READ |
| // Description : If 1, the read address increments with each transfer. If 0, |
| // each read is directed to the same, initial address. |
| // |
| // Generally this should be disabled for peripheral-to-memory |
| // transfers. |
| #define DMA_CH1_CTRL_TRIG_INCR_READ_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) |
| #define DMA_CH1_CTRL_TRIG_INCR_READ_MSB _u(4) |
| #define DMA_CH1_CTRL_TRIG_INCR_READ_LSB _u(4) |
| #define DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_DATA_SIZE |
| // Description : Set the size of each bus transfer (byte/halfword/word). |
| // READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) |
| // with each transfer. |
| // 0x0 -> SIZE_BYTE |
| // 0x1 -> SIZE_HALFWORD |
| // 0x2 -> SIZE_WORD |
| #define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) |
| #define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB _u(3) |
| #define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB _u(2) |
| #define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) |
| #define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_HIGH_PRIORITY |
| // Description : HIGH_PRIORITY gives a channel preferential treatment in issue |
| // scheduling: in each scheduling round, all high priority |
| // channels are considered first, and then only a single low |
| // priority channel, before returning to the high priority |
| // channels. |
| // |
| // This only affects the order in which the DMA schedules |
| // channels. The DMA's bus priority is not changed. If the DMA is |
| // not saturated then a low priority channel will see no loss of |
| // throughput. |
| #define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) |
| #define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) |
| #define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) |
| #define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH1_CTRL_TRIG_EN |
| // Description : DMA Channel Enable. |
| // When 1, the channel will respond to triggering events, which |
| // will cause it to become BUSY and start transferring data. When |
| // 0, the channel will ignore triggers, stop issuing transfers, |
| // and pause the current transfer sequence (i.e. BUSY will remain |
| // high if already high) |
| #define DMA_CH1_CTRL_TRIG_EN_RESET _u(0x0) |
| #define DMA_CH1_CTRL_TRIG_EN_BITS _u(0x00000001) |
| #define DMA_CH1_CTRL_TRIG_EN_MSB _u(0) |
| #define DMA_CH1_CTRL_TRIG_EN_LSB _u(0) |
| #define DMA_CH1_CTRL_TRIG_EN_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH1_AL1_CTRL |
| // Description : Alias for channel 1 CTRL register |
| #define DMA_CH1_AL1_CTRL_OFFSET _u(0x00000050) |
| #define DMA_CH1_AL1_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH1_AL1_CTRL_RESET "-" |
| #define DMA_CH1_AL1_CTRL_MSB _u(31) |
| #define DMA_CH1_AL1_CTRL_LSB _u(0) |
| #define DMA_CH1_AL1_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH1_AL1_READ_ADDR |
| // Description : Alias for channel 1 READ_ADDR register |
| #define DMA_CH1_AL1_READ_ADDR_OFFSET _u(0x00000054) |
| #define DMA_CH1_AL1_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH1_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH1_AL1_READ_ADDR_MSB _u(31) |
| #define DMA_CH1_AL1_READ_ADDR_LSB _u(0) |
| #define DMA_CH1_AL1_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH1_AL1_WRITE_ADDR |
| // Description : Alias for channel 1 WRITE_ADDR register |
| #define DMA_CH1_AL1_WRITE_ADDR_OFFSET _u(0x00000058) |
| #define DMA_CH1_AL1_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH1_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH1_AL1_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH1_AL1_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH1_AL1_TRANS_COUNT_TRIG |
| // Description : Alias for channel 1 TRANS_COUNT register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000005c) |
| #define DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB _u(31) |
| #define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB _u(0) |
| #define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH1_AL2_CTRL |
| // Description : Alias for channel 1 CTRL register |
| #define DMA_CH1_AL2_CTRL_OFFSET _u(0x00000060) |
| #define DMA_CH1_AL2_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH1_AL2_CTRL_RESET "-" |
| #define DMA_CH1_AL2_CTRL_MSB _u(31) |
| #define DMA_CH1_AL2_CTRL_LSB _u(0) |
| #define DMA_CH1_AL2_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH1_AL2_TRANS_COUNT |
| // Description : Alias for channel 1 TRANS_COUNT register |
| #define DMA_CH1_AL2_TRANS_COUNT_OFFSET _u(0x00000064) |
| #define DMA_CH1_AL2_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH1_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH1_AL2_TRANS_COUNT_MSB _u(31) |
| #define DMA_CH1_AL2_TRANS_COUNT_LSB _u(0) |
| #define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH1_AL2_READ_ADDR |
| // Description : Alias for channel 1 READ_ADDR register |
| #define DMA_CH1_AL2_READ_ADDR_OFFSET _u(0x00000068) |
| #define DMA_CH1_AL2_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH1_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH1_AL2_READ_ADDR_MSB _u(31) |
| #define DMA_CH1_AL2_READ_ADDR_LSB _u(0) |
| #define DMA_CH1_AL2_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH1_AL2_WRITE_ADDR_TRIG |
| // Description : Alias for channel 1 WRITE_ADDR register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000006c) |
| #define DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB _u(31) |
| #define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB _u(0) |
| #define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH1_AL3_CTRL |
| // Description : Alias for channel 1 CTRL register |
| #define DMA_CH1_AL3_CTRL_OFFSET _u(0x00000070) |
| #define DMA_CH1_AL3_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH1_AL3_CTRL_RESET "-" |
| #define DMA_CH1_AL3_CTRL_MSB _u(31) |
| #define DMA_CH1_AL3_CTRL_LSB _u(0) |
| #define DMA_CH1_AL3_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH1_AL3_WRITE_ADDR |
| // Description : Alias for channel 1 WRITE_ADDR register |
| #define DMA_CH1_AL3_WRITE_ADDR_OFFSET _u(0x00000074) |
| #define DMA_CH1_AL3_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH1_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH1_AL3_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH1_AL3_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH1_AL3_TRANS_COUNT |
| // Description : Alias for channel 1 TRANS_COUNT register |
| #define DMA_CH1_AL3_TRANS_COUNT_OFFSET _u(0x00000078) |
| #define DMA_CH1_AL3_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH1_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH1_AL3_TRANS_COUNT_MSB _u(31) |
| #define DMA_CH1_AL3_TRANS_COUNT_LSB _u(0) |
| #define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH1_AL3_READ_ADDR_TRIG |
| // Description : Alias for channel 1 READ_ADDR register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000007c) |
| #define DMA_CH1_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH1_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH1_AL3_READ_ADDR_TRIG_MSB _u(31) |
| #define DMA_CH1_AL3_READ_ADDR_TRIG_LSB _u(0) |
| #define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH2_READ_ADDR |
| // Description : DMA Channel 2 Read Address pointer |
| // This register updates automatically each time a read completes. |
| // The current value is the next address to be read by this |
| // channel. |
| #define DMA_CH2_READ_ADDR_OFFSET _u(0x00000080) |
| #define DMA_CH2_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH2_READ_ADDR_RESET _u(0x00000000) |
| #define DMA_CH2_READ_ADDR_MSB _u(31) |
| #define DMA_CH2_READ_ADDR_LSB _u(0) |
| #define DMA_CH2_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH2_WRITE_ADDR |
| // Description : DMA Channel 2 Write Address pointer |
| // This register updates automatically each time a write |
| // completes. The current value is the next address to be written |
| // by this channel. |
| #define DMA_CH2_WRITE_ADDR_OFFSET _u(0x00000084) |
| #define DMA_CH2_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH2_WRITE_ADDR_RESET _u(0x00000000) |
| #define DMA_CH2_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH2_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH2_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH2_TRANS_COUNT |
| // Description : DMA Channel 2 Transfer Count |
| #define DMA_CH2_TRANS_COUNT_OFFSET _u(0x00000088) |
| #define DMA_CH2_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH2_TRANS_COUNT_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_TRANS_COUNT_MODE |
| // Description : When MODE is 0x0, the transfer count decrements with each |
| // transfer until 0, and then the channel triggers the next |
| // channel indicated by CTRL_CHAIN_TO. |
| // |
| // When MODE is 0x1, the transfer count decrements with each |
| // transfer until 0, and then the channel re-triggers itself, in |
| // addition to the trigger indicated by CTRL_CHAIN_TO. This is |
| // useful for e.g. an endless ring-buffer DMA with periodic |
| // interrupts. |
| // |
| // When MODE is 0xf, the transfer count does not decrement. The |
| // DMA channel performs an endless sequence of transfers, never |
| // triggering other channels or raising interrupts, until an ABORT |
| // is raised. |
| // |
| // All other values are reserved. |
| // 0x0 -> NORMAL |
| // 0x1 -> TRIGGER_SELF |
| // 0xf -> ENDLESS |
| #define DMA_CH2_TRANS_COUNT_MODE_RESET _u(0x0) |
| #define DMA_CH2_TRANS_COUNT_MODE_BITS _u(0xf0000000) |
| #define DMA_CH2_TRANS_COUNT_MODE_MSB _u(31) |
| #define DMA_CH2_TRANS_COUNT_MODE_LSB _u(28) |
| #define DMA_CH2_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH2_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) |
| #define DMA_CH2_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) |
| #define DMA_CH2_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_TRANS_COUNT_COUNT |
| // Description : 28-bit transfer count (256 million transfers maximum). |
| // |
| // Program the number of bus transfers a channel will perform |
| // before halting. Note that, if transfers are larger than one |
| // byte in size, this is not equal to the number of bytes |
| // transferred (see CTRL_DATA_SIZE). |
| // |
| // When the channel is active, reading this register shows the |
| // number of transfers remaining, updating automatically each time |
| // a write transfer completes. |
| // |
| // Writing this register sets the RELOAD value for the transfer |
| // counter. Each time this channel is triggered, the RELOAD value |
| // is copied into the live transfer counter. The channel can be |
| // started multiple times, and will perform the same number of |
| // transfers each time, as programmed by most recent write. |
| // |
| // The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT |
| // is used as a trigger, the written value is used immediately as |
| // the length of the new transfer sequence, as well as being |
| // written to RELOAD. |
| #define DMA_CH2_TRANS_COUNT_COUNT_RESET _u(0x0000000) |
| #define DMA_CH2_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) |
| #define DMA_CH2_TRANS_COUNT_COUNT_MSB _u(27) |
| #define DMA_CH2_TRANS_COUNT_COUNT_LSB _u(0) |
| #define DMA_CH2_TRANS_COUNT_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH2_CTRL_TRIG |
| // Description : DMA Channel 2 Control and Status |
| #define DMA_CH2_CTRL_TRIG_OFFSET _u(0x0000008c) |
| #define DMA_CH2_CTRL_TRIG_BITS _u(0xe7ffffff) |
| #define DMA_CH2_CTRL_TRIG_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_AHB_ERROR |
| // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel |
| // halts when it encounters any bus error, and always raises its |
| // channel IRQ flag. |
| #define DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) |
| #define DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB _u(31) |
| #define DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB _u(31) |
| #define DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_READ_ERROR |
| // Description : If 1, the channel received a read bus error. Write one to |
| // clear. |
| // READ_ADDR shows the approximate address where the bus error was |
| // encountered (will not be earlier, or more than 3 transfers |
| // later) |
| #define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) |
| #define DMA_CH2_CTRL_TRIG_READ_ERROR_MSB _u(30) |
| #define DMA_CH2_CTRL_TRIG_READ_ERROR_LSB _u(30) |
| #define DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_WRITE_ERROR |
| // Description : If 1, the channel received a write bus error. Write one to |
| // clear. |
| // WRITE_ADDR shows the approximate address where the bus error |
| // was encountered (will not be earlier, or more than 5 transfers |
| // later) |
| #define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) |
| #define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB _u(29) |
| #define DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB _u(29) |
| #define DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_BUSY |
| // Description : This flag goes high when the channel starts a new transfer |
| // sequence, and low when the last transfer of that sequence |
| // completes. Clearing EN while BUSY is high pauses the channel, |
| // and BUSY will stay high while paused. |
| // |
| // To terminate a sequence early (and clear the BUSY flag), see |
| // CHAN_ABORT. |
| #define DMA_CH2_CTRL_TRIG_BUSY_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_BUSY_BITS _u(0x04000000) |
| #define DMA_CH2_CTRL_TRIG_BUSY_MSB _u(26) |
| #define DMA_CH2_CTRL_TRIG_BUSY_LSB _u(26) |
| #define DMA_CH2_CTRL_TRIG_BUSY_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_SNIFF_EN |
| // Description : If 1, this channel's data transfers are visible to the sniff |
| // hardware, and each transfer will advance the state of the |
| // checksum. This only applies if the sniff hardware is enabled, |
| // and has this channel selected. |
| // |
| // This allows checksum to be enabled or disabled on a per- |
| // control- block basis. |
| #define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) |
| #define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB _u(25) |
| #define DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB _u(25) |
| #define DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_BSWAP |
| // Description : Apply byte-swap transformation to DMA data. |
| // For byte data, this has no effect. For halfword data, the two |
| // bytes of each halfword are swapped. For word data, the four |
| // bytes of each word are swapped to reverse order. |
| #define DMA_CH2_CTRL_TRIG_BSWAP_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_BSWAP_BITS _u(0x01000000) |
| #define DMA_CH2_CTRL_TRIG_BSWAP_MSB _u(24) |
| #define DMA_CH2_CTRL_TRIG_BSWAP_LSB _u(24) |
| #define DMA_CH2_CTRL_TRIG_BSWAP_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_IRQ_QUIET |
| // Description : In QUIET mode, the channel does not generate IRQs at the end of |
| // every transfer block. Instead, an IRQ is raised when NULL is |
| // written to a trigger register, indicating the end of a control |
| // block chain. |
| // |
| // This reduces the number of interrupts to be serviced by the CPU |
| // when transferring a DMA chain of many small control blocks. |
| #define DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) |
| #define DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB _u(23) |
| #define DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB _u(23) |
| #define DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_TREQ_SEL |
| // Description : Select a Transfer Request signal. |
| // The channel uses the transfer request signal to pace its data |
| // transfer rate. Sources for TREQ signals are internal (TIMERS) |
| // or external (DREQ, a Data Request from the system). |
| // 0x0 to 0x3a -> select DREQ n as TREQ |
| // 0x3b -> Select Timer 0 as TREQ |
| // 0x3c -> Select Timer 1 as TREQ |
| // 0x3d -> Select Timer 2 as TREQ (Optional) |
| // 0x3e -> Select Timer 3 as TREQ (Optional) |
| // 0x3f -> Permanent request, for unpaced transfers. |
| #define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) |
| #define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) |
| #define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(22) |
| #define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB _u(17) |
| #define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) |
| #define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) |
| #define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) |
| #define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) |
| #define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_CHAIN_TO |
| // Description : When this channel completes, it will trigger the channel |
| // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this |
| // channel)_. |
| // |
| // Note this field resets to 0, so channels 1 and above will chain |
| // to channel 0 by default. Set this field to avoid this |
| // behaviour. |
| #define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) |
| #define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB _u(16) |
| #define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB _u(13) |
| #define DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_RING_SEL |
| // Description : Select whether RING_SIZE applies to read or write addresses. |
| // If 0, read addresses are wrapped on a (1 << RING_SIZE) |
| // boundary. If 1, write addresses are wrapped. |
| #define DMA_CH2_CTRL_TRIG_RING_SEL_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) |
| #define DMA_CH2_CTRL_TRIG_RING_SEL_MSB _u(12) |
| #define DMA_CH2_CTRL_TRIG_RING_SEL_LSB _u(12) |
| #define DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_RING_SIZE |
| // Description : Size of address wrap region. If 0, don't wrap. For values n > |
| // 0, only the lower n bits of the address will change. This wraps |
| // the address on a (1 << n) byte boundary, facilitating access to |
| // naturally-aligned ring buffers. |
| // |
| // Ring sizes between 2 and 32768 bytes are possible. This can |
| // apply to either read or write addresses, based on value of |
| // RING_SEL. |
| // 0x0 -> RING_NONE |
| #define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) |
| #define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB _u(11) |
| #define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB _u(8) |
| #define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_INCR_WRITE_REV |
| // Description : If 1, and INCR_WRITE is 1, the write address is decremented |
| // rather than incremented with each transfer. |
| // |
| // If 1, and INCR_WRITE is 0, this otherwise-unused combination |
| // causes the write address to be incremented by twice the |
| // transfer size, i.e. skipping over alternate addresses. |
| #define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) |
| #define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) |
| #define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) |
| #define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_INCR_WRITE |
| // Description : If 1, the write address increments with each transfer. If 0, |
| // each write is directed to the same, initial address. |
| // |
| // Generally this should be disabled for memory-to-peripheral |
| // transfers. |
| #define DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) |
| #define DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB _u(6) |
| #define DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB _u(6) |
| #define DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_INCR_READ_REV |
| // Description : If 1, and INCR_READ is 1, the read address is decremented |
| // rather than incremented with each transfer. |
| // |
| // If 1, and INCR_READ is 0, this otherwise-unused combination |
| // causes the read address to be incremented by twice the transfer |
| // size, i.e. skipping over alternate addresses. |
| #define DMA_CH2_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) |
| #define DMA_CH2_CTRL_TRIG_INCR_READ_REV_MSB _u(5) |
| #define DMA_CH2_CTRL_TRIG_INCR_READ_REV_LSB _u(5) |
| #define DMA_CH2_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_INCR_READ |
| // Description : If 1, the read address increments with each transfer. If 0, |
| // each read is directed to the same, initial address. |
| // |
| // Generally this should be disabled for peripheral-to-memory |
| // transfers. |
| #define DMA_CH2_CTRL_TRIG_INCR_READ_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) |
| #define DMA_CH2_CTRL_TRIG_INCR_READ_MSB _u(4) |
| #define DMA_CH2_CTRL_TRIG_INCR_READ_LSB _u(4) |
| #define DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_DATA_SIZE |
| // Description : Set the size of each bus transfer (byte/halfword/word). |
| // READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) |
| // with each transfer. |
| // 0x0 -> SIZE_BYTE |
| // 0x1 -> SIZE_HALFWORD |
| // 0x2 -> SIZE_WORD |
| #define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) |
| #define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB _u(3) |
| #define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB _u(2) |
| #define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) |
| #define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_HIGH_PRIORITY |
| // Description : HIGH_PRIORITY gives a channel preferential treatment in issue |
| // scheduling: in each scheduling round, all high priority |
| // channels are considered first, and then only a single low |
| // priority channel, before returning to the high priority |
| // channels. |
| // |
| // This only affects the order in which the DMA schedules |
| // channels. The DMA's bus priority is not changed. If the DMA is |
| // not saturated then a low priority channel will see no loss of |
| // throughput. |
| #define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) |
| #define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) |
| #define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) |
| #define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH2_CTRL_TRIG_EN |
| // Description : DMA Channel Enable. |
| // When 1, the channel will respond to triggering events, which |
| // will cause it to become BUSY and start transferring data. When |
| // 0, the channel will ignore triggers, stop issuing transfers, |
| // and pause the current transfer sequence (i.e. BUSY will remain |
| // high if already high) |
| #define DMA_CH2_CTRL_TRIG_EN_RESET _u(0x0) |
| #define DMA_CH2_CTRL_TRIG_EN_BITS _u(0x00000001) |
| #define DMA_CH2_CTRL_TRIG_EN_MSB _u(0) |
| #define DMA_CH2_CTRL_TRIG_EN_LSB _u(0) |
| #define DMA_CH2_CTRL_TRIG_EN_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH2_AL1_CTRL |
| // Description : Alias for channel 2 CTRL register |
| #define DMA_CH2_AL1_CTRL_OFFSET _u(0x00000090) |
| #define DMA_CH2_AL1_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH2_AL1_CTRL_RESET "-" |
| #define DMA_CH2_AL1_CTRL_MSB _u(31) |
| #define DMA_CH2_AL1_CTRL_LSB _u(0) |
| #define DMA_CH2_AL1_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH2_AL1_READ_ADDR |
| // Description : Alias for channel 2 READ_ADDR register |
| #define DMA_CH2_AL1_READ_ADDR_OFFSET _u(0x00000094) |
| #define DMA_CH2_AL1_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH2_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH2_AL1_READ_ADDR_MSB _u(31) |
| #define DMA_CH2_AL1_READ_ADDR_LSB _u(0) |
| #define DMA_CH2_AL1_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH2_AL1_WRITE_ADDR |
| // Description : Alias for channel 2 WRITE_ADDR register |
| #define DMA_CH2_AL1_WRITE_ADDR_OFFSET _u(0x00000098) |
| #define DMA_CH2_AL1_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH2_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH2_AL1_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH2_AL1_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH2_AL1_TRANS_COUNT_TRIG |
| // Description : Alias for channel 2 TRANS_COUNT register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000009c) |
| #define DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB _u(31) |
| #define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB _u(0) |
| #define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH2_AL2_CTRL |
| // Description : Alias for channel 2 CTRL register |
| #define DMA_CH2_AL2_CTRL_OFFSET _u(0x000000a0) |
| #define DMA_CH2_AL2_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH2_AL2_CTRL_RESET "-" |
| #define DMA_CH2_AL2_CTRL_MSB _u(31) |
| #define DMA_CH2_AL2_CTRL_LSB _u(0) |
| #define DMA_CH2_AL2_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH2_AL2_TRANS_COUNT |
| // Description : Alias for channel 2 TRANS_COUNT register |
| #define DMA_CH2_AL2_TRANS_COUNT_OFFSET _u(0x000000a4) |
| #define DMA_CH2_AL2_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH2_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH2_AL2_TRANS_COUNT_MSB _u(31) |
| #define DMA_CH2_AL2_TRANS_COUNT_LSB _u(0) |
| #define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH2_AL2_READ_ADDR |
| // Description : Alias for channel 2 READ_ADDR register |
| #define DMA_CH2_AL2_READ_ADDR_OFFSET _u(0x000000a8) |
| #define DMA_CH2_AL2_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH2_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH2_AL2_READ_ADDR_MSB _u(31) |
| #define DMA_CH2_AL2_READ_ADDR_LSB _u(0) |
| #define DMA_CH2_AL2_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH2_AL2_WRITE_ADDR_TRIG |
| // Description : Alias for channel 2 WRITE_ADDR register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ac) |
| #define DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB _u(31) |
| #define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB _u(0) |
| #define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH2_AL3_CTRL |
| // Description : Alias for channel 2 CTRL register |
| #define DMA_CH2_AL3_CTRL_OFFSET _u(0x000000b0) |
| #define DMA_CH2_AL3_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH2_AL3_CTRL_RESET "-" |
| #define DMA_CH2_AL3_CTRL_MSB _u(31) |
| #define DMA_CH2_AL3_CTRL_LSB _u(0) |
| #define DMA_CH2_AL3_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH2_AL3_WRITE_ADDR |
| // Description : Alias for channel 2 WRITE_ADDR register |
| #define DMA_CH2_AL3_WRITE_ADDR_OFFSET _u(0x000000b4) |
| #define DMA_CH2_AL3_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH2_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH2_AL3_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH2_AL3_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH2_AL3_TRANS_COUNT |
| // Description : Alias for channel 2 TRANS_COUNT register |
| #define DMA_CH2_AL3_TRANS_COUNT_OFFSET _u(0x000000b8) |
| #define DMA_CH2_AL3_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH2_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH2_AL3_TRANS_COUNT_MSB _u(31) |
| #define DMA_CH2_AL3_TRANS_COUNT_LSB _u(0) |
| #define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH2_AL3_READ_ADDR_TRIG |
| // Description : Alias for channel 2 READ_ADDR register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000bc) |
| #define DMA_CH2_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH2_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH2_AL3_READ_ADDR_TRIG_MSB _u(31) |
| #define DMA_CH2_AL3_READ_ADDR_TRIG_LSB _u(0) |
| #define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH3_READ_ADDR |
| // Description : DMA Channel 3 Read Address pointer |
| // This register updates automatically each time a read completes. |
| // The current value is the next address to be read by this |
| // channel. |
| #define DMA_CH3_READ_ADDR_OFFSET _u(0x000000c0) |
| #define DMA_CH3_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH3_READ_ADDR_RESET _u(0x00000000) |
| #define DMA_CH3_READ_ADDR_MSB _u(31) |
| #define DMA_CH3_READ_ADDR_LSB _u(0) |
| #define DMA_CH3_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH3_WRITE_ADDR |
| // Description : DMA Channel 3 Write Address pointer |
| // This register updates automatically each time a write |
| // completes. The current value is the next address to be written |
| // by this channel. |
| #define DMA_CH3_WRITE_ADDR_OFFSET _u(0x000000c4) |
| #define DMA_CH3_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH3_WRITE_ADDR_RESET _u(0x00000000) |
| #define DMA_CH3_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH3_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH3_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH3_TRANS_COUNT |
| // Description : DMA Channel 3 Transfer Count |
| #define DMA_CH3_TRANS_COUNT_OFFSET _u(0x000000c8) |
| #define DMA_CH3_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH3_TRANS_COUNT_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_TRANS_COUNT_MODE |
| // Description : When MODE is 0x0, the transfer count decrements with each |
| // transfer until 0, and then the channel triggers the next |
| // channel indicated by CTRL_CHAIN_TO. |
| // |
| // When MODE is 0x1, the transfer count decrements with each |
| // transfer until 0, and then the channel re-triggers itself, in |
| // addition to the trigger indicated by CTRL_CHAIN_TO. This is |
| // useful for e.g. an endless ring-buffer DMA with periodic |
| // interrupts. |
| // |
| // When MODE is 0xf, the transfer count does not decrement. The |
| // DMA channel performs an endless sequence of transfers, never |
| // triggering other channels or raising interrupts, until an ABORT |
| // is raised. |
| // |
| // All other values are reserved. |
| // 0x0 -> NORMAL |
| // 0x1 -> TRIGGER_SELF |
| // 0xf -> ENDLESS |
| #define DMA_CH3_TRANS_COUNT_MODE_RESET _u(0x0) |
| #define DMA_CH3_TRANS_COUNT_MODE_BITS _u(0xf0000000) |
| #define DMA_CH3_TRANS_COUNT_MODE_MSB _u(31) |
| #define DMA_CH3_TRANS_COUNT_MODE_LSB _u(28) |
| #define DMA_CH3_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH3_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) |
| #define DMA_CH3_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) |
| #define DMA_CH3_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_TRANS_COUNT_COUNT |
| // Description : 28-bit transfer count (256 million transfers maximum). |
| // |
| // Program the number of bus transfers a channel will perform |
| // before halting. Note that, if transfers are larger than one |
| // byte in size, this is not equal to the number of bytes |
| // transferred (see CTRL_DATA_SIZE). |
| // |
| // When the channel is active, reading this register shows the |
| // number of transfers remaining, updating automatically each time |
| // a write transfer completes. |
| // |
| // Writing this register sets the RELOAD value for the transfer |
| // counter. Each time this channel is triggered, the RELOAD value |
| // is copied into the live transfer counter. The channel can be |
| // started multiple times, and will perform the same number of |
| // transfers each time, as programmed by most recent write. |
| // |
| // The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT |
| // is used as a trigger, the written value is used immediately as |
| // the length of the new transfer sequence, as well as being |
| // written to RELOAD. |
| #define DMA_CH3_TRANS_COUNT_COUNT_RESET _u(0x0000000) |
| #define DMA_CH3_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) |
| #define DMA_CH3_TRANS_COUNT_COUNT_MSB _u(27) |
| #define DMA_CH3_TRANS_COUNT_COUNT_LSB _u(0) |
| #define DMA_CH3_TRANS_COUNT_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH3_CTRL_TRIG |
| // Description : DMA Channel 3 Control and Status |
| #define DMA_CH3_CTRL_TRIG_OFFSET _u(0x000000cc) |
| #define DMA_CH3_CTRL_TRIG_BITS _u(0xe7ffffff) |
| #define DMA_CH3_CTRL_TRIG_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_AHB_ERROR |
| // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel |
| // halts when it encounters any bus error, and always raises its |
| // channel IRQ flag. |
| #define DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) |
| #define DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB _u(31) |
| #define DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB _u(31) |
| #define DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_READ_ERROR |
| // Description : If 1, the channel received a read bus error. Write one to |
| // clear. |
| // READ_ADDR shows the approximate address where the bus error was |
| // encountered (will not be earlier, or more than 3 transfers |
| // later) |
| #define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) |
| #define DMA_CH3_CTRL_TRIG_READ_ERROR_MSB _u(30) |
| #define DMA_CH3_CTRL_TRIG_READ_ERROR_LSB _u(30) |
| #define DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_WRITE_ERROR |
| // Description : If 1, the channel received a write bus error. Write one to |
| // clear. |
| // WRITE_ADDR shows the approximate address where the bus error |
| // was encountered (will not be earlier, or more than 5 transfers |
| // later) |
| #define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) |
| #define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB _u(29) |
| #define DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB _u(29) |
| #define DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_BUSY |
| // Description : This flag goes high when the channel starts a new transfer |
| // sequence, and low when the last transfer of that sequence |
| // completes. Clearing EN while BUSY is high pauses the channel, |
| // and BUSY will stay high while paused. |
| // |
| // To terminate a sequence early (and clear the BUSY flag), see |
| // CHAN_ABORT. |
| #define DMA_CH3_CTRL_TRIG_BUSY_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_BUSY_BITS _u(0x04000000) |
| #define DMA_CH3_CTRL_TRIG_BUSY_MSB _u(26) |
| #define DMA_CH3_CTRL_TRIG_BUSY_LSB _u(26) |
| #define DMA_CH3_CTRL_TRIG_BUSY_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_SNIFF_EN |
| // Description : If 1, this channel's data transfers are visible to the sniff |
| // hardware, and each transfer will advance the state of the |
| // checksum. This only applies if the sniff hardware is enabled, |
| // and has this channel selected. |
| // |
| // This allows checksum to be enabled or disabled on a per- |
| // control- block basis. |
| #define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) |
| #define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB _u(25) |
| #define DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB _u(25) |
| #define DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_BSWAP |
| // Description : Apply byte-swap transformation to DMA data. |
| // For byte data, this has no effect. For halfword data, the two |
| // bytes of each halfword are swapped. For word data, the four |
| // bytes of each word are swapped to reverse order. |
| #define DMA_CH3_CTRL_TRIG_BSWAP_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_BSWAP_BITS _u(0x01000000) |
| #define DMA_CH3_CTRL_TRIG_BSWAP_MSB _u(24) |
| #define DMA_CH3_CTRL_TRIG_BSWAP_LSB _u(24) |
| #define DMA_CH3_CTRL_TRIG_BSWAP_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_IRQ_QUIET |
| // Description : In QUIET mode, the channel does not generate IRQs at the end of |
| // every transfer block. Instead, an IRQ is raised when NULL is |
| // written to a trigger register, indicating the end of a control |
| // block chain. |
| // |
| // This reduces the number of interrupts to be serviced by the CPU |
| // when transferring a DMA chain of many small control blocks. |
| #define DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) |
| #define DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB _u(23) |
| #define DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB _u(23) |
| #define DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_TREQ_SEL |
| // Description : Select a Transfer Request signal. |
| // The channel uses the transfer request signal to pace its data |
| // transfer rate. Sources for TREQ signals are internal (TIMERS) |
| // or external (DREQ, a Data Request from the system). |
| // 0x0 to 0x3a -> select DREQ n as TREQ |
| // 0x3b -> Select Timer 0 as TREQ |
| // 0x3c -> Select Timer 1 as TREQ |
| // 0x3d -> Select Timer 2 as TREQ (Optional) |
| // 0x3e -> Select Timer 3 as TREQ (Optional) |
| // 0x3f -> Permanent request, for unpaced transfers. |
| #define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) |
| #define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) |
| #define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(22) |
| #define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB _u(17) |
| #define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) |
| #define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) |
| #define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) |
| #define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) |
| #define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_CHAIN_TO |
| // Description : When this channel completes, it will trigger the channel |
| // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this |
| // channel)_. |
| // |
| // Note this field resets to 0, so channels 1 and above will chain |
| // to channel 0 by default. Set this field to avoid this |
| // behaviour. |
| #define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) |
| #define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB _u(16) |
| #define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB _u(13) |
| #define DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_RING_SEL |
| // Description : Select whether RING_SIZE applies to read or write addresses. |
| // If 0, read addresses are wrapped on a (1 << RING_SIZE) |
| // boundary. If 1, write addresses are wrapped. |
| #define DMA_CH3_CTRL_TRIG_RING_SEL_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) |
| #define DMA_CH3_CTRL_TRIG_RING_SEL_MSB _u(12) |
| #define DMA_CH3_CTRL_TRIG_RING_SEL_LSB _u(12) |
| #define DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_RING_SIZE |
| // Description : Size of address wrap region. If 0, don't wrap. For values n > |
| // 0, only the lower n bits of the address will change. This wraps |
| // the address on a (1 << n) byte boundary, facilitating access to |
| // naturally-aligned ring buffers. |
| // |
| // Ring sizes between 2 and 32768 bytes are possible. This can |
| // apply to either read or write addresses, based on value of |
| // RING_SEL. |
| // 0x0 -> RING_NONE |
| #define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) |
| #define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB _u(11) |
| #define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB _u(8) |
| #define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_INCR_WRITE_REV |
| // Description : If 1, and INCR_WRITE is 1, the write address is decremented |
| // rather than incremented with each transfer. |
| // |
| // If 1, and INCR_WRITE is 0, this otherwise-unused combination |
| // causes the write address to be incremented by twice the |
| // transfer size, i.e. skipping over alternate addresses. |
| #define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) |
| #define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) |
| #define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) |
| #define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_INCR_WRITE |
| // Description : If 1, the write address increments with each transfer. If 0, |
| // each write is directed to the same, initial address. |
| // |
| // Generally this should be disabled for memory-to-peripheral |
| // transfers. |
| #define DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) |
| #define DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB _u(6) |
| #define DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB _u(6) |
| #define DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_INCR_READ_REV |
| // Description : If 1, and INCR_READ is 1, the read address is decremented |
| // rather than incremented with each transfer. |
| // |
| // If 1, and INCR_READ is 0, this otherwise-unused combination |
| // causes the read address to be incremented by twice the transfer |
| // size, i.e. skipping over alternate addresses. |
| #define DMA_CH3_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) |
| #define DMA_CH3_CTRL_TRIG_INCR_READ_REV_MSB _u(5) |
| #define DMA_CH3_CTRL_TRIG_INCR_READ_REV_LSB _u(5) |
| #define DMA_CH3_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_INCR_READ |
| // Description : If 1, the read address increments with each transfer. If 0, |
| // each read is directed to the same, initial address. |
| // |
| // Generally this should be disabled for peripheral-to-memory |
| // transfers. |
| #define DMA_CH3_CTRL_TRIG_INCR_READ_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) |
| #define DMA_CH3_CTRL_TRIG_INCR_READ_MSB _u(4) |
| #define DMA_CH3_CTRL_TRIG_INCR_READ_LSB _u(4) |
| #define DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_DATA_SIZE |
| // Description : Set the size of each bus transfer (byte/halfword/word). |
| // READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) |
| // with each transfer. |
| // 0x0 -> SIZE_BYTE |
| // 0x1 -> SIZE_HALFWORD |
| // 0x2 -> SIZE_WORD |
| #define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) |
| #define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB _u(3) |
| #define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB _u(2) |
| #define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) |
| #define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_HIGH_PRIORITY |
| // Description : HIGH_PRIORITY gives a channel preferential treatment in issue |
| // scheduling: in each scheduling round, all high priority |
| // channels are considered first, and then only a single low |
| // priority channel, before returning to the high priority |
| // channels. |
| // |
| // This only affects the order in which the DMA schedules |
| // channels. The DMA's bus priority is not changed. If the DMA is |
| // not saturated then a low priority channel will see no loss of |
| // throughput. |
| #define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) |
| #define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) |
| #define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) |
| #define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH3_CTRL_TRIG_EN |
| // Description : DMA Channel Enable. |
| // When 1, the channel will respond to triggering events, which |
| // will cause it to become BUSY and start transferring data. When |
| // 0, the channel will ignore triggers, stop issuing transfers, |
| // and pause the current transfer sequence (i.e. BUSY will remain |
| // high if already high) |
| #define DMA_CH3_CTRL_TRIG_EN_RESET _u(0x0) |
| #define DMA_CH3_CTRL_TRIG_EN_BITS _u(0x00000001) |
| #define DMA_CH3_CTRL_TRIG_EN_MSB _u(0) |
| #define DMA_CH3_CTRL_TRIG_EN_LSB _u(0) |
| #define DMA_CH3_CTRL_TRIG_EN_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH3_AL1_CTRL |
| // Description : Alias for channel 3 CTRL register |
| #define DMA_CH3_AL1_CTRL_OFFSET _u(0x000000d0) |
| #define DMA_CH3_AL1_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH3_AL1_CTRL_RESET "-" |
| #define DMA_CH3_AL1_CTRL_MSB _u(31) |
| #define DMA_CH3_AL1_CTRL_LSB _u(0) |
| #define DMA_CH3_AL1_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH3_AL1_READ_ADDR |
| // Description : Alias for channel 3 READ_ADDR register |
| #define DMA_CH3_AL1_READ_ADDR_OFFSET _u(0x000000d4) |
| #define DMA_CH3_AL1_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH3_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH3_AL1_READ_ADDR_MSB _u(31) |
| #define DMA_CH3_AL1_READ_ADDR_LSB _u(0) |
| #define DMA_CH3_AL1_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH3_AL1_WRITE_ADDR |
| // Description : Alias for channel 3 WRITE_ADDR register |
| #define DMA_CH3_AL1_WRITE_ADDR_OFFSET _u(0x000000d8) |
| #define DMA_CH3_AL1_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH3_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH3_AL1_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH3_AL1_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH3_AL1_TRANS_COUNT_TRIG |
| // Description : Alias for channel 3 TRANS_COUNT register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000000dc) |
| #define DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB _u(31) |
| #define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB _u(0) |
| #define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH3_AL2_CTRL |
| // Description : Alias for channel 3 CTRL register |
| #define DMA_CH3_AL2_CTRL_OFFSET _u(0x000000e0) |
| #define DMA_CH3_AL2_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH3_AL2_CTRL_RESET "-" |
| #define DMA_CH3_AL2_CTRL_MSB _u(31) |
| #define DMA_CH3_AL2_CTRL_LSB _u(0) |
| #define DMA_CH3_AL2_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH3_AL2_TRANS_COUNT |
| // Description : Alias for channel 3 TRANS_COUNT register |
| #define DMA_CH3_AL2_TRANS_COUNT_OFFSET _u(0x000000e4) |
| #define DMA_CH3_AL2_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH3_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH3_AL2_TRANS_COUNT_MSB _u(31) |
| #define DMA_CH3_AL2_TRANS_COUNT_LSB _u(0) |
| #define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH3_AL2_READ_ADDR |
| // Description : Alias for channel 3 READ_ADDR register |
| #define DMA_CH3_AL2_READ_ADDR_OFFSET _u(0x000000e8) |
| #define DMA_CH3_AL2_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH3_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH3_AL2_READ_ADDR_MSB _u(31) |
| #define DMA_CH3_AL2_READ_ADDR_LSB _u(0) |
| #define DMA_CH3_AL2_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH3_AL2_WRITE_ADDR_TRIG |
| // Description : Alias for channel 3 WRITE_ADDR register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ec) |
| #define DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB _u(31) |
| #define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB _u(0) |
| #define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH3_AL3_CTRL |
| // Description : Alias for channel 3 CTRL register |
| #define DMA_CH3_AL3_CTRL_OFFSET _u(0x000000f0) |
| #define DMA_CH3_AL3_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH3_AL3_CTRL_RESET "-" |
| #define DMA_CH3_AL3_CTRL_MSB _u(31) |
| #define DMA_CH3_AL3_CTRL_LSB _u(0) |
| #define DMA_CH3_AL3_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH3_AL3_WRITE_ADDR |
| // Description : Alias for channel 3 WRITE_ADDR register |
| #define DMA_CH3_AL3_WRITE_ADDR_OFFSET _u(0x000000f4) |
| #define DMA_CH3_AL3_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH3_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH3_AL3_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH3_AL3_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH3_AL3_TRANS_COUNT |
| // Description : Alias for channel 3 TRANS_COUNT register |
| #define DMA_CH3_AL3_TRANS_COUNT_OFFSET _u(0x000000f8) |
| #define DMA_CH3_AL3_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH3_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH3_AL3_TRANS_COUNT_MSB _u(31) |
| #define DMA_CH3_AL3_TRANS_COUNT_LSB _u(0) |
| #define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH3_AL3_READ_ADDR_TRIG |
| // Description : Alias for channel 3 READ_ADDR register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000fc) |
| #define DMA_CH3_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH3_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH3_AL3_READ_ADDR_TRIG_MSB _u(31) |
| #define DMA_CH3_AL3_READ_ADDR_TRIG_LSB _u(0) |
| #define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH4_READ_ADDR |
| // Description : DMA Channel 4 Read Address pointer |
| // This register updates automatically each time a read completes. |
| // The current value is the next address to be read by this |
| // channel. |
| #define DMA_CH4_READ_ADDR_OFFSET _u(0x00000100) |
| #define DMA_CH4_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH4_READ_ADDR_RESET _u(0x00000000) |
| #define DMA_CH4_READ_ADDR_MSB _u(31) |
| #define DMA_CH4_READ_ADDR_LSB _u(0) |
| #define DMA_CH4_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH4_WRITE_ADDR |
| // Description : DMA Channel 4 Write Address pointer |
| // This register updates automatically each time a write |
| // completes. The current value is the next address to be written |
| // by this channel. |
| #define DMA_CH4_WRITE_ADDR_OFFSET _u(0x00000104) |
| #define DMA_CH4_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH4_WRITE_ADDR_RESET _u(0x00000000) |
| #define DMA_CH4_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH4_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH4_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH4_TRANS_COUNT |
| // Description : DMA Channel 4 Transfer Count |
| #define DMA_CH4_TRANS_COUNT_OFFSET _u(0x00000108) |
| #define DMA_CH4_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH4_TRANS_COUNT_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_TRANS_COUNT_MODE |
| // Description : When MODE is 0x0, the transfer count decrements with each |
| // transfer until 0, and then the channel triggers the next |
| // channel indicated by CTRL_CHAIN_TO. |
| // |
| // When MODE is 0x1, the transfer count decrements with each |
| // transfer until 0, and then the channel re-triggers itself, in |
| // addition to the trigger indicated by CTRL_CHAIN_TO. This is |
| // useful for e.g. an endless ring-buffer DMA with periodic |
| // interrupts. |
| // |
| // When MODE is 0xf, the transfer count does not decrement. The |
| // DMA channel performs an endless sequence of transfers, never |
| // triggering other channels or raising interrupts, until an ABORT |
| // is raised. |
| // |
| // All other values are reserved. |
| // 0x0 -> NORMAL |
| // 0x1 -> TRIGGER_SELF |
| // 0xf -> ENDLESS |
| #define DMA_CH4_TRANS_COUNT_MODE_RESET _u(0x0) |
| #define DMA_CH4_TRANS_COUNT_MODE_BITS _u(0xf0000000) |
| #define DMA_CH4_TRANS_COUNT_MODE_MSB _u(31) |
| #define DMA_CH4_TRANS_COUNT_MODE_LSB _u(28) |
| #define DMA_CH4_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH4_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) |
| #define DMA_CH4_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) |
| #define DMA_CH4_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_TRANS_COUNT_COUNT |
| // Description : 28-bit transfer count (256 million transfers maximum). |
| // |
| // Program the number of bus transfers a channel will perform |
| // before halting. Note that, if transfers are larger than one |
| // byte in size, this is not equal to the number of bytes |
| // transferred (see CTRL_DATA_SIZE). |
| // |
| // When the channel is active, reading this register shows the |
| // number of transfers remaining, updating automatically each time |
| // a write transfer completes. |
| // |
| // Writing this register sets the RELOAD value for the transfer |
| // counter. Each time this channel is triggered, the RELOAD value |
| // is copied into the live transfer counter. The channel can be |
| // started multiple times, and will perform the same number of |
| // transfers each time, as programmed by most recent write. |
| // |
| // The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT |
| // is used as a trigger, the written value is used immediately as |
| // the length of the new transfer sequence, as well as being |
| // written to RELOAD. |
| #define DMA_CH4_TRANS_COUNT_COUNT_RESET _u(0x0000000) |
| #define DMA_CH4_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) |
| #define DMA_CH4_TRANS_COUNT_COUNT_MSB _u(27) |
| #define DMA_CH4_TRANS_COUNT_COUNT_LSB _u(0) |
| #define DMA_CH4_TRANS_COUNT_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH4_CTRL_TRIG |
| // Description : DMA Channel 4 Control and Status |
| #define DMA_CH4_CTRL_TRIG_OFFSET _u(0x0000010c) |
| #define DMA_CH4_CTRL_TRIG_BITS _u(0xe7ffffff) |
| #define DMA_CH4_CTRL_TRIG_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_AHB_ERROR |
| // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel |
| // halts when it encounters any bus error, and always raises its |
| // channel IRQ flag. |
| #define DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) |
| #define DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB _u(31) |
| #define DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB _u(31) |
| #define DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_READ_ERROR |
| // Description : If 1, the channel received a read bus error. Write one to |
| // clear. |
| // READ_ADDR shows the approximate address where the bus error was |
| // encountered (will not be earlier, or more than 3 transfers |
| // later) |
| #define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) |
| #define DMA_CH4_CTRL_TRIG_READ_ERROR_MSB _u(30) |
| #define DMA_CH4_CTRL_TRIG_READ_ERROR_LSB _u(30) |
| #define DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_WRITE_ERROR |
| // Description : If 1, the channel received a write bus error. Write one to |
| // clear. |
| // WRITE_ADDR shows the approximate address where the bus error |
| // was encountered (will not be earlier, or more than 5 transfers |
| // later) |
| #define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) |
| #define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB _u(29) |
| #define DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB _u(29) |
| #define DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_BUSY |
| // Description : This flag goes high when the channel starts a new transfer |
| // sequence, and low when the last transfer of that sequence |
| // completes. Clearing EN while BUSY is high pauses the channel, |
| // and BUSY will stay high while paused. |
| // |
| // To terminate a sequence early (and clear the BUSY flag), see |
| // CHAN_ABORT. |
| #define DMA_CH4_CTRL_TRIG_BUSY_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_BUSY_BITS _u(0x04000000) |
| #define DMA_CH4_CTRL_TRIG_BUSY_MSB _u(26) |
| #define DMA_CH4_CTRL_TRIG_BUSY_LSB _u(26) |
| #define DMA_CH4_CTRL_TRIG_BUSY_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_SNIFF_EN |
| // Description : If 1, this channel's data transfers are visible to the sniff |
| // hardware, and each transfer will advance the state of the |
| // checksum. This only applies if the sniff hardware is enabled, |
| // and has this channel selected. |
| // |
| // This allows checksum to be enabled or disabled on a per- |
| // control- block basis. |
| #define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) |
| #define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB _u(25) |
| #define DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB _u(25) |
| #define DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_BSWAP |
| // Description : Apply byte-swap transformation to DMA data. |
| // For byte data, this has no effect. For halfword data, the two |
| // bytes of each halfword are swapped. For word data, the four |
| // bytes of each word are swapped to reverse order. |
| #define DMA_CH4_CTRL_TRIG_BSWAP_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_BSWAP_BITS _u(0x01000000) |
| #define DMA_CH4_CTRL_TRIG_BSWAP_MSB _u(24) |
| #define DMA_CH4_CTRL_TRIG_BSWAP_LSB _u(24) |
| #define DMA_CH4_CTRL_TRIG_BSWAP_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_IRQ_QUIET |
| // Description : In QUIET mode, the channel does not generate IRQs at the end of |
| // every transfer block. Instead, an IRQ is raised when NULL is |
| // written to a trigger register, indicating the end of a control |
| // block chain. |
| // |
| // This reduces the number of interrupts to be serviced by the CPU |
| // when transferring a DMA chain of many small control blocks. |
| #define DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) |
| #define DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB _u(23) |
| #define DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB _u(23) |
| #define DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_TREQ_SEL |
| // Description : Select a Transfer Request signal. |
| // The channel uses the transfer request signal to pace its data |
| // transfer rate. Sources for TREQ signals are internal (TIMERS) |
| // or external (DREQ, a Data Request from the system). |
| // 0x0 to 0x3a -> select DREQ n as TREQ |
| // 0x3b -> Select Timer 0 as TREQ |
| // 0x3c -> Select Timer 1 as TREQ |
| // 0x3d -> Select Timer 2 as TREQ (Optional) |
| // 0x3e -> Select Timer 3 as TREQ (Optional) |
| // 0x3f -> Permanent request, for unpaced transfers. |
| #define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) |
| #define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) |
| #define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(22) |
| #define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB _u(17) |
| #define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) |
| #define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) |
| #define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) |
| #define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) |
| #define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_CHAIN_TO |
| // Description : When this channel completes, it will trigger the channel |
| // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this |
| // channel)_. |
| // |
| // Note this field resets to 0, so channels 1 and above will chain |
| // to channel 0 by default. Set this field to avoid this |
| // behaviour. |
| #define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) |
| #define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB _u(16) |
| #define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB _u(13) |
| #define DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_RING_SEL |
| // Description : Select whether RING_SIZE applies to read or write addresses. |
| // If 0, read addresses are wrapped on a (1 << RING_SIZE) |
| // boundary. If 1, write addresses are wrapped. |
| #define DMA_CH4_CTRL_TRIG_RING_SEL_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) |
| #define DMA_CH4_CTRL_TRIG_RING_SEL_MSB _u(12) |
| #define DMA_CH4_CTRL_TRIG_RING_SEL_LSB _u(12) |
| #define DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_RING_SIZE |
| // Description : Size of address wrap region. If 0, don't wrap. For values n > |
| // 0, only the lower n bits of the address will change. This wraps |
| // the address on a (1 << n) byte boundary, facilitating access to |
| // naturally-aligned ring buffers. |
| // |
| // Ring sizes between 2 and 32768 bytes are possible. This can |
| // apply to either read or write addresses, based on value of |
| // RING_SEL. |
| // 0x0 -> RING_NONE |
| #define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) |
| #define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB _u(11) |
| #define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB _u(8) |
| #define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_INCR_WRITE_REV |
| // Description : If 1, and INCR_WRITE is 1, the write address is decremented |
| // rather than incremented with each transfer. |
| // |
| // If 1, and INCR_WRITE is 0, this otherwise-unused combination |
| // causes the write address to be incremented by twice the |
| // transfer size, i.e. skipping over alternate addresses. |
| #define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) |
| #define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) |
| #define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) |
| #define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_INCR_WRITE |
| // Description : If 1, the write address increments with each transfer. If 0, |
| // each write is directed to the same, initial address. |
| // |
| // Generally this should be disabled for memory-to-peripheral |
| // transfers. |
| #define DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) |
| #define DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB _u(6) |
| #define DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB _u(6) |
| #define DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_INCR_READ_REV |
| // Description : If 1, and INCR_READ is 1, the read address is decremented |
| // rather than incremented with each transfer. |
| // |
| // If 1, and INCR_READ is 0, this otherwise-unused combination |
| // causes the read address to be incremented by twice the transfer |
| // size, i.e. skipping over alternate addresses. |
| #define DMA_CH4_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) |
| #define DMA_CH4_CTRL_TRIG_INCR_READ_REV_MSB _u(5) |
| #define DMA_CH4_CTRL_TRIG_INCR_READ_REV_LSB _u(5) |
| #define DMA_CH4_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_INCR_READ |
| // Description : If 1, the read address increments with each transfer. If 0, |
| // each read is directed to the same, initial address. |
| // |
| // Generally this should be disabled for peripheral-to-memory |
| // transfers. |
| #define DMA_CH4_CTRL_TRIG_INCR_READ_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) |
| #define DMA_CH4_CTRL_TRIG_INCR_READ_MSB _u(4) |
| #define DMA_CH4_CTRL_TRIG_INCR_READ_LSB _u(4) |
| #define DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_DATA_SIZE |
| // Description : Set the size of each bus transfer (byte/halfword/word). |
| // READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) |
| // with each transfer. |
| // 0x0 -> SIZE_BYTE |
| // 0x1 -> SIZE_HALFWORD |
| // 0x2 -> SIZE_WORD |
| #define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) |
| #define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB _u(3) |
| #define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB _u(2) |
| #define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) |
| #define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_HIGH_PRIORITY |
| // Description : HIGH_PRIORITY gives a channel preferential treatment in issue |
| // scheduling: in each scheduling round, all high priority |
| // channels are considered first, and then only a single low |
| // priority channel, before returning to the high priority |
| // channels. |
| // |
| // This only affects the order in which the DMA schedules |
| // channels. The DMA's bus priority is not changed. If the DMA is |
| // not saturated then a low priority channel will see no loss of |
| // throughput. |
| #define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) |
| #define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) |
| #define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) |
| #define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH4_CTRL_TRIG_EN |
| // Description : DMA Channel Enable. |
| // When 1, the channel will respond to triggering events, which |
| // will cause it to become BUSY and start transferring data. When |
| // 0, the channel will ignore triggers, stop issuing transfers, |
| // and pause the current transfer sequence (i.e. BUSY will remain |
| // high if already high) |
| #define DMA_CH4_CTRL_TRIG_EN_RESET _u(0x0) |
| #define DMA_CH4_CTRL_TRIG_EN_BITS _u(0x00000001) |
| #define DMA_CH4_CTRL_TRIG_EN_MSB _u(0) |
| #define DMA_CH4_CTRL_TRIG_EN_LSB _u(0) |
| #define DMA_CH4_CTRL_TRIG_EN_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH4_AL1_CTRL |
| // Description : Alias for channel 4 CTRL register |
| #define DMA_CH4_AL1_CTRL_OFFSET _u(0x00000110) |
| #define DMA_CH4_AL1_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH4_AL1_CTRL_RESET "-" |
| #define DMA_CH4_AL1_CTRL_MSB _u(31) |
| #define DMA_CH4_AL1_CTRL_LSB _u(0) |
| #define DMA_CH4_AL1_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH4_AL1_READ_ADDR |
| // Description : Alias for channel 4 READ_ADDR register |
| #define DMA_CH4_AL1_READ_ADDR_OFFSET _u(0x00000114) |
| #define DMA_CH4_AL1_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH4_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH4_AL1_READ_ADDR_MSB _u(31) |
| #define DMA_CH4_AL1_READ_ADDR_LSB _u(0) |
| #define DMA_CH4_AL1_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH4_AL1_WRITE_ADDR |
| // Description : Alias for channel 4 WRITE_ADDR register |
| #define DMA_CH4_AL1_WRITE_ADDR_OFFSET _u(0x00000118) |
| #define DMA_CH4_AL1_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH4_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH4_AL1_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH4_AL1_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH4_AL1_TRANS_COUNT_TRIG |
| // Description : Alias for channel 4 TRANS_COUNT register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000011c) |
| #define DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB _u(31) |
| #define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB _u(0) |
| #define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH4_AL2_CTRL |
| // Description : Alias for channel 4 CTRL register |
| #define DMA_CH4_AL2_CTRL_OFFSET _u(0x00000120) |
| #define DMA_CH4_AL2_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH4_AL2_CTRL_RESET "-" |
| #define DMA_CH4_AL2_CTRL_MSB _u(31) |
| #define DMA_CH4_AL2_CTRL_LSB _u(0) |
| #define DMA_CH4_AL2_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH4_AL2_TRANS_COUNT |
| // Description : Alias for channel 4 TRANS_COUNT register |
| #define DMA_CH4_AL2_TRANS_COUNT_OFFSET _u(0x00000124) |
| #define DMA_CH4_AL2_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH4_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH4_AL2_TRANS_COUNT_MSB _u(31) |
| #define DMA_CH4_AL2_TRANS_COUNT_LSB _u(0) |
| #define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH4_AL2_READ_ADDR |
| // Description : Alias for channel 4 READ_ADDR register |
| #define DMA_CH4_AL2_READ_ADDR_OFFSET _u(0x00000128) |
| #define DMA_CH4_AL2_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH4_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH4_AL2_READ_ADDR_MSB _u(31) |
| #define DMA_CH4_AL2_READ_ADDR_LSB _u(0) |
| #define DMA_CH4_AL2_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH4_AL2_WRITE_ADDR_TRIG |
| // Description : Alias for channel 4 WRITE_ADDR register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000012c) |
| #define DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB _u(31) |
| #define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB _u(0) |
| #define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH4_AL3_CTRL |
| // Description : Alias for channel 4 CTRL register |
| #define DMA_CH4_AL3_CTRL_OFFSET _u(0x00000130) |
| #define DMA_CH4_AL3_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH4_AL3_CTRL_RESET "-" |
| #define DMA_CH4_AL3_CTRL_MSB _u(31) |
| #define DMA_CH4_AL3_CTRL_LSB _u(0) |
| #define DMA_CH4_AL3_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH4_AL3_WRITE_ADDR |
| // Description : Alias for channel 4 WRITE_ADDR register |
| #define DMA_CH4_AL3_WRITE_ADDR_OFFSET _u(0x00000134) |
| #define DMA_CH4_AL3_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH4_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH4_AL3_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH4_AL3_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH4_AL3_TRANS_COUNT |
| // Description : Alias for channel 4 TRANS_COUNT register |
| #define DMA_CH4_AL3_TRANS_COUNT_OFFSET _u(0x00000138) |
| #define DMA_CH4_AL3_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH4_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH4_AL3_TRANS_COUNT_MSB _u(31) |
| #define DMA_CH4_AL3_TRANS_COUNT_LSB _u(0) |
| #define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH4_AL3_READ_ADDR_TRIG |
| // Description : Alias for channel 4 READ_ADDR register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000013c) |
| #define DMA_CH4_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH4_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH4_AL3_READ_ADDR_TRIG_MSB _u(31) |
| #define DMA_CH4_AL3_READ_ADDR_TRIG_LSB _u(0) |
| #define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH5_READ_ADDR |
| // Description : DMA Channel 5 Read Address pointer |
| // This register updates automatically each time a read completes. |
| // The current value is the next address to be read by this |
| // channel. |
| #define DMA_CH5_READ_ADDR_OFFSET _u(0x00000140) |
| #define DMA_CH5_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH5_READ_ADDR_RESET _u(0x00000000) |
| #define DMA_CH5_READ_ADDR_MSB _u(31) |
| #define DMA_CH5_READ_ADDR_LSB _u(0) |
| #define DMA_CH5_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH5_WRITE_ADDR |
| // Description : DMA Channel 5 Write Address pointer |
| // This register updates automatically each time a write |
| // completes. The current value is the next address to be written |
| // by this channel. |
| #define DMA_CH5_WRITE_ADDR_OFFSET _u(0x00000144) |
| #define DMA_CH5_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH5_WRITE_ADDR_RESET _u(0x00000000) |
| #define DMA_CH5_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH5_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH5_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH5_TRANS_COUNT |
| // Description : DMA Channel 5 Transfer Count |
| #define DMA_CH5_TRANS_COUNT_OFFSET _u(0x00000148) |
| #define DMA_CH5_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH5_TRANS_COUNT_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_TRANS_COUNT_MODE |
| // Description : When MODE is 0x0, the transfer count decrements with each |
| // transfer until 0, and then the channel triggers the next |
| // channel indicated by CTRL_CHAIN_TO. |
| // |
| // When MODE is 0x1, the transfer count decrements with each |
| // transfer until 0, and then the channel re-triggers itself, in |
| // addition to the trigger indicated by CTRL_CHAIN_TO. This is |
| // useful for e.g. an endless ring-buffer DMA with periodic |
| // interrupts. |
| // |
| // When MODE is 0xf, the transfer count does not decrement. The |
| // DMA channel performs an endless sequence of transfers, never |
| // triggering other channels or raising interrupts, until an ABORT |
| // is raised. |
| // |
| // All other values are reserved. |
| // 0x0 -> NORMAL |
| // 0x1 -> TRIGGER_SELF |
| // 0xf -> ENDLESS |
| #define DMA_CH5_TRANS_COUNT_MODE_RESET _u(0x0) |
| #define DMA_CH5_TRANS_COUNT_MODE_BITS _u(0xf0000000) |
| #define DMA_CH5_TRANS_COUNT_MODE_MSB _u(31) |
| #define DMA_CH5_TRANS_COUNT_MODE_LSB _u(28) |
| #define DMA_CH5_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH5_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) |
| #define DMA_CH5_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) |
| #define DMA_CH5_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_TRANS_COUNT_COUNT |
| // Description : 28-bit transfer count (256 million transfers maximum). |
| // |
| // Program the number of bus transfers a channel will perform |
| // before halting. Note that, if transfers are larger than one |
| // byte in size, this is not equal to the number of bytes |
| // transferred (see CTRL_DATA_SIZE). |
| // |
| // When the channel is active, reading this register shows the |
| // number of transfers remaining, updating automatically each time |
| // a write transfer completes. |
| // |
| // Writing this register sets the RELOAD value for the transfer |
| // counter. Each time this channel is triggered, the RELOAD value |
| // is copied into the live transfer counter. The channel can be |
| // started multiple times, and will perform the same number of |
| // transfers each time, as programmed by most recent write. |
| // |
| // The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT |
| // is used as a trigger, the written value is used immediately as |
| // the length of the new transfer sequence, as well as being |
| // written to RELOAD. |
| #define DMA_CH5_TRANS_COUNT_COUNT_RESET _u(0x0000000) |
| #define DMA_CH5_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) |
| #define DMA_CH5_TRANS_COUNT_COUNT_MSB _u(27) |
| #define DMA_CH5_TRANS_COUNT_COUNT_LSB _u(0) |
| #define DMA_CH5_TRANS_COUNT_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH5_CTRL_TRIG |
| // Description : DMA Channel 5 Control and Status |
| #define DMA_CH5_CTRL_TRIG_OFFSET _u(0x0000014c) |
| #define DMA_CH5_CTRL_TRIG_BITS _u(0xe7ffffff) |
| #define DMA_CH5_CTRL_TRIG_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_AHB_ERROR |
| // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel |
| // halts when it encounters any bus error, and always raises its |
| // channel IRQ flag. |
| #define DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) |
| #define DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB _u(31) |
| #define DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB _u(31) |
| #define DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_READ_ERROR |
| // Description : If 1, the channel received a read bus error. Write one to |
| // clear. |
| // READ_ADDR shows the approximate address where the bus error was |
| // encountered (will not be earlier, or more than 3 transfers |
| // later) |
| #define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) |
| #define DMA_CH5_CTRL_TRIG_READ_ERROR_MSB _u(30) |
| #define DMA_CH5_CTRL_TRIG_READ_ERROR_LSB _u(30) |
| #define DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_WRITE_ERROR |
| // Description : If 1, the channel received a write bus error. Write one to |
| // clear. |
| // WRITE_ADDR shows the approximate address where the bus error |
| // was encountered (will not be earlier, or more than 5 transfers |
| // later) |
| #define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) |
| #define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB _u(29) |
| #define DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB _u(29) |
| #define DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_BUSY |
| // Description : This flag goes high when the channel starts a new transfer |
| // sequence, and low when the last transfer of that sequence |
| // completes. Clearing EN while BUSY is high pauses the channel, |
| // and BUSY will stay high while paused. |
| // |
| // To terminate a sequence early (and clear the BUSY flag), see |
| // CHAN_ABORT. |
| #define DMA_CH5_CTRL_TRIG_BUSY_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_BUSY_BITS _u(0x04000000) |
| #define DMA_CH5_CTRL_TRIG_BUSY_MSB _u(26) |
| #define DMA_CH5_CTRL_TRIG_BUSY_LSB _u(26) |
| #define DMA_CH5_CTRL_TRIG_BUSY_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_SNIFF_EN |
| // Description : If 1, this channel's data transfers are visible to the sniff |
| // hardware, and each transfer will advance the state of the |
| // checksum. This only applies if the sniff hardware is enabled, |
| // and has this channel selected. |
| // |
| // This allows checksum to be enabled or disabled on a per- |
| // control- block basis. |
| #define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) |
| #define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB _u(25) |
| #define DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB _u(25) |
| #define DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_BSWAP |
| // Description : Apply byte-swap transformation to DMA data. |
| // For byte data, this has no effect. For halfword data, the two |
| // bytes of each halfword are swapped. For word data, the four |
| // bytes of each word are swapped to reverse order. |
| #define DMA_CH5_CTRL_TRIG_BSWAP_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_BSWAP_BITS _u(0x01000000) |
| #define DMA_CH5_CTRL_TRIG_BSWAP_MSB _u(24) |
| #define DMA_CH5_CTRL_TRIG_BSWAP_LSB _u(24) |
| #define DMA_CH5_CTRL_TRIG_BSWAP_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_IRQ_QUIET |
| // Description : In QUIET mode, the channel does not generate IRQs at the end of |
| // every transfer block. Instead, an IRQ is raised when NULL is |
| // written to a trigger register, indicating the end of a control |
| // block chain. |
| // |
| // This reduces the number of interrupts to be serviced by the CPU |
| // when transferring a DMA chain of many small control blocks. |
| #define DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) |
| #define DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB _u(23) |
| #define DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB _u(23) |
| #define DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_TREQ_SEL |
| // Description : Select a Transfer Request signal. |
| // The channel uses the transfer request signal to pace its data |
| // transfer rate. Sources for TREQ signals are internal (TIMERS) |
| // or external (DREQ, a Data Request from the system). |
| // 0x0 to 0x3a -> select DREQ n as TREQ |
| // 0x3b -> Select Timer 0 as TREQ |
| // 0x3c -> Select Timer 1 as TREQ |
| // 0x3d -> Select Timer 2 as TREQ (Optional) |
| // 0x3e -> Select Timer 3 as TREQ (Optional) |
| // 0x3f -> Permanent request, for unpaced transfers. |
| #define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) |
| #define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) |
| #define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(22) |
| #define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB _u(17) |
| #define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) |
| #define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) |
| #define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) |
| #define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) |
| #define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_CHAIN_TO |
| // Description : When this channel completes, it will trigger the channel |
| // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this |
| // channel)_. |
| // |
| // Note this field resets to 0, so channels 1 and above will chain |
| // to channel 0 by default. Set this field to avoid this |
| // behaviour. |
| #define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) |
| #define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB _u(16) |
| #define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB _u(13) |
| #define DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_RING_SEL |
| // Description : Select whether RING_SIZE applies to read or write addresses. |
| // If 0, read addresses are wrapped on a (1 << RING_SIZE) |
| // boundary. If 1, write addresses are wrapped. |
| #define DMA_CH5_CTRL_TRIG_RING_SEL_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) |
| #define DMA_CH5_CTRL_TRIG_RING_SEL_MSB _u(12) |
| #define DMA_CH5_CTRL_TRIG_RING_SEL_LSB _u(12) |
| #define DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_RING_SIZE |
| // Description : Size of address wrap region. If 0, don't wrap. For values n > |
| // 0, only the lower n bits of the address will change. This wraps |
| // the address on a (1 << n) byte boundary, facilitating access to |
| // naturally-aligned ring buffers. |
| // |
| // Ring sizes between 2 and 32768 bytes are possible. This can |
| // apply to either read or write addresses, based on value of |
| // RING_SEL. |
| // 0x0 -> RING_NONE |
| #define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) |
| #define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB _u(11) |
| #define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB _u(8) |
| #define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_INCR_WRITE_REV |
| // Description : If 1, and INCR_WRITE is 1, the write address is decremented |
| // rather than incremented with each transfer. |
| // |
| // If 1, and INCR_WRITE is 0, this otherwise-unused combination |
| // causes the write address to be incremented by twice the |
| // transfer size, i.e. skipping over alternate addresses. |
| #define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) |
| #define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) |
| #define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) |
| #define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_INCR_WRITE |
| // Description : If 1, the write address increments with each transfer. If 0, |
| // each write is directed to the same, initial address. |
| // |
| // Generally this should be disabled for memory-to-peripheral |
| // transfers. |
| #define DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) |
| #define DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB _u(6) |
| #define DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB _u(6) |
| #define DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_INCR_READ_REV |
| // Description : If 1, and INCR_READ is 1, the read address is decremented |
| // rather than incremented with each transfer. |
| // |
| // If 1, and INCR_READ is 0, this otherwise-unused combination |
| // causes the read address to be incremented by twice the transfer |
| // size, i.e. skipping over alternate addresses. |
| #define DMA_CH5_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) |
| #define DMA_CH5_CTRL_TRIG_INCR_READ_REV_MSB _u(5) |
| #define DMA_CH5_CTRL_TRIG_INCR_READ_REV_LSB _u(5) |
| #define DMA_CH5_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_INCR_READ |
| // Description : If 1, the read address increments with each transfer. If 0, |
| // each read is directed to the same, initial address. |
| // |
| // Generally this should be disabled for peripheral-to-memory |
| // transfers. |
| #define DMA_CH5_CTRL_TRIG_INCR_READ_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) |
| #define DMA_CH5_CTRL_TRIG_INCR_READ_MSB _u(4) |
| #define DMA_CH5_CTRL_TRIG_INCR_READ_LSB _u(4) |
| #define DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_DATA_SIZE |
| // Description : Set the size of each bus transfer (byte/halfword/word). |
| // READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) |
| // with each transfer. |
| // 0x0 -> SIZE_BYTE |
| // 0x1 -> SIZE_HALFWORD |
| // 0x2 -> SIZE_WORD |
| #define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) |
| #define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB _u(3) |
| #define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB _u(2) |
| #define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) |
| #define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_HIGH_PRIORITY |
| // Description : HIGH_PRIORITY gives a channel preferential treatment in issue |
| // scheduling: in each scheduling round, all high priority |
| // channels are considered first, and then only a single low |
| // priority channel, before returning to the high priority |
| // channels. |
| // |
| // This only affects the order in which the DMA schedules |
| // channels. The DMA's bus priority is not changed. If the DMA is |
| // not saturated then a low priority channel will see no loss of |
| // throughput. |
| #define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) |
| #define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) |
| #define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) |
| #define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH5_CTRL_TRIG_EN |
| // Description : DMA Channel Enable. |
| // When 1, the channel will respond to triggering events, which |
| // will cause it to become BUSY and start transferring data. When |
| // 0, the channel will ignore triggers, stop issuing transfers, |
| // and pause the current transfer sequence (i.e. BUSY will remain |
| // high if already high) |
| #define DMA_CH5_CTRL_TRIG_EN_RESET _u(0x0) |
| #define DMA_CH5_CTRL_TRIG_EN_BITS _u(0x00000001) |
| #define DMA_CH5_CTRL_TRIG_EN_MSB _u(0) |
| #define DMA_CH5_CTRL_TRIG_EN_LSB _u(0) |
| #define DMA_CH5_CTRL_TRIG_EN_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH5_AL1_CTRL |
| // Description : Alias for channel 5 CTRL register |
| #define DMA_CH5_AL1_CTRL_OFFSET _u(0x00000150) |
| #define DMA_CH5_AL1_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH5_AL1_CTRL_RESET "-" |
| #define DMA_CH5_AL1_CTRL_MSB _u(31) |
| #define DMA_CH5_AL1_CTRL_LSB _u(0) |
| #define DMA_CH5_AL1_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH5_AL1_READ_ADDR |
| // Description : Alias for channel 5 READ_ADDR register |
| #define DMA_CH5_AL1_READ_ADDR_OFFSET _u(0x00000154) |
| #define DMA_CH5_AL1_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH5_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH5_AL1_READ_ADDR_MSB _u(31) |
| #define DMA_CH5_AL1_READ_ADDR_LSB _u(0) |
| #define DMA_CH5_AL1_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH5_AL1_WRITE_ADDR |
| // Description : Alias for channel 5 WRITE_ADDR register |
| #define DMA_CH5_AL1_WRITE_ADDR_OFFSET _u(0x00000158) |
| #define DMA_CH5_AL1_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH5_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH5_AL1_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH5_AL1_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH5_AL1_TRANS_COUNT_TRIG |
| // Description : Alias for channel 5 TRANS_COUNT register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000015c) |
| #define DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB _u(31) |
| #define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB _u(0) |
| #define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH5_AL2_CTRL |
| // Description : Alias for channel 5 CTRL register |
| #define DMA_CH5_AL2_CTRL_OFFSET _u(0x00000160) |
| #define DMA_CH5_AL2_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH5_AL2_CTRL_RESET "-" |
| #define DMA_CH5_AL2_CTRL_MSB _u(31) |
| #define DMA_CH5_AL2_CTRL_LSB _u(0) |
| #define DMA_CH5_AL2_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH5_AL2_TRANS_COUNT |
| // Description : Alias for channel 5 TRANS_COUNT register |
| #define DMA_CH5_AL2_TRANS_COUNT_OFFSET _u(0x00000164) |
| #define DMA_CH5_AL2_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH5_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH5_AL2_TRANS_COUNT_MSB _u(31) |
| #define DMA_CH5_AL2_TRANS_COUNT_LSB _u(0) |
| #define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH5_AL2_READ_ADDR |
| // Description : Alias for channel 5 READ_ADDR register |
| #define DMA_CH5_AL2_READ_ADDR_OFFSET _u(0x00000168) |
| #define DMA_CH5_AL2_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH5_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH5_AL2_READ_ADDR_MSB _u(31) |
| #define DMA_CH5_AL2_READ_ADDR_LSB _u(0) |
| #define DMA_CH5_AL2_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH5_AL2_WRITE_ADDR_TRIG |
| // Description : Alias for channel 5 WRITE_ADDR register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000016c) |
| #define DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB _u(31) |
| #define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB _u(0) |
| #define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH5_AL3_CTRL |
| // Description : Alias for channel 5 CTRL register |
| #define DMA_CH5_AL3_CTRL_OFFSET _u(0x00000170) |
| #define DMA_CH5_AL3_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH5_AL3_CTRL_RESET "-" |
| #define DMA_CH5_AL3_CTRL_MSB _u(31) |
| #define DMA_CH5_AL3_CTRL_LSB _u(0) |
| #define DMA_CH5_AL3_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH5_AL3_WRITE_ADDR |
| // Description : Alias for channel 5 WRITE_ADDR register |
| #define DMA_CH5_AL3_WRITE_ADDR_OFFSET _u(0x00000174) |
| #define DMA_CH5_AL3_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH5_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH5_AL3_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH5_AL3_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH5_AL3_TRANS_COUNT |
| // Description : Alias for channel 5 TRANS_COUNT register |
| #define DMA_CH5_AL3_TRANS_COUNT_OFFSET _u(0x00000178) |
| #define DMA_CH5_AL3_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH5_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH5_AL3_TRANS_COUNT_MSB _u(31) |
| #define DMA_CH5_AL3_TRANS_COUNT_LSB _u(0) |
| #define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH5_AL3_READ_ADDR_TRIG |
| // Description : Alias for channel 5 READ_ADDR register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000017c) |
| #define DMA_CH5_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH5_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH5_AL3_READ_ADDR_TRIG_MSB _u(31) |
| #define DMA_CH5_AL3_READ_ADDR_TRIG_LSB _u(0) |
| #define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH6_READ_ADDR |
| // Description : DMA Channel 6 Read Address pointer |
| // This register updates automatically each time a read completes. |
| // The current value is the next address to be read by this |
| // channel. |
| #define DMA_CH6_READ_ADDR_OFFSET _u(0x00000180) |
| #define DMA_CH6_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH6_READ_ADDR_RESET _u(0x00000000) |
| #define DMA_CH6_READ_ADDR_MSB _u(31) |
| #define DMA_CH6_READ_ADDR_LSB _u(0) |
| #define DMA_CH6_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH6_WRITE_ADDR |
| // Description : DMA Channel 6 Write Address pointer |
| // This register updates automatically each time a write |
| // completes. The current value is the next address to be written |
| // by this channel. |
| #define DMA_CH6_WRITE_ADDR_OFFSET _u(0x00000184) |
| #define DMA_CH6_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH6_WRITE_ADDR_RESET _u(0x00000000) |
| #define DMA_CH6_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH6_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH6_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH6_TRANS_COUNT |
| // Description : DMA Channel 6 Transfer Count |
| #define DMA_CH6_TRANS_COUNT_OFFSET _u(0x00000188) |
| #define DMA_CH6_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH6_TRANS_COUNT_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_TRANS_COUNT_MODE |
| // Description : When MODE is 0x0, the transfer count decrements with each |
| // transfer until 0, and then the channel triggers the next |
| // channel indicated by CTRL_CHAIN_TO. |
| // |
| // When MODE is 0x1, the transfer count decrements with each |
| // transfer until 0, and then the channel re-triggers itself, in |
| // addition to the trigger indicated by CTRL_CHAIN_TO. This is |
| // useful for e.g. an endless ring-buffer DMA with periodic |
| // interrupts. |
| // |
| // When MODE is 0xf, the transfer count does not decrement. The |
| // DMA channel performs an endless sequence of transfers, never |
| // triggering other channels or raising interrupts, until an ABORT |
| // is raised. |
| // |
| // All other values are reserved. |
| // 0x0 -> NORMAL |
| // 0x1 -> TRIGGER_SELF |
| // 0xf -> ENDLESS |
| #define DMA_CH6_TRANS_COUNT_MODE_RESET _u(0x0) |
| #define DMA_CH6_TRANS_COUNT_MODE_BITS _u(0xf0000000) |
| #define DMA_CH6_TRANS_COUNT_MODE_MSB _u(31) |
| #define DMA_CH6_TRANS_COUNT_MODE_LSB _u(28) |
| #define DMA_CH6_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH6_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) |
| #define DMA_CH6_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) |
| #define DMA_CH6_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_TRANS_COUNT_COUNT |
| // Description : 28-bit transfer count (256 million transfers maximum). |
| // |
| // Program the number of bus transfers a channel will perform |
| // before halting. Note that, if transfers are larger than one |
| // byte in size, this is not equal to the number of bytes |
| // transferred (see CTRL_DATA_SIZE). |
| // |
| // When the channel is active, reading this register shows the |
| // number of transfers remaining, updating automatically each time |
| // a write transfer completes. |
| // |
| // Writing this register sets the RELOAD value for the transfer |
| // counter. Each time this channel is triggered, the RELOAD value |
| // is copied into the live transfer counter. The channel can be |
| // started multiple times, and will perform the same number of |
| // transfers each time, as programmed by most recent write. |
| // |
| // The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT |
| // is used as a trigger, the written value is used immediately as |
| // the length of the new transfer sequence, as well as being |
| // written to RELOAD. |
| #define DMA_CH6_TRANS_COUNT_COUNT_RESET _u(0x0000000) |
| #define DMA_CH6_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) |
| #define DMA_CH6_TRANS_COUNT_COUNT_MSB _u(27) |
| #define DMA_CH6_TRANS_COUNT_COUNT_LSB _u(0) |
| #define DMA_CH6_TRANS_COUNT_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH6_CTRL_TRIG |
| // Description : DMA Channel 6 Control and Status |
| #define DMA_CH6_CTRL_TRIG_OFFSET _u(0x0000018c) |
| #define DMA_CH6_CTRL_TRIG_BITS _u(0xe7ffffff) |
| #define DMA_CH6_CTRL_TRIG_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_AHB_ERROR |
| // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel |
| // halts when it encounters any bus error, and always raises its |
| // channel IRQ flag. |
| #define DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) |
| #define DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB _u(31) |
| #define DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB _u(31) |
| #define DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_READ_ERROR |
| // Description : If 1, the channel received a read bus error. Write one to |
| // clear. |
| // READ_ADDR shows the approximate address where the bus error was |
| // encountered (will not be earlier, or more than 3 transfers |
| // later) |
| #define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) |
| #define DMA_CH6_CTRL_TRIG_READ_ERROR_MSB _u(30) |
| #define DMA_CH6_CTRL_TRIG_READ_ERROR_LSB _u(30) |
| #define DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_WRITE_ERROR |
| // Description : If 1, the channel received a write bus error. Write one to |
| // clear. |
| // WRITE_ADDR shows the approximate address where the bus error |
| // was encountered (will not be earlier, or more than 5 transfers |
| // later) |
| #define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) |
| #define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB _u(29) |
| #define DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB _u(29) |
| #define DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_BUSY |
| // Description : This flag goes high when the channel starts a new transfer |
| // sequence, and low when the last transfer of that sequence |
| // completes. Clearing EN while BUSY is high pauses the channel, |
| // and BUSY will stay high while paused. |
| // |
| // To terminate a sequence early (and clear the BUSY flag), see |
| // CHAN_ABORT. |
| #define DMA_CH6_CTRL_TRIG_BUSY_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_BUSY_BITS _u(0x04000000) |
| #define DMA_CH6_CTRL_TRIG_BUSY_MSB _u(26) |
| #define DMA_CH6_CTRL_TRIG_BUSY_LSB _u(26) |
| #define DMA_CH6_CTRL_TRIG_BUSY_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_SNIFF_EN |
| // Description : If 1, this channel's data transfers are visible to the sniff |
| // hardware, and each transfer will advance the state of the |
| // checksum. This only applies if the sniff hardware is enabled, |
| // and has this channel selected. |
| // |
| // This allows checksum to be enabled or disabled on a per- |
| // control- block basis. |
| #define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) |
| #define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB _u(25) |
| #define DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB _u(25) |
| #define DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_BSWAP |
| // Description : Apply byte-swap transformation to DMA data. |
| // For byte data, this has no effect. For halfword data, the two |
| // bytes of each halfword are swapped. For word data, the four |
| // bytes of each word are swapped to reverse order. |
| #define DMA_CH6_CTRL_TRIG_BSWAP_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_BSWAP_BITS _u(0x01000000) |
| #define DMA_CH6_CTRL_TRIG_BSWAP_MSB _u(24) |
| #define DMA_CH6_CTRL_TRIG_BSWAP_LSB _u(24) |
| #define DMA_CH6_CTRL_TRIG_BSWAP_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_IRQ_QUIET |
| // Description : In QUIET mode, the channel does not generate IRQs at the end of |
| // every transfer block. Instead, an IRQ is raised when NULL is |
| // written to a trigger register, indicating the end of a control |
| // block chain. |
| // |
| // This reduces the number of interrupts to be serviced by the CPU |
| // when transferring a DMA chain of many small control blocks. |
| #define DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) |
| #define DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB _u(23) |
| #define DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB _u(23) |
| #define DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_TREQ_SEL |
| // Description : Select a Transfer Request signal. |
| // The channel uses the transfer request signal to pace its data |
| // transfer rate. Sources for TREQ signals are internal (TIMERS) |
| // or external (DREQ, a Data Request from the system). |
| // 0x0 to 0x3a -> select DREQ n as TREQ |
| // 0x3b -> Select Timer 0 as TREQ |
| // 0x3c -> Select Timer 1 as TREQ |
| // 0x3d -> Select Timer 2 as TREQ (Optional) |
| // 0x3e -> Select Timer 3 as TREQ (Optional) |
| // 0x3f -> Permanent request, for unpaced transfers. |
| #define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) |
| #define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) |
| #define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(22) |
| #define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB _u(17) |
| #define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) |
| #define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) |
| #define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) |
| #define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) |
| #define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_CHAIN_TO |
| // Description : When this channel completes, it will trigger the channel |
| // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this |
| // channel)_. |
| // |
| // Note this field resets to 0, so channels 1 and above will chain |
| // to channel 0 by default. Set this field to avoid this |
| // behaviour. |
| #define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) |
| #define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB _u(16) |
| #define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB _u(13) |
| #define DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_RING_SEL |
| // Description : Select whether RING_SIZE applies to read or write addresses. |
| // If 0, read addresses are wrapped on a (1 << RING_SIZE) |
| // boundary. If 1, write addresses are wrapped. |
| #define DMA_CH6_CTRL_TRIG_RING_SEL_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) |
| #define DMA_CH6_CTRL_TRIG_RING_SEL_MSB _u(12) |
| #define DMA_CH6_CTRL_TRIG_RING_SEL_LSB _u(12) |
| #define DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_RING_SIZE |
| // Description : Size of address wrap region. If 0, don't wrap. For values n > |
| // 0, only the lower n bits of the address will change. This wraps |
| // the address on a (1 << n) byte boundary, facilitating access to |
| // naturally-aligned ring buffers. |
| // |
| // Ring sizes between 2 and 32768 bytes are possible. This can |
| // apply to either read or write addresses, based on value of |
| // RING_SEL. |
| // 0x0 -> RING_NONE |
| #define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) |
| #define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB _u(11) |
| #define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB _u(8) |
| #define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_INCR_WRITE_REV |
| // Description : If 1, and INCR_WRITE is 1, the write address is decremented |
| // rather than incremented with each transfer. |
| // |
| // If 1, and INCR_WRITE is 0, this otherwise-unused combination |
| // causes the write address to be incremented by twice the |
| // transfer size, i.e. skipping over alternate addresses. |
| #define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) |
| #define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) |
| #define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) |
| #define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_INCR_WRITE |
| // Description : If 1, the write address increments with each transfer. If 0, |
| // each write is directed to the same, initial address. |
| // |
| // Generally this should be disabled for memory-to-peripheral |
| // transfers. |
| #define DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) |
| #define DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB _u(6) |
| #define DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB _u(6) |
| #define DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_INCR_READ_REV |
| // Description : If 1, and INCR_READ is 1, the read address is decremented |
| // rather than incremented with each transfer. |
| // |
| // If 1, and INCR_READ is 0, this otherwise-unused combination |
| // causes the read address to be incremented by twice the transfer |
| // size, i.e. skipping over alternate addresses. |
| #define DMA_CH6_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) |
| #define DMA_CH6_CTRL_TRIG_INCR_READ_REV_MSB _u(5) |
| #define DMA_CH6_CTRL_TRIG_INCR_READ_REV_LSB _u(5) |
| #define DMA_CH6_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_INCR_READ |
| // Description : If 1, the read address increments with each transfer. If 0, |
| // each read is directed to the same, initial address. |
| // |
| // Generally this should be disabled for peripheral-to-memory |
| // transfers. |
| #define DMA_CH6_CTRL_TRIG_INCR_READ_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) |
| #define DMA_CH6_CTRL_TRIG_INCR_READ_MSB _u(4) |
| #define DMA_CH6_CTRL_TRIG_INCR_READ_LSB _u(4) |
| #define DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_DATA_SIZE |
| // Description : Set the size of each bus transfer (byte/halfword/word). |
| // READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) |
| // with each transfer. |
| // 0x0 -> SIZE_BYTE |
| // 0x1 -> SIZE_HALFWORD |
| // 0x2 -> SIZE_WORD |
| #define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) |
| #define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB _u(3) |
| #define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB _u(2) |
| #define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) |
| #define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_HIGH_PRIORITY |
| // Description : HIGH_PRIORITY gives a channel preferential treatment in issue |
| // scheduling: in each scheduling round, all high priority |
| // channels are considered first, and then only a single low |
| // priority channel, before returning to the high priority |
| // channels. |
| // |
| // This only affects the order in which the DMA schedules |
| // channels. The DMA's bus priority is not changed. If the DMA is |
| // not saturated then a low priority channel will see no loss of |
| // throughput. |
| #define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) |
| #define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) |
| #define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) |
| #define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH6_CTRL_TRIG_EN |
| // Description : DMA Channel Enable. |
| // When 1, the channel will respond to triggering events, which |
| // will cause it to become BUSY and start transferring data. When |
| // 0, the channel will ignore triggers, stop issuing transfers, |
| // and pause the current transfer sequence (i.e. BUSY will remain |
| // high if already high) |
| #define DMA_CH6_CTRL_TRIG_EN_RESET _u(0x0) |
| #define DMA_CH6_CTRL_TRIG_EN_BITS _u(0x00000001) |
| #define DMA_CH6_CTRL_TRIG_EN_MSB _u(0) |
| #define DMA_CH6_CTRL_TRIG_EN_LSB _u(0) |
| #define DMA_CH6_CTRL_TRIG_EN_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH6_AL1_CTRL |
| // Description : Alias for channel 6 CTRL register |
| #define DMA_CH6_AL1_CTRL_OFFSET _u(0x00000190) |
| #define DMA_CH6_AL1_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH6_AL1_CTRL_RESET "-" |
| #define DMA_CH6_AL1_CTRL_MSB _u(31) |
| #define DMA_CH6_AL1_CTRL_LSB _u(0) |
| #define DMA_CH6_AL1_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH6_AL1_READ_ADDR |
| // Description : Alias for channel 6 READ_ADDR register |
| #define DMA_CH6_AL1_READ_ADDR_OFFSET _u(0x00000194) |
| #define DMA_CH6_AL1_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH6_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH6_AL1_READ_ADDR_MSB _u(31) |
| #define DMA_CH6_AL1_READ_ADDR_LSB _u(0) |
| #define DMA_CH6_AL1_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH6_AL1_WRITE_ADDR |
| // Description : Alias for channel 6 WRITE_ADDR register |
| #define DMA_CH6_AL1_WRITE_ADDR_OFFSET _u(0x00000198) |
| #define DMA_CH6_AL1_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH6_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH6_AL1_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH6_AL1_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH6_AL1_TRANS_COUNT_TRIG |
| // Description : Alias for channel 6 TRANS_COUNT register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000019c) |
| #define DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB _u(31) |
| #define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB _u(0) |
| #define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH6_AL2_CTRL |
| // Description : Alias for channel 6 CTRL register |
| #define DMA_CH6_AL2_CTRL_OFFSET _u(0x000001a0) |
| #define DMA_CH6_AL2_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH6_AL2_CTRL_RESET "-" |
| #define DMA_CH6_AL2_CTRL_MSB _u(31) |
| #define DMA_CH6_AL2_CTRL_LSB _u(0) |
| #define DMA_CH6_AL2_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH6_AL2_TRANS_COUNT |
| // Description : Alias for channel 6 TRANS_COUNT register |
| #define DMA_CH6_AL2_TRANS_COUNT_OFFSET _u(0x000001a4) |
| #define DMA_CH6_AL2_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH6_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH6_AL2_TRANS_COUNT_MSB _u(31) |
| #define DMA_CH6_AL2_TRANS_COUNT_LSB _u(0) |
| #define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH6_AL2_READ_ADDR |
| // Description : Alias for channel 6 READ_ADDR register |
| #define DMA_CH6_AL2_READ_ADDR_OFFSET _u(0x000001a8) |
| #define DMA_CH6_AL2_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH6_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH6_AL2_READ_ADDR_MSB _u(31) |
| #define DMA_CH6_AL2_READ_ADDR_LSB _u(0) |
| #define DMA_CH6_AL2_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH6_AL2_WRITE_ADDR_TRIG |
| // Description : Alias for channel 6 WRITE_ADDR register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ac) |
| #define DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB _u(31) |
| #define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB _u(0) |
| #define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH6_AL3_CTRL |
| // Description : Alias for channel 6 CTRL register |
| #define DMA_CH6_AL3_CTRL_OFFSET _u(0x000001b0) |
| #define DMA_CH6_AL3_CTRL_BITS _u(0xffffffff) |
| #define DMA_CH6_AL3_CTRL_RESET "-" |
| #define DMA_CH6_AL3_CTRL_MSB _u(31) |
| #define DMA_CH6_AL3_CTRL_LSB _u(0) |
| #define DMA_CH6_AL3_CTRL_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH6_AL3_WRITE_ADDR |
| // Description : Alias for channel 6 WRITE_ADDR register |
| #define DMA_CH6_AL3_WRITE_ADDR_OFFSET _u(0x000001b4) |
| #define DMA_CH6_AL3_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH6_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH6_AL3_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH6_AL3_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH6_AL3_TRANS_COUNT |
| // Description : Alias for channel 6 TRANS_COUNT register |
| #define DMA_CH6_AL3_TRANS_COUNT_OFFSET _u(0x000001b8) |
| #define DMA_CH6_AL3_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH6_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH6_AL3_TRANS_COUNT_MSB _u(31) |
| #define DMA_CH6_AL3_TRANS_COUNT_LSB _u(0) |
| #define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH6_AL3_READ_ADDR_TRIG |
| // Description : Alias for channel 6 READ_ADDR register |
| // This is a trigger register (0xc). Writing a nonzero value will |
| // reload the channel counter and start the channel. |
| #define DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001bc) |
| #define DMA_CH6_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) |
| #define DMA_CH6_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH6_AL3_READ_ADDR_TRIG_MSB _u(31) |
| #define DMA_CH6_AL3_READ_ADDR_TRIG_LSB _u(0) |
| #define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH7_READ_ADDR |
| // Description : DMA Channel 7 Read Address pointer |
| // This register updates automatically each time a read completes. |
| // The current value is the next address to be read by this |
| // channel. |
| #define DMA_CH7_READ_ADDR_OFFSET _u(0x000001c0) |
| #define DMA_CH7_READ_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH7_READ_ADDR_RESET _u(0x00000000) |
| #define DMA_CH7_READ_ADDR_MSB _u(31) |
| #define DMA_CH7_READ_ADDR_LSB _u(0) |
| #define DMA_CH7_READ_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH7_WRITE_ADDR |
| // Description : DMA Channel 7 Write Address pointer |
| // This register updates automatically each time a write |
| // completes. The current value is the next address to be written |
| // by this channel. |
| #define DMA_CH7_WRITE_ADDR_OFFSET _u(0x000001c4) |
| #define DMA_CH7_WRITE_ADDR_BITS _u(0xffffffff) |
| #define DMA_CH7_WRITE_ADDR_RESET _u(0x00000000) |
| #define DMA_CH7_WRITE_ADDR_MSB _u(31) |
| #define DMA_CH7_WRITE_ADDR_LSB _u(0) |
| #define DMA_CH7_WRITE_ADDR_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH7_TRANS_COUNT |
| // Description : DMA Channel 7 Transfer Count |
| #define DMA_CH7_TRANS_COUNT_OFFSET _u(0x000001c8) |
| #define DMA_CH7_TRANS_COUNT_BITS _u(0xffffffff) |
| #define DMA_CH7_TRANS_COUNT_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH7_TRANS_COUNT_MODE |
| // Description : When MODE is 0x0, the transfer count decrements with each |
| // transfer until 0, and then the channel triggers the next |
| // channel indicated by CTRL_CHAIN_TO. |
| // |
| // When MODE is 0x1, the transfer count decrements with each |
| // transfer until 0, and then the channel re-triggers itself, in |
| // addition to the trigger indicated by CTRL_CHAIN_TO. This is |
| // useful for e.g. an endless ring-buffer DMA with periodic |
| // interrupts. |
| // |
| // When MODE is 0xf, the transfer count does not decrement. The |
| // DMA channel performs an endless sequence of transfers, never |
| // triggering other channels or raising interrupts, until an ABORT |
| // is raised. |
| // |
| // All other values are reserved. |
| // 0x0 -> NORMAL |
| // 0x1 -> TRIGGER_SELF |
| // 0xf -> ENDLESS |
| #define DMA_CH7_TRANS_COUNT_MODE_RESET _u(0x0) |
| #define DMA_CH7_TRANS_COUNT_MODE_BITS _u(0xf0000000) |
| #define DMA_CH7_TRANS_COUNT_MODE_MSB _u(31) |
| #define DMA_CH7_TRANS_COUNT_MODE_LSB _u(28) |
| #define DMA_CH7_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH7_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) |
| #define DMA_CH7_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) |
| #define DMA_CH7_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH7_TRANS_COUNT_COUNT |
| // Description : 28-bit transfer count (256 million transfers maximum). |
| // |
| // Program the number of bus transfers a channel will perform |
| // before halting. Note that, if transfers are larger than one |
| // byte in size, this is not equal to the number of bytes |
| // transferred (see CTRL_DATA_SIZE). |
| // |
| // When the channel is active, reading this register shows the |
| // number of transfers remaining, updating automatically each time |
| // a write transfer completes. |
| // |
| // Writing this register sets the RELOAD value for the transfer |
| // counter. Each time this channel is triggered, the RELOAD value |
| // is copied into the live transfer counter. The channel can be |
| // started multiple times, and will perform the same number of |
| // transfers each time, as programmed by most recent write. |
| // |
| // The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT |
| // is used as a trigger, the written value is used immediately as |
| // the length of the new transfer sequence, as well as being |
| // written to RELOAD. |
| #define DMA_CH7_TRANS_COUNT_COUNT_RESET _u(0x0000000) |
| #define DMA_CH7_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) |
| #define DMA_CH7_TRANS_COUNT_COUNT_MSB _u(27) |
| #define DMA_CH7_TRANS_COUNT_COUNT_LSB _u(0) |
| #define DMA_CH7_TRANS_COUNT_COUNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : DMA_CH7_CTRL_TRIG |
| // Description : DMA Channel 7 Control and Status |
| #define DMA_CH7_CTRL_TRIG_OFFSET _u(0x000001cc) |
| #define DMA_CH7_CTRL_TRIG_BITS _u(0xe7ffffff) |
| #define DMA_CH7_CTRL_TRIG_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH7_CTRL_TRIG_AHB_ERROR |
| // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel |
| // halts when it encounters any bus error, and always raises its |
| // channel IRQ flag. |
| #define DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) |
| #define DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) |
| #define DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB _u(31) |
| #define DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB _u(31) |
| #define DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH7_CTRL_TRIG_READ_ERROR |
| // Description : If 1, the channel received a read bus error. Write one to |
| // clear. |
| // READ_ADDR shows the approximate address where the bus error was |
| // encountered (will not be earlier, or more than 3 transfers |
| // later) |
| #define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET _u(0x0) |
| #define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) |
| #define DMA_CH7_CTRL_TRIG_READ_ERROR_MSB _u(30) |
| #define DMA_CH7_CTRL_TRIG_READ_ERROR_LSB _u(30) |
| #define DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH7_CTRL_TRIG_WRITE_ERROR |
| // Description : If 1, the channel received a write bus error. Write one to |
| // clear. |
| // WRITE_ADDR shows the approximate address where the bus error |
| // was encountered (will not be earlier, or more than 5 transfers |
| // later) |
| #define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) |
| #define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) |
| #define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB _u(29) |
| #define DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB _u(29) |
| #define DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH7_CTRL_TRIG_BUSY |
| // Description : This flag goes high when the channel starts a new transfer |
| // sequence, and low when the last transfer of that sequence |
| // completes. Clearing EN while BUSY is high pauses the channel, |
| // and BUSY will stay high while paused. |
| // |
| // To terminate a sequence early (and clear the BUSY flag), see |
| // CHAN_ABORT. |
| #define DMA_CH7_CTRL_TRIG_BUSY_RESET _u(0x0) |
| #define DMA_CH7_CTRL_TRIG_BUSY_BITS _u(0x04000000) |
| #define DMA_CH7_CTRL_TRIG_BUSY_MSB _u(26) |
| #define DMA_CH7_CTRL_TRIG_BUSY_LSB _u(26) |
| #define DMA_CH7_CTRL_TRIG_BUSY_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH7_CTRL_TRIG_SNIFF_EN |
| // Description : If 1, this channel's data transfers are visible to the sniff |
| // hardware, and each transfer will advance the state of the |
| // checksum. This only applies if the sniff hardware is enabled, |
| // and has this channel selected. |
| // |
| // This allows checksum to be enabled or disabled on a per- |
| // control- block basis. |
| #define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) |
| #define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) |
| #define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB _u(25) |
| #define DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB _u(25) |
| #define DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH7_CTRL_TRIG_BSWAP |
| // Description : Apply byte-swap transformation to DMA data. |
| // For byte data, this has no effect. For halfword data, the two |
| // bytes of each halfword are swapped. For word data, the four |
| // bytes of each word are swapped to reverse order. |
| #define DMA_CH7_CTRL_TRIG_BSWAP_RESET _u(0x0) |
| #define DMA_CH7_CTRL_TRIG_BSWAP_BITS _u(0x01000000) |
| #define DMA_CH7_CTRL_TRIG_BSWAP_MSB _u(24) |
| #define DMA_CH7_CTRL_TRIG_BSWAP_LSB _u(24) |
| #define DMA_CH7_CTRL_TRIG_BSWAP_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH7_CTRL_TRIG_IRQ_QUIET |
| // Description : In QUIET mode, the channel does not generate IRQs at the end of |
| // every transfer block. Instead, an IRQ is raised when NULL is |
| // written to a trigger register, indicating the end of a control |
| // block chain. |
| // |
| // This reduces the number of interrupts to be serviced by the CPU |
| // when transferring a DMA chain of many small control blocks. |
| #define DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) |
| #define DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) |
| #define DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB _u(23) |
| #define DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB _u(23) |
| #define DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH7_CTRL_TRIG_TREQ_SEL |
| // Description : Select a Transfer Request signal. |
| // The channel uses the transfer request signal to pace its data |
| // transfer rate. Sources for TREQ signals are internal (TIMERS) |
| // or external (DREQ, a Data Request from the system). |
| // 0x0 to 0x3a -> select DREQ n as TREQ |
| // 0x3b -> Select Timer 0 as TREQ |
| // 0x3c -> Select Timer 1 as TREQ |
| // 0x3d -> Select Timer 2 as TREQ (Optional) |
| // 0x3e -> Select Timer 3 as TREQ (Optional) |
| // 0x3f -> Permanent request, for unpaced transfers. |
| #define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) |
| #define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) |
| #define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(22) |
| #define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB _u(17) |
| #define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) |
| #define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) |
| #define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) |
| #define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) |
| #define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH7_CTRL_TRIG_CHAIN_TO |
| // Description : When this channel completes, it will trigger the channel |
| // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this |
| // channel)_. |
| // |
| // Note this field resets to 0, so channels 1 and above will chain |
| // to channel 0 by default. Set this field to avoid this |
| // behaviour. |
| #define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) |
| #define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) |
| #define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB _u(16) |
| #define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB _u(13) |
| #define DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : DMA_CH7_CTRL_TRIG_RING_SEL |
| // Description : Select whether RING_SIZE applies to read or write addresses. |
