| // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT |
| |
| /** |
| * Copyright (c) 2024 Raspberry Pi Ltd. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| // ============================================================================= |
| // Register block : IO_BANK0 |
| // Version : 1 |
| // Bus type : apb |
| // ============================================================================= |
| #ifndef _HARDWARE_REGS_IO_BANK0_H |
| #define _HARDWARE_REGS_IO_BANK0_H |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO0_STATUS |
| #define IO_BANK0_GPIO0_STATUS_OFFSET _u(0x00000000) |
| #define IO_BANK0_GPIO0_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO0_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO0_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO0_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO0_CTRL |
| #define IO_BANK0_GPIO0_CTRL_OFFSET _u(0x00000004) |
| #define IO_BANK0_GPIO0_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO0_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO0_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO0_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO0_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO0_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO0_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x00 -> jtag_tck |
| // 0x01 -> spi0_rx |
| // 0x02 -> uart0_tx |
| // 0x03 -> i2c0_sda |
| // 0x04 -> pwm_a_0 |
| // 0x05 -> siob_proc_0 |
| // 0x06 -> pio0_0 |
| // 0x07 -> pio1_0 |
| // 0x08 -> pio2_0 |
| // 0x09 -> xip_ss_n_1 |
| // 0x0a -> usb_muxing_overcurr_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK _u(0x00) |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIOB_PROC_0 _u(0x05) |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _u(0x06) |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _u(0x07) |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO2_0 _u(0x08) |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09) |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) |
| #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO1_STATUS |
| #define IO_BANK0_GPIO1_STATUS_OFFSET _u(0x00000008) |
| #define IO_BANK0_GPIO1_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO1_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO1_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO1_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO1_CTRL |
| #define IO_BANK0_GPIO1_CTRL_OFFSET _u(0x0000000c) |
| #define IO_BANK0_GPIO1_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO1_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO1_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO1_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO1_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO1_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO1_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x00 -> jtag_tms |
| // 0x01 -> spi0_ss_n |
| // 0x02 -> uart0_rx |
| // 0x03 -> i2c0_scl |
| // 0x04 -> pwm_b_0 |
| // 0x05 -> siob_proc_1 |
| // 0x06 -> pio0_1 |
| // 0x07 -> pio1_1 |
| // 0x08 -> pio2_1 |
| // 0x09 -> coresight_traceclk |
| // 0x0a -> usb_muxing_vbus_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS _u(0x00) |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIOB_PROC_1 _u(0x05) |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _u(0x06) |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _u(0x07) |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO2_1 _u(0x08) |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACECLK _u(0x09) |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) |
| #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO2_STATUS |
| #define IO_BANK0_GPIO2_STATUS_OFFSET _u(0x00000010) |
| #define IO_BANK0_GPIO2_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO2_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO2_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO2_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO2_CTRL |
| #define IO_BANK0_GPIO2_CTRL_OFFSET _u(0x00000014) |
| #define IO_BANK0_GPIO2_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO2_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO2_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO2_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO2_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO2_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO2_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x00 -> jtag_tdi |
| // 0x01 -> spi0_sclk |
| // 0x02 -> uart0_cts |
| // 0x03 -> i2c1_sda |
| // 0x04 -> pwm_a_1 |
| // 0x05 -> siob_proc_2 |
| // 0x06 -> pio0_2 |
| // 0x07 -> pio1_2 |
| // 0x08 -> pio2_2 |
| // 0x09 -> coresight_tracedata_0 |
| // 0x0a -> usb_muxing_vbus_en |
| // 0x0b -> uart0_tx |
| // 0x1f -> null |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI _u(0x00) |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIOB_PROC_2 _u(0x05) |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _u(0x06) |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _u(0x07) |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO2_2 _u(0x08) |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_0 _u(0x09) |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) |
| #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO3_STATUS |
| #define IO_BANK0_GPIO3_STATUS_OFFSET _u(0x00000018) |
| #define IO_BANK0_GPIO3_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO3_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO3_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO3_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO3_CTRL |
| #define IO_BANK0_GPIO3_CTRL_OFFSET _u(0x0000001c) |
| #define IO_BANK0_GPIO3_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO3_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO3_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO3_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO3_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO3_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO3_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x00 -> jtag_tdo |
| // 0x01 -> spi0_tx |
| // 0x02 -> uart0_rts |
| // 0x03 -> i2c1_scl |
| // 0x04 -> pwm_b_1 |
| // 0x05 -> siob_proc_3 |
| // 0x06 -> pio0_3 |
| // 0x07 -> pio1_3 |
| // 0x08 -> pio2_3 |
| // 0x09 -> coresight_tracedata_1 |
| // 0x0a -> usb_muxing_overcurr_detect |
| // 0x0b -> uart0_rx |
| // 0x1f -> null |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO _u(0x00) |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIOB_PROC_3 _u(0x05) |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _u(0x06) |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _u(0x07) |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO2_3 _u(0x08) |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_1 _u(0x09) |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) |
| #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO4_STATUS |
| #define IO_BANK0_GPIO4_STATUS_OFFSET _u(0x00000020) |
| #define IO_BANK0_GPIO4_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO4_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO4_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO4_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO4_CTRL |
| #define IO_BANK0_GPIO4_CTRL_OFFSET _u(0x00000024) |
| #define IO_BANK0_GPIO4_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO4_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO4_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO4_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO4_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO4_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO4_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi0_rx |
| // 0x02 -> uart1_tx |
| // 0x03 -> i2c0_sda |
| // 0x04 -> pwm_a_2 |
| // 0x05 -> siob_proc_4 |
| // 0x06 -> pio0_4 |
| // 0x07 -> pio1_4 |
| // 0x08 -> pio2_4 |
| // 0x09 -> coresight_tracedata_2 |
| // 0x0a -> usb_muxing_vbus_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIOB_PROC_4 _u(0x05) |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _u(0x06) |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _u(0x07) |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO2_4 _u(0x08) |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_2 _u(0x09) |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) |
| #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO5_STATUS |
| #define IO_BANK0_GPIO5_STATUS_OFFSET _u(0x00000028) |
| #define IO_BANK0_GPIO5_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO5_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO5_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO5_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO5_CTRL |
| #define IO_BANK0_GPIO5_CTRL_OFFSET _u(0x0000002c) |
| #define IO_BANK0_GPIO5_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO5_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO5_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO5_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO5_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO5_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO5_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi0_ss_n |
| // 0x02 -> uart1_rx |
| // 0x03 -> i2c0_scl |
| // 0x04 -> pwm_b_2 |
| // 0x05 -> siob_proc_5 |
| // 0x06 -> pio0_5 |
| // 0x07 -> pio1_5 |
| // 0x08 -> pio2_5 |
| // 0x09 -> coresight_tracedata_3 |
| // 0x0a -> usb_muxing_vbus_en |
| // 0x1f -> null |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIOB_PROC_5 _u(0x05) |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _u(0x06) |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _u(0x07) |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO2_5 _u(0x08) |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_3 _u(0x09) |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) |
| #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO6_STATUS |
| #define IO_BANK0_GPIO6_STATUS_OFFSET _u(0x00000030) |
| #define IO_BANK0_GPIO6_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO6_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO6_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO6_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO6_CTRL |
| #define IO_BANK0_GPIO6_CTRL_OFFSET _u(0x00000034) |
| #define IO_BANK0_GPIO6_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO6_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO6_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO6_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO6_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO6_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO6_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi0_sclk |
| // 0x02 -> uart1_cts |
| // 0x03 -> i2c1_sda |
| // 0x04 -> pwm_a_3 |
| // 0x05 -> siob_proc_6 |
| // 0x06 -> pio0_6 |
| // 0x07 -> pio1_6 |
| // 0x08 -> pio2_6 |
| // 0x0a -> usb_muxing_overcurr_detect |
| // 0x0b -> uart1_tx |
| // 0x1f -> null |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIOB_PROC_6 _u(0x05) |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _u(0x06) |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _u(0x07) |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO2_6 _u(0x08) |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) |
| #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO7_STATUS |
| #define IO_BANK0_GPIO7_STATUS_OFFSET _u(0x00000038) |
| #define IO_BANK0_GPIO7_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO7_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO7_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO7_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO7_CTRL |
| #define IO_BANK0_GPIO7_CTRL_OFFSET _u(0x0000003c) |
| #define IO_BANK0_GPIO7_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO7_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO7_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO7_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO7_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO7_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO7_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi0_tx |
| // 0x02 -> uart1_rts |
| // 0x03 -> i2c1_scl |
| // 0x04 -> pwm_b_3 |
| // 0x05 -> siob_proc_7 |
| // 0x06 -> pio0_7 |
| // 0x07 -> pio1_7 |
| // 0x08 -> pio2_7 |
| // 0x0a -> usb_muxing_vbus_detect |
| // 0x0b -> uart1_rx |
| // 0x1f -> null |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIOB_PROC_7 _u(0x05) |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _u(0x06) |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _u(0x07) |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO2_7 _u(0x08) |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) |
| #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO8_STATUS |
| #define IO_BANK0_GPIO8_STATUS_OFFSET _u(0x00000040) |
| #define IO_BANK0_GPIO8_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO8_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO8_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO8_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO8_CTRL |
| #define IO_BANK0_GPIO8_CTRL_OFFSET _u(0x00000044) |
| #define IO_BANK0_GPIO8_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO8_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO8_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO8_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO8_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO8_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO8_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi1_rx |
| // 0x02 -> uart1_tx |
| // 0x03 -> i2c0_sda |
| // 0x04 -> pwm_a_4 |
| // 0x05 -> siob_proc_8 |
| // 0x06 -> pio0_8 |
| // 0x07 -> pio1_8 |
| // 0x08 -> pio2_8 |
| // 0x09 -> xip_ss_n_1 |
| // 0x0a -> usb_muxing_vbus_en |
| // 0x1f -> null |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIOB_PROC_8 _u(0x05) |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _u(0x06) |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _u(0x07) |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO2_8 _u(0x08) |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09) |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) |
| #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO9_STATUS |
| #define IO_BANK0_GPIO9_STATUS_OFFSET _u(0x00000048) |
| #define IO_BANK0_GPIO9_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO9_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO9_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO9_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO9_CTRL |
| #define IO_BANK0_GPIO9_CTRL_OFFSET _u(0x0000004c) |
| #define IO_BANK0_GPIO9_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO9_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO9_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO9_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO9_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO9_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO9_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi1_ss_n |
| // 0x02 -> uart1_rx |
| // 0x03 -> i2c0_scl |
| // 0x04 -> pwm_b_4 |
| // 0x05 -> siob_proc_9 |
| // 0x06 -> pio0_9 |
| // 0x07 -> pio1_9 |
| // 0x08 -> pio2_9 |
| // 0x0a -> usb_muxing_overcurr_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIOB_PROC_9 _u(0x05) |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _u(0x06) |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _u(0x07) |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO2_9 _u(0x08) |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) |
| #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO10_STATUS |
| #define IO_BANK0_GPIO10_STATUS_OFFSET _u(0x00000050) |
| #define IO_BANK0_GPIO10_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO10_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO10_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO10_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO10_CTRL |
| #define IO_BANK0_GPIO10_CTRL_OFFSET _u(0x00000054) |
| #define IO_BANK0_GPIO10_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO10_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO10_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO10_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO10_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO10_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO10_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi1_sclk |
| // 0x02 -> uart1_cts |
| // 0x03 -> i2c1_sda |
| // 0x04 -> pwm_a_5 |
| // 0x05 -> siob_proc_10 |
| // 0x06 -> pio0_10 |
| // 0x07 -> pio1_10 |
| // 0x08 -> pio2_10 |
| // 0x0a -> usb_muxing_vbus_detect |
| // 0x0b -> uart1_tx |
| // 0x1f -> null |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIOB_PROC_10 _u(0x05) |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _u(0x06) |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _u(0x07) |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO2_10 _u(0x08) |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) |
| #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO11_STATUS |
| #define IO_BANK0_GPIO11_STATUS_OFFSET _u(0x00000058) |
| #define IO_BANK0_GPIO11_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO11_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO11_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO11_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO11_CTRL |
| #define IO_BANK0_GPIO11_CTRL_OFFSET _u(0x0000005c) |
| #define IO_BANK0_GPIO11_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO11_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO11_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO11_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO11_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO11_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO11_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi1_tx |
| // 0x02 -> uart1_rts |
| // 0x03 -> i2c1_scl |
| // 0x04 -> pwm_b_5 |
| // 0x05 -> siob_proc_11 |
| // 0x06 -> pio0_11 |
| // 0x07 -> pio1_11 |
| // 0x08 -> pio2_11 |
| // 0x0a -> usb_muxing_vbus_en |
| // 0x0b -> uart1_rx |
| // 0x1f -> null |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIOB_PROC_11 _u(0x05) |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _u(0x06) |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _u(0x07) |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO2_11 _u(0x08) |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) |
| #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO12_STATUS |
| #define IO_BANK0_GPIO12_STATUS_OFFSET _u(0x00000060) |
| #define IO_BANK0_GPIO12_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO12_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO12_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO12_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO12_CTRL |
| #define IO_BANK0_GPIO12_CTRL_OFFSET _u(0x00000064) |
| #define IO_BANK0_GPIO12_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO12_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO12_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO12_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO12_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO12_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO12_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x00 -> hstx_0 |
| // 0x01 -> spi1_rx |
| // 0x02 -> uart0_tx |
| // 0x03 -> i2c0_sda |
| // 0x04 -> pwm_a_6 |
| // 0x05 -> siob_proc_12 |
| // 0x06 -> pio0_12 |
| // 0x07 -> pio1_12 |
| // 0x08 -> pio2_12 |
| // 0x09 -> clocks_gpin_0 |
| // 0x0a -> usb_muxing_overcurr_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_HSTX_0 _u(0x00) |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIOB_PROC_12 _u(0x05) |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _u(0x06) |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _u(0x07) |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO2_12 _u(0x08) |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x09) |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) |
| #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO13_STATUS |
| #define IO_BANK0_GPIO13_STATUS_OFFSET _u(0x00000068) |
| #define IO_BANK0_GPIO13_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO13_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO13_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO13_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO13_CTRL |
| #define IO_BANK0_GPIO13_CTRL_OFFSET _u(0x0000006c) |
| #define IO_BANK0_GPIO13_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO13_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO13_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO13_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO13_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO13_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO13_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x00 -> hstx_1 |
| // 0x01 -> spi1_ss_n |
| // 0x02 -> uart0_rx |
| // 0x03 -> i2c0_scl |
| // 0x04 -> pwm_b_6 |
| // 0x05 -> siob_proc_13 |
| // 0x06 -> pio0_13 |
| // 0x07 -> pio1_13 |
| // 0x08 -> pio2_13 |
| // 0x09 -> clocks_gpout_0 |
| // 0x0a -> usb_muxing_vbus_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_HSTX_1 _u(0x00) |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIOB_PROC_13 _u(0x05) |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _u(0x06) |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _u(0x07) |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO2_13 _u(0x08) |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x09) |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) |
| #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO14_STATUS |
| #define IO_BANK0_GPIO14_STATUS_OFFSET _u(0x00000070) |
| #define IO_BANK0_GPIO14_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO14_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO14_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO14_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO14_CTRL |
| #define IO_BANK0_GPIO14_CTRL_OFFSET _u(0x00000074) |
| #define IO_BANK0_GPIO14_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO14_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO14_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO14_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO14_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO14_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO14_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x00 -> hstx_2 |
| // 0x01 -> spi1_sclk |
| // 0x02 -> uart0_cts |
| // 0x03 -> i2c1_sda |
| // 0x04 -> pwm_a_7 |
| // 0x05 -> siob_proc_14 |
| // 0x06 -> pio0_14 |
| // 0x07 -> pio1_14 |
| // 0x08 -> pio2_14 |
| // 0x09 -> clocks_gpin_1 |
| // 0x0a -> usb_muxing_vbus_en |
| // 0x0b -> uart0_tx |
| // 0x1f -> null |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_HSTX_2 _u(0x00) |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIOB_PROC_14 _u(0x05) |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _u(0x06) |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _u(0x07) |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO2_14 _u(0x08) |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x09) |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) |
| #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO15_STATUS |
| #define IO_BANK0_GPIO15_STATUS_OFFSET _u(0x00000078) |
| #define IO_BANK0_GPIO15_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO15_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO15_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO15_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO15_CTRL |
| #define IO_BANK0_GPIO15_CTRL_OFFSET _u(0x0000007c) |
| #define IO_BANK0_GPIO15_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO15_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO15_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO15_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO15_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO15_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO15_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x00 -> hstx_3 |
| // 0x01 -> spi1_tx |
| // 0x02 -> uart0_rts |
| // 0x03 -> i2c1_scl |
| // 0x04 -> pwm_b_7 |
| // 0x05 -> siob_proc_15 |
| // 0x06 -> pio0_15 |
| // 0x07 -> pio1_15 |
| // 0x08 -> pio2_15 |
| // 0x09 -> clocks_gpout_1 |
| // 0x0a -> usb_muxing_overcurr_detect |
| // 0x0b -> uart0_rx |
| // 0x1f -> null |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_HSTX_3 _u(0x00) |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIOB_PROC_15 _u(0x05) |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _u(0x06) |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _u(0x07) |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO2_15 _u(0x08) |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x09) |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) |
| #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO16_STATUS |
| #define IO_BANK0_GPIO16_STATUS_OFFSET _u(0x00000080) |
| #define IO_BANK0_GPIO16_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO16_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO16_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO16_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO16_CTRL |
| #define IO_BANK0_GPIO16_CTRL_OFFSET _u(0x00000084) |
| #define IO_BANK0_GPIO16_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO16_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO16_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO16_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO16_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO16_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO16_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x00 -> hstx_4 |
| // 0x01 -> spi0_rx |
| // 0x02 -> uart0_tx |
| // 0x03 -> i2c0_sda |
| // 0x04 -> pwm_a_0 |
| // 0x05 -> siob_proc_16 |
| // 0x06 -> pio0_16 |
| // 0x07 -> pio1_16 |
| // 0x08 -> pio2_16 |
| // 0x0a -> usb_muxing_vbus_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_HSTX_4 _u(0x00) |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIOB_PROC_16 _u(0x05) |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _u(0x06) |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _u(0x07) |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO2_16 _u(0x08) |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) |
| #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO17_STATUS |
| #define IO_BANK0_GPIO17_STATUS_OFFSET _u(0x00000088) |
| #define IO_BANK0_GPIO17_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO17_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO17_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO17_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO17_CTRL |
| #define IO_BANK0_GPIO17_CTRL_OFFSET _u(0x0000008c) |
| #define IO_BANK0_GPIO17_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO17_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO17_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO17_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO17_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO17_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO17_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x00 -> hstx_5 |
| // 0x01 -> spi0_ss_n |
| // 0x02 -> uart0_rx |
| // 0x03 -> i2c0_scl |
| // 0x04 -> pwm_b_0 |
| // 0x05 -> siob_proc_17 |
| // 0x06 -> pio0_17 |
| // 0x07 -> pio1_17 |
| // 0x08 -> pio2_17 |
| // 0x0a -> usb_muxing_vbus_en |
| // 0x1f -> null |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_HSTX_5 _u(0x00) |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIOB_PROC_17 _u(0x05) |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _u(0x06) |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _u(0x07) |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO2_17 _u(0x08) |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) |
| #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO18_STATUS |
| #define IO_BANK0_GPIO18_STATUS_OFFSET _u(0x00000090) |
| #define IO_BANK0_GPIO18_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO18_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO18_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO18_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO18_CTRL |
| #define IO_BANK0_GPIO18_CTRL_OFFSET _u(0x00000094) |
| #define IO_BANK0_GPIO18_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO18_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO18_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO18_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO18_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO18_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO18_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x00 -> hstx_6 |
| // 0x01 -> spi0_sclk |
| // 0x02 -> uart0_cts |
| // 0x03 -> i2c1_sda |
| // 0x04 -> pwm_a_1 |
| // 0x05 -> siob_proc_18 |
| // 0x06 -> pio0_18 |
| // 0x07 -> pio1_18 |
| // 0x08 -> pio2_18 |
| // 0x0a -> usb_muxing_overcurr_detect |
| // 0x0b -> uart0_tx |
| // 0x1f -> null |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_HSTX_6 _u(0x00) |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIOB_PROC_18 _u(0x05) |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _u(0x06) |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _u(0x07) |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO2_18 _u(0x08) |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) |
| #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO19_STATUS |
| #define IO_BANK0_GPIO19_STATUS_OFFSET _u(0x00000098) |
| #define IO_BANK0_GPIO19_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO19_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO19_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO19_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO19_CTRL |
| #define IO_BANK0_GPIO19_CTRL_OFFSET _u(0x0000009c) |
| #define IO_BANK0_GPIO19_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO19_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO19_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO19_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO19_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO19_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO19_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x00 -> hstx_7 |
| // 0x01 -> spi0_tx |
| // 0x02 -> uart0_rts |
| // 0x03 -> i2c1_scl |
| // 0x04 -> pwm_b_1 |
| // 0x05 -> siob_proc_19 |
| // 0x06 -> pio0_19 |
| // 0x07 -> pio1_19 |
| // 0x08 -> pio2_19 |
| // 0x09 -> xip_ss_n_1 |
| // 0x0a -> usb_muxing_vbus_detect |
| // 0x0b -> uart0_rx |
| // 0x1f -> null |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_HSTX_7 _u(0x00) |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIOB_PROC_19 _u(0x05) |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _u(0x06) |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _u(0x07) |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO2_19 _u(0x08) |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09) |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) |
| #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO20_STATUS |
| #define IO_BANK0_GPIO20_STATUS_OFFSET _u(0x000000a0) |
| #define IO_BANK0_GPIO20_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO20_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO20_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO20_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO20_CTRL |
| #define IO_BANK0_GPIO20_CTRL_OFFSET _u(0x000000a4) |
| #define IO_BANK0_GPIO20_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO20_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO20_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO20_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO20_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO20_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO20_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO20_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO20_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO20_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi0_rx |
| // 0x02 -> uart1_tx |
| // 0x03 -> i2c0_sda |
| // 0x04 -> pwm_a_2 |
| // 0x05 -> siob_proc_20 |
| // 0x06 -> pio0_20 |
| // 0x07 -> pio1_20 |
| // 0x08 -> pio2_20 |
| // 0x09 -> clocks_gpin_0 |
| // 0x0a -> usb_muxing_vbus_en |
| // 0x1f -> null |
| #define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) |
| #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) |
| #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) |
| #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) |
| #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIOB_PROC_20 _u(0x05) |
| #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _u(0x06) |
| #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _u(0x07) |
| #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO2_20 _u(0x08) |
| #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x09) |
| #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) |
| #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO21_STATUS |
| #define IO_BANK0_GPIO21_STATUS_OFFSET _u(0x000000a8) |
| #define IO_BANK0_GPIO21_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO21_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO21_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO21_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO21_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO21_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO21_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO21_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO21_CTRL |
| #define IO_BANK0_GPIO21_CTRL_OFFSET _u(0x000000ac) |
| #define IO_BANK0_GPIO21_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO21_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO21_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO21_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO21_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO21_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO21_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO21_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO21_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO21_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO21_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO21_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO21_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO21_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi0_ss_n |
| // 0x02 -> uart1_rx |
| // 0x03 -> i2c0_scl |
| // 0x04 -> pwm_b_2 |
| // 0x05 -> siob_proc_21 |
| // 0x06 -> pio0_21 |
| // 0x07 -> pio1_21 |
| // 0x08 -> pio2_21 |
| // 0x09 -> clocks_gpout_0 |
| // 0x0a -> usb_muxing_overcurr_detect |
| // 0x1f -> null |
| #define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) |
| #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) |
| #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) |
| #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) |
| #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIOB_PROC_21 _u(0x05) |
| #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _u(0x06) |
| #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _u(0x07) |
| #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO2_21 _u(0x08) |
| #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x09) |
| #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) |
| #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO22_STATUS |
| #define IO_BANK0_GPIO22_STATUS_OFFSET _u(0x000000b0) |
| #define IO_BANK0_GPIO22_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO22_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO22_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO22_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO22_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO22_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO22_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO22_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO22_CTRL |
| #define IO_BANK0_GPIO22_CTRL_OFFSET _u(0x000000b4) |
| #define IO_BANK0_GPIO22_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO22_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO22_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO22_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO22_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO22_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO22_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO22_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO22_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO22_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO22_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO22_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO22_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO22_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi0_sclk |
| // 0x02 -> uart1_cts |
| // 0x03 -> i2c1_sda |
| // 0x04 -> pwm_a_3 |
| // 0x05 -> siob_proc_22 |
| // 0x06 -> pio0_22 |
| // 0x07 -> pio1_22 |
| // 0x08 -> pio2_22 |
| // 0x09 -> clocks_gpin_1 |
| // 0x0a -> usb_muxing_vbus_detect |
| // 0x0b -> uart1_tx |
| // 0x1f -> null |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET _u(0x1f) |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS _u(0x0000001f) |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB _u(4) |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB _u(0) |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW" |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIOB_PROC_22 _u(0x05) |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _u(0x06) |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _u(0x07) |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO2_22 _u(0x08) |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x09) |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) |
| #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO23_STATUS |
| #define IO_BANK0_GPIO23_STATUS_OFFSET _u(0x000000b8) |
| #define IO_BANK0_GPIO23_STATUS_BITS _u(0x04022200) |
| #define IO_BANK0_GPIO23_STATUS_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO23_STATUS_IRQTOPROC |
| // Description : interrupt to processors, after override is applied |
| #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET _u(0x0) |
| #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS _u(0x04000000) |
| #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB _u(26) |
| #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB _u(26) |
| #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO23_STATUS_INFROMPAD |
| // Description : input signal from pad, before filtering and override are |
| // applied |
| #define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS _u(0x00020000) |
| #define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB _u(17) |
| #define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB _u(17) |
| #define IO_BANK0_GPIO23_STATUS_INFROMPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO23_STATUS_OETOPAD |
| // Description : output enable to pad after register override is applied |
| #define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS _u(0x00002000) |
| #define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB _u(13) |
| #define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB _u(13) |
| #define IO_BANK0_GPIO23_STATUS_OETOPAD_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO23_STATUS_OUTTOPAD |
| // Description : output signal to pad after register override is applied |
| #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET _u(0x0) |
| #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS _u(0x00000200) |
| #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB _u(9) |
| #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB _u(9) |
| #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_ACCESS "RO" |
| // ============================================================================= |
| // Register : IO_BANK0_GPIO23_CTRL |
| #define IO_BANK0_GPIO23_CTRL_OFFSET _u(0x000000bc) |
| #define IO_BANK0_GPIO23_CTRL_BITS _u(0x3003f01f) |
| #define IO_BANK0_GPIO23_CTRL_RESET _u(0x0000001f) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO23_CTRL_IRQOVER |
| // 0x0 -> don't invert the interrupt |
| // 0x1 -> invert the interrupt |
| // 0x2 -> drive interrupt low |
| // 0x3 -> drive interrupt high |
| #define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS _u(0x30000000) |
| #define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB _u(29) |
| #define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB _u(28) |
| #define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO23_CTRL_INOVER |
| // 0x0 -> don't invert the peri input |
| // 0x1 -> invert the peri input |
| // 0x2 -> drive peri input low |
| // 0x3 -> drive peri input high |
| #define IO_BANK0_GPIO23_CTRL_INOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO23_CTRL_INOVER_BITS _u(0x00030000) |
| #define IO_BANK0_GPIO23_CTRL_INOVER_MSB _u(17) |
| #define IO_BANK0_GPIO23_CTRL_INOVER_LSB _u(16) |
| #define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO23_CTRL_OEOVER |
| // 0x0 -> drive output enable from peripheral signal selected by funcsel |
| // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel |
| // 0x2 -> disable output |
| // 0x3 -> enable output |
| #define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO23_CTRL_OEOVER_BITS _u(0x0000c000) |
| #define IO_BANK0_GPIO23_CTRL_OEOVER_MSB _u(15) |
| #define IO_BANK0_GPIO23_CTRL_OEOVER_LSB _u(14) |
| #define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE _u(0x2) |
| #define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO23_CTRL_OUTOVER |
| // 0x0 -> drive output from peripheral signal selected by funcsel |
| // 0x1 -> drive output from inverse of peripheral signal selected by funcsel |
| // 0x2 -> drive output low |
| // 0x3 -> drive output high |
| #define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0) |
| #define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS _u(0x00003000) |
| #define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB _u(13) |
| #define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB _u(12) |
| #define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW" |
| #define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) |
| #define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT _u(0x1) |
| #define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW _u(0x2) |
| #define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH _u(0x3) |
| // ----------------------------------------------------------------------------- |
| // Field : IO_BANK0_GPIO23_CTRL_FUNCSEL |
| // Description : 0-31 -> selects pin function according to the gpio table |
| // 31 == NULL |
| // 0x01 -> spi0_tx |
| // 0x02 -> uart1_rts |
| // 0x03 -> i2c1_scl |
