| // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT |
| |
| /** |
| * Copyright (c) 2024 Raspberry Pi Ltd. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| // ============================================================================= |
| // Register block : M33 |
| // Version : 1 |
| // Bus type : apb |
| // Description : TEAL registers accessible through the debug interface |
| // ============================================================================= |
| #ifndef _HARDWARE_REGS_M33_H |
| #define _HARDWARE_REGS_M33_H |
| // ============================================================================= |
| // Register : M33_ITM_STIM0 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM0_OFFSET _u(0x00000000) |
| #define M33_ITM_STIM0_BITS _u(0xffffffff) |
| #define M33_ITM_STIM0_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM0_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM0_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM0_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM0_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM0_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM0_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM1 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM1_OFFSET _u(0x00000004) |
| #define M33_ITM_STIM1_BITS _u(0xffffffff) |
| #define M33_ITM_STIM1_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM1_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM1_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM1_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM1_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM1_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM1_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM2 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM2_OFFSET _u(0x00000008) |
| #define M33_ITM_STIM2_BITS _u(0xffffffff) |
| #define M33_ITM_STIM2_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM2_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM2_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM2_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM2_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM2_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM2_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM3 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM3_OFFSET _u(0x0000000c) |
| #define M33_ITM_STIM3_BITS _u(0xffffffff) |
| #define M33_ITM_STIM3_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM3_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM3_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM3_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM3_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM3_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM3_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM4 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM4_OFFSET _u(0x00000010) |
| #define M33_ITM_STIM4_BITS _u(0xffffffff) |
| #define M33_ITM_STIM4_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM4_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM4_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM4_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM4_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM4_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM4_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM5 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM5_OFFSET _u(0x00000014) |
| #define M33_ITM_STIM5_BITS _u(0xffffffff) |
| #define M33_ITM_STIM5_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM5_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM5_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM5_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM5_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM5_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM5_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM6 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM6_OFFSET _u(0x00000018) |
| #define M33_ITM_STIM6_BITS _u(0xffffffff) |
| #define M33_ITM_STIM6_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM6_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM6_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM6_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM6_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM6_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM6_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM7 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM7_OFFSET _u(0x0000001c) |
| #define M33_ITM_STIM7_BITS _u(0xffffffff) |
| #define M33_ITM_STIM7_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM7_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM7_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM7_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM7_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM7_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM7_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM8 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM8_OFFSET _u(0x00000020) |
| #define M33_ITM_STIM8_BITS _u(0xffffffff) |
| #define M33_ITM_STIM8_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM8_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM8_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM8_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM8_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM8_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM8_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM9 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM9_OFFSET _u(0x00000024) |
| #define M33_ITM_STIM9_BITS _u(0xffffffff) |
| #define M33_ITM_STIM9_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM9_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM9_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM9_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM9_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM9_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM9_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM10 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM10_OFFSET _u(0x00000028) |
| #define M33_ITM_STIM10_BITS _u(0xffffffff) |
| #define M33_ITM_STIM10_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM10_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM10_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM10_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM10_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM10_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM10_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM11 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM11_OFFSET _u(0x0000002c) |
| #define M33_ITM_STIM11_BITS _u(0xffffffff) |
| #define M33_ITM_STIM11_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM11_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM11_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM11_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM11_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM11_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM11_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM12 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM12_OFFSET _u(0x00000030) |
| #define M33_ITM_STIM12_BITS _u(0xffffffff) |
| #define M33_ITM_STIM12_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM12_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM12_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM12_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM12_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM12_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM12_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM13 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM13_OFFSET _u(0x00000034) |
| #define M33_ITM_STIM13_BITS _u(0xffffffff) |
| #define M33_ITM_STIM13_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM13_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM13_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM13_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM13_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM13_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM13_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM14 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM14_OFFSET _u(0x00000038) |
| #define M33_ITM_STIM14_BITS _u(0xffffffff) |
| #define M33_ITM_STIM14_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM14_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM14_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM14_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM14_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM14_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM14_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM15 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM15_OFFSET _u(0x0000003c) |
| #define M33_ITM_STIM15_BITS _u(0xffffffff) |
| #define M33_ITM_STIM15_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM15_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM15_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM15_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM15_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM15_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM15_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM16 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM16_OFFSET _u(0x00000040) |
| #define M33_ITM_STIM16_BITS _u(0xffffffff) |
| #define M33_ITM_STIM16_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM16_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM16_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM16_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM16_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM16_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM16_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM17 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM17_OFFSET _u(0x00000044) |
| #define M33_ITM_STIM17_BITS _u(0xffffffff) |
| #define M33_ITM_STIM17_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM17_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM17_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM17_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM17_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM17_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM17_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM18 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM18_OFFSET _u(0x00000048) |
| #define M33_ITM_STIM18_BITS _u(0xffffffff) |
| #define M33_ITM_STIM18_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM18_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM18_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM18_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM18_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM18_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM18_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM19 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM19_OFFSET _u(0x0000004c) |
| #define M33_ITM_STIM19_BITS _u(0xffffffff) |
| #define M33_ITM_STIM19_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM19_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM19_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM19_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM19_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM19_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM19_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM20 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM20_OFFSET _u(0x00000050) |
| #define M33_ITM_STIM20_BITS _u(0xffffffff) |
| #define M33_ITM_STIM20_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM20_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM20_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM20_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM20_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM20_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM20_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM21 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM21_OFFSET _u(0x00000054) |
| #define M33_ITM_STIM21_BITS _u(0xffffffff) |
| #define M33_ITM_STIM21_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM21_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM21_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM21_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM21_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM21_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM21_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM22 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM22_OFFSET _u(0x00000058) |
| #define M33_ITM_STIM22_BITS _u(0xffffffff) |
| #define M33_ITM_STIM22_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM22_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM22_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM22_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM22_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM22_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM22_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM23 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM23_OFFSET _u(0x0000005c) |
| #define M33_ITM_STIM23_BITS _u(0xffffffff) |
| #define M33_ITM_STIM23_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM23_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM23_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM23_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM23_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM23_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM23_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM24 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM24_OFFSET _u(0x00000060) |
| #define M33_ITM_STIM24_BITS _u(0xffffffff) |
| #define M33_ITM_STIM24_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM24_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM24_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM24_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM24_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM24_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM24_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM25 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM25_OFFSET _u(0x00000064) |
| #define M33_ITM_STIM25_BITS _u(0xffffffff) |
| #define M33_ITM_STIM25_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM25_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM25_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM25_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM25_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM25_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM25_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM26 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM26_OFFSET _u(0x00000068) |
| #define M33_ITM_STIM26_BITS _u(0xffffffff) |
| #define M33_ITM_STIM26_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM26_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM26_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM26_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM26_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM26_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM26_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM27 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM27_OFFSET _u(0x0000006c) |
| #define M33_ITM_STIM27_BITS _u(0xffffffff) |
| #define M33_ITM_STIM27_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM27_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM27_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM27_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM27_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM27_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM27_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM28 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM28_OFFSET _u(0x00000070) |
| #define M33_ITM_STIM28_BITS _u(0xffffffff) |
| #define M33_ITM_STIM28_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM28_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM28_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM28_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM28_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM28_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM28_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM29 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM29_OFFSET _u(0x00000074) |
| #define M33_ITM_STIM29_BITS _u(0xffffffff) |
| #define M33_ITM_STIM29_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM29_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM29_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM29_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM29_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM29_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM29_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM30 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM30_OFFSET _u(0x00000078) |
| #define M33_ITM_STIM30_BITS _u(0xffffffff) |
| #define M33_ITM_STIM30_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM30_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM30_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM30_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM30_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM30_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM30_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_STIM31 |
| // Description : Provides the interface for generating Instrumentation packets |
| #define M33_ITM_STIM31_OFFSET _u(0x0000007c) |
| #define M33_ITM_STIM31_BITS _u(0xffffffff) |
| #define M33_ITM_STIM31_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_STIM31_STIMULUS |
| // Description : Data to write to the Stimulus Port FIFO, for forwarding as an |
| // Instrumentation packet. The size of write access determines the |
| // type of Instrumentation packet generated. |
| #define M33_ITM_STIM31_STIMULUS_RESET _u(0x00000000) |
| #define M33_ITM_STIM31_STIMULUS_BITS _u(0xffffffff) |
| #define M33_ITM_STIM31_STIMULUS_MSB _u(31) |
| #define M33_ITM_STIM31_STIMULUS_LSB _u(0) |
| #define M33_ITM_STIM31_STIMULUS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_TER0 |
| // Description : Provide an individual enable bit for each ITM_STIM register |
| #define M33_ITM_TER0_OFFSET _u(0x00000e00) |
| #define M33_ITM_TER0_BITS _u(0xffffffff) |
| #define M33_ITM_TER0_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_TER0_STIMENA |
| // Description : For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + |
| // m) is enabled |
| #define M33_ITM_TER0_STIMENA_RESET _u(0x00000000) |
| #define M33_ITM_TER0_STIMENA_BITS _u(0xffffffff) |
| #define M33_ITM_TER0_STIMENA_MSB _u(31) |
| #define M33_ITM_TER0_STIMENA_LSB _u(0) |
| #define M33_ITM_TER0_STIMENA_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_TPR |
| // Description : Controls which stimulus ports can be accessed by unprivileged |
| // code |
| #define M33_ITM_TPR_OFFSET _u(0x00000e40) |
| #define M33_ITM_TPR_BITS _u(0x0000000f) |
| #define M33_ITM_TPR_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_TPR_PRIVMASK |
| // Description : Bit mask to enable tracing on ITM stimulus ports |
| #define M33_ITM_TPR_PRIVMASK_RESET _u(0x0) |
| #define M33_ITM_TPR_PRIVMASK_BITS _u(0x0000000f) |
| #define M33_ITM_TPR_PRIVMASK_MSB _u(3) |
| #define M33_ITM_TPR_PRIVMASK_LSB _u(0) |
| #define M33_ITM_TPR_PRIVMASK_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_TCR |
| // Description : Configures and controls transfers through the ITM interface |
| #define M33_ITM_TCR_OFFSET _u(0x00000e80) |
| #define M33_ITM_TCR_BITS _u(0x00ff0f3f) |
| #define M33_ITM_TCR_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_TCR_BUSY |
| // Description : Indicates whether the ITM is currently processing events |
| #define M33_ITM_TCR_BUSY_RESET _u(0x0) |
| #define M33_ITM_TCR_BUSY_BITS _u(0x00800000) |
| #define M33_ITM_TCR_BUSY_MSB _u(23) |
| #define M33_ITM_TCR_BUSY_LSB _u(23) |
| #define M33_ITM_TCR_BUSY_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_TCR_TRACEBUSID |
| // Description : Identifier for multi-source trace stream formatting. If multi- |
| // source trace is in use, the debugger must write a unique non- |
| // zero trace ID value to this field |
| #define M33_ITM_TCR_TRACEBUSID_RESET _u(0x00) |
| #define M33_ITM_TCR_TRACEBUSID_BITS _u(0x007f0000) |
| #define M33_ITM_TCR_TRACEBUSID_MSB _u(22) |
| #define M33_ITM_TCR_TRACEBUSID_LSB _u(16) |
| #define M33_ITM_TCR_TRACEBUSID_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_TCR_GTSFREQ |
| // Description : Defines how often the ITM generates a global timestamp, based |
| // on the global timestamp clock frequency, or disables generation |
| // of global timestamps |
| #define M33_ITM_TCR_GTSFREQ_RESET _u(0x0) |
| #define M33_ITM_TCR_GTSFREQ_BITS _u(0x00000c00) |
| #define M33_ITM_TCR_GTSFREQ_MSB _u(11) |
| #define M33_ITM_TCR_GTSFREQ_LSB _u(10) |
| #define M33_ITM_TCR_GTSFREQ_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_TCR_TSPRESCALE |
| // Description : Local timestamp prescaler, used with the trace packet reference |
| // clock |
| #define M33_ITM_TCR_TSPRESCALE_RESET _u(0x0) |
| #define M33_ITM_TCR_TSPRESCALE_BITS _u(0x00000300) |
| #define M33_ITM_TCR_TSPRESCALE_MSB _u(9) |
| #define M33_ITM_TCR_TSPRESCALE_LSB _u(8) |
| #define M33_ITM_TCR_TSPRESCALE_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_TCR_STALLENA |
| // Description : Stall the PE to guarantee delivery of Data Trace packets. |
| #define M33_ITM_TCR_STALLENA_RESET _u(0x0) |
| #define M33_ITM_TCR_STALLENA_BITS _u(0x00000020) |
| #define M33_ITM_TCR_STALLENA_MSB _u(5) |
| #define M33_ITM_TCR_STALLENA_LSB _u(5) |
| #define M33_ITM_TCR_STALLENA_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_TCR_SWOENA |
| // Description : Enables asynchronous clocking of the timestamp counter |
| #define M33_ITM_TCR_SWOENA_RESET _u(0x0) |
| #define M33_ITM_TCR_SWOENA_BITS _u(0x00000010) |
| #define M33_ITM_TCR_SWOENA_MSB _u(4) |
| #define M33_ITM_TCR_SWOENA_LSB _u(4) |
| #define M33_ITM_TCR_SWOENA_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_TCR_TXENA |
| // Description : Enables forwarding of hardware event packet from the DWT unit |
| // to the ITM for output to the TPIU |
| #define M33_ITM_TCR_TXENA_RESET _u(0x0) |
| #define M33_ITM_TCR_TXENA_BITS _u(0x00000008) |
| #define M33_ITM_TCR_TXENA_MSB _u(3) |
| #define M33_ITM_TCR_TXENA_LSB _u(3) |
| #define M33_ITM_TCR_TXENA_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_TCR_SYNCENA |
| // Description : Enables Synchronization packet transmission for a synchronous |
| // TPIU |
| #define M33_ITM_TCR_SYNCENA_RESET _u(0x0) |
| #define M33_ITM_TCR_SYNCENA_BITS _u(0x00000004) |
| #define M33_ITM_TCR_SYNCENA_MSB _u(2) |
| #define M33_ITM_TCR_SYNCENA_LSB _u(2) |
| #define M33_ITM_TCR_SYNCENA_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_TCR_TSENA |
| // Description : Enables Local timestamp generation |
| #define M33_ITM_TCR_TSENA_RESET _u(0x0) |
| #define M33_ITM_TCR_TSENA_BITS _u(0x00000002) |
| #define M33_ITM_TCR_TSENA_MSB _u(1) |
| #define M33_ITM_TCR_TSENA_LSB _u(1) |
| #define M33_ITM_TCR_TSENA_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_TCR_ITMENA |
| // Description : Enables the ITM |
| #define M33_ITM_TCR_ITMENA_RESET _u(0x0) |
| #define M33_ITM_TCR_ITMENA_BITS _u(0x00000001) |
| #define M33_ITM_TCR_ITMENA_MSB _u(0) |
| #define M33_ITM_TCR_ITMENA_LSB _u(0) |
| #define M33_ITM_TCR_ITMENA_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_INT_ATREADY |
| // Description : Integration Mode: Read ATB Ready |
| #define M33_INT_ATREADY_OFFSET _u(0x00000ef0) |
| #define M33_INT_ATREADY_BITS _u(0x00000003) |
| #define M33_INT_ATREADY_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_INT_ATREADY_AFVALID |
| // Description : A read of this bit returns the value of AFVALID |
| #define M33_INT_ATREADY_AFVALID_RESET _u(0x0) |
| #define M33_INT_ATREADY_AFVALID_BITS _u(0x00000002) |
| #define M33_INT_ATREADY_AFVALID_MSB _u(1) |
| #define M33_INT_ATREADY_AFVALID_LSB _u(1) |
| #define M33_INT_ATREADY_AFVALID_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_INT_ATREADY_ATREADY |
| // Description : A read of this bit returns the value of ATREADY |
| #define M33_INT_ATREADY_ATREADY_RESET _u(0x0) |
| #define M33_INT_ATREADY_ATREADY_BITS _u(0x00000001) |
| #define M33_INT_ATREADY_ATREADY_MSB _u(0) |
| #define M33_INT_ATREADY_ATREADY_LSB _u(0) |
| #define M33_INT_ATREADY_ATREADY_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_INT_ATVALID |
| // Description : Integration Mode: Write ATB Valid |
| #define M33_INT_ATVALID_OFFSET _u(0x00000ef8) |
| #define M33_INT_ATVALID_BITS _u(0x00000003) |
| #define M33_INT_ATVALID_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_INT_ATVALID_AFREADY |
| // Description : A write to this bit gives the value of AFREADY |
| #define M33_INT_ATVALID_AFREADY_RESET _u(0x0) |
| #define M33_INT_ATVALID_AFREADY_BITS _u(0x00000002) |
| #define M33_INT_ATVALID_AFREADY_MSB _u(1) |
| #define M33_INT_ATVALID_AFREADY_LSB _u(1) |
| #define M33_INT_ATVALID_AFREADY_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_INT_ATVALID_ATREADY |
| // Description : A write to this bit gives the value of ATVALID |
| #define M33_INT_ATVALID_ATREADY_RESET _u(0x0) |
| #define M33_INT_ATVALID_ATREADY_BITS _u(0x00000001) |
| #define M33_INT_ATVALID_ATREADY_MSB _u(0) |
| #define M33_INT_ATVALID_ATREADY_LSB _u(0) |
| #define M33_INT_ATVALID_ATREADY_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_ITCTRL |
| // Description : Integration Mode Control Register |
| #define M33_ITM_ITCTRL_OFFSET _u(0x00000f00) |
| #define M33_ITM_ITCTRL_BITS _u(0x00000001) |
| #define M33_ITM_ITCTRL_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_ITCTRL_IME |
| // Description : Integration mode enable bit - The possible values are: 0 - The |
| // trace unit is not in integration mode. 1 - The trace unit is in |
| // integration mode. This mode enables: A debug agent to perform |
| // topology detection. SoC test software to perform integration |
| // testing. |
| #define M33_ITM_ITCTRL_IME_RESET _u(0x0) |
| #define M33_ITM_ITCTRL_IME_BITS _u(0x00000001) |
| #define M33_ITM_ITCTRL_IME_MSB _u(0) |
| #define M33_ITM_ITCTRL_IME_LSB _u(0) |
| #define M33_ITM_ITCTRL_IME_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_DEVARCH |
| // Description : Provides CoreSight discovery information for the ITM |
| #define M33_ITM_DEVARCH_OFFSET _u(0x00000fbc) |
| #define M33_ITM_DEVARCH_BITS _u(0xffffffff) |
| #define M33_ITM_DEVARCH_RESET _u(0x47701a01) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_DEVARCH_ARCHITECT |
| // Description : Defines the architect of the component. Bits [31:28] are the |
| // JEP106 continuation code (JEP106 bank ID, minus 1) and bits |
| // [27:21] are the JEP106 ID code. |
| #define M33_ITM_DEVARCH_ARCHITECT_RESET _u(0x23b) |
| #define M33_ITM_DEVARCH_ARCHITECT_BITS _u(0xffe00000) |
| #define M33_ITM_DEVARCH_ARCHITECT_MSB _u(31) |
| #define M33_ITM_DEVARCH_ARCHITECT_LSB _u(21) |
| #define M33_ITM_DEVARCH_ARCHITECT_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_DEVARCH_PRESENT |
| // Description : Defines that the DEVARCH register is present |
| #define M33_ITM_DEVARCH_PRESENT_RESET _u(0x1) |
| #define M33_ITM_DEVARCH_PRESENT_BITS _u(0x00100000) |
| #define M33_ITM_DEVARCH_PRESENT_MSB _u(20) |
| #define M33_ITM_DEVARCH_PRESENT_LSB _u(20) |
| #define M33_ITM_DEVARCH_PRESENT_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_DEVARCH_REVISION |
| // Description : Defines the architecture revision of the component |
| #define M33_ITM_DEVARCH_REVISION_RESET _u(0x0) |
| #define M33_ITM_DEVARCH_REVISION_BITS _u(0x000f0000) |
| #define M33_ITM_DEVARCH_REVISION_MSB _u(19) |
| #define M33_ITM_DEVARCH_REVISION_LSB _u(16) |
| #define M33_ITM_DEVARCH_REVISION_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_DEVARCH_ARCHVER |
| // Description : Defines the architecture version of the component |
| #define M33_ITM_DEVARCH_ARCHVER_RESET _u(0x1) |
| #define M33_ITM_DEVARCH_ARCHVER_BITS _u(0x0000f000) |
| #define M33_ITM_DEVARCH_ARCHVER_MSB _u(15) |
| #define M33_ITM_DEVARCH_ARCHVER_LSB _u(12) |
| #define M33_ITM_DEVARCH_ARCHVER_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_DEVARCH_ARCHPART |
| // Description : Defines the architecture of the component |
| #define M33_ITM_DEVARCH_ARCHPART_RESET _u(0xa01) |
| #define M33_ITM_DEVARCH_ARCHPART_BITS _u(0x00000fff) |
| #define M33_ITM_DEVARCH_ARCHPART_MSB _u(11) |
| #define M33_ITM_DEVARCH_ARCHPART_LSB _u(0) |
| #define M33_ITM_DEVARCH_ARCHPART_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_ITM_DEVTYPE |
| // Description : Provides CoreSight discovery information for the ITM |
| #define M33_ITM_DEVTYPE_OFFSET _u(0x00000fcc) |
| #define M33_ITM_DEVTYPE_BITS _u(0x000000ff) |
| #define M33_ITM_DEVTYPE_RESET _u(0x00000043) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_DEVTYPE_SUB |
| // Description : Component sub-type |
| #define M33_ITM_DEVTYPE_SUB_RESET _u(0x4) |
| #define M33_ITM_DEVTYPE_SUB_BITS _u(0x000000f0) |
| #define M33_ITM_DEVTYPE_SUB_MSB _u(7) |
| #define M33_ITM_DEVTYPE_SUB_LSB _u(4) |
| #define M33_ITM_DEVTYPE_SUB_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_DEVTYPE_MAJOR |
| // Description : Component major type |
| #define M33_ITM_DEVTYPE_MAJOR_RESET _u(0x3) |
| #define M33_ITM_DEVTYPE_MAJOR_BITS _u(0x0000000f) |
| #define M33_ITM_DEVTYPE_MAJOR_MSB _u(3) |
| #define M33_ITM_DEVTYPE_MAJOR_LSB _u(0) |
| #define M33_ITM_DEVTYPE_MAJOR_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_ITM_PIDR4 |
| // Description : Provides CoreSight discovery information for the ITM |
| #define M33_ITM_PIDR4_OFFSET _u(0x00000fd0) |
| #define M33_ITM_PIDR4_BITS _u(0x000000ff) |
| #define M33_ITM_PIDR4_RESET _u(0x00000004) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_PIDR4_SIZE |
| // Description : See CoreSight Architecture Specification |
| #define M33_ITM_PIDR4_SIZE_RESET _u(0x0) |
| #define M33_ITM_PIDR4_SIZE_BITS _u(0x000000f0) |
| #define M33_ITM_PIDR4_SIZE_MSB _u(7) |
| #define M33_ITM_PIDR4_SIZE_LSB _u(4) |
| #define M33_ITM_PIDR4_SIZE_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_PIDR4_DES_2 |
| // Description : See CoreSight Architecture Specification |
| #define M33_ITM_PIDR4_DES_2_RESET _u(0x4) |
| #define M33_ITM_PIDR4_DES_2_BITS _u(0x0000000f) |
| #define M33_ITM_PIDR4_DES_2_MSB _u(3) |
| #define M33_ITM_PIDR4_DES_2_LSB _u(0) |
| #define M33_ITM_PIDR4_DES_2_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_ITM_PIDR5 |
| // Description : Provides CoreSight discovery information for the ITM |
| #define M33_ITM_PIDR5_OFFSET _u(0x00000fd4) |
| #define M33_ITM_PIDR5_BITS _u(0x00000000) |
| #define M33_ITM_PIDR5_RESET _u(0x00000000) |
| #define M33_ITM_PIDR5_MSB _u(31) |
| #define M33_ITM_PIDR5_LSB _u(0) |
| #define M33_ITM_PIDR5_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_PIDR6 |
| // Description : Provides CoreSight discovery information for the ITM |
| #define M33_ITM_PIDR6_OFFSET _u(0x00000fd8) |
| #define M33_ITM_PIDR6_BITS _u(0x00000000) |
| #define M33_ITM_PIDR6_RESET _u(0x00000000) |
| #define M33_ITM_PIDR6_MSB _u(31) |
| #define M33_ITM_PIDR6_LSB _u(0) |
| #define M33_ITM_PIDR6_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_PIDR7 |
| // Description : Provides CoreSight discovery information for the ITM |
| #define M33_ITM_PIDR7_OFFSET _u(0x00000fdc) |
| #define M33_ITM_PIDR7_BITS _u(0x00000000) |
| #define M33_ITM_PIDR7_RESET _u(0x00000000) |
| #define M33_ITM_PIDR7_MSB _u(31) |
| #define M33_ITM_PIDR7_LSB _u(0) |
| #define M33_ITM_PIDR7_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_ITM_PIDR0 |
| // Description : Provides CoreSight discovery information for the ITM |
| #define M33_ITM_PIDR0_OFFSET _u(0x00000fe0) |
| #define M33_ITM_PIDR0_BITS _u(0x000000ff) |
| #define M33_ITM_PIDR0_RESET _u(0x00000021) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_PIDR0_PART_0 |
| // Description : See CoreSight Architecture Specification |
| #define M33_ITM_PIDR0_PART_0_RESET _u(0x21) |
| #define M33_ITM_PIDR0_PART_0_BITS _u(0x000000ff) |
| #define M33_ITM_PIDR0_PART_0_MSB _u(7) |
| #define M33_ITM_PIDR0_PART_0_LSB _u(0) |
| #define M33_ITM_PIDR0_PART_0_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_ITM_PIDR1 |
| // Description : Provides CoreSight discovery information for the ITM |
| #define M33_ITM_PIDR1_OFFSET _u(0x00000fe4) |
| #define M33_ITM_PIDR1_BITS _u(0x000000ff) |
| #define M33_ITM_PIDR1_RESET _u(0x000000bd) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_PIDR1_DES_0 |
| // Description : See CoreSight Architecture Specification |
| #define M33_ITM_PIDR1_DES_0_RESET _u(0xb) |
| #define M33_ITM_PIDR1_DES_0_BITS _u(0x000000f0) |
| #define M33_ITM_PIDR1_DES_0_MSB _u(7) |
| #define M33_ITM_PIDR1_DES_0_LSB _u(4) |
| #define M33_ITM_PIDR1_DES_0_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_PIDR1_PART_1 |
| // Description : See CoreSight Architecture Specification |
| #define M33_ITM_PIDR1_PART_1_RESET _u(0xd) |
| #define M33_ITM_PIDR1_PART_1_BITS _u(0x0000000f) |
| #define M33_ITM_PIDR1_PART_1_MSB _u(3) |
| #define M33_ITM_PIDR1_PART_1_LSB _u(0) |
| #define M33_ITM_PIDR1_PART_1_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_ITM_PIDR2 |
| // Description : Provides CoreSight discovery information for the ITM |
| #define M33_ITM_PIDR2_OFFSET _u(0x00000fe8) |
| #define M33_ITM_PIDR2_BITS _u(0x000000ff) |
| #define M33_ITM_PIDR2_RESET _u(0x0000000b) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_PIDR2_REVISION |
| // Description : See CoreSight Architecture Specification |
| #define M33_ITM_PIDR2_REVISION_RESET _u(0x0) |
| #define M33_ITM_PIDR2_REVISION_BITS _u(0x000000f0) |
| #define M33_ITM_PIDR2_REVISION_MSB _u(7) |
| #define M33_ITM_PIDR2_REVISION_LSB _u(4) |
| #define M33_ITM_PIDR2_REVISION_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_PIDR2_JEDEC |
| // Description : See CoreSight Architecture Specification |
| #define M33_ITM_PIDR2_JEDEC_RESET _u(0x1) |
| #define M33_ITM_PIDR2_JEDEC_BITS _u(0x00000008) |
| #define M33_ITM_PIDR2_JEDEC_MSB _u(3) |
| #define M33_ITM_PIDR2_JEDEC_LSB _u(3) |
| #define M33_ITM_PIDR2_JEDEC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_PIDR2_DES_1 |
| // Description : See CoreSight Architecture Specification |
| #define M33_ITM_PIDR2_DES_1_RESET _u(0x3) |
| #define M33_ITM_PIDR2_DES_1_BITS _u(0x00000007) |
| #define M33_ITM_PIDR2_DES_1_MSB _u(2) |
| #define M33_ITM_PIDR2_DES_1_LSB _u(0) |
| #define M33_ITM_PIDR2_DES_1_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_ITM_PIDR3 |
| // Description : Provides CoreSight discovery information for the ITM |
| #define M33_ITM_PIDR3_OFFSET _u(0x00000fec) |
| #define M33_ITM_PIDR3_BITS _u(0x000000ff) |
| #define M33_ITM_PIDR3_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_PIDR3_REVAND |
| // Description : See CoreSight Architecture Specification |
| #define M33_ITM_PIDR3_REVAND_RESET _u(0x0) |
| #define M33_ITM_PIDR3_REVAND_BITS _u(0x000000f0) |
| #define M33_ITM_PIDR3_REVAND_MSB _u(7) |
| #define M33_ITM_PIDR3_REVAND_LSB _u(4) |
| #define M33_ITM_PIDR3_REVAND_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_PIDR3_CMOD |
| // Description : See CoreSight Architecture Specification |
| #define M33_ITM_PIDR3_CMOD_RESET _u(0x0) |
| #define M33_ITM_PIDR3_CMOD_BITS _u(0x0000000f) |
| #define M33_ITM_PIDR3_CMOD_MSB _u(3) |
| #define M33_ITM_PIDR3_CMOD_LSB _u(0) |
| #define M33_ITM_PIDR3_CMOD_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_ITM_CIDR0 |
| // Description : Provides CoreSight discovery information for the ITM |
| #define M33_ITM_CIDR0_OFFSET _u(0x00000ff0) |
| #define M33_ITM_CIDR0_BITS _u(0x000000ff) |
| #define M33_ITM_CIDR0_RESET _u(0x0000000d) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_CIDR0_PRMBL_0 |
| // Description : See CoreSight Architecture Specification |
| #define M33_ITM_CIDR0_PRMBL_0_RESET _u(0x0d) |
| #define M33_ITM_CIDR0_PRMBL_0_BITS _u(0x000000ff) |
| #define M33_ITM_CIDR0_PRMBL_0_MSB _u(7) |
| #define M33_ITM_CIDR0_PRMBL_0_LSB _u(0) |
| #define M33_ITM_CIDR0_PRMBL_0_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_ITM_CIDR1 |
| // Description : Provides CoreSight discovery information for the ITM |
| #define M33_ITM_CIDR1_OFFSET _u(0x00000ff4) |
| #define M33_ITM_CIDR1_BITS _u(0x000000ff) |
| #define M33_ITM_CIDR1_RESET _u(0x00000090) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_CIDR1_CLASS |
| // Description : See CoreSight Architecture Specification |
| #define M33_ITM_CIDR1_CLASS_RESET _u(0x9) |
| #define M33_ITM_CIDR1_CLASS_BITS _u(0x000000f0) |
| #define M33_ITM_CIDR1_CLASS_MSB _u(7) |
| #define M33_ITM_CIDR1_CLASS_LSB _u(4) |
| #define M33_ITM_CIDR1_CLASS_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_CIDR1_PRMBL_1 |
| // Description : See CoreSight Architecture Specification |
| #define M33_ITM_CIDR1_PRMBL_1_RESET _u(0x0) |
| #define M33_ITM_CIDR1_PRMBL_1_BITS _u(0x0000000f) |
| #define M33_ITM_CIDR1_PRMBL_1_MSB _u(3) |
| #define M33_ITM_CIDR1_PRMBL_1_LSB _u(0) |
| #define M33_ITM_CIDR1_PRMBL_1_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_ITM_CIDR2 |
| // Description : Provides CoreSight discovery information for the ITM |
| #define M33_ITM_CIDR2_OFFSET _u(0x00000ff8) |
| #define M33_ITM_CIDR2_BITS _u(0x000000ff) |
| #define M33_ITM_CIDR2_RESET _u(0x00000005) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_CIDR2_PRMBL_2 |
| // Description : See CoreSight Architecture Specification |
| #define M33_ITM_CIDR2_PRMBL_2_RESET _u(0x05) |
| #define M33_ITM_CIDR2_PRMBL_2_BITS _u(0x000000ff) |
| #define M33_ITM_CIDR2_PRMBL_2_MSB _u(7) |
| #define M33_ITM_CIDR2_PRMBL_2_LSB _u(0) |
| #define M33_ITM_CIDR2_PRMBL_2_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_ITM_CIDR3 |
| // Description : Provides CoreSight discovery information for the ITM |
| #define M33_ITM_CIDR3_OFFSET _u(0x00000ffc) |
| #define M33_ITM_CIDR3_BITS _u(0x000000ff) |
| #define M33_ITM_CIDR3_RESET _u(0x000000b1) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ITM_CIDR3_PRMBL_3 |
| // Description : See CoreSight Architecture Specification |
| #define M33_ITM_CIDR3_PRMBL_3_RESET _u(0xb1) |
| #define M33_ITM_CIDR3_PRMBL_3_BITS _u(0x000000ff) |
| #define M33_ITM_CIDR3_PRMBL_3_MSB _u(7) |
| #define M33_ITM_CIDR3_PRMBL_3_LSB _u(0) |
| #define M33_ITM_CIDR3_PRMBL_3_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_DWT_CTRL |
| // Description : Provides configuration and status information for the DWT unit, |
| // and used to control features of the unit |
| #define M33_DWT_CTRL_OFFSET _u(0x00001000) |
| #define M33_DWT_CTRL_BITS _u(0xffff1fff) |
| #define M33_DWT_CTRL_RESET _u(0x73741824) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_NUMCOMP |
| // Description : Number of DWT comparators implemented |
| #define M33_DWT_CTRL_NUMCOMP_RESET _u(0x7) |
| #define M33_DWT_CTRL_NUMCOMP_BITS _u(0xf0000000) |
| #define M33_DWT_CTRL_NUMCOMP_MSB _u(31) |
| #define M33_DWT_CTRL_NUMCOMP_LSB _u(28) |
| #define M33_DWT_CTRL_NUMCOMP_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_NOTRCPKT |
| // Description : Indicates whether the implementation does not support trace |
| #define M33_DWT_CTRL_NOTRCPKT_RESET _u(0x0) |
| #define M33_DWT_CTRL_NOTRCPKT_BITS _u(0x08000000) |
| #define M33_DWT_CTRL_NOTRCPKT_MSB _u(27) |
| #define M33_DWT_CTRL_NOTRCPKT_LSB _u(27) |
| #define M33_DWT_CTRL_NOTRCPKT_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_NOEXTTRIG |
| // Description : Reserved, RAZ |
| #define M33_DWT_CTRL_NOEXTTRIG_RESET _u(0x0) |
| #define M33_DWT_CTRL_NOEXTTRIG_BITS _u(0x04000000) |
| #define M33_DWT_CTRL_NOEXTTRIG_MSB _u(26) |
| #define M33_DWT_CTRL_NOEXTTRIG_LSB _u(26) |
| #define M33_DWT_CTRL_NOEXTTRIG_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_NOCYCCNT |
| // Description : Indicates whether the implementation does not include a cycle |
| // counter |
| #define M33_DWT_CTRL_NOCYCCNT_RESET _u(0x1) |
| #define M33_DWT_CTRL_NOCYCCNT_BITS _u(0x02000000) |
| #define M33_DWT_CTRL_NOCYCCNT_MSB _u(25) |
| #define M33_DWT_CTRL_NOCYCCNT_LSB _u(25) |
| #define M33_DWT_CTRL_NOCYCCNT_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_NOPRFCNT |
| // Description : Indicates whether the implementation does not include the |
| // profiling counters |
| #define M33_DWT_CTRL_NOPRFCNT_RESET _u(0x1) |
| #define M33_DWT_CTRL_NOPRFCNT_BITS _u(0x01000000) |
| #define M33_DWT_CTRL_NOPRFCNT_MSB _u(24) |
| #define M33_DWT_CTRL_NOPRFCNT_LSB _u(24) |
| #define M33_DWT_CTRL_NOPRFCNT_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_CYCDISS |
| // Description : Controls whether the cycle counter is disabled in Secure state |
| #define M33_DWT_CTRL_CYCDISS_RESET _u(0x0) |
| #define M33_DWT_CTRL_CYCDISS_BITS _u(0x00800000) |
| #define M33_DWT_CTRL_CYCDISS_MSB _u(23) |
| #define M33_DWT_CTRL_CYCDISS_LSB _u(23) |
| #define M33_DWT_CTRL_CYCDISS_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_CYCEVTENA |
| // Description : Enables Event Counter packet generation on POSTCNT underflow |
| #define M33_DWT_CTRL_CYCEVTENA_RESET _u(0x1) |
| #define M33_DWT_CTRL_CYCEVTENA_BITS _u(0x00400000) |
| #define M33_DWT_CTRL_CYCEVTENA_MSB _u(22) |
| #define M33_DWT_CTRL_CYCEVTENA_LSB _u(22) |
| #define M33_DWT_CTRL_CYCEVTENA_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_FOLDEVTENA |
| // Description : Enables DWT_FOLDCNT counter |
| #define M33_DWT_CTRL_FOLDEVTENA_RESET _u(0x1) |
| #define M33_DWT_CTRL_FOLDEVTENA_BITS _u(0x00200000) |
| #define M33_DWT_CTRL_FOLDEVTENA_MSB _u(21) |
| #define M33_DWT_CTRL_FOLDEVTENA_LSB _u(21) |
| #define M33_DWT_CTRL_FOLDEVTENA_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_LSUEVTENA |
| // Description : Enables DWT_LSUCNT counter |
| #define M33_DWT_CTRL_LSUEVTENA_RESET _u(0x1) |
| #define M33_DWT_CTRL_LSUEVTENA_BITS _u(0x00100000) |
| #define M33_DWT_CTRL_LSUEVTENA_MSB _u(20) |
| #define M33_DWT_CTRL_LSUEVTENA_LSB _u(20) |
| #define M33_DWT_CTRL_LSUEVTENA_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_SLEEPEVTENA |
| // Description : Enable DWT_SLEEPCNT counter |
| #define M33_DWT_CTRL_SLEEPEVTENA_RESET _u(0x0) |
| #define M33_DWT_CTRL_SLEEPEVTENA_BITS _u(0x00080000) |
| #define M33_DWT_CTRL_SLEEPEVTENA_MSB _u(19) |
| #define M33_DWT_CTRL_SLEEPEVTENA_LSB _u(19) |
| #define M33_DWT_CTRL_SLEEPEVTENA_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_EXCEVTENA |
| // Description : Enables DWT_EXCCNT counter |
| #define M33_DWT_CTRL_EXCEVTENA_RESET _u(0x1) |
| #define M33_DWT_CTRL_EXCEVTENA_BITS _u(0x00040000) |
| #define M33_DWT_CTRL_EXCEVTENA_MSB _u(18) |
| #define M33_DWT_CTRL_EXCEVTENA_LSB _u(18) |
| #define M33_DWT_CTRL_EXCEVTENA_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_CPIEVTENA |
| // Description : Enables DWT_CPICNT counter |
| #define M33_DWT_CTRL_CPIEVTENA_RESET _u(0x0) |
| #define M33_DWT_CTRL_CPIEVTENA_BITS _u(0x00020000) |
| #define M33_DWT_CTRL_CPIEVTENA_MSB _u(17) |
| #define M33_DWT_CTRL_CPIEVTENA_LSB _u(17) |
| #define M33_DWT_CTRL_CPIEVTENA_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_EXTTRCENA |
| // Description : Enables generation of Exception Trace packets |
| #define M33_DWT_CTRL_EXTTRCENA_RESET _u(0x0) |
| #define M33_DWT_CTRL_EXTTRCENA_BITS _u(0x00010000) |
| #define M33_DWT_CTRL_EXTTRCENA_MSB _u(16) |
| #define M33_DWT_CTRL_EXTTRCENA_LSB _u(16) |
| #define M33_DWT_CTRL_EXTTRCENA_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_PCSAMPLENA |
| // Description : Enables use of POSTCNT counter as a timer for Periodic PC |
| // Sample packet generation |
| #define M33_DWT_CTRL_PCSAMPLENA_RESET _u(0x1) |
| #define M33_DWT_CTRL_PCSAMPLENA_BITS _u(0x00001000) |
| #define M33_DWT_CTRL_PCSAMPLENA_MSB _u(12) |
| #define M33_DWT_CTRL_PCSAMPLENA_LSB _u(12) |
| #define M33_DWT_CTRL_PCSAMPLENA_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_SYNCTAP |
| // Description : Selects the position of the synchronization packet counter tap |
| // on the CYCCNT counter. This determines the Synchronization |
| // packet rate |
| #define M33_DWT_CTRL_SYNCTAP_RESET _u(0x2) |
| #define M33_DWT_CTRL_SYNCTAP_BITS _u(0x00000c00) |
| #define M33_DWT_CTRL_SYNCTAP_MSB _u(11) |
| #define M33_DWT_CTRL_SYNCTAP_LSB _u(10) |
| #define M33_DWT_CTRL_SYNCTAP_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_CYCTAP |
| // Description : Selects the position of the POSTCNT tap on the CYCCNT counter |
| #define M33_DWT_CTRL_CYCTAP_RESET _u(0x0) |
| #define M33_DWT_CTRL_CYCTAP_BITS _u(0x00000200) |
| #define M33_DWT_CTRL_CYCTAP_MSB _u(9) |
| #define M33_DWT_CTRL_CYCTAP_LSB _u(9) |
| #define M33_DWT_CTRL_CYCTAP_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_POSTINIT |
| // Description : Initial value for the POSTCNT counter |
| #define M33_DWT_CTRL_POSTINIT_RESET _u(0x1) |
| #define M33_DWT_CTRL_POSTINIT_BITS _u(0x000001e0) |
| #define M33_DWT_CTRL_POSTINIT_MSB _u(8) |
| #define M33_DWT_CTRL_POSTINIT_LSB _u(5) |
| #define M33_DWT_CTRL_POSTINIT_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_POSTPRESET |
| // Description : Reload value for the POSTCNT counter |
| #define M33_DWT_CTRL_POSTPRESET_RESET _u(0x2) |
| #define M33_DWT_CTRL_POSTPRESET_BITS _u(0x0000001e) |
| #define M33_DWT_CTRL_POSTPRESET_MSB _u(4) |
| #define M33_DWT_CTRL_POSTPRESET_LSB _u(1) |
| #define M33_DWT_CTRL_POSTPRESET_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CTRL_CYCCNTENA |
| // Description : Enables CYCCNT |
| #define M33_DWT_CTRL_CYCCNTENA_RESET _u(0x0) |
| #define M33_DWT_CTRL_CYCCNTENA_BITS _u(0x00000001) |
| #define M33_DWT_CTRL_CYCCNTENA_MSB _u(0) |
| #define M33_DWT_CTRL_CYCCNTENA_LSB _u(0) |
| #define M33_DWT_CTRL_CYCCNTENA_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_DWT_CYCCNT |
| // Description : Shows or sets the value of the processor cycle counter, CYCCNT |
| #define M33_DWT_CYCCNT_OFFSET _u(0x00001004) |
| #define M33_DWT_CYCCNT_BITS _u(0xffffffff) |
| #define M33_DWT_CYCCNT_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CYCCNT_CYCCNT |
| // Description : Increments one on each processor clock cycle when |
| // DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, |
| // CYCCNT wraps to zero |
| #define M33_DWT_CYCCNT_CYCCNT_RESET _u(0x00000000) |
| #define M33_DWT_CYCCNT_CYCCNT_BITS _u(0xffffffff) |
| #define M33_DWT_CYCCNT_CYCCNT_MSB _u(31) |
| #define M33_DWT_CYCCNT_CYCCNT_LSB _u(0) |
| #define M33_DWT_CYCCNT_CYCCNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_DWT_EXCCNT |
| // Description : Counts the total cycles spent in exception processing |
| #define M33_DWT_EXCCNT_OFFSET _u(0x0000100c) |
| #define M33_DWT_EXCCNT_BITS _u(0x000000ff) |
| #define M33_DWT_EXCCNT_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_EXCCNT_EXCCNT |
| // Description : Counts one on each cycle when all of the following are true: - |
| // DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction |
| // is executed, see DWT_CPICNT. - An exception-entry or exception- |
| // exit related operation is in progress. - Either |
| // SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the |
| // operation is set to Non-secure and NoninvasiveDebugAllowed() == |
| // TRUE. |
| #define M33_DWT_EXCCNT_EXCCNT_RESET _u(0x00) |
| #define M33_DWT_EXCCNT_EXCCNT_BITS _u(0x000000ff) |
| #define M33_DWT_EXCCNT_EXCCNT_MSB _u(7) |
| #define M33_DWT_EXCCNT_EXCCNT_LSB _u(0) |
| #define M33_DWT_EXCCNT_EXCCNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_DWT_LSUCNT |
| // Description : Increments on the additional cycles required to execute all |
| // load or store instructions |
| #define M33_DWT_LSUCNT_OFFSET _u(0x00001014) |
| #define M33_DWT_LSUCNT_BITS _u(0x000000ff) |
| #define M33_DWT_LSUCNT_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_LSUCNT_LSUCNT |
| // Description : Counts one on each cycle when all of the following are true: - |
| // DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction |
| // is executed, see DWT_CPICNT. - No exception-entry or exception- |
| // exit operation is in progress, see DWT_EXCCNT. - A load-store |
| // operation is in progress. - Either |
| // SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the |
| // operation is set to Non-secure and NoninvasiveDebugAllowed() == |
| // TRUE. |
| #define M33_DWT_LSUCNT_LSUCNT_RESET _u(0x00) |
| #define M33_DWT_LSUCNT_LSUCNT_BITS _u(0x000000ff) |
| #define M33_DWT_LSUCNT_LSUCNT_MSB _u(7) |
| #define M33_DWT_LSUCNT_LSUCNT_LSB _u(0) |
| #define M33_DWT_LSUCNT_LSUCNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_DWT_FOLDCNT |
| // Description : Increments on the additional cycles required to execute all |
| // load or store instructions |
| #define M33_DWT_FOLDCNT_OFFSET _u(0x00001018) |
| #define M33_DWT_FOLDCNT_BITS _u(0x000000ff) |
| #define M33_DWT_FOLDCNT_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FOLDCNT_FOLDCNT |
| // Description : Counts on each cycle when all of the following are true: - |
| // DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two |
| // instructions are executed, see DWT_CPICNT. - Either |
| // SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non- |
| // secure state and NoninvasiveDebugAllowed() == TRUE. The counter |
| // is incremented by the number of instructions executed, minus |
| // one |
| #define M33_DWT_FOLDCNT_FOLDCNT_RESET _u(0x00) |
| #define M33_DWT_FOLDCNT_FOLDCNT_BITS _u(0x000000ff) |
| #define M33_DWT_FOLDCNT_FOLDCNT_MSB _u(7) |
| #define M33_DWT_FOLDCNT_FOLDCNT_LSB _u(0) |
| #define M33_DWT_FOLDCNT_FOLDCNT_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_DWT_COMP0 |
| // Description : Provides a reference value for use by watchpoint comparator 0 |
| #define M33_DWT_COMP0_OFFSET _u(0x00001020) |
| #define M33_DWT_COMP0_BITS _u(0xffffffff) |
| #define M33_DWT_COMP0_RESET _u(0x00000000) |
| #define M33_DWT_COMP0_MSB _u(31) |
| #define M33_DWT_COMP0_LSB _u(0) |
| #define M33_DWT_COMP0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_DWT_FUNCTION0 |
| // Description : Controls the operation of watchpoint comparator 0 |
| #define M33_DWT_FUNCTION0_OFFSET _u(0x00001028) |
| #define M33_DWT_FUNCTION0_BITS _u(0xf9000c3f) |
| #define M33_DWT_FUNCTION0_RESET _u(0x58000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION0_ID |
| // Description : Identifies the capabilities for MATCH for comparator *n |
| #define M33_DWT_FUNCTION0_ID_RESET _u(0x0b) |
| #define M33_DWT_FUNCTION0_ID_BITS _u(0xf8000000) |
| #define M33_DWT_FUNCTION0_ID_MSB _u(31) |
| #define M33_DWT_FUNCTION0_ID_LSB _u(27) |
| #define M33_DWT_FUNCTION0_ID_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION0_MATCHED |
| // Description : Set to 1 when the comparator matches |
| #define M33_DWT_FUNCTION0_MATCHED_RESET _u(0x0) |
| #define M33_DWT_FUNCTION0_MATCHED_BITS _u(0x01000000) |
| #define M33_DWT_FUNCTION0_MATCHED_MSB _u(24) |
| #define M33_DWT_FUNCTION0_MATCHED_LSB _u(24) |
| #define M33_DWT_FUNCTION0_MATCHED_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION0_DATAVSIZE |
| // Description : Defines the size of the object being watched for by Data Value |
| // and Data Address comparators |
| #define M33_DWT_FUNCTION0_DATAVSIZE_RESET _u(0x0) |
| #define M33_DWT_FUNCTION0_DATAVSIZE_BITS _u(0x00000c00) |
| #define M33_DWT_FUNCTION0_DATAVSIZE_MSB _u(11) |
| #define M33_DWT_FUNCTION0_DATAVSIZE_LSB _u(10) |
| #define M33_DWT_FUNCTION0_DATAVSIZE_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION0_ACTION |
| // Description : Defines the action on a match. This field is ignored and the |
| // comparator generates no actions if it is disabled by MATCH |
| #define M33_DWT_FUNCTION0_ACTION_RESET _u(0x0) |
| #define M33_DWT_FUNCTION0_ACTION_BITS _u(0x00000030) |
| #define M33_DWT_FUNCTION0_ACTION_MSB _u(5) |
| #define M33_DWT_FUNCTION0_ACTION_LSB _u(4) |
| #define M33_DWT_FUNCTION0_ACTION_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION0_MATCH |
| // Description : Controls the type of match generated by this comparator |
| #define M33_DWT_FUNCTION0_MATCH_RESET _u(0x0) |
| #define M33_DWT_FUNCTION0_MATCH_BITS _u(0x0000000f) |
| #define M33_DWT_FUNCTION0_MATCH_MSB _u(3) |
| #define M33_DWT_FUNCTION0_MATCH_LSB _u(0) |
| #define M33_DWT_FUNCTION0_MATCH_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_DWT_COMP1 |
| // Description : Provides a reference value for use by watchpoint comparator 1 |
| #define M33_DWT_COMP1_OFFSET _u(0x00001030) |
| #define M33_DWT_COMP1_BITS _u(0xffffffff) |
| #define M33_DWT_COMP1_RESET _u(0x00000000) |
| #define M33_DWT_COMP1_MSB _u(31) |
| #define M33_DWT_COMP1_LSB _u(0) |
| #define M33_DWT_COMP1_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_DWT_FUNCTION1 |
| // Description : Controls the operation of watchpoint comparator 1 |
| #define M33_DWT_FUNCTION1_OFFSET _u(0x00001038) |
| #define M33_DWT_FUNCTION1_BITS _u(0xf9000c3f) |
| #define M33_DWT_FUNCTION1_RESET _u(0x89000828) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION1_ID |
| // Description : Identifies the capabilities for MATCH for comparator *n |
| #define M33_DWT_FUNCTION1_ID_RESET _u(0x11) |
| #define M33_DWT_FUNCTION1_ID_BITS _u(0xf8000000) |
| #define M33_DWT_FUNCTION1_ID_MSB _u(31) |
| #define M33_DWT_FUNCTION1_ID_LSB _u(27) |
| #define M33_DWT_FUNCTION1_ID_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION1_MATCHED |
| // Description : Set to 1 when the comparator matches |
| #define M33_DWT_FUNCTION1_MATCHED_RESET _u(0x1) |
| #define M33_DWT_FUNCTION1_MATCHED_BITS _u(0x01000000) |
| #define M33_DWT_FUNCTION1_MATCHED_MSB _u(24) |
| #define M33_DWT_FUNCTION1_MATCHED_LSB _u(24) |
| #define M33_DWT_FUNCTION1_MATCHED_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION1_DATAVSIZE |
| // Description : Defines the size of the object being watched for by Data Value |
| // and Data Address comparators |
| #define M33_DWT_FUNCTION1_DATAVSIZE_RESET _u(0x2) |
| #define M33_DWT_FUNCTION1_DATAVSIZE_BITS _u(0x00000c00) |
| #define M33_DWT_FUNCTION1_DATAVSIZE_MSB _u(11) |
| #define M33_DWT_FUNCTION1_DATAVSIZE_LSB _u(10) |
| #define M33_DWT_FUNCTION1_DATAVSIZE_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION1_ACTION |
| // Description : Defines the action on a match. This field is ignored and the |
| // comparator generates no actions if it is disabled by MATCH |
| #define M33_DWT_FUNCTION1_ACTION_RESET _u(0x2) |
| #define M33_DWT_FUNCTION1_ACTION_BITS _u(0x00000030) |
| #define M33_DWT_FUNCTION1_ACTION_MSB _u(5) |
| #define M33_DWT_FUNCTION1_ACTION_LSB _u(4) |
| #define M33_DWT_FUNCTION1_ACTION_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION1_MATCH |
| // Description : Controls the type of match generated by this comparator |
| #define M33_DWT_FUNCTION1_MATCH_RESET _u(0x8) |
| #define M33_DWT_FUNCTION1_MATCH_BITS _u(0x0000000f) |
| #define M33_DWT_FUNCTION1_MATCH_MSB _u(3) |
| #define M33_DWT_FUNCTION1_MATCH_LSB _u(0) |
| #define M33_DWT_FUNCTION1_MATCH_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_DWT_COMP2 |
| // Description : Provides a reference value for use by watchpoint comparator 2 |
| #define M33_DWT_COMP2_OFFSET _u(0x00001040) |
| #define M33_DWT_COMP2_BITS _u(0xffffffff) |
| #define M33_DWT_COMP2_RESET _u(0x00000000) |
| #define M33_DWT_COMP2_MSB _u(31) |
| #define M33_DWT_COMP2_LSB _u(0) |
| #define M33_DWT_COMP2_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_DWT_FUNCTION2 |
| // Description : Controls the operation of watchpoint comparator 2 |
| #define M33_DWT_FUNCTION2_OFFSET _u(0x00001048) |
| #define M33_DWT_FUNCTION2_BITS _u(0xf9000c3f) |
| #define M33_DWT_FUNCTION2_RESET _u(0x50000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION2_ID |
| // Description : Identifies the capabilities for MATCH for comparator *n |
| #define M33_DWT_FUNCTION2_ID_RESET _u(0x0a) |
| #define M33_DWT_FUNCTION2_ID_BITS _u(0xf8000000) |
| #define M33_DWT_FUNCTION2_ID_MSB _u(31) |
| #define M33_DWT_FUNCTION2_ID_LSB _u(27) |
| #define M33_DWT_FUNCTION2_ID_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION2_MATCHED |
| // Description : Set to 1 when the comparator matches |
| #define M33_DWT_FUNCTION2_MATCHED_RESET _u(0x0) |
| #define M33_DWT_FUNCTION2_MATCHED_BITS _u(0x01000000) |
| #define M33_DWT_FUNCTION2_MATCHED_MSB _u(24) |
| #define M33_DWT_FUNCTION2_MATCHED_LSB _u(24) |
| #define M33_DWT_FUNCTION2_MATCHED_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION2_DATAVSIZE |
| // Description : Defines the size of the object being watched for by Data Value |
| // and Data Address comparators |
| #define M33_DWT_FUNCTION2_DATAVSIZE_RESET _u(0x0) |
| #define M33_DWT_FUNCTION2_DATAVSIZE_BITS _u(0x00000c00) |
| #define M33_DWT_FUNCTION2_DATAVSIZE_MSB _u(11) |
| #define M33_DWT_FUNCTION2_DATAVSIZE_LSB _u(10) |
| #define M33_DWT_FUNCTION2_DATAVSIZE_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION2_ACTION |
| // Description : Defines the action on a match. This field is ignored and the |
| // comparator generates no actions if it is disabled by MATCH |
| #define M33_DWT_FUNCTION2_ACTION_RESET _u(0x0) |
| #define M33_DWT_FUNCTION2_ACTION_BITS _u(0x00000030) |
| #define M33_DWT_FUNCTION2_ACTION_MSB _u(5) |
| #define M33_DWT_FUNCTION2_ACTION_LSB _u(4) |
| #define M33_DWT_FUNCTION2_ACTION_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION2_MATCH |
| // Description : Controls the type of match generated by this comparator |
| #define M33_DWT_FUNCTION2_MATCH_RESET _u(0x0) |
| #define M33_DWT_FUNCTION2_MATCH_BITS _u(0x0000000f) |
| #define M33_DWT_FUNCTION2_MATCH_MSB _u(3) |
| #define M33_DWT_FUNCTION2_MATCH_LSB _u(0) |
| #define M33_DWT_FUNCTION2_MATCH_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_DWT_COMP3 |
| // Description : Provides a reference value for use by watchpoint comparator 3 |
| #define M33_DWT_COMP3_OFFSET _u(0x00001050) |
| #define M33_DWT_COMP3_BITS _u(0xffffffff) |
| #define M33_DWT_COMP3_RESET _u(0x00000000) |
| #define M33_DWT_COMP3_MSB _u(31) |
| #define M33_DWT_COMP3_LSB _u(0) |
| #define M33_DWT_COMP3_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_DWT_FUNCTION3 |
| // Description : Controls the operation of watchpoint comparator 3 |
| #define M33_DWT_FUNCTION3_OFFSET _u(0x00001058) |
| #define M33_DWT_FUNCTION3_BITS _u(0xf9000c3f) |
| #define M33_DWT_FUNCTION3_RESET _u(0x20000800) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION3_ID |
| // Description : Identifies the capabilities for MATCH for comparator *n |
| #define M33_DWT_FUNCTION3_ID_RESET _u(0x04) |
| #define M33_DWT_FUNCTION3_ID_BITS _u(0xf8000000) |
| #define M33_DWT_FUNCTION3_ID_MSB _u(31) |
| #define M33_DWT_FUNCTION3_ID_LSB _u(27) |
| #define M33_DWT_FUNCTION3_ID_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION3_MATCHED |
| // Description : Set to 1 when the comparator matches |
| #define M33_DWT_FUNCTION3_MATCHED_RESET _u(0x0) |
| #define M33_DWT_FUNCTION3_MATCHED_BITS _u(0x01000000) |
| #define M33_DWT_FUNCTION3_MATCHED_MSB _u(24) |
| #define M33_DWT_FUNCTION3_MATCHED_LSB _u(24) |
| #define M33_DWT_FUNCTION3_MATCHED_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION3_DATAVSIZE |
| // Description : Defines the size of the object being watched for by Data Value |
| // and Data Address comparators |
| #define M33_DWT_FUNCTION3_DATAVSIZE_RESET _u(0x2) |
| #define M33_DWT_FUNCTION3_DATAVSIZE_BITS _u(0x00000c00) |
| #define M33_DWT_FUNCTION3_DATAVSIZE_MSB _u(11) |
| #define M33_DWT_FUNCTION3_DATAVSIZE_LSB _u(10) |
| #define M33_DWT_FUNCTION3_DATAVSIZE_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION3_ACTION |
| // Description : Defines the action on a match. This field is ignored and the |
| // comparator generates no actions if it is disabled by MATCH |
| #define M33_DWT_FUNCTION3_ACTION_RESET _u(0x0) |
| #define M33_DWT_FUNCTION3_ACTION_BITS _u(0x00000030) |
| #define M33_DWT_FUNCTION3_ACTION_MSB _u(5) |
| #define M33_DWT_FUNCTION3_ACTION_LSB _u(4) |
| #define M33_DWT_FUNCTION3_ACTION_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_FUNCTION3_MATCH |
| // Description : Controls the type of match generated by this comparator |
| #define M33_DWT_FUNCTION3_MATCH_RESET _u(0x0) |
| #define M33_DWT_FUNCTION3_MATCH_BITS _u(0x0000000f) |
| #define M33_DWT_FUNCTION3_MATCH_MSB _u(3) |
| #define M33_DWT_FUNCTION3_MATCH_LSB _u(0) |
| #define M33_DWT_FUNCTION3_MATCH_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_DWT_DEVARCH |
| // Description : Provides CoreSight discovery information for the DWT |
| #define M33_DWT_DEVARCH_OFFSET _u(0x00001fbc) |
| #define M33_DWT_DEVARCH_BITS _u(0xffffffff) |
| #define M33_DWT_DEVARCH_RESET _u(0x47701a02) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_DEVARCH_ARCHITECT |
| // Description : Defines the architect of the component. Bits [31:28] are the |
| // JEP106 continuation code (JEP106 bank ID, minus 1) and bits |
| // [27:21] are the JEP106 ID code. |
| #define M33_DWT_DEVARCH_ARCHITECT_RESET _u(0x23b) |
| #define M33_DWT_DEVARCH_ARCHITECT_BITS _u(0xffe00000) |
| #define M33_DWT_DEVARCH_ARCHITECT_MSB _u(31) |
| #define M33_DWT_DEVARCH_ARCHITECT_LSB _u(21) |
| #define M33_DWT_DEVARCH_ARCHITECT_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_DEVARCH_PRESENT |
| // Description : Defines that the DEVARCH register is present |
| #define M33_DWT_DEVARCH_PRESENT_RESET _u(0x1) |
| #define M33_DWT_DEVARCH_PRESENT_BITS _u(0x00100000) |
| #define M33_DWT_DEVARCH_PRESENT_MSB _u(20) |
| #define M33_DWT_DEVARCH_PRESENT_LSB _u(20) |
| #define M33_DWT_DEVARCH_PRESENT_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_DEVARCH_REVISION |
| // Description : Defines the architecture revision of the component |
| #define M33_DWT_DEVARCH_REVISION_RESET _u(0x0) |
| #define M33_DWT_DEVARCH_REVISION_BITS _u(0x000f0000) |
| #define M33_DWT_DEVARCH_REVISION_MSB _u(19) |
| #define M33_DWT_DEVARCH_REVISION_LSB _u(16) |
| #define M33_DWT_DEVARCH_REVISION_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_DEVARCH_ARCHVER |
| // Description : Defines the architecture version of the component |
| #define M33_DWT_DEVARCH_ARCHVER_RESET _u(0x1) |
| #define M33_DWT_DEVARCH_ARCHVER_BITS _u(0x0000f000) |
| #define M33_DWT_DEVARCH_ARCHVER_MSB _u(15) |
| #define M33_DWT_DEVARCH_ARCHVER_LSB _u(12) |
| #define M33_DWT_DEVARCH_ARCHVER_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_DEVARCH_ARCHPART |
| // Description : Defines the architecture of the component |
| #define M33_DWT_DEVARCH_ARCHPART_RESET _u(0xa02) |
| #define M33_DWT_DEVARCH_ARCHPART_BITS _u(0x00000fff) |
| #define M33_DWT_DEVARCH_ARCHPART_MSB _u(11) |
| #define M33_DWT_DEVARCH_ARCHPART_LSB _u(0) |
| #define M33_DWT_DEVARCH_ARCHPART_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_DWT_DEVTYPE |
| // Description : Provides CoreSight discovery information for the DWT |
| #define M33_DWT_DEVTYPE_OFFSET _u(0x00001fcc) |
| #define M33_DWT_DEVTYPE_BITS _u(0x000000ff) |
| #define M33_DWT_DEVTYPE_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_DEVTYPE_SUB |
| // Description : Component sub-type |
| #define M33_DWT_DEVTYPE_SUB_RESET _u(0x0) |
| #define M33_DWT_DEVTYPE_SUB_BITS _u(0x000000f0) |
| #define M33_DWT_DEVTYPE_SUB_MSB _u(7) |
| #define M33_DWT_DEVTYPE_SUB_LSB _u(4) |
| #define M33_DWT_DEVTYPE_SUB_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_DEVTYPE_MAJOR |
| // Description : Component major type |
| #define M33_DWT_DEVTYPE_MAJOR_RESET _u(0x0) |
| #define M33_DWT_DEVTYPE_MAJOR_BITS _u(0x0000000f) |
| #define M33_DWT_DEVTYPE_MAJOR_MSB _u(3) |
| #define M33_DWT_DEVTYPE_MAJOR_LSB _u(0) |
| #define M33_DWT_DEVTYPE_MAJOR_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_DWT_PIDR4 |
| // Description : Provides CoreSight discovery information for the DWT |
| #define M33_DWT_PIDR4_OFFSET _u(0x00001fd0) |
| #define M33_DWT_PIDR4_BITS _u(0x000000ff) |
| #define M33_DWT_PIDR4_RESET _u(0x00000004) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_PIDR4_SIZE |
| // Description : See CoreSight Architecture Specification |
| #define M33_DWT_PIDR4_SIZE_RESET _u(0x0) |
| #define M33_DWT_PIDR4_SIZE_BITS _u(0x000000f0) |
| #define M33_DWT_PIDR4_SIZE_MSB _u(7) |
| #define M33_DWT_PIDR4_SIZE_LSB _u(4) |
| #define M33_DWT_PIDR4_SIZE_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_PIDR4_DES_2 |
| // Description : See CoreSight Architecture Specification |
| #define M33_DWT_PIDR4_DES_2_RESET _u(0x4) |
| #define M33_DWT_PIDR4_DES_2_BITS _u(0x0000000f) |
| #define M33_DWT_PIDR4_DES_2_MSB _u(3) |
| #define M33_DWT_PIDR4_DES_2_LSB _u(0) |
| #define M33_DWT_PIDR4_DES_2_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_DWT_PIDR5 |
| // Description : Provides CoreSight discovery information for the DWT |
| #define M33_DWT_PIDR5_OFFSET _u(0x00001fd4) |
| #define M33_DWT_PIDR5_BITS _u(0x00000000) |
| #define M33_DWT_PIDR5_RESET _u(0x00000000) |
| #define M33_DWT_PIDR5_MSB _u(31) |
| #define M33_DWT_PIDR5_LSB _u(0) |
| #define M33_DWT_PIDR5_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_DWT_PIDR6 |
| // Description : Provides CoreSight discovery information for the DWT |
| #define M33_DWT_PIDR6_OFFSET _u(0x00001fd8) |
| #define M33_DWT_PIDR6_BITS _u(0x00000000) |
| #define M33_DWT_PIDR6_RESET _u(0x00000000) |
| #define M33_DWT_PIDR6_MSB _u(31) |
| #define M33_DWT_PIDR6_LSB _u(0) |
| #define M33_DWT_PIDR6_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_DWT_PIDR7 |
| // Description : Provides CoreSight discovery information for the DWT |
| #define M33_DWT_PIDR7_OFFSET _u(0x00001fdc) |
| #define M33_DWT_PIDR7_BITS _u(0x00000000) |
| #define M33_DWT_PIDR7_RESET _u(0x00000000) |
| #define M33_DWT_PIDR7_MSB _u(31) |
| #define M33_DWT_PIDR7_LSB _u(0) |
| #define M33_DWT_PIDR7_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_DWT_PIDR0 |
| // Description : Provides CoreSight discovery information for the DWT |
| #define M33_DWT_PIDR0_OFFSET _u(0x00001fe0) |
| #define M33_DWT_PIDR0_BITS _u(0x000000ff) |
| #define M33_DWT_PIDR0_RESET _u(0x00000021) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_PIDR0_PART_0 |
| // Description : See CoreSight Architecture Specification |
| #define M33_DWT_PIDR0_PART_0_RESET _u(0x21) |
| #define M33_DWT_PIDR0_PART_0_BITS _u(0x000000ff) |
| #define M33_DWT_PIDR0_PART_0_MSB _u(7) |
| #define M33_DWT_PIDR0_PART_0_LSB _u(0) |
| #define M33_DWT_PIDR0_PART_0_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_DWT_PIDR1 |
| // Description : Provides CoreSight discovery information for the DWT |
| #define M33_DWT_PIDR1_OFFSET _u(0x00001fe4) |
| #define M33_DWT_PIDR1_BITS _u(0x000000ff) |
| #define M33_DWT_PIDR1_RESET _u(0x000000bd) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_PIDR1_DES_0 |
| // Description : See CoreSight Architecture Specification |
| #define M33_DWT_PIDR1_DES_0_RESET _u(0xb) |
| #define M33_DWT_PIDR1_DES_0_BITS _u(0x000000f0) |
| #define M33_DWT_PIDR1_DES_0_MSB _u(7) |
| #define M33_DWT_PIDR1_DES_0_LSB _u(4) |
| #define M33_DWT_PIDR1_DES_0_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_PIDR1_PART_1 |
| // Description : See CoreSight Architecture Specification |
| #define M33_DWT_PIDR1_PART_1_RESET _u(0xd) |
| #define M33_DWT_PIDR1_PART_1_BITS _u(0x0000000f) |
| #define M33_DWT_PIDR1_PART_1_MSB _u(3) |
| #define M33_DWT_PIDR1_PART_1_LSB _u(0) |
| #define M33_DWT_PIDR1_PART_1_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_DWT_PIDR2 |
| // Description : Provides CoreSight discovery information for the DWT |
| #define M33_DWT_PIDR2_OFFSET _u(0x00001fe8) |
| #define M33_DWT_PIDR2_BITS _u(0x000000ff) |
| #define M33_DWT_PIDR2_RESET _u(0x0000000b) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_PIDR2_REVISION |
| // Description : See CoreSight Architecture Specification |
| #define M33_DWT_PIDR2_REVISION_RESET _u(0x0) |
| #define M33_DWT_PIDR2_REVISION_BITS _u(0x000000f0) |
| #define M33_DWT_PIDR2_REVISION_MSB _u(7) |
| #define M33_DWT_PIDR2_REVISION_LSB _u(4) |
| #define M33_DWT_PIDR2_REVISION_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_PIDR2_JEDEC |
| // Description : See CoreSight Architecture Specification |
| #define M33_DWT_PIDR2_JEDEC_RESET _u(0x1) |
| #define M33_DWT_PIDR2_JEDEC_BITS _u(0x00000008) |
| #define M33_DWT_PIDR2_JEDEC_MSB _u(3) |
| #define M33_DWT_PIDR2_JEDEC_LSB _u(3) |
| #define M33_DWT_PIDR2_JEDEC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_PIDR2_DES_1 |
| // Description : See CoreSight Architecture Specification |
| #define M33_DWT_PIDR2_DES_1_RESET _u(0x3) |
| #define M33_DWT_PIDR2_DES_1_BITS _u(0x00000007) |
| #define M33_DWT_PIDR2_DES_1_MSB _u(2) |
| #define M33_DWT_PIDR2_DES_1_LSB _u(0) |
| #define M33_DWT_PIDR2_DES_1_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_DWT_PIDR3 |
| // Description : Provides CoreSight discovery information for the DWT |
| #define M33_DWT_PIDR3_OFFSET _u(0x00001fec) |
| #define M33_DWT_PIDR3_BITS _u(0x000000ff) |
| #define M33_DWT_PIDR3_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_PIDR3_REVAND |
| // Description : See CoreSight Architecture Specification |
| #define M33_DWT_PIDR3_REVAND_RESET _u(0x0) |
| #define M33_DWT_PIDR3_REVAND_BITS _u(0x000000f0) |
| #define M33_DWT_PIDR3_REVAND_MSB _u(7) |
| #define M33_DWT_PIDR3_REVAND_LSB _u(4) |
| #define M33_DWT_PIDR3_REVAND_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_PIDR3_CMOD |
| // Description : See CoreSight Architecture Specification |
| #define M33_DWT_PIDR3_CMOD_RESET _u(0x0) |
| #define M33_DWT_PIDR3_CMOD_BITS _u(0x0000000f) |
| #define M33_DWT_PIDR3_CMOD_MSB _u(3) |
| #define M33_DWT_PIDR3_CMOD_LSB _u(0) |
| #define M33_DWT_PIDR3_CMOD_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_DWT_CIDR0 |
| // Description : Provides CoreSight discovery information for the DWT |
| #define M33_DWT_CIDR0_OFFSET _u(0x00001ff0) |
| #define M33_DWT_CIDR0_BITS _u(0x000000ff) |
| #define M33_DWT_CIDR0_RESET _u(0x0000000d) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CIDR0_PRMBL_0 |
| // Description : See CoreSight Architecture Specification |
| #define M33_DWT_CIDR0_PRMBL_0_RESET _u(0x0d) |
| #define M33_DWT_CIDR0_PRMBL_0_BITS _u(0x000000ff) |
| #define M33_DWT_CIDR0_PRMBL_0_MSB _u(7) |
| #define M33_DWT_CIDR0_PRMBL_0_LSB _u(0) |
| #define M33_DWT_CIDR0_PRMBL_0_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_DWT_CIDR1 |
| // Description : Provides CoreSight discovery information for the DWT |
| #define M33_DWT_CIDR1_OFFSET _u(0x00001ff4) |
| #define M33_DWT_CIDR1_BITS _u(0x000000ff) |
| #define M33_DWT_CIDR1_RESET _u(0x00000090) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CIDR1_CLASS |
| // Description : See CoreSight Architecture Specification |
| #define M33_DWT_CIDR1_CLASS_RESET _u(0x9) |
| #define M33_DWT_CIDR1_CLASS_BITS _u(0x000000f0) |
| #define M33_DWT_CIDR1_CLASS_MSB _u(7) |
| #define M33_DWT_CIDR1_CLASS_LSB _u(4) |
| #define M33_DWT_CIDR1_CLASS_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CIDR1_PRMBL_1 |
| // Description : See CoreSight Architecture Specification |
| #define M33_DWT_CIDR1_PRMBL_1_RESET _u(0x0) |
| #define M33_DWT_CIDR1_PRMBL_1_BITS _u(0x0000000f) |
| #define M33_DWT_CIDR1_PRMBL_1_MSB _u(3) |
| #define M33_DWT_CIDR1_PRMBL_1_LSB _u(0) |
| #define M33_DWT_CIDR1_PRMBL_1_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_DWT_CIDR2 |
| // Description : Provides CoreSight discovery information for the DWT |
| #define M33_DWT_CIDR2_OFFSET _u(0x00001ff8) |
| #define M33_DWT_CIDR2_BITS _u(0x000000ff) |
| #define M33_DWT_CIDR2_RESET _u(0x00000005) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CIDR2_PRMBL_2 |
| // Description : See CoreSight Architecture Specification |
| #define M33_DWT_CIDR2_PRMBL_2_RESET _u(0x05) |
| #define M33_DWT_CIDR2_PRMBL_2_BITS _u(0x000000ff) |
| #define M33_DWT_CIDR2_PRMBL_2_MSB _u(7) |
| #define M33_DWT_CIDR2_PRMBL_2_LSB _u(0) |
| #define M33_DWT_CIDR2_PRMBL_2_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_DWT_CIDR3 |
| // Description : Provides CoreSight discovery information for the DWT |
| #define M33_DWT_CIDR3_OFFSET _u(0x00001ffc) |
| #define M33_DWT_CIDR3_BITS _u(0x000000ff) |
| #define M33_DWT_CIDR3_RESET _u(0x000000b1) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_DWT_CIDR3_PRMBL_3 |
| // Description : See CoreSight Architecture Specification |
| #define M33_DWT_CIDR3_PRMBL_3_RESET _u(0xb1) |
| #define M33_DWT_CIDR3_PRMBL_3_BITS _u(0x000000ff) |
| #define M33_DWT_CIDR3_PRMBL_3_MSB _u(7) |
| #define M33_DWT_CIDR3_PRMBL_3_LSB _u(0) |
| #define M33_DWT_CIDR3_PRMBL_3_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_FP_CTRL |
| // Description : Provides FPB implementation information, and the global enable |
| // for the FPB unit |
| #define M33_FP_CTRL_OFFSET _u(0x00002000) |
| #define M33_FP_CTRL_BITS _u(0xf0007ff3) |
| #define M33_FP_CTRL_RESET _u(0x60005580) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_CTRL_REV |
| // Description : Flash Patch and Breakpoint Unit architecture revision |
| #define M33_FP_CTRL_REV_RESET _u(0x6) |
| #define M33_FP_CTRL_REV_BITS _u(0xf0000000) |
| #define M33_FP_CTRL_REV_MSB _u(31) |
| #define M33_FP_CTRL_REV_LSB _u(28) |
| #define M33_FP_CTRL_REV_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_CTRL_NUM_CODE_14_12_ |
| // Description : Indicates the number of implemented instruction address |
| // comparators. Zero indicates no Instruction Address comparators |
| // are implemented. The Instruction Address comparators are |
| // numbered from 0 to NUM_CODE - 1 |
| #define M33_FP_CTRL_NUM_CODE_14_12__RESET _u(0x5) |
| #define M33_FP_CTRL_NUM_CODE_14_12__BITS _u(0x00007000) |
| #define M33_FP_CTRL_NUM_CODE_14_12__MSB _u(14) |
| #define M33_FP_CTRL_NUM_CODE_14_12__LSB _u(12) |
| #define M33_FP_CTRL_NUM_CODE_14_12__ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_CTRL_NUM_LIT |
| // Description : Indicates the number of implemented literal address |
| // comparators. The Literal Address comparators are numbered from |
| // NUM_CODE to NUM_CODE + NUM_LIT - 1 |
| #define M33_FP_CTRL_NUM_LIT_RESET _u(0x5) |
| #define M33_FP_CTRL_NUM_LIT_BITS _u(0x00000f00) |
| #define M33_FP_CTRL_NUM_LIT_MSB _u(11) |
| #define M33_FP_CTRL_NUM_LIT_LSB _u(8) |
| #define M33_FP_CTRL_NUM_LIT_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_CTRL_NUM_CODE_7_4_ |
| // Description : Indicates the number of implemented instruction address |
| // comparators. Zero indicates no Instruction Address comparators |
| // are implemented. The Instruction Address comparators are |
| // numbered from 0 to NUM_CODE - 1 |
| #define M33_FP_CTRL_NUM_CODE_7_4__RESET _u(0x8) |
| #define M33_FP_CTRL_NUM_CODE_7_4__BITS _u(0x000000f0) |
| #define M33_FP_CTRL_NUM_CODE_7_4__MSB _u(7) |
| #define M33_FP_CTRL_NUM_CODE_7_4__LSB _u(4) |
| #define M33_FP_CTRL_NUM_CODE_7_4__ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_CTRL_KEY |
| // Description : Writes to the FP_CTRL are ignored unless KEY is concurrently |
| // written to one |
| #define M33_FP_CTRL_KEY_RESET _u(0x0) |
| #define M33_FP_CTRL_KEY_BITS _u(0x00000002) |
| #define M33_FP_CTRL_KEY_MSB _u(1) |
| #define M33_FP_CTRL_KEY_LSB _u(1) |
| #define M33_FP_CTRL_KEY_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_CTRL_ENABLE |
| // Description : Enables the FPB |
| #define M33_FP_CTRL_ENABLE_RESET _u(0x0) |
| #define M33_FP_CTRL_ENABLE_BITS _u(0x00000001) |
| #define M33_FP_CTRL_ENABLE_MSB _u(0) |
| #define M33_FP_CTRL_ENABLE_LSB _u(0) |
| #define M33_FP_CTRL_ENABLE_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_FP_REMAP |
| // Description : Indicates whether the implementation supports Flash Patch remap |
| // and, if it does, holds the target address for remap |
| #define M33_FP_REMAP_OFFSET _u(0x00002004) |
| #define M33_FP_REMAP_BITS _u(0x3fffffe0) |
| #define M33_FP_REMAP_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_REMAP_RMPSPT |
| // Description : Indicates whether the FPB unit supports the Flash Patch remap |
| // function |
| #define M33_FP_REMAP_RMPSPT_RESET _u(0x0) |
| #define M33_FP_REMAP_RMPSPT_BITS _u(0x20000000) |
| #define M33_FP_REMAP_RMPSPT_MSB _u(29) |
| #define M33_FP_REMAP_RMPSPT_LSB _u(29) |
| #define M33_FP_REMAP_RMPSPT_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_REMAP_REMAP |
| // Description : Holds the bits[28:5] of the Flash Patch remap address |
| #define M33_FP_REMAP_REMAP_RESET _u(0x000000) |
| #define M33_FP_REMAP_REMAP_BITS _u(0x1fffffe0) |
| #define M33_FP_REMAP_REMAP_MSB _u(28) |
| #define M33_FP_REMAP_REMAP_LSB _u(5) |
| #define M33_FP_REMAP_REMAP_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_FP_COMP0 |
| // Description : Holds an address for comparison. The effect of the match |
| // depends on the configuration of the FPB and whether the |
| // comparator is an instruction address comparator or a literal |
| // address comparator |
| #define M33_FP_COMP0_OFFSET _u(0x00002008) |
| #define M33_FP_COMP0_BITS _u(0x00000001) |
| #define M33_FP_COMP0_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_COMP0_BE |
| // Description : Selects between flashpatch and breakpoint functionality |
| #define M33_FP_COMP0_BE_RESET _u(0x0) |
| #define M33_FP_COMP0_BE_BITS _u(0x00000001) |
| #define M33_FP_COMP0_BE_MSB _u(0) |
| #define M33_FP_COMP0_BE_LSB _u(0) |
| #define M33_FP_COMP0_BE_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_FP_COMP1 |
| // Description : Holds an address for comparison. The effect of the match |
| // depends on the configuration of the FPB and whether the |
| // comparator is an instruction address comparator or a literal |
| // address comparator |
| #define M33_FP_COMP1_OFFSET _u(0x0000200c) |
| #define M33_FP_COMP1_BITS _u(0x00000001) |
| #define M33_FP_COMP1_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_COMP1_BE |
| // Description : Selects between flashpatch and breakpoint functionality |
| #define M33_FP_COMP1_BE_RESET _u(0x0) |
| #define M33_FP_COMP1_BE_BITS _u(0x00000001) |
| #define M33_FP_COMP1_BE_MSB _u(0) |
| #define M33_FP_COMP1_BE_LSB _u(0) |
| #define M33_FP_COMP1_BE_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_FP_COMP2 |
| // Description : Holds an address for comparison. The effect of the match |
| // depends on the configuration of the FPB and whether the |
| // comparator is an instruction address comparator or a literal |
| // address comparator |
| #define M33_FP_COMP2_OFFSET _u(0x00002010) |
| #define M33_FP_COMP2_BITS _u(0x00000001) |
| #define M33_FP_COMP2_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_COMP2_BE |
| // Description : Selects between flashpatch and breakpoint functionality |
| #define M33_FP_COMP2_BE_RESET _u(0x0) |
| #define M33_FP_COMP2_BE_BITS _u(0x00000001) |
| #define M33_FP_COMP2_BE_MSB _u(0) |
| #define M33_FP_COMP2_BE_LSB _u(0) |
| #define M33_FP_COMP2_BE_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_FP_COMP3 |
| // Description : Holds an address for comparison. The effect of the match |
| // depends on the configuration of the FPB and whether the |
| // comparator is an instruction address comparator or a literal |
| // address comparator |
| #define M33_FP_COMP3_OFFSET _u(0x00002014) |
| #define M33_FP_COMP3_BITS _u(0x00000001) |
| #define M33_FP_COMP3_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_COMP3_BE |
| // Description : Selects between flashpatch and breakpoint functionality |
| #define M33_FP_COMP3_BE_RESET _u(0x0) |
| #define M33_FP_COMP3_BE_BITS _u(0x00000001) |
| #define M33_FP_COMP3_BE_MSB _u(0) |
| #define M33_FP_COMP3_BE_LSB _u(0) |
| #define M33_FP_COMP3_BE_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_FP_COMP4 |
| // Description : Holds an address for comparison. The effect of the match |
| // depends on the configuration of the FPB and whether the |
| // comparator is an instruction address comparator or a literal |
| // address comparator |
| #define M33_FP_COMP4_OFFSET _u(0x00002018) |
| #define M33_FP_COMP4_BITS _u(0x00000001) |
| #define M33_FP_COMP4_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_COMP4_BE |
| // Description : Selects between flashpatch and breakpoint functionality |
| #define M33_FP_COMP4_BE_RESET _u(0x0) |
| #define M33_FP_COMP4_BE_BITS _u(0x00000001) |
| #define M33_FP_COMP4_BE_MSB _u(0) |
| #define M33_FP_COMP4_BE_LSB _u(0) |
| #define M33_FP_COMP4_BE_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_FP_COMP5 |
| // Description : Holds an address for comparison. The effect of the match |
| // depends on the configuration of the FPB and whether the |
| // comparator is an instruction address comparator or a literal |
| // address comparator |
| #define M33_FP_COMP5_OFFSET _u(0x0000201c) |
| #define M33_FP_COMP5_BITS _u(0x00000001) |
| #define M33_FP_COMP5_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_COMP5_BE |
| // Description : Selects between flashpatch and breakpoint functionality |
| #define M33_FP_COMP5_BE_RESET _u(0x0) |
| #define M33_FP_COMP5_BE_BITS _u(0x00000001) |
| #define M33_FP_COMP5_BE_MSB _u(0) |
| #define M33_FP_COMP5_BE_LSB _u(0) |
| #define M33_FP_COMP5_BE_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_FP_COMP6 |
| // Description : Holds an address for comparison. The effect of the match |
| // depends on the configuration of the FPB and whether the |
| // comparator is an instruction address comparator or a literal |
| // address comparator |
| #define M33_FP_COMP6_OFFSET _u(0x00002020) |
| #define M33_FP_COMP6_BITS _u(0x00000001) |
| #define M33_FP_COMP6_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_COMP6_BE |
| // Description : Selects between flashpatch and breakpoint functionality |
| #define M33_FP_COMP6_BE_RESET _u(0x0) |
| #define M33_FP_COMP6_BE_BITS _u(0x00000001) |
| #define M33_FP_COMP6_BE_MSB _u(0) |
| #define M33_FP_COMP6_BE_LSB _u(0) |
| #define M33_FP_COMP6_BE_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_FP_COMP7 |
| // Description : Holds an address for comparison. The effect of the match |
| // depends on the configuration of the FPB and whether the |
| // comparator is an instruction address comparator or a literal |
| // address comparator |
| #define M33_FP_COMP7_OFFSET _u(0x00002024) |
| #define M33_FP_COMP7_BITS _u(0x00000001) |
| #define M33_FP_COMP7_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_COMP7_BE |
| // Description : Selects between flashpatch and breakpoint functionality |
| #define M33_FP_COMP7_BE_RESET _u(0x0) |
| #define M33_FP_COMP7_BE_BITS _u(0x00000001) |
| #define M33_FP_COMP7_BE_MSB _u(0) |
| #define M33_FP_COMP7_BE_LSB _u(0) |
| #define M33_FP_COMP7_BE_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_FP_DEVARCH |
| // Description : Provides CoreSight discovery information for the FPB |
| #define M33_FP_DEVARCH_OFFSET _u(0x00002fbc) |
| #define M33_FP_DEVARCH_BITS _u(0xffffffff) |
| #define M33_FP_DEVARCH_RESET _u(0x47701a03) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_DEVARCH_ARCHITECT |
| // Description : Defines the architect of the component. Bits [31:28] are the |
| // JEP106 continuation code (JEP106 bank ID, minus 1) and bits |
| // [27:21] are the JEP106 ID code. |
| #define M33_FP_DEVARCH_ARCHITECT_RESET _u(0x23b) |
| #define M33_FP_DEVARCH_ARCHITECT_BITS _u(0xffe00000) |
| #define M33_FP_DEVARCH_ARCHITECT_MSB _u(31) |
| #define M33_FP_DEVARCH_ARCHITECT_LSB _u(21) |
| #define M33_FP_DEVARCH_ARCHITECT_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_DEVARCH_PRESENT |
| // Description : Defines that the DEVARCH register is present |
| #define M33_FP_DEVARCH_PRESENT_RESET _u(0x1) |
| #define M33_FP_DEVARCH_PRESENT_BITS _u(0x00100000) |
| #define M33_FP_DEVARCH_PRESENT_MSB _u(20) |
| #define M33_FP_DEVARCH_PRESENT_LSB _u(20) |
| #define M33_FP_DEVARCH_PRESENT_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_DEVARCH_REVISION |
| // Description : Defines the architecture revision of the component |
| #define M33_FP_DEVARCH_REVISION_RESET _u(0x0) |
| #define M33_FP_DEVARCH_REVISION_BITS _u(0x000f0000) |
| #define M33_FP_DEVARCH_REVISION_MSB _u(19) |
| #define M33_FP_DEVARCH_REVISION_LSB _u(16) |
| #define M33_FP_DEVARCH_REVISION_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_DEVARCH_ARCHVER |
| // Description : Defines the architecture version of the component |
| #define M33_FP_DEVARCH_ARCHVER_RESET _u(0x1) |
| #define M33_FP_DEVARCH_ARCHVER_BITS _u(0x0000f000) |
| #define M33_FP_DEVARCH_ARCHVER_MSB _u(15) |
| #define M33_FP_DEVARCH_ARCHVER_LSB _u(12) |
| #define M33_FP_DEVARCH_ARCHVER_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_DEVARCH_ARCHPART |
| // Description : Defines the architecture of the component |
| #define M33_FP_DEVARCH_ARCHPART_RESET _u(0xa03) |
| #define M33_FP_DEVARCH_ARCHPART_BITS _u(0x00000fff) |
| #define M33_FP_DEVARCH_ARCHPART_MSB _u(11) |
| #define M33_FP_DEVARCH_ARCHPART_LSB _u(0) |
| #define M33_FP_DEVARCH_ARCHPART_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_FP_DEVTYPE |
| // Description : Provides CoreSight discovery information for the FPB |
| #define M33_FP_DEVTYPE_OFFSET _u(0x00002fcc) |
| #define M33_FP_DEVTYPE_BITS _u(0x000000ff) |
| #define M33_FP_DEVTYPE_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_DEVTYPE_SUB |
| // Description : Component sub-type |
| #define M33_FP_DEVTYPE_SUB_RESET _u(0x0) |
| #define M33_FP_DEVTYPE_SUB_BITS _u(0x000000f0) |
| #define M33_FP_DEVTYPE_SUB_MSB _u(7) |
| #define M33_FP_DEVTYPE_SUB_LSB _u(4) |
| #define M33_FP_DEVTYPE_SUB_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_DEVTYPE_MAJOR |
| // Description : Component major type |
| #define M33_FP_DEVTYPE_MAJOR_RESET _u(0x0) |
| #define M33_FP_DEVTYPE_MAJOR_BITS _u(0x0000000f) |
| #define M33_FP_DEVTYPE_MAJOR_MSB _u(3) |
| #define M33_FP_DEVTYPE_MAJOR_LSB _u(0) |
| #define M33_FP_DEVTYPE_MAJOR_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_FP_PIDR4 |
| // Description : Provides CoreSight discovery information for the FP |
| #define M33_FP_PIDR4_OFFSET _u(0x00002fd0) |
| #define M33_FP_PIDR4_BITS _u(0x000000ff) |
| #define M33_FP_PIDR4_RESET _u(0x00000004) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_PIDR4_SIZE |
| // Description : See CoreSight Architecture Specification |
| #define M33_FP_PIDR4_SIZE_RESET _u(0x0) |
| #define M33_FP_PIDR4_SIZE_BITS _u(0x000000f0) |
| #define M33_FP_PIDR4_SIZE_MSB _u(7) |
| #define M33_FP_PIDR4_SIZE_LSB _u(4) |
| #define M33_FP_PIDR4_SIZE_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_PIDR4_DES_2 |
| // Description : See CoreSight Architecture Specification |
| #define M33_FP_PIDR4_DES_2_RESET _u(0x4) |
| #define M33_FP_PIDR4_DES_2_BITS _u(0x0000000f) |
| #define M33_FP_PIDR4_DES_2_MSB _u(3) |
| #define M33_FP_PIDR4_DES_2_LSB _u(0) |
| #define M33_FP_PIDR4_DES_2_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_FP_PIDR5 |
| // Description : Provides CoreSight discovery information for the FP |
| #define M33_FP_PIDR5_OFFSET _u(0x00002fd4) |
| #define M33_FP_PIDR5_BITS _u(0x00000000) |
| #define M33_FP_PIDR5_RESET _u(0x00000000) |
| #define M33_FP_PIDR5_MSB _u(31) |
| #define M33_FP_PIDR5_LSB _u(0) |
| #define M33_FP_PIDR5_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_FP_PIDR6 |
| // Description : Provides CoreSight discovery information for the FP |
| #define M33_FP_PIDR6_OFFSET _u(0x00002fd8) |
| #define M33_FP_PIDR6_BITS _u(0x00000000) |
| #define M33_FP_PIDR6_RESET _u(0x00000000) |
| #define M33_FP_PIDR6_MSB _u(31) |
| #define M33_FP_PIDR6_LSB _u(0) |
| #define M33_FP_PIDR6_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_FP_PIDR7 |
| // Description : Provides CoreSight discovery information for the FP |
| #define M33_FP_PIDR7_OFFSET _u(0x00002fdc) |
| #define M33_FP_PIDR7_BITS _u(0x00000000) |
| #define M33_FP_PIDR7_RESET _u(0x00000000) |
| #define M33_FP_PIDR7_MSB _u(31) |
| #define M33_FP_PIDR7_LSB _u(0) |
| #define M33_FP_PIDR7_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_FP_PIDR0 |
| // Description : Provides CoreSight discovery information for the FP |
| #define M33_FP_PIDR0_OFFSET _u(0x00002fe0) |
| #define M33_FP_PIDR0_BITS _u(0x000000ff) |
| #define M33_FP_PIDR0_RESET _u(0x00000021) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_PIDR0_PART_0 |
| // Description : See CoreSight Architecture Specification |
| #define M33_FP_PIDR0_PART_0_RESET _u(0x21) |
| #define M33_FP_PIDR0_PART_0_BITS _u(0x000000ff) |
| #define M33_FP_PIDR0_PART_0_MSB _u(7) |
| #define M33_FP_PIDR0_PART_0_LSB _u(0) |
| #define M33_FP_PIDR0_PART_0_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_FP_PIDR1 |
| // Description : Provides CoreSight discovery information for the FP |
| #define M33_FP_PIDR1_OFFSET _u(0x00002fe4) |
| #define M33_FP_PIDR1_BITS _u(0x000000ff) |
| #define M33_FP_PIDR1_RESET _u(0x000000bd) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_PIDR1_DES_0 |
| // Description : See CoreSight Architecture Specification |
| #define M33_FP_PIDR1_DES_0_RESET _u(0xb) |
| #define M33_FP_PIDR1_DES_0_BITS _u(0x000000f0) |
| #define M33_FP_PIDR1_DES_0_MSB _u(7) |
| #define M33_FP_PIDR1_DES_0_LSB _u(4) |
| #define M33_FP_PIDR1_DES_0_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_PIDR1_PART_1 |
| // Description : See CoreSight Architecture Specification |
| #define M33_FP_PIDR1_PART_1_RESET _u(0xd) |
| #define M33_FP_PIDR1_PART_1_BITS _u(0x0000000f) |
| #define M33_FP_PIDR1_PART_1_MSB _u(3) |
| #define M33_FP_PIDR1_PART_1_LSB _u(0) |
| #define M33_FP_PIDR1_PART_1_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_FP_PIDR2 |
| // Description : Provides CoreSight discovery information for the FP |
| #define M33_FP_PIDR2_OFFSET _u(0x00002fe8) |
| #define M33_FP_PIDR2_BITS _u(0x000000ff) |
| #define M33_FP_PIDR2_RESET _u(0x0000000b) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_PIDR2_REVISION |
| // Description : See CoreSight Architecture Specification |
| #define M33_FP_PIDR2_REVISION_RESET _u(0x0) |
| #define M33_FP_PIDR2_REVISION_BITS _u(0x000000f0) |
| #define M33_FP_PIDR2_REVISION_MSB _u(7) |
| #define M33_FP_PIDR2_REVISION_LSB _u(4) |
| #define M33_FP_PIDR2_REVISION_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_PIDR2_JEDEC |
| // Description : See CoreSight Architecture Specification |
| #define M33_FP_PIDR2_JEDEC_RESET _u(0x1) |
| #define M33_FP_PIDR2_JEDEC_BITS _u(0x00000008) |
| #define M33_FP_PIDR2_JEDEC_MSB _u(3) |
| #define M33_FP_PIDR2_JEDEC_LSB _u(3) |
| #define M33_FP_PIDR2_JEDEC_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_PIDR2_DES_1 |
| // Description : See CoreSight Architecture Specification |
| #define M33_FP_PIDR2_DES_1_RESET _u(0x3) |
| #define M33_FP_PIDR2_DES_1_BITS _u(0x00000007) |
| #define M33_FP_PIDR2_DES_1_MSB _u(2) |
| #define M33_FP_PIDR2_DES_1_LSB _u(0) |
| #define M33_FP_PIDR2_DES_1_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_FP_PIDR3 |
| // Description : Provides CoreSight discovery information for the FP |
| #define M33_FP_PIDR3_OFFSET _u(0x00002fec) |
| #define M33_FP_PIDR3_BITS _u(0x000000ff) |
| #define M33_FP_PIDR3_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_PIDR3_REVAND |
| // Description : See CoreSight Architecture Specification |
| #define M33_FP_PIDR3_REVAND_RESET _u(0x0) |
| #define M33_FP_PIDR3_REVAND_BITS _u(0x000000f0) |
| #define M33_FP_PIDR3_REVAND_MSB _u(7) |
| #define M33_FP_PIDR3_REVAND_LSB _u(4) |
| #define M33_FP_PIDR3_REVAND_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_PIDR3_CMOD |
| // Description : See CoreSight Architecture Specification |
| #define M33_FP_PIDR3_CMOD_RESET _u(0x0) |
| #define M33_FP_PIDR3_CMOD_BITS _u(0x0000000f) |
| #define M33_FP_PIDR3_CMOD_MSB _u(3) |
| #define M33_FP_PIDR3_CMOD_LSB _u(0) |
| #define M33_FP_PIDR3_CMOD_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_FP_CIDR0 |
| // Description : Provides CoreSight discovery information for the FP |
| #define M33_FP_CIDR0_OFFSET _u(0x00002ff0) |
| #define M33_FP_CIDR0_BITS _u(0x000000ff) |
| #define M33_FP_CIDR0_RESET _u(0x0000000d) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_CIDR0_PRMBL_0 |
| // Description : See CoreSight Architecture Specification |
| #define M33_FP_CIDR0_PRMBL_0_RESET _u(0x0d) |
| #define M33_FP_CIDR0_PRMBL_0_BITS _u(0x000000ff) |
| #define M33_FP_CIDR0_PRMBL_0_MSB _u(7) |
| #define M33_FP_CIDR0_PRMBL_0_LSB _u(0) |
| #define M33_FP_CIDR0_PRMBL_0_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_FP_CIDR1 |
| // Description : Provides CoreSight discovery information for the FP |
| #define M33_FP_CIDR1_OFFSET _u(0x00002ff4) |
| #define M33_FP_CIDR1_BITS _u(0x000000ff) |
| #define M33_FP_CIDR1_RESET _u(0x00000090) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_CIDR1_CLASS |
| // Description : See CoreSight Architecture Specification |
| #define M33_FP_CIDR1_CLASS_RESET _u(0x9) |
| #define M33_FP_CIDR1_CLASS_BITS _u(0x000000f0) |
| #define M33_FP_CIDR1_CLASS_MSB _u(7) |
| #define M33_FP_CIDR1_CLASS_LSB _u(4) |
| #define M33_FP_CIDR1_CLASS_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_CIDR1_PRMBL_1 |
| // Description : See CoreSight Architecture Specification |
| #define M33_FP_CIDR1_PRMBL_1_RESET _u(0x0) |
| #define M33_FP_CIDR1_PRMBL_1_BITS _u(0x0000000f) |
| #define M33_FP_CIDR1_PRMBL_1_MSB _u(3) |
| #define M33_FP_CIDR1_PRMBL_1_LSB _u(0) |
| #define M33_FP_CIDR1_PRMBL_1_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_FP_CIDR2 |
| // Description : Provides CoreSight discovery information for the FP |
| #define M33_FP_CIDR2_OFFSET _u(0x00002ff8) |
| #define M33_FP_CIDR2_BITS _u(0x000000ff) |
| #define M33_FP_CIDR2_RESET _u(0x00000005) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_CIDR2_PRMBL_2 |
| // Description : See CoreSight Architecture Specification |
| #define M33_FP_CIDR2_PRMBL_2_RESET _u(0x05) |
| #define M33_FP_CIDR2_PRMBL_2_BITS _u(0x000000ff) |
| #define M33_FP_CIDR2_PRMBL_2_MSB _u(7) |
| #define M33_FP_CIDR2_PRMBL_2_LSB _u(0) |
| #define M33_FP_CIDR2_PRMBL_2_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_FP_CIDR3 |
| // Description : Provides CoreSight discovery information for the FP |
| #define M33_FP_CIDR3_OFFSET _u(0x00002ffc) |
| #define M33_FP_CIDR3_BITS _u(0x000000ff) |
| #define M33_FP_CIDR3_RESET _u(0x000000b1) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_FP_CIDR3_PRMBL_3 |
| // Description : See CoreSight Architecture Specification |
| #define M33_FP_CIDR3_PRMBL_3_RESET _u(0xb1) |
| #define M33_FP_CIDR3_PRMBL_3_BITS _u(0x000000ff) |
| #define M33_FP_CIDR3_PRMBL_3_MSB _u(7) |
| #define M33_FP_CIDR3_PRMBL_3_LSB _u(0) |
| #define M33_FP_CIDR3_PRMBL_3_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_ICTR |
| // Description : Provides information about the interrupt controller |
| #define M33_ICTR_OFFSET _u(0x0000e004) |
| #define M33_ICTR_BITS _u(0x0000000f) |
| #define M33_ICTR_RESET _u(0x00000001) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ICTR_INTLINESNUM |
| // Description : Indicates the number of the highest implemented register in |
| // each of the NVIC control register sets, or in the case of |
| // NVIC_IPR*n, 4×INTLINESNUM |
| #define M33_ICTR_INTLINESNUM_RESET _u(0x1) |
| #define M33_ICTR_INTLINESNUM_BITS _u(0x0000000f) |
| #define M33_ICTR_INTLINESNUM_MSB _u(3) |
| #define M33_ICTR_INTLINESNUM_LSB _u(0) |
| #define M33_ICTR_INTLINESNUM_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_ACTLR |
| // Description : Provides IMPLEMENTATION DEFINED configuration and control |
| // options |
| #define M33_ACTLR_OFFSET _u(0x0000e008) |
| #define M33_ACTLR_BITS _u(0x20001605) |
| #define M33_ACTLR_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ACTLR_EXTEXCLALL |
| // Description : External Exclusives Allowed with no MPU |
| #define M33_ACTLR_EXTEXCLALL_RESET _u(0x0) |
| #define M33_ACTLR_EXTEXCLALL_BITS _u(0x20000000) |
| #define M33_ACTLR_EXTEXCLALL_MSB _u(29) |
| #define M33_ACTLR_EXTEXCLALL_LSB _u(29) |
| #define M33_ACTLR_EXTEXCLALL_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ACTLR_DISITMATBFLUSH |
| // Description : Disable ATB Flush |
| #define M33_ACTLR_DISITMATBFLUSH_RESET _u(0x0) |
| #define M33_ACTLR_DISITMATBFLUSH_BITS _u(0x00001000) |
| #define M33_ACTLR_DISITMATBFLUSH_MSB _u(12) |
| #define M33_ACTLR_DISITMATBFLUSH_LSB _u(12) |
| #define M33_ACTLR_DISITMATBFLUSH_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ACTLR_FPEXCODIS |
| // Description : Disable FPU exception outputs |
| #define M33_ACTLR_FPEXCODIS_RESET _u(0x0) |
| #define M33_ACTLR_FPEXCODIS_BITS _u(0x00000400) |
| #define M33_ACTLR_FPEXCODIS_MSB _u(10) |
| #define M33_ACTLR_FPEXCODIS_LSB _u(10) |
| #define M33_ACTLR_FPEXCODIS_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ACTLR_DISOOFP |
| // Description : Disable out-of-order FP instruction completion |
| #define M33_ACTLR_DISOOFP_RESET _u(0x0) |
| #define M33_ACTLR_DISOOFP_BITS _u(0x00000200) |
| #define M33_ACTLR_DISOOFP_MSB _u(9) |
| #define M33_ACTLR_DISOOFP_LSB _u(9) |
| #define M33_ACTLR_DISOOFP_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ACTLR_DISFOLD |
| // Description : Disable dual-issue. |
| #define M33_ACTLR_DISFOLD_RESET _u(0x0) |
| #define M33_ACTLR_DISFOLD_BITS _u(0x00000004) |
| #define M33_ACTLR_DISFOLD_MSB _u(2) |
| #define M33_ACTLR_DISFOLD_LSB _u(2) |
| #define M33_ACTLR_DISFOLD_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_ACTLR_DISMCYCINT |
| // Description : Disable dual-issue. |
| #define M33_ACTLR_DISMCYCINT_RESET _u(0x0) |
| #define M33_ACTLR_DISMCYCINT_BITS _u(0x00000001) |
| #define M33_ACTLR_DISMCYCINT_MSB _u(0) |
| #define M33_ACTLR_DISMCYCINT_LSB _u(0) |
| #define M33_ACTLR_DISMCYCINT_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_SYST_CSR |
| // Description : Use the SysTick Control and Status Register to enable the |
| // SysTick features. |
| #define M33_SYST_CSR_OFFSET _u(0x0000e010) |
| #define M33_SYST_CSR_BITS _u(0x00010007) |
| #define M33_SYST_CSR_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_SYST_CSR_COUNTFLAG |
| // Description : Returns 1 if timer counted to 0 since last time this was read. |
| // Clears on read by application or debugger. |
| #define M33_SYST_CSR_COUNTFLAG_RESET _u(0x0) |
| #define M33_SYST_CSR_COUNTFLAG_BITS _u(0x00010000) |
| #define M33_SYST_CSR_COUNTFLAG_MSB _u(16) |
| #define M33_SYST_CSR_COUNTFLAG_LSB _u(16) |
| #define M33_SYST_CSR_COUNTFLAG_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_SYST_CSR_CLKSOURCE |
| // Description : SysTick clock source. Always reads as one if SYST_CALIB reports |
| // NOREF. |
| // Selects the SysTick timer clock source: |
| // 0 = External reference clock. |
| // 1 = Processor clock. |
| #define M33_SYST_CSR_CLKSOURCE_RESET _u(0x0) |
| #define M33_SYST_CSR_CLKSOURCE_BITS _u(0x00000004) |
| #define M33_SYST_CSR_CLKSOURCE_MSB _u(2) |
| #define M33_SYST_CSR_CLKSOURCE_LSB _u(2) |
| #define M33_SYST_CSR_CLKSOURCE_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_SYST_CSR_TICKINT |
| // Description : Enables SysTick exception request: |
| // 0 = Counting down to zero does not assert the SysTick exception |
| // request. |
| // 1 = Counting down to zero to asserts the SysTick exception |
| // request. |
| #define M33_SYST_CSR_TICKINT_RESET _u(0x0) |
| #define M33_SYST_CSR_TICKINT_BITS _u(0x00000002) |
| #define M33_SYST_CSR_TICKINT_MSB _u(1) |
| #define M33_SYST_CSR_TICKINT_LSB _u(1) |
| #define M33_SYST_CSR_TICKINT_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_SYST_CSR_ENABLE |
| // Description : Enable SysTick counter: |
| // 0 = Counter disabled. |
| // 1 = Counter enabled. |
| #define M33_SYST_CSR_ENABLE_RESET _u(0x0) |
| #define M33_SYST_CSR_ENABLE_BITS _u(0x00000001) |
| #define M33_SYST_CSR_ENABLE_MSB _u(0) |
| #define M33_SYST_CSR_ENABLE_LSB _u(0) |
| #define M33_SYST_CSR_ENABLE_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_SYST_RVR |
| // Description : Use the SysTick Reload Value Register to specify the start |
| // value to load into the current value register when the counter |
| // reaches 0. It can be any value between 0 and 0x00FFFFFF. A |
| // start value of 0 is possible, but has no effect because the |
| // SysTick interrupt and COUNTFLAG are activated when counting |
| // from 1 to 0. The reset value of this register is UNKNOWN. |
| // To generate a multi-shot timer with a period of N processor |
| // clock cycles, use a RELOAD value of N-1. For example, if the |
| // SysTick interrupt is required every 100 clock pulses, set |
| // RELOAD to 99. |
| #define M33_SYST_RVR_OFFSET _u(0x0000e014) |
| #define M33_SYST_RVR_BITS _u(0x00ffffff) |
| #define M33_SYST_RVR_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_SYST_RVR_RELOAD |
| // Description : Value to load into the SysTick Current Value Register when the |
| // counter reaches 0. |
| #define M33_SYST_RVR_RELOAD_RESET _u(0x000000) |
| #define M33_SYST_RVR_RELOAD_BITS _u(0x00ffffff) |
| #define M33_SYST_RVR_RELOAD_MSB _u(23) |
| #define M33_SYST_RVR_RELOAD_LSB _u(0) |
| #define M33_SYST_RVR_RELOAD_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_SYST_CVR |
| // Description : Use the SysTick Current Value Register to find the current |
| // value in the register. The reset value of this register is |
| // UNKNOWN. |
| #define M33_SYST_CVR_OFFSET _u(0x0000e018) |
| #define M33_SYST_CVR_BITS _u(0x00ffffff) |
| #define M33_SYST_CVR_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_SYST_CVR_CURRENT |
| // Description : Reads return the current value of the SysTick counter. This |
| // register is write-clear. Writing to it with any value clears |
| // the register to 0. Clearing this register also clears the |
| // COUNTFLAG bit of the SysTick Control and Status Register. |
| #define M33_SYST_CVR_CURRENT_RESET _u(0x000000) |
| #define M33_SYST_CVR_CURRENT_BITS _u(0x00ffffff) |
| #define M33_SYST_CVR_CURRENT_MSB _u(23) |
| #define M33_SYST_CVR_CURRENT_LSB _u(0) |
| #define M33_SYST_CVR_CURRENT_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_SYST_CALIB |
| // Description : Use the SysTick Calibration Value Register to enable software |
| // to scale to any required speed using divide and multiply. |
| #define M33_SYST_CALIB_OFFSET _u(0x0000e01c) |
| #define M33_SYST_CALIB_BITS _u(0xc0ffffff) |
| #define M33_SYST_CALIB_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_SYST_CALIB_NOREF |
| // Description : If reads as 1, the Reference clock is not provided - the |
| // CLKSOURCE bit of the SysTick Control and Status register will |
| // be forced to 1 and cannot be cleared to 0. |
| #define M33_SYST_CALIB_NOREF_RESET _u(0x0) |
| #define M33_SYST_CALIB_NOREF_BITS _u(0x80000000) |
| #define M33_SYST_CALIB_NOREF_MSB _u(31) |
| #define M33_SYST_CALIB_NOREF_LSB _u(31) |
| #define M33_SYST_CALIB_NOREF_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_SYST_CALIB_SKEW |
| // Description : If reads as 1, the calibration value for 10ms is inexact (due |
| // to clock frequency). |
| #define M33_SYST_CALIB_SKEW_RESET _u(0x0) |
| #define M33_SYST_CALIB_SKEW_BITS _u(0x40000000) |
| #define M33_SYST_CALIB_SKEW_MSB _u(30) |
| #define M33_SYST_CALIB_SKEW_LSB _u(30) |
| #define M33_SYST_CALIB_SKEW_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_SYST_CALIB_TENMS |
| // Description : An optional Reload value to be used for 10ms (100Hz) timing, |
| // subject to system clock skew errors. If the value reads as 0, |
| // the calibration value is not known. |
| #define M33_SYST_CALIB_TENMS_RESET _u(0x000000) |
| #define M33_SYST_CALIB_TENMS_BITS _u(0x00ffffff) |
| #define M33_SYST_CALIB_TENMS_MSB _u(23) |
| #define M33_SYST_CALIB_TENMS_LSB _u(0) |
| #define M33_SYST_CALIB_TENMS_ACCESS "RO" |
| // ============================================================================= |
| // Register : M33_NVIC_ISER0 |
| // Description : Enables or reads the enabled state of each group of 32 |
| // interrupts |
| #define M33_NVIC_ISER0_OFFSET _u(0x0000e100) |
| #define M33_NVIC_ISER0_BITS _u(0xffffffff) |
| #define M33_NVIC_ISER0_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_ISER0_SETENA |
| // Description : For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n |
| // + m is enabled |
| #define M33_NVIC_ISER0_SETENA_RESET _u(0x00000000) |
| #define M33_NVIC_ISER0_SETENA_BITS _u(0xffffffff) |
| #define M33_NVIC_ISER0_SETENA_MSB _u(31) |
| #define M33_NVIC_ISER0_SETENA_LSB _u(0) |
| #define M33_NVIC_ISER0_SETENA_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_ISER1 |
| // Description : Enables or reads the enabled state of each group of 32 |
| // interrupts |
| #define M33_NVIC_ISER1_OFFSET _u(0x0000e104) |
| #define M33_NVIC_ISER1_BITS _u(0xffffffff) |
| #define M33_NVIC_ISER1_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_ISER1_SETENA |
| // Description : For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n |
| // + m is enabled |
| #define M33_NVIC_ISER1_SETENA_RESET _u(0x00000000) |
| #define M33_NVIC_ISER1_SETENA_BITS _u(0xffffffff) |
| #define M33_NVIC_ISER1_SETENA_MSB _u(31) |
| #define M33_NVIC_ISER1_SETENA_LSB _u(0) |
| #define M33_NVIC_ISER1_SETENA_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_ICER0 |
| // Description : Clears or reads the enabled state of each group of 32 |
| // interrupts |
| #define M33_NVIC_ICER0_OFFSET _u(0x0000e180) |
| #define M33_NVIC_ICER0_BITS _u(0xffffffff) |
| #define M33_NVIC_ICER0_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_ICER0_CLRENA |
| // Description : For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n |
| // + m is enabled |
| #define M33_NVIC_ICER0_CLRENA_RESET _u(0x00000000) |
| #define M33_NVIC_ICER0_CLRENA_BITS _u(0xffffffff) |
| #define M33_NVIC_ICER0_CLRENA_MSB _u(31) |
| #define M33_NVIC_ICER0_CLRENA_LSB _u(0) |
| #define M33_NVIC_ICER0_CLRENA_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_ICER1 |
| // Description : Clears or reads the enabled state of each group of 32 |
| // interrupts |
| #define M33_NVIC_ICER1_OFFSET _u(0x0000e184) |
| #define M33_NVIC_ICER1_BITS _u(0xffffffff) |
| #define M33_NVIC_ICER1_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_ICER1_CLRENA |
| // Description : For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n |
| // + m is enabled |
| #define M33_NVIC_ICER1_CLRENA_RESET _u(0x00000000) |
| #define M33_NVIC_ICER1_CLRENA_BITS _u(0xffffffff) |
| #define M33_NVIC_ICER1_CLRENA_MSB _u(31) |
| #define M33_NVIC_ICER1_CLRENA_LSB _u(0) |
| #define M33_NVIC_ICER1_CLRENA_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_ISPR0 |
| // Description : Enables or reads the pending state of each group of 32 |
| // interrupts |
| #define M33_NVIC_ISPR0_OFFSET _u(0x0000e200) |
| #define M33_NVIC_ISPR0_BITS _u(0xffffffff) |
| #define M33_NVIC_ISPR0_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_ISPR0_SETPEND |
| // Description : For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n |
| // + m is pending |
| #define M33_NVIC_ISPR0_SETPEND_RESET _u(0x00000000) |
| #define M33_NVIC_ISPR0_SETPEND_BITS _u(0xffffffff) |
| #define M33_NVIC_ISPR0_SETPEND_MSB _u(31) |
| #define M33_NVIC_ISPR0_SETPEND_LSB _u(0) |
| #define M33_NVIC_ISPR0_SETPEND_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_ISPR1 |
| // Description : Enables or reads the pending state of each group of 32 |
| // interrupts |
| #define M33_NVIC_ISPR1_OFFSET _u(0x0000e204) |
| #define M33_NVIC_ISPR1_BITS _u(0xffffffff) |
| #define M33_NVIC_ISPR1_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_ISPR1_SETPEND |
| // Description : For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n |
| // + m is pending |
| #define M33_NVIC_ISPR1_SETPEND_RESET _u(0x00000000) |
| #define M33_NVIC_ISPR1_SETPEND_BITS _u(0xffffffff) |
| #define M33_NVIC_ISPR1_SETPEND_MSB _u(31) |
| #define M33_NVIC_ISPR1_SETPEND_LSB _u(0) |
| #define M33_NVIC_ISPR1_SETPEND_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_ICPR0 |
| // Description : Clears or reads the pending state of each group of 32 |
| // interrupts |
| #define M33_NVIC_ICPR0_OFFSET _u(0x0000e280) |
| #define M33_NVIC_ICPR0_BITS _u(0xffffffff) |
| #define M33_NVIC_ICPR0_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_ICPR0_CLRPEND |
| // Description : For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n |
| // + m is pending |
| #define M33_NVIC_ICPR0_CLRPEND_RESET _u(0x00000000) |
| #define M33_NVIC_ICPR0_CLRPEND_BITS _u(0xffffffff) |
| #define M33_NVIC_ICPR0_CLRPEND_MSB _u(31) |
| #define M33_NVIC_ICPR0_CLRPEND_LSB _u(0) |
| #define M33_NVIC_ICPR0_CLRPEND_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_ICPR1 |
| // Description : Clears or reads the pending state of each group of 32 |
| // interrupts |
| #define M33_NVIC_ICPR1_OFFSET _u(0x0000e284) |
| #define M33_NVIC_ICPR1_BITS _u(0xffffffff) |
| #define M33_NVIC_ICPR1_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_ICPR1_CLRPEND |
| // Description : For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n |
| // + m is pending |
| #define M33_NVIC_ICPR1_CLRPEND_RESET _u(0x00000000) |
| #define M33_NVIC_ICPR1_CLRPEND_BITS _u(0xffffffff) |
| #define M33_NVIC_ICPR1_CLRPEND_MSB _u(31) |
| #define M33_NVIC_ICPR1_CLRPEND_LSB _u(0) |
| #define M33_NVIC_ICPR1_CLRPEND_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IABR0 |
| // Description : For each group of 32 interrupts, shows the active state of each |
| // interrupt |
| #define M33_NVIC_IABR0_OFFSET _u(0x0000e300) |
| #define M33_NVIC_IABR0_BITS _u(0xffffffff) |
| #define M33_NVIC_IABR0_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IABR0_ACTIVE |
| // Description : For ACTIVE[m] in NVIC_IABR*n, indicates the active state for |
| // interrupt 32*n+m |
| #define M33_NVIC_IABR0_ACTIVE_RESET _u(0x00000000) |
| #define M33_NVIC_IABR0_ACTIVE_BITS _u(0xffffffff) |
| #define M33_NVIC_IABR0_ACTIVE_MSB _u(31) |
| #define M33_NVIC_IABR0_ACTIVE_LSB _u(0) |
| #define M33_NVIC_IABR0_ACTIVE_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IABR1 |
| // Description : For each group of 32 interrupts, shows the active state of each |
| // interrupt |
| #define M33_NVIC_IABR1_OFFSET _u(0x0000e304) |
| #define M33_NVIC_IABR1_BITS _u(0xffffffff) |
| #define M33_NVIC_IABR1_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IABR1_ACTIVE |
| // Description : For ACTIVE[m] in NVIC_IABR*n, indicates the active state for |
| // interrupt 32*n+m |
| #define M33_NVIC_IABR1_ACTIVE_RESET _u(0x00000000) |
| #define M33_NVIC_IABR1_ACTIVE_BITS _u(0xffffffff) |
| #define M33_NVIC_IABR1_ACTIVE_MSB _u(31) |
| #define M33_NVIC_IABR1_ACTIVE_LSB _u(0) |
| #define M33_NVIC_IABR1_ACTIVE_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_ITNS0 |
| // Description : For each group of 32 interrupts, determines whether each |
| // interrupt targets Non-secure or Secure state |
| #define M33_NVIC_ITNS0_OFFSET _u(0x0000e380) |
| #define M33_NVIC_ITNS0_BITS _u(0xffffffff) |
| #define M33_NVIC_ITNS0_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_ITNS0_ITNS |
| // Description : For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state |
| // for interrupt 32*n+m |
| #define M33_NVIC_ITNS0_ITNS_RESET _u(0x00000000) |
| #define M33_NVIC_ITNS0_ITNS_BITS _u(0xffffffff) |
| #define M33_NVIC_ITNS0_ITNS_MSB _u(31) |
| #define M33_NVIC_ITNS0_ITNS_LSB _u(0) |
| #define M33_NVIC_ITNS0_ITNS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_ITNS1 |
| // Description : For each group of 32 interrupts, determines whether each |
| // interrupt targets Non-secure or Secure state |
| #define M33_NVIC_ITNS1_OFFSET _u(0x0000e384) |
| #define M33_NVIC_ITNS1_BITS _u(0xffffffff) |
| #define M33_NVIC_ITNS1_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_ITNS1_ITNS |
| // Description : For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state |
| // for interrupt 32*n+m |
| #define M33_NVIC_ITNS1_ITNS_RESET _u(0x00000000) |
| #define M33_NVIC_ITNS1_ITNS_BITS _u(0xffffffff) |
| #define M33_NVIC_ITNS1_ITNS_MSB _u(31) |
| #define M33_NVIC_ITNS1_ITNS_LSB _u(0) |
| #define M33_NVIC_ITNS1_ITNS_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IPR0 |
| // Description : Sets or reads interrupt priorities |
| #define M33_NVIC_IPR0_OFFSET _u(0x0000e400) |
| #define M33_NVIC_IPR0_BITS _u(0xf0f0f0f0) |
| #define M33_NVIC_IPR0_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR0_PRI_N3 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR0_PRI_N3_RESET _u(0x0) |
| #define M33_NVIC_IPR0_PRI_N3_BITS _u(0xf0000000) |
| #define M33_NVIC_IPR0_PRI_N3_MSB _u(31) |
| #define M33_NVIC_IPR0_PRI_N3_LSB _u(28) |
| #define M33_NVIC_IPR0_PRI_N3_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR0_PRI_N2 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR0_PRI_N2_RESET _u(0x0) |
| #define M33_NVIC_IPR0_PRI_N2_BITS _u(0x00f00000) |
| #define M33_NVIC_IPR0_PRI_N2_MSB _u(23) |
| #define M33_NVIC_IPR0_PRI_N2_LSB _u(20) |
| #define M33_NVIC_IPR0_PRI_N2_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR0_PRI_N1 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR0_PRI_N1_RESET _u(0x0) |
| #define M33_NVIC_IPR0_PRI_N1_BITS _u(0x0000f000) |
| #define M33_NVIC_IPR0_PRI_N1_MSB _u(15) |
| #define M33_NVIC_IPR0_PRI_N1_LSB _u(12) |
| #define M33_NVIC_IPR0_PRI_N1_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR0_PRI_N0 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR0_PRI_N0_RESET _u(0x0) |
| #define M33_NVIC_IPR0_PRI_N0_BITS _u(0x000000f0) |
| #define M33_NVIC_IPR0_PRI_N0_MSB _u(7) |
| #define M33_NVIC_IPR0_PRI_N0_LSB _u(4) |
| #define M33_NVIC_IPR0_PRI_N0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IPR1 |
| // Description : Sets or reads interrupt priorities |
| #define M33_NVIC_IPR1_OFFSET _u(0x0000e404) |
| #define M33_NVIC_IPR1_BITS _u(0xf0f0f0f0) |
| #define M33_NVIC_IPR1_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR1_PRI_N3 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR1_PRI_N3_RESET _u(0x0) |
| #define M33_NVIC_IPR1_PRI_N3_BITS _u(0xf0000000) |
| #define M33_NVIC_IPR1_PRI_N3_MSB _u(31) |
| #define M33_NVIC_IPR1_PRI_N3_LSB _u(28) |
| #define M33_NVIC_IPR1_PRI_N3_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR1_PRI_N2 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR1_PRI_N2_RESET _u(0x0) |
| #define M33_NVIC_IPR1_PRI_N2_BITS _u(0x00f00000) |
| #define M33_NVIC_IPR1_PRI_N2_MSB _u(23) |
| #define M33_NVIC_IPR1_PRI_N2_LSB _u(20) |
| #define M33_NVIC_IPR1_PRI_N2_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR1_PRI_N1 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR1_PRI_N1_RESET _u(0x0) |
| #define M33_NVIC_IPR1_PRI_N1_BITS _u(0x0000f000) |
| #define M33_NVIC_IPR1_PRI_N1_MSB _u(15) |
| #define M33_NVIC_IPR1_PRI_N1_LSB _u(12) |
| #define M33_NVIC_IPR1_PRI_N1_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR1_PRI_N0 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR1_PRI_N0_RESET _u(0x0) |
| #define M33_NVIC_IPR1_PRI_N0_BITS _u(0x000000f0) |
| #define M33_NVIC_IPR1_PRI_N0_MSB _u(7) |
| #define M33_NVIC_IPR1_PRI_N0_LSB _u(4) |
| #define M33_NVIC_IPR1_PRI_N0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IPR2 |
| // Description : Sets or reads interrupt priorities |
| #define M33_NVIC_IPR2_OFFSET _u(0x0000e408) |
| #define M33_NVIC_IPR2_BITS _u(0xf0f0f0f0) |
| #define M33_NVIC_IPR2_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR2_PRI_N3 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR2_PRI_N3_RESET _u(0x0) |
| #define M33_NVIC_IPR2_PRI_N3_BITS _u(0xf0000000) |
| #define M33_NVIC_IPR2_PRI_N3_MSB _u(31) |
| #define M33_NVIC_IPR2_PRI_N3_LSB _u(28) |
| #define M33_NVIC_IPR2_PRI_N3_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR2_PRI_N2 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR2_PRI_N2_RESET _u(0x0) |
| #define M33_NVIC_IPR2_PRI_N2_BITS _u(0x00f00000) |
| #define M33_NVIC_IPR2_PRI_N2_MSB _u(23) |
| #define M33_NVIC_IPR2_PRI_N2_LSB _u(20) |
| #define M33_NVIC_IPR2_PRI_N2_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR2_PRI_N1 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR2_PRI_N1_RESET _u(0x0) |
| #define M33_NVIC_IPR2_PRI_N1_BITS _u(0x0000f000) |
| #define M33_NVIC_IPR2_PRI_N1_MSB _u(15) |
| #define M33_NVIC_IPR2_PRI_N1_LSB _u(12) |
| #define M33_NVIC_IPR2_PRI_N1_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR2_PRI_N0 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR2_PRI_N0_RESET _u(0x0) |
| #define M33_NVIC_IPR2_PRI_N0_BITS _u(0x000000f0) |
| #define M33_NVIC_IPR2_PRI_N0_MSB _u(7) |
| #define M33_NVIC_IPR2_PRI_N0_LSB _u(4) |
| #define M33_NVIC_IPR2_PRI_N0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IPR3 |
| // Description : Sets or reads interrupt priorities |
| #define M33_NVIC_IPR3_OFFSET _u(0x0000e40c) |
| #define M33_NVIC_IPR3_BITS _u(0xf0f0f0f0) |
| #define M33_NVIC_IPR3_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR3_PRI_N3 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR3_PRI_N3_RESET _u(0x0) |
| #define M33_NVIC_IPR3_PRI_N3_BITS _u(0xf0000000) |
| #define M33_NVIC_IPR3_PRI_N3_MSB _u(31) |
| #define M33_NVIC_IPR3_PRI_N3_LSB _u(28) |
| #define M33_NVIC_IPR3_PRI_N3_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR3_PRI_N2 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR3_PRI_N2_RESET _u(0x0) |
| #define M33_NVIC_IPR3_PRI_N2_BITS _u(0x00f00000) |
| #define M33_NVIC_IPR3_PRI_N2_MSB _u(23) |
| #define M33_NVIC_IPR3_PRI_N2_LSB _u(20) |
| #define M33_NVIC_IPR3_PRI_N2_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR3_PRI_N1 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR3_PRI_N1_RESET _u(0x0) |
| #define M33_NVIC_IPR3_PRI_N1_BITS _u(0x0000f000) |
| #define M33_NVIC_IPR3_PRI_N1_MSB _u(15) |
| #define M33_NVIC_IPR3_PRI_N1_LSB _u(12) |
| #define M33_NVIC_IPR3_PRI_N1_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR3_PRI_N0 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR3_PRI_N0_RESET _u(0x0) |
| #define M33_NVIC_IPR3_PRI_N0_BITS _u(0x000000f0) |
| #define M33_NVIC_IPR3_PRI_N0_MSB _u(7) |
| #define M33_NVIC_IPR3_PRI_N0_LSB _u(4) |
| #define M33_NVIC_IPR3_PRI_N0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IPR4 |
| // Description : Sets or reads interrupt priorities |
| #define M33_NVIC_IPR4_OFFSET _u(0x0000e410) |
| #define M33_NVIC_IPR4_BITS _u(0xf0f0f0f0) |
| #define M33_NVIC_IPR4_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR4_PRI_N3 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR4_PRI_N3_RESET _u(0x0) |
| #define M33_NVIC_IPR4_PRI_N3_BITS _u(0xf0000000) |
| #define M33_NVIC_IPR4_PRI_N3_MSB _u(31) |
| #define M33_NVIC_IPR4_PRI_N3_LSB _u(28) |
| #define M33_NVIC_IPR4_PRI_N3_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR4_PRI_N2 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR4_PRI_N2_RESET _u(0x0) |
| #define M33_NVIC_IPR4_PRI_N2_BITS _u(0x00f00000) |
| #define M33_NVIC_IPR4_PRI_N2_MSB _u(23) |
| #define M33_NVIC_IPR4_PRI_N2_LSB _u(20) |
| #define M33_NVIC_IPR4_PRI_N2_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR4_PRI_N1 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR4_PRI_N1_RESET _u(0x0) |
| #define M33_NVIC_IPR4_PRI_N1_BITS _u(0x0000f000) |
| #define M33_NVIC_IPR4_PRI_N1_MSB _u(15) |
| #define M33_NVIC_IPR4_PRI_N1_LSB _u(12) |
| #define M33_NVIC_IPR4_PRI_N1_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR4_PRI_N0 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR4_PRI_N0_RESET _u(0x0) |
| #define M33_NVIC_IPR4_PRI_N0_BITS _u(0x000000f0) |
| #define M33_NVIC_IPR4_PRI_N0_MSB _u(7) |
| #define M33_NVIC_IPR4_PRI_N0_LSB _u(4) |
| #define M33_NVIC_IPR4_PRI_N0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IPR5 |
| // Description : Sets or reads interrupt priorities |
| #define M33_NVIC_IPR5_OFFSET _u(0x0000e414) |
| #define M33_NVIC_IPR5_BITS _u(0xf0f0f0f0) |
| #define M33_NVIC_IPR5_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR5_PRI_N3 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR5_PRI_N3_RESET _u(0x0) |
| #define M33_NVIC_IPR5_PRI_N3_BITS _u(0xf0000000) |
| #define M33_NVIC_IPR5_PRI_N3_MSB _u(31) |
| #define M33_NVIC_IPR5_PRI_N3_LSB _u(28) |
| #define M33_NVIC_IPR5_PRI_N3_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR5_PRI_N2 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR5_PRI_N2_RESET _u(0x0) |
| #define M33_NVIC_IPR5_PRI_N2_BITS _u(0x00f00000) |
| #define M33_NVIC_IPR5_PRI_N2_MSB _u(23) |
| #define M33_NVIC_IPR5_PRI_N2_LSB _u(20) |
| #define M33_NVIC_IPR5_PRI_N2_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR5_PRI_N1 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR5_PRI_N1_RESET _u(0x0) |
| #define M33_NVIC_IPR5_PRI_N1_BITS _u(0x0000f000) |
| #define M33_NVIC_IPR5_PRI_N1_MSB _u(15) |
| #define M33_NVIC_IPR5_PRI_N1_LSB _u(12) |
| #define M33_NVIC_IPR5_PRI_N1_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR5_PRI_N0 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR5_PRI_N0_RESET _u(0x0) |
| #define M33_NVIC_IPR5_PRI_N0_BITS _u(0x000000f0) |
| #define M33_NVIC_IPR5_PRI_N0_MSB _u(7) |
| #define M33_NVIC_IPR5_PRI_N0_LSB _u(4) |
| #define M33_NVIC_IPR5_PRI_N0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IPR6 |
| // Description : Sets or reads interrupt priorities |
| #define M33_NVIC_IPR6_OFFSET _u(0x0000e418) |
| #define M33_NVIC_IPR6_BITS _u(0xf0f0f0f0) |
| #define M33_NVIC_IPR6_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR6_PRI_N3 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR6_PRI_N3_RESET _u(0x0) |
| #define M33_NVIC_IPR6_PRI_N3_BITS _u(0xf0000000) |
| #define M33_NVIC_IPR6_PRI_N3_MSB _u(31) |
| #define M33_NVIC_IPR6_PRI_N3_LSB _u(28) |
| #define M33_NVIC_IPR6_PRI_N3_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR6_PRI_N2 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR6_PRI_N2_RESET _u(0x0) |
| #define M33_NVIC_IPR6_PRI_N2_BITS _u(0x00f00000) |
| #define M33_NVIC_IPR6_PRI_N2_MSB _u(23) |
| #define M33_NVIC_IPR6_PRI_N2_LSB _u(20) |
| #define M33_NVIC_IPR6_PRI_N2_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR6_PRI_N1 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR6_PRI_N1_RESET _u(0x0) |
| #define M33_NVIC_IPR6_PRI_N1_BITS _u(0x0000f000) |
| #define M33_NVIC_IPR6_PRI_N1_MSB _u(15) |
| #define M33_NVIC_IPR6_PRI_N1_LSB _u(12) |
| #define M33_NVIC_IPR6_PRI_N1_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR6_PRI_N0 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR6_PRI_N0_RESET _u(0x0) |
| #define M33_NVIC_IPR6_PRI_N0_BITS _u(0x000000f0) |
| #define M33_NVIC_IPR6_PRI_N0_MSB _u(7) |
| #define M33_NVIC_IPR6_PRI_N0_LSB _u(4) |
| #define M33_NVIC_IPR6_PRI_N0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IPR7 |
| // Description : Sets or reads interrupt priorities |
| #define M33_NVIC_IPR7_OFFSET _u(0x0000e41c) |
| #define M33_NVIC_IPR7_BITS _u(0xf0f0f0f0) |
| #define M33_NVIC_IPR7_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR7_PRI_N3 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR7_PRI_N3_RESET _u(0x0) |
| #define M33_NVIC_IPR7_PRI_N3_BITS _u(0xf0000000) |
| #define M33_NVIC_IPR7_PRI_N3_MSB _u(31) |
| #define M33_NVIC_IPR7_PRI_N3_LSB _u(28) |
| #define M33_NVIC_IPR7_PRI_N3_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR7_PRI_N2 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR7_PRI_N2_RESET _u(0x0) |
| #define M33_NVIC_IPR7_PRI_N2_BITS _u(0x00f00000) |
| #define M33_NVIC_IPR7_PRI_N2_MSB _u(23) |
| #define M33_NVIC_IPR7_PRI_N2_LSB _u(20) |
| #define M33_NVIC_IPR7_PRI_N2_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR7_PRI_N1 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR7_PRI_N1_RESET _u(0x0) |
| #define M33_NVIC_IPR7_PRI_N1_BITS _u(0x0000f000) |
| #define M33_NVIC_IPR7_PRI_N1_MSB _u(15) |
| #define M33_NVIC_IPR7_PRI_N1_LSB _u(12) |
| #define M33_NVIC_IPR7_PRI_N1_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR7_PRI_N0 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR7_PRI_N0_RESET _u(0x0) |
| #define M33_NVIC_IPR7_PRI_N0_BITS _u(0x000000f0) |
| #define M33_NVIC_IPR7_PRI_N0_MSB _u(7) |
| #define M33_NVIC_IPR7_PRI_N0_LSB _u(4) |
| #define M33_NVIC_IPR7_PRI_N0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IPR8 |
| // Description : Sets or reads interrupt priorities |
| #define M33_NVIC_IPR8_OFFSET _u(0x0000e420) |
| #define M33_NVIC_IPR8_BITS _u(0xf0f0f0f0) |
| #define M33_NVIC_IPR8_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR8_PRI_N3 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR8_PRI_N3_RESET _u(0x0) |
| #define M33_NVIC_IPR8_PRI_N3_BITS _u(0xf0000000) |
| #define M33_NVIC_IPR8_PRI_N3_MSB _u(31) |
| #define M33_NVIC_IPR8_PRI_N3_LSB _u(28) |
| #define M33_NVIC_IPR8_PRI_N3_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR8_PRI_N2 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR8_PRI_N2_RESET _u(0x0) |
| #define M33_NVIC_IPR8_PRI_N2_BITS _u(0x00f00000) |
| #define M33_NVIC_IPR8_PRI_N2_MSB _u(23) |
| #define M33_NVIC_IPR8_PRI_N2_LSB _u(20) |
| #define M33_NVIC_IPR8_PRI_N2_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR8_PRI_N1 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR8_PRI_N1_RESET _u(0x0) |
| #define M33_NVIC_IPR8_PRI_N1_BITS _u(0x0000f000) |
| #define M33_NVIC_IPR8_PRI_N1_MSB _u(15) |
| #define M33_NVIC_IPR8_PRI_N1_LSB _u(12) |
| #define M33_NVIC_IPR8_PRI_N1_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR8_PRI_N0 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR8_PRI_N0_RESET _u(0x0) |
| #define M33_NVIC_IPR8_PRI_N0_BITS _u(0x000000f0) |
| #define M33_NVIC_IPR8_PRI_N0_MSB _u(7) |
| #define M33_NVIC_IPR8_PRI_N0_LSB _u(4) |
| #define M33_NVIC_IPR8_PRI_N0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IPR9 |
| // Description : Sets or reads interrupt priorities |
| #define M33_NVIC_IPR9_OFFSET _u(0x0000e424) |
| #define M33_NVIC_IPR9_BITS _u(0xf0f0f0f0) |
| #define M33_NVIC_IPR9_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR9_PRI_N3 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR9_PRI_N3_RESET _u(0x0) |
| #define M33_NVIC_IPR9_PRI_N3_BITS _u(0xf0000000) |
| #define M33_NVIC_IPR9_PRI_N3_MSB _u(31) |
| #define M33_NVIC_IPR9_PRI_N3_LSB _u(28) |
| #define M33_NVIC_IPR9_PRI_N3_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR9_PRI_N2 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR9_PRI_N2_RESET _u(0x0) |
| #define M33_NVIC_IPR9_PRI_N2_BITS _u(0x00f00000) |
| #define M33_NVIC_IPR9_PRI_N2_MSB _u(23) |
| #define M33_NVIC_IPR9_PRI_N2_LSB _u(20) |
| #define M33_NVIC_IPR9_PRI_N2_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR9_PRI_N1 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR9_PRI_N1_RESET _u(0x0) |
| #define M33_NVIC_IPR9_PRI_N1_BITS _u(0x0000f000) |
| #define M33_NVIC_IPR9_PRI_N1_MSB _u(15) |
| #define M33_NVIC_IPR9_PRI_N1_LSB _u(12) |
| #define M33_NVIC_IPR9_PRI_N1_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR9_PRI_N0 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR9_PRI_N0_RESET _u(0x0) |
| #define M33_NVIC_IPR9_PRI_N0_BITS _u(0x000000f0) |
| #define M33_NVIC_IPR9_PRI_N0_MSB _u(7) |
| #define M33_NVIC_IPR9_PRI_N0_LSB _u(4) |
| #define M33_NVIC_IPR9_PRI_N0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IPR10 |
| // Description : Sets or reads interrupt priorities |
| #define M33_NVIC_IPR10_OFFSET _u(0x0000e428) |
| #define M33_NVIC_IPR10_BITS _u(0xf0f0f0f0) |
| #define M33_NVIC_IPR10_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR10_PRI_N3 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR10_PRI_N3_RESET _u(0x0) |
| #define M33_NVIC_IPR10_PRI_N3_BITS _u(0xf0000000) |
| #define M33_NVIC_IPR10_PRI_N3_MSB _u(31) |
| #define M33_NVIC_IPR10_PRI_N3_LSB _u(28) |
| #define M33_NVIC_IPR10_PRI_N3_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR10_PRI_N2 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR10_PRI_N2_RESET _u(0x0) |
| #define M33_NVIC_IPR10_PRI_N2_BITS _u(0x00f00000) |
| #define M33_NVIC_IPR10_PRI_N2_MSB _u(23) |
| #define M33_NVIC_IPR10_PRI_N2_LSB _u(20) |
| #define M33_NVIC_IPR10_PRI_N2_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR10_PRI_N1 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR10_PRI_N1_RESET _u(0x0) |
| #define M33_NVIC_IPR10_PRI_N1_BITS _u(0x0000f000) |
| #define M33_NVIC_IPR10_PRI_N1_MSB _u(15) |
| #define M33_NVIC_IPR10_PRI_N1_LSB _u(12) |
| #define M33_NVIC_IPR10_PRI_N1_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR10_PRI_N0 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR10_PRI_N0_RESET _u(0x0) |
| #define M33_NVIC_IPR10_PRI_N0_BITS _u(0x000000f0) |
| #define M33_NVIC_IPR10_PRI_N0_MSB _u(7) |
| #define M33_NVIC_IPR10_PRI_N0_LSB _u(4) |
| #define M33_NVIC_IPR10_PRI_N0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IPR11 |
| // Description : Sets or reads interrupt priorities |
| #define M33_NVIC_IPR11_OFFSET _u(0x0000e42c) |
| #define M33_NVIC_IPR11_BITS _u(0xf0f0f0f0) |
| #define M33_NVIC_IPR11_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR11_PRI_N3 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR11_PRI_N3_RESET _u(0x0) |
| #define M33_NVIC_IPR11_PRI_N3_BITS _u(0xf0000000) |
| #define M33_NVIC_IPR11_PRI_N3_MSB _u(31) |
| #define M33_NVIC_IPR11_PRI_N3_LSB _u(28) |
| #define M33_NVIC_IPR11_PRI_N3_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR11_PRI_N2 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR11_PRI_N2_RESET _u(0x0) |
| #define M33_NVIC_IPR11_PRI_N2_BITS _u(0x00f00000) |
| #define M33_NVIC_IPR11_PRI_N2_MSB _u(23) |
| #define M33_NVIC_IPR11_PRI_N2_LSB _u(20) |
| #define M33_NVIC_IPR11_PRI_N2_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR11_PRI_N1 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR11_PRI_N1_RESET _u(0x0) |
| #define M33_NVIC_IPR11_PRI_N1_BITS _u(0x0000f000) |
| #define M33_NVIC_IPR11_PRI_N1_MSB _u(15) |
| #define M33_NVIC_IPR11_PRI_N1_LSB _u(12) |
| #define M33_NVIC_IPR11_PRI_N1_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR11_PRI_N0 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR11_PRI_N0_RESET _u(0x0) |
| #define M33_NVIC_IPR11_PRI_N0_BITS _u(0x000000f0) |
| #define M33_NVIC_IPR11_PRI_N0_MSB _u(7) |
| #define M33_NVIC_IPR11_PRI_N0_LSB _u(4) |
| #define M33_NVIC_IPR11_PRI_N0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IPR12 |
| // Description : Sets or reads interrupt priorities |
| #define M33_NVIC_IPR12_OFFSET _u(0x0000e430) |
| #define M33_NVIC_IPR12_BITS _u(0xf0f0f0f0) |
| #define M33_NVIC_IPR12_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR12_PRI_N3 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR12_PRI_N3_RESET _u(0x0) |
| #define M33_NVIC_IPR12_PRI_N3_BITS _u(0xf0000000) |
| #define M33_NVIC_IPR12_PRI_N3_MSB _u(31) |
| #define M33_NVIC_IPR12_PRI_N3_LSB _u(28) |
| #define M33_NVIC_IPR12_PRI_N3_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR12_PRI_N2 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR12_PRI_N2_RESET _u(0x0) |
| #define M33_NVIC_IPR12_PRI_N2_BITS _u(0x00f00000) |
| #define M33_NVIC_IPR12_PRI_N2_MSB _u(23) |
| #define M33_NVIC_IPR12_PRI_N2_LSB _u(20) |
| #define M33_NVIC_IPR12_PRI_N2_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR12_PRI_N1 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR12_PRI_N1_RESET _u(0x0) |
| #define M33_NVIC_IPR12_PRI_N1_BITS _u(0x0000f000) |
| #define M33_NVIC_IPR12_PRI_N1_MSB _u(15) |
| #define M33_NVIC_IPR12_PRI_N1_LSB _u(12) |
| #define M33_NVIC_IPR12_PRI_N1_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR12_PRI_N0 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR12_PRI_N0_RESET _u(0x0) |
| #define M33_NVIC_IPR12_PRI_N0_BITS _u(0x000000f0) |
| #define M33_NVIC_IPR12_PRI_N0_MSB _u(7) |
| #define M33_NVIC_IPR12_PRI_N0_LSB _u(4) |
| #define M33_NVIC_IPR12_PRI_N0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IPR13 |
| // Description : Sets or reads interrupt priorities |
| #define M33_NVIC_IPR13_OFFSET _u(0x0000e434) |
| #define M33_NVIC_IPR13_BITS _u(0xf0f0f0f0) |
| #define M33_NVIC_IPR13_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR13_PRI_N3 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR13_PRI_N3_RESET _u(0x0) |
| #define M33_NVIC_IPR13_PRI_N3_BITS _u(0xf0000000) |
| #define M33_NVIC_IPR13_PRI_N3_MSB _u(31) |
| #define M33_NVIC_IPR13_PRI_N3_LSB _u(28) |
| #define M33_NVIC_IPR13_PRI_N3_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR13_PRI_N2 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR13_PRI_N2_RESET _u(0x0) |
| #define M33_NVIC_IPR13_PRI_N2_BITS _u(0x00f00000) |
| #define M33_NVIC_IPR13_PRI_N2_MSB _u(23) |
| #define M33_NVIC_IPR13_PRI_N2_LSB _u(20) |
| #define M33_NVIC_IPR13_PRI_N2_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR13_PRI_N1 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR13_PRI_N1_RESET _u(0x0) |
| #define M33_NVIC_IPR13_PRI_N1_BITS _u(0x0000f000) |
| #define M33_NVIC_IPR13_PRI_N1_MSB _u(15) |
| #define M33_NVIC_IPR13_PRI_N1_LSB _u(12) |
| #define M33_NVIC_IPR13_PRI_N1_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR13_PRI_N0 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR13_PRI_N0_RESET _u(0x0) |
| #define M33_NVIC_IPR13_PRI_N0_BITS _u(0x000000f0) |
| #define M33_NVIC_IPR13_PRI_N0_MSB _u(7) |
| #define M33_NVIC_IPR13_PRI_N0_LSB _u(4) |
| #define M33_NVIC_IPR13_PRI_N0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IPR14 |
| // Description : Sets or reads interrupt priorities |
| #define M33_NVIC_IPR14_OFFSET _u(0x0000e438) |
| #define M33_NVIC_IPR14_BITS _u(0xf0f0f0f0) |
| #define M33_NVIC_IPR14_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR14_PRI_N3 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR14_PRI_N3_RESET _u(0x0) |
| #define M33_NVIC_IPR14_PRI_N3_BITS _u(0xf0000000) |
| #define M33_NVIC_IPR14_PRI_N3_MSB _u(31) |
| #define M33_NVIC_IPR14_PRI_N3_LSB _u(28) |
| #define M33_NVIC_IPR14_PRI_N3_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR14_PRI_N2 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR14_PRI_N2_RESET _u(0x0) |
| #define M33_NVIC_IPR14_PRI_N2_BITS _u(0x00f00000) |
| #define M33_NVIC_IPR14_PRI_N2_MSB _u(23) |
| #define M33_NVIC_IPR14_PRI_N2_LSB _u(20) |
| #define M33_NVIC_IPR14_PRI_N2_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR14_PRI_N1 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR14_PRI_N1_RESET _u(0x0) |
| #define M33_NVIC_IPR14_PRI_N1_BITS _u(0x0000f000) |
| #define M33_NVIC_IPR14_PRI_N1_MSB _u(15) |
| #define M33_NVIC_IPR14_PRI_N1_LSB _u(12) |
| #define M33_NVIC_IPR14_PRI_N1_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR14_PRI_N0 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR14_PRI_N0_RESET _u(0x0) |
| #define M33_NVIC_IPR14_PRI_N0_BITS _u(0x000000f0) |
| #define M33_NVIC_IPR14_PRI_N0_MSB _u(7) |
| #define M33_NVIC_IPR14_PRI_N0_LSB _u(4) |
| #define M33_NVIC_IPR14_PRI_N0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_NVIC_IPR15 |
| // Description : Sets or reads interrupt priorities |
| #define M33_NVIC_IPR15_OFFSET _u(0x0000e43c) |
| #define M33_NVIC_IPR15_BITS _u(0xf0f0f0f0) |
| #define M33_NVIC_IPR15_RESET _u(0x00000000) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR15_PRI_N3 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR15_PRI_N3_RESET _u(0x0) |
| #define M33_NVIC_IPR15_PRI_N3_BITS _u(0xf0000000) |
| #define M33_NVIC_IPR15_PRI_N3_MSB _u(31) |
| #define M33_NVIC_IPR15_PRI_N3_LSB _u(28) |
| #define M33_NVIC_IPR15_PRI_N3_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR15_PRI_N2 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR15_PRI_N2_RESET _u(0x0) |
| #define M33_NVIC_IPR15_PRI_N2_BITS _u(0x00f00000) |
| #define M33_NVIC_IPR15_PRI_N2_MSB _u(23) |
| #define M33_NVIC_IPR15_PRI_N2_LSB _u(20) |
| #define M33_NVIC_IPR15_PRI_N2_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR15_PRI_N1 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR15_PRI_N1_RESET _u(0x0) |
| #define M33_NVIC_IPR15_PRI_N1_BITS _u(0x0000f000) |
| #define M33_NVIC_IPR15_PRI_N1_MSB _u(15) |
| #define M33_NVIC_IPR15_PRI_N1_LSB _u(12) |
| #define M33_NVIC_IPR15_PRI_N1_ACCESS "RW" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_NVIC_IPR15_PRI_N0 |
| // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, |
| // or RES0 if the PE does not implement this interrupt |
| #define M33_NVIC_IPR15_PRI_N0_RESET _u(0x0) |
| #define M33_NVIC_IPR15_PRI_N0_BITS _u(0x000000f0) |
| #define M33_NVIC_IPR15_PRI_N0_MSB _u(7) |
| #define M33_NVIC_IPR15_PRI_N0_LSB _u(4) |
| #define M33_NVIC_IPR15_PRI_N0_ACCESS "RW" |
| // ============================================================================= |
| // Register : M33_CPUID |
| // Description : Provides identification information for the PE, including an |
| // implementer code for the device and a device ID number |
| #define M33_CPUID_OFFSET _u(0x0000ed00) |
| #define M33_CPUID_BITS _u(0xffffffff) |
| #define M33_CPUID_RESET _u(0x411fd210) |
| // ----------------------------------------------------------------------------- |
| // Field : M33_CPUID_IMPLEMENTER |
| // Description : This field must hold an implementer code that has been assigned |
| // by ARM |
| #define M33_CPUID_IMPLEMENTER_RESET _u(0x41) |
| #define M33_CPUID_IMPLEMENTER_BITS _u(0xff000000) |
| #define M33_CPUID_IMPLEMENTER_MSB _u(31) |
| #define M33_CPUID_IMPLEMENTER_LSB _u(24) |
| #define M33_CPUID_IMPLEMENTER_ACCESS "RO" |
| // ----------------------------------------------------------------------------- |
| // Field : M33_CPUID_VARIANT |
| // Description : IMPLEMENTATION DEFINED variant number. Typically, this field is |
| // used to distinguish between different product variants, or |
| // major revisions of a product |
| #define M33_CPUID_VARIANT_RESET _u(0x1) |
| #define M33_CPUID_VARIANT_BITS _u(0x00f00000) |
| #define M33_CPUID_VARIANT_MSB _u(23) |
| #define M33_CPUID_VARIANT_LSB _u(20) |
