src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_clang.h - third_party/github/raspberrypi/pico-sdk - Git at Google

 /**************************************************************************//**
  * @file     cmsis_clang.h
  * @brief    CMSIS compiler LLVM/Clang header file
  * @version  V6.0.0
  * @date     27. July 2024
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the License); you may
  * not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
  * www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */

 #ifndef __CMSIS_CLANG_H
 #define __CMSIS_CLANG_H

 #pragma clang system_header   /* treat file as system include file */

 #if (__ARM_ACLE >= 200)
 #include <arm_acle.h>
 #else
 #error Compiler must support ACLE V2.0
 #endif /* (__ARM_ACLE >= 200) */

 /* Fallback for __has_builtin */
 #ifndef __has_builtin
 #define __has_builtin(x) (0)
 #endif

 /* CMSIS compiler specific defines */
 #ifndef   __ASM
 #define __ASM                                  __asm
 #endif
 #ifndef   __INLINE
 #define __INLINE                               inline
 #endif
 #ifndef   __STATIC_INLINE
 #define __STATIC_INLINE                        static inline
 #endif
 #ifndef   __STATIC_FORCEINLINE
 #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
 #endif
 #ifndef   __NO_RETURN
 #define __NO_RETURN                            __attribute__((__noreturn__))
 #endif
 #ifndef   CMSIS_DEPRECATED
 #define CMSIS_DEPRECATED                       __attribute__((deprecated))
 #endif
 #ifndef   __USED
 #define __USED                                 __attribute__((used))
 #endif
 #ifndef   __WEAK
 #define __WEAK                                 __attribute__((weak))
 #endif
 #ifndef   __PACKED
 #define __PACKED                               __attribute__((packed, aligned(1)))
 #endif
 #ifndef   __PACKED_STRUCT
 #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
 #endif
 #ifndef   __PACKED_UNION
 #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
 #endif
 #ifndef   __UNALIGNED_UINT16_WRITE
 #pragma clang diagnostic push
 #pragma clang diagnostic ignored "-Wpacked"
 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
 #pragma clang diagnostic pop
 #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
 #endif
 #ifndef   __UNALIGNED_UINT16_READ
 #pragma clang diagnostic push
 #pragma clang diagnostic ignored "-Wpacked"
 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
 #pragma clang diagnostic pop
 #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
 #endif
 #ifndef   __UNALIGNED_UINT32_WRITE
 #pragma clang diagnostic push
 #pragma clang diagnostic ignored "-Wpacked"
 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
 #pragma clang diagnostic pop
 #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
 #endif
 #ifndef   __UNALIGNED_UINT32_READ
 #pragma clang diagnostic push
 #pragma clang diagnostic ignored "-Wpacked"
 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 #pragma clang diagnostic pop
 #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
 #endif
 #ifndef   __ALIGNED
 #define __ALIGNED(x)                           __attribute__((aligned(x)))
 #endif
 #ifndef   __RESTRICT
 #define __RESTRICT                             __restrict
 #endif
 #ifndef   __COMPILER_BARRIER
 #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
 #endif
 #ifndef __NO_INIT
 #define __NO_INIT                              __attribute__ ((section (".noinit")))
 #endif
 #ifndef __ALIAS
 #define __ALIAS(x)                             __attribute__ ((alias(x)))
 #endif

 /* ##########################  Core Instruction Access  ######################### */
 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
   Access to dedicated instructions
   @{
 */

 /* Define macros for porting to both thumb1 and thumb2.
  * For thumb1, use low register (r0-r7), specified by constraint "l"
  * Otherwise, use general registers, specified by constraint "r" */
 #if defined (__thumb__) && !defined (__thumb2__)
 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 #define __CMSIS_GCC_RW_REG(r) "+l" (r)
 #define __CMSIS_GCC_USE_REG(r) "l" (r)
 #else
 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
 #define __CMSIS_GCC_RW_REG(r) "+r" (r)
 #define __CMSIS_GCC_USE_REG(r) "r" (r)
 #endif

 /**
   \brief   No Operation
   \details No Operation does nothing. This instruction can be used for code alignment purposes.
  */
 #define __NOP()         __nop()


 /**
   \brief   Wait For Interrupt
   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
  */
 #define __WFI()         __wfi()


 /**
   \brief   Wait For Event
   \details Wait For Event is a hint instruction that permits the processor to enter
            a low-power state until one of a number of events occurs.
  */
 #define __WFE()         __wfe()


 /**
   \brief   Send Event
   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  */
 #define __SEV()         __sev()


 /**
   \brief   Instruction Synchronization Barrier
   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
            so that all instructions following the ISB are fetched from cache or memory,
            after the instruction has been completed.
  */
 #define __ISB()         __isb(0xF)


 /**
   \brief   Data Synchronization Barrier
   \details Acts as a special kind of Data Memory Barrier.
            It completes when all explicit memory accesses before this instruction complete.
  */
 #define __DSB()         __dsb(0xF)


 /**
   \brief   Data Memory Barrier
   \details Ensures the apparent order of the explicit memory operations before
            and after the instruction, without ensuring their completion.
  */
 #define __DMB()         __dmb(0xF)


 /**
   \brief   Reverse byte order (32 bit)
   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
   \param [in]    value  Value to reverse
   \return               Reversed value
  */
 #define __REV(value)    __rev(value)


 /**
   \brief   Reverse byte order (16 bit)
   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
   \param [in]    value  Value to reverse
   \return               Reversed value
  */
 #define __REV16(value)  __rev16(value)


 /**
   \brief   Reverse byte order (16 bit)
   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
   \param [in]    value  Value to reverse
   \return               Reversed value
  */
 #define __REVSH(value)  __revsh(value)


 /**
   \brief   Rotate Right in unsigned value (32 bit)
   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
   \param [in]    op1  Value to rotate
   \param [in]    op2  Number of Bits to rotate
   \return               Rotated value
  */
 #define __ROR(op1, op2) __ror(op1, op2)


 /**
   \brief   Breakpoint
   \details Causes the processor to enter Debug state.
            Debug tools can use this to investigate system state when the instruction at a particular address is reached.
   \param [in]    value  is ignored by the processor.
                  If required, a debugger can use it to store additional information about the breakpoint.
  */
 #define __BKPT(value)   __ASM volatile ("bkpt "#value)


 /**
   \brief   Reverse bit order of value
   \details Reverses the bit order of the given value.
   \param [in]    value  Value to reverse
   \return               Reversed value
  */
 #define __RBIT(value)   __rbit(value)


 /**
   \brief   Count leading zeros
   \details Counts the number of leading zeros of a data value.
   \param [in]  value  Value to count the leading zeros
   \return             number of leading zeros in value
  */
 #define __CLZ(value)    __clz(value)


 #if ((__ARM_FEATURE_SAT    >= 1) && \
      (__ARM_ARCH_ISA_THUMB >= 2)    )
 /* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */
 /**
   \brief   Signed Saturate
   \details Saturates a signed value.
   \param [in]  value  Value to be saturated
   \param [in]    sat  Bit position to saturate to (1..32)
   \return             Saturated value
  */
 #define __SSAT(value, sat) __ssat(value, sat)


 /**
   \brief   Unsigned Saturate
   \details Saturates an unsigned value.
   \param [in]  value  Value to be saturated
   \param [in]    sat  Bit position to saturate to (0..31)
   \return             Saturated value
  */
 #define __USAT(value, sat) __usat(value, sat)

 #else /* (__ARM_FEATURE_SAT >= 1) */
 /**
   \brief   Signed Saturate
   \details Saturates a signed value.
   \param [in]  value  Value to be saturated
   \param [in]    sat  Bit position to saturate to (1..32)
   \return             Saturated value
  */
 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
 {
   if ((sat >= 1U) && (sat <= 32U))
   {
     const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
     const int32_t min = -1 - max ;
     if (val > max)
     {
       return (max);
     }
     else if (val < min)
     {
       return (min);
     }
   }
   return (val);
 }


 /**
   \brief   Unsigned Saturate
   \details Saturates an unsigned value.
   \param [in]  value  Value to be saturated
   \param [in]    sat  Bit position to saturate to (0..31)
   \return             Saturated value
  */
 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
 {
   if (sat <= 31U)
   {
     const uint32_t max = ((1U << sat) - 1U);
     if (val > (int32_t)max)
     {
       return (max);
     }
     else if (val < 0)
     {
       return (0U);
     }
   }
   return ((uint32_t)val);
 }
 #endif /* (__ARM_FEATURE_SAT >= 1) */


 #if (__ARM_FEATURE_LDREX >= 1)
 /**
   \brief   Remove the exclusive lock
   \details Removes the exclusive lock which is created by LDREX.
  */
 #define __CLREX             __builtin_arm_clrex


 /**
   \brief   LDR Exclusive (8 bit)
   \details Executes a exclusive LDR instruction for 8 bit value.
   \param [in]    ptr  Pointer to data
   \return             value of type uint8_t at (*ptr)
  */
 #define __LDREXB        (uint8_t)__builtin_arm_ldrex


 /**
   \brief   STR Exclusive (8 bit)
   \details Executes a exclusive STR instruction for 8 bit values.
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
   \return          0  Function succeeded
   \return          1  Function failed
  */
 #define __STREXB        (uint32_t)__builtin_arm_strex
 #endif /* (__ARM_FEATURE_LDREX >= 1) */


 #if (__ARM_FEATURE_LDREX >= 2)
 /**
   \brief   LDR Exclusive (16 bit)
   \details Executes a exclusive LDR instruction for 16 bit values.
   \param [in]    ptr  Pointer to data
   \return        value of type uint16_t at (*ptr)
  */
 #define __LDREXH        (uint16_t)__builtin_arm_ldrex


 /**
   \brief   STR Exclusive (16 bit)
   \details Executes a exclusive STR instruction for 16 bit values.
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
   \return          0  Function succeeded
   \return          1  Function failed
  */
 #define __STREXH        (uint32_t)__builtin_arm_strex
 #endif /* (__ARM_FEATURE_LDREX >= 2) */


 #if (__ARM_FEATURE_LDREX >= 4)
 /**
   \brief   LDR Exclusive (32 bit)
   \details Executes a exclusive LDR instruction for 32 bit values.
   \param [in]    ptr  Pointer to data
   \return        value of type uint32_t at (*ptr)
  */
 #define __LDREXW        (uint32_t)__builtin_arm_ldrex


 /**
   \brief   STR Exclusive (32 bit)
   \details Executes a exclusive STR instruction for 32 bit values.
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
   \return          0  Function succeeded
   \return          1  Function failed
  */
 #define __STREXW        (uint32_t)__builtin_arm_strex
 #endif /* (__ARM_FEATURE_LDREX >= 4) */


 #if (__ARM_ARCH_ISA_THUMB >= 2)
 /**
   \brief   Rotate Right with Extend (32 bit)
   \details Moves each bit of a bitstring right by one bit.
            The carry input is shifted in at the left end of the bitstring.
   \param [in]    value  Value to rotate
   \return               Rotated value
  */
 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
 {
     uint32_t result;

     __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value));
     return (result);
 }


 /**
   \brief   LDRT Unprivileged (8 bit)
   \details Executes a Unprivileged LDRT instruction for 8 bit value.
   \param [in]    ptr  Pointer to data
   \return             value of type uint8_t at (*ptr)
  */
 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
 {
     uint32_t result;

     __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
     return ((uint8_t)result);    /* Add explicit type cast here */
 }


 /**
   \brief   LDRT Unprivileged (16 bit)
   \details Executes a Unprivileged LDRT instruction for 16 bit values.
   \param [in]    ptr  Pointer to data
   \return        value of type uint16_t at (*ptr)
  */
 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
 {
     uint32_t result;

     __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
     return ((uint16_t)result);    /* Add explicit type cast here */
 }


 /**
   \brief   LDRT Unprivileged (32 bit)
   \details Executes a Unprivileged LDRT instruction for 32 bit values.
   \param [in]    ptr  Pointer to data
   \return        value of type uint32_t at (*ptr)
  */
 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
 {
     uint32_t result;

     __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
     return (result);
 }
 #endif /* (__ARM_ARCH_ISA_THUMB >= 2) */


 #if (__ARM_ARCH >= 8)
 /**
   \brief   Load-Acquire (8 bit)
   \details Executes a LDAB instruction for 8 bit value.
   \param [in]    ptr  Pointer to data
   \return             value of type uint8_t at (*ptr)
  */
 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
 {
     uint32_t result;

     __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
     return ((uint8_t)result);    /* Add explicit type cast here */
 }


 /**
   \brief   Load-Acquire (16 bit)
   \details Executes a LDAH instruction for 16 bit values.
   \param [in]    ptr  Pointer to data
   \return        value of type uint16_t at (*ptr)
  */
 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
 {
     uint32_t result;

     __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
     return ((uint16_t)result);    /* Add explicit type cast here */
 }


 /**
   \brief   Load-Acquire (32 bit)
   \details Executes a LDA instruction for 32 bit values.
   \param [in]    ptr  Pointer to data
   \return        value of type uint32_t at (*ptr)
  */
 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
 {
     uint32_t result;

     __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
     return (result);
 }


 /**
   \brief   Store-Release (8 bit)
   \details Executes a STLB instruction for 8 bit values.
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
  */
 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
 {
     __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 }


 /**
   \brief   Store-Release (16 bit)
   \details Executes a STLH instruction for 16 bit values.
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
  */
 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
 {
     __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 }


 /**
   \brief   Store-Release (32 bit)
   \details Executes a STL instruction for 32 bit values.
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
  */
 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
 {
     __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 }


 /**
   \brief   Load-Acquire Exclusive (8 bit)
   \details Executes a LDAB exclusive instruction for 8 bit value.
   \param [in]    ptr  Pointer to data
   \return             value of type uint8_t at (*ptr)
  */
 #define __LDAEXB                 (uint8_t)__builtin_arm_ldaex


 /**
   \brief   Load-Acquire Exclusive (16 bit)
   \details Executes a LDAH exclusive instruction for 16 bit values.
   \param [in]    ptr  Pointer to data
   \return        value of type uint16_t at (*ptr)
  */
 #define __LDAEXH                 (uint16_t)__builtin_arm_ldaex


 /**
   \brief   Load-Acquire Exclusive (32 bit)
   \details Executes a LDA exclusive instruction for 32 bit values.
   \param [in]    ptr  Pointer to data
   \return        value of type uint32_t at (*ptr)
  */
 #define __LDAEX                  (uint32_t)__builtin_arm_ldaex


 /**
   \brief   Store-Release Exclusive (8 bit)
   \details Executes a STLB exclusive instruction for 8 bit values.
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
   \return          0  Function succeeded
   \return          1  Function failed
  */
 #define __STLEXB                 (uint32_t)__builtin_arm_stlex


 /**
   \brief   Store-Release Exclusive (16 bit)
   \details Executes a STLH exclusive instruction for 16 bit values.
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
   \return          0  Function succeeded
   \return          1  Function failed
  */
 #define __STLEXH                 (uint32_t)__builtin_arm_stlex


 /**
   \brief   Store-Release Exclusive (32 bit)
   \details Executes a STL exclusive instruction for 32 bit values.
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
   \return          0  Function succeeded
   \return          1  Function failed
  */
 #define __STLEX                  (uint32_t)__builtin_arm_stlex

 #endif /* (__ARM_ARCH >= 8) */

 /** @}*/ /* end of group CMSIS_Core_InstructionInterface */


 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
   @{
  */

 /**
   \brief   Enable IRQ Interrupts
   \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
            Can only be executed in Privileged modes.
  */
 __STATIC_FORCEINLINE void __enable_irq(void)
 {
     __ASM volatile ("cpsie i" : : : "memory");
 }


 /**
   \brief   Disable IRQ Interrupts
   \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
            Can only be executed in Privileged modes.
  */
 __STATIC_FORCEINLINE void __disable_irq(void)
 {
     __ASM volatile ("cpsid i" : : : "memory");
 }

 #if (__ARM_ARCH_ISA_THUMB >= 2)
 /**
   \brief   Enable FIQ
   \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
            Can only be executed in Privileged modes.
  */
 __STATIC_FORCEINLINE void __enable_fault_irq(void)
 {
     __ASM volatile ("cpsie f" : : : "memory");
 }


 /**
   \brief   Disable FIQ
   \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
            Can only be executed in Privileged modes.
  */
 __STATIC_FORCEINLINE void __disable_fault_irq(void)
 {
     __ASM volatile ("cpsid f" : : : "memory");
 }
 #endif


 /**
   \brief   Get FPSCR
   \details Returns the current value of the Floating Point Status/Control register.
   \return               Floating Point Status/Control register value
  */
 __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
 {
 #if (defined(__ARM_FP) && (__ARM_FP >= 1))
     return (__builtin_arm_get_fpscr());
 #else
     return (0U);
 #endif
 }


 /**
   \brief   Set FPSCR
   \details Assigns the given value to the Floating Point Status/Control register.
   \param [in]    fpscr  Floating Point Status/Control value to set
  */
 __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
 {
 #if (defined(__ARM_FP) && (__ARM_FP >= 1))
     __builtin_arm_set_fpscr(fpscr);
 #else
     (void)fpscr;
 #endif
 }

 /** @} end of CMSIS_Core_RegAccFunctions */

 // Include the profile specific settings:
 #if __ARM_ARCH_PROFILE == 'A'
 #include "./a-profile/cmsis_clang_a.h"
 #elif __ARM_ARCH_PROFILE == 'R'
 #include "./r-profile/cmsis_clang_r.h"
 #elif __ARM_ARCH_PROFILE == 'M'
 #include "./m-profile/cmsis_clang_m.h"
 #else
 #error "Unknown Arm architecture profile"
 #endif

 #endif /* __CMSIS_CLANG_H */
	/************************************************************************//
	* @file cmsis_clang.h
	* @brief CMSIS compiler LLVM/Clang header file
	* @version V6.0.0
	* @date 27. July 2024
	******************************************************************************/
	/*
	* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
	*
	* SPDX-License-Identifier: Apache-2.0
	*
	* Licensed under the Apache License, Version 2.0 (the License); you may
	* not use this file except in compliance with the License.
	* You may obtain a copy of the License at
	*
	* www.apache.org/licenses/LICENSE-2.0
	*
	* Unless required by applicable law or agreed to in writing, software
	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
	* See the License for the specific language governing permissions and
	* limitations under the License.
	*/

	#ifndef __CMSIS_CLANG_H
	#define __CMSIS_CLANG_H

	#pragma clang system_header /* treat file as system include file */

	#if (__ARM_ACLE >= 200)
	#include <arm_acle.h>
	#else
	#error Compiler must support ACLE V2.0
	#endif /* (__ARM_ACLE >= 200) */

	/* Fallback for __has_builtin */
	#ifndef __has_builtin
	#define __has_builtin(x) (0)
	#endif

	/* CMSIS compiler specific defines */
	#ifndef __ASM
	#define __ASM __asm
	#endif
	#ifndef __INLINE
	#define __INLINE inline
	#endif
	#ifndef __STATIC_INLINE
	#define __STATIC_INLINE static inline
	#endif
	#ifndef __STATIC_FORCEINLINE
	#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
	#endif
	#ifndef __NO_RETURN
	#define __NO_RETURN __attribute__((__noreturn__))
	#endif
	#ifndef CMSIS_DEPRECATED
	#define CMSIS_DEPRECATED __attribute__((deprecated))
	#endif
	#ifndef __USED
	#define __USED __attribute__((used))
	#endif
	#ifndef __WEAK
	#define __WEAK __attribute__((weak))
	#endif
	#ifndef __PACKED
	#define __PACKED __attribute__((packed, aligned(1)))
	#endif
	#ifndef __PACKED_STRUCT
	#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
	#endif
	#ifndef __PACKED_UNION
	#define __PACKED_UNION union __attribute__((packed, aligned(1)))
	#endif
	#ifndef __UNALIGNED_UINT16_WRITE
	#pragma clang diagnostic push
	#pragma clang diagnostic ignored "-Wpacked"
	__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
	#pragma clang diagnostic pop
	#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE )(void )(addr))->v) = (val))
	#endif
	#ifndef __UNALIGNED_UINT16_READ
	#pragma clang diagnostic push
	#pragma clang diagnostic ignored "-Wpacked"
	__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
	#pragma clang diagnostic pop
	#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ )(const void )(addr))->v)
	#endif
	#ifndef __UNALIGNED_UINT32_WRITE
	#pragma clang diagnostic push
	#pragma clang diagnostic ignored "-Wpacked"
	__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
	#pragma clang diagnostic pop
	#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE )(void )(addr))->v) = (val))
	#endif
	#ifndef __UNALIGNED_UINT32_READ
	#pragma clang diagnostic push
	#pragma clang diagnostic ignored "-Wpacked"
	__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
	#pragma clang diagnostic pop
	#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ )(const void )(addr))->v)
	#endif
	#ifndef __ALIGNED
	#define __ALIGNED(x) __attribute__((aligned(x)))
	#endif
	#ifndef __RESTRICT
	#define __RESTRICT __restrict
	#endif
	#ifndef __COMPILER_BARRIER
	#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
	#endif
	#ifndef __NO_INIT
	#define __NO_INIT __attribute__ ((section (".noinit")))
	#endif
	#ifndef __ALIAS
	#define __ALIAS(x) __attribute__ ((alias(x)))
	#endif

	/* ########################## Core Instruction Access ######################### */
	/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
	Access to dedicated instructions
	@{
	*/

	/* Define macros for porting to both thumb1 and thumb2.
	* For thumb1, use low register (r0-r7), specified by constraint "l"
	* Otherwise, use general registers, specified by constraint "r" */
	#if defined (__thumb__) && !defined (__thumb2__)
	#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
	#define __CMSIS_GCC_RW_REG(r) "+l" (r)
	#define __CMSIS_GCC_USE_REG(r) "l" (r)
	#else
	#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
	#define __CMSIS_GCC_RW_REG(r) "+r" (r)
	#define __CMSIS_GCC_USE_REG(r) "r" (r)
	#endif

	/**
	\brief No Operation
	\details No Operation does nothing. This instruction can be used for code alignment purposes.
	*/
	#define __NOP() __nop()


	/**
	\brief Wait For Interrupt
	\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
	*/
	#define __WFI() __wfi()


	/**
	\brief Wait For Event
	\details Wait For Event is a hint instruction that permits the processor to enter
	a low-power state until one of a number of events occurs.
	*/
	#define __WFE() __wfe()


	/**
	\brief Send Event
	\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
	*/
	#define __SEV() __sev()


	/**
	\brief Instruction Synchronization Barrier
	\details Instruction Synchronization Barrier flushes the pipeline in the processor,
	so that all instructions following the ISB are fetched from cache or memory,
	after the instruction has been completed.
	*/
	#define __ISB() __isb(0xF)


	/**
	\brief Data Synchronization Barrier
	\details Acts as a special kind of Data Memory Barrier.
	It completes when all explicit memory accesses before this instruction complete.
	*/
	#define __DSB() __dsb(0xF)


	/**
	\brief Data Memory Barrier
	\details Ensures the apparent order of the explicit memory operations before
	and after the instruction, without ensuring their completion.
	*/
	#define __DMB() __dmb(0xF)


	/**
	\brief Reverse byte order (32 bit)
	\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
	\param [in] value Value to reverse
	\return Reversed value
	*/
	#define __REV(value) __rev(value)


	/**
	\brief Reverse byte order (16 bit)
	\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
	\param [in] value Value to reverse
	\return Reversed value
	*/
	#define __REV16(value) __rev16(value)


	/**
	\brief Reverse byte order (16 bit)
	\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
	\param [in] value Value to reverse
	\return Reversed value
	*/
	#define __REVSH(value) __revsh(value)


	/**
	\brief Rotate Right in unsigned value (32 bit)
	\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
	\param [in] op1 Value to rotate
	\param [in] op2 Number of Bits to rotate
	\return Rotated value
	*/
	#define __ROR(op1, op2) __ror(op1, op2)


	/**
	\brief Breakpoint
	\details Causes the processor to enter Debug state.
	Debug tools can use this to investigate system state when the instruction at a particular address is reached.
	\param [in] value is ignored by the processor.
	If required, a debugger can use it to store additional information about the breakpoint.
	*/
	#define __BKPT(value) __ASM volatile ("bkpt "#value)


	/**
	\brief Reverse bit order of value
	\details Reverses the bit order of the given value.
	\param [in] value Value to reverse
	\return Reversed value
	*/
	#define __RBIT(value) __rbit(value)


	/**
	\brief Count leading zeros
	\details Counts the number of leading zeros of a data value.
	\param [in] value Value to count the leading zeros
	\return number of leading zeros in value
	*/
	#define __CLZ(value) __clz(value)


	#if ((__ARM_FEATURE_SAT >= 1) && \
	(__ARM_ARCH_ISA_THUMB >= 2) )
	/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */
	/**
	\brief Signed Saturate
	\details Saturates a signed value.
	\param [in] value Value to be saturated
	\param [in] sat Bit position to saturate to (1..32)
	\return Saturated value
	*/
	#define __SSAT(value, sat) __ssat(value, sat)


	/**
	\brief Unsigned Saturate
	\details Saturates an unsigned value.
	\param [in] value Value to be saturated
	\param [in] sat Bit position to saturate to (0..31)
	\return Saturated value
	*/
	#define __USAT(value, sat) __usat(value, sat)

	#else /* (__ARM_FEATURE_SAT >= 1) */
	/**
	\brief Signed Saturate
	\details Saturates a signed value.
	\param [in] value Value to be saturated
	\param [in] sat Bit position to saturate to (1..32)
	\return Saturated value
	*/
	__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
	{
	if ((sat >= 1U) && (sat <= 32U))
	{
	const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
	const int32_t min = -1 - max ;
	if (val > max)
	{
	return (max);
	}
	else if (val < min)
	{
	return (min);
	}
	}
	return (val);
	}


	/**
	\brief Unsigned Saturate
	\details Saturates an unsigned value.
	\param [in] value Value to be saturated
	\param [in] sat Bit position to saturate to (0..31)
	\return Saturated value
	*/
	__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
	{
	if (sat <= 31U)
	{
	const uint32_t max = ((1U << sat) - 1U);
	if (val > (int32_t)max)
	{
	return (max);
	}
	else if (val < 0)
	{
	return (0U);
	}
	}
	return ((uint32_t)val);
	}
	#endif /* (__ARM_FEATURE_SAT >= 1) */


	#if (__ARM_FEATURE_LDREX >= 1)
	/**
	\brief Remove the exclusive lock
	\details Removes the exclusive lock which is created by LDREX.
	*/
	#define __CLREX __builtin_arm_clrex


	/**
	\brief LDR Exclusive (8 bit)
	\details Executes a exclusive LDR instruction for 8 bit value.
	\param [in] ptr Pointer to data
	\return value of type uint8_t at (*ptr)
	*/
	#define __LDREXB (uint8_t)__builtin_arm_ldrex


	/**
	\brief STR Exclusive (8 bit)
	\details Executes a exclusive STR instruction for 8 bit values.
	\param [in] value Value to store
	\param [in] ptr Pointer to location
	\return 0 Function succeeded
	\return 1 Function failed
	*/
	#define __STREXB (uint32_t)__builtin_arm_strex
	#endif /* (__ARM_FEATURE_LDREX >= 1) */


	#if (__ARM_FEATURE_LDREX >= 2)
	/**
	\brief LDR Exclusive (16 bit)
	\details Executes a exclusive LDR instruction for 16 bit values.
	\param [in] ptr Pointer to data
	\return value of type uint16_t at (*ptr)
	*/
	#define __LDREXH (uint16_t)__builtin_arm_ldrex


	/**
	\brief STR Exclusive (16 bit)
	\details Executes a exclusive STR instruction for 16 bit values.
	\param [in] value Value to store
	\param [in] ptr Pointer to location
	\return 0 Function succeeded
	\return 1 Function failed
	*/
	#define __STREXH (uint32_t)__builtin_arm_strex
	#endif /* (__ARM_FEATURE_LDREX >= 2) */


	#if (__ARM_FEATURE_LDREX >= 4)
	/**
	\brief LDR Exclusive (32 bit)
	\details Executes a exclusive LDR instruction for 32 bit values.
	\param [in] ptr Pointer to data
	\return value of type uint32_t at (*ptr)
	*/
	#define __LDREXW (uint32_t)__builtin_arm_ldrex


	/**
	\brief STR Exclusive (32 bit)
	\details Executes a exclusive STR instruction for 32 bit values.
	\param [in] value Value to store
	\param [in] ptr Pointer to location
	\return 0 Function succeeded
	\return 1 Function failed
	*/
	#define __STREXW (uint32_t)__builtin_arm_strex
	#endif /* (__ARM_FEATURE_LDREX >= 4) */


	#if (__ARM_ARCH_ISA_THUMB >= 2)
	/**
	\brief Rotate Right with Extend (32 bit)
	\details Moves each bit of a bitstring right by one bit.
	The carry input is shifted in at the left end of the bitstring.
	\param [in] value Value to rotate
	\return Rotated value
	*/
	__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
	{
	uint32_t result;

	__ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value));
	return (result);
	}


	/**
	\brief LDRT Unprivileged (8 bit)
	\details Executes a Unprivileged LDRT instruction for 8 bit value.
	\param [in] ptr Pointer to data
	\return value of type uint8_t at (*ptr)
	*/
	__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
	{
	uint32_t result;

	__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
	return ((uint8_t)result); /* Add explicit type cast here */
	}


	/**
	\brief LDRT Unprivileged (16 bit)
	\details Executes a Unprivileged LDRT instruction for 16 bit values.
	\param [in] ptr Pointer to data
	\return value of type uint16_t at (*ptr)
	*/
	__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
	{
	uint32_t result;

	__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
	return ((uint16_t)result); /* Add explicit type cast here */
	}


	/**
	\brief LDRT Unprivileged (32 bit)
	\details Executes a Unprivileged LDRT instruction for 32 bit values.
	\param [in] ptr Pointer to data
	\return value of type uint32_t at (*ptr)
	*/
	__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
	{
	uint32_t result;

	__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
	return (result);
	}
	#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */


	#if (__ARM_ARCH >= 8)
	/**
	\brief Load-Acquire (8 bit)
	\details Executes a LDAB instruction for 8 bit value.
	\param [in] ptr Pointer to data
	\return value of type uint8_t at (*ptr)
	*/
	__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
	{
	uint32_t result;

	__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
	return ((uint8_t)result); /* Add explicit type cast here */
	}


	/**
	\brief Load-Acquire (16 bit)
	\details Executes a LDAH instruction for 16 bit values.
	\param [in] ptr Pointer to data
	\return value of type uint16_t at (*ptr)
	*/
	__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
	{
	uint32_t result;

	__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
	return ((uint16_t)result); /* Add explicit type cast here */
	}


	/**
	\brief Load-Acquire (32 bit)
	\details Executes a LDA instruction for 32 bit values.
	\param [in] ptr Pointer to data
	\return value of type uint32_t at (*ptr)
	*/
	__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
	{
	uint32_t result;

	__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
	return (result);
	}


	/**
	\brief Store-Release (8 bit)
	\details Executes a STLB instruction for 8 bit values.
	\param [in] value Value to store
	\param [in] ptr Pointer to location
	*/
	__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
	{
	__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
	}


	/**
	\brief Store-Release (16 bit)
	\details Executes a STLH instruction for 16 bit values.
	\param [in] value Value to store
	\param [in] ptr Pointer to location
	*/
	__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
	{
	__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
	}


	/**
	\brief Store-Release (32 bit)
	\details Executes a STL instruction for 32 bit values.
	\param [in] value Value to store
	\param [in] ptr Pointer to location
	*/
	__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
	{
	__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
	}


	/**
	\brief Load-Acquire Exclusive (8 bit)
	\details Executes a LDAB exclusive instruction for 8 bit value.
	\param [in] ptr Pointer to data
	\return value of type uint8_t at (*ptr)
	*/
	#define __LDAEXB (uint8_t)__builtin_arm_ldaex


	/**
	\brief Load-Acquire Exclusive (16 bit)
	\details Executes a LDAH exclusive instruction for 16 bit values.
	\param [in] ptr Pointer to data
	\return value of type uint16_t at (*ptr)
	*/
	#define __LDAEXH (uint16_t)__builtin_arm_ldaex


	/**
	\brief Load-Acquire Exclusive (32 bit)
	\details Executes a LDA exclusive instruction for 32 bit values.
	\param [in] ptr Pointer to data
	\return value of type uint32_t at (*ptr)
	*/
	#define __LDAEX (uint32_t)__builtin_arm_ldaex


	/**
	\brief Store-Release Exclusive (8 bit)
	\details Executes a STLB exclusive instruction for 8 bit values.
	\param [in] value Value to store
	\param [in] ptr Pointer to location
	\return 0 Function succeeded
	\return 1 Function failed
	*/
	#define __STLEXB (uint32_t)__builtin_arm_stlex


	/**
	\brief Store-Release Exclusive (16 bit)
	\details Executes a STLH exclusive instruction for 16 bit values.
	\param [in] value Value to store
	\param [in] ptr Pointer to location
	\return 0 Function succeeded
	\return 1 Function failed
	*/
	#define __STLEXH (uint32_t)__builtin_arm_stlex


	/**
	\brief Store-Release Exclusive (32 bit)
	\details Executes a STL exclusive instruction for 32 bit values.
	\param [in] value Value to store
	\param [in] ptr Pointer to location
	\return 0 Function succeeded
	\return 1 Function failed
	*/
	#define __STLEX (uint32_t)__builtin_arm_stlex

	#endif /* (__ARM_ARCH >= 8) */

	/** @}/ / end of group CMSIS_Core_InstructionInterface */


	/* ########################### Core Function Access ########################### */
	/** \ingroup CMSIS_Core_FunctionInterface
	\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
	@{
	*/

	/**
	\brief Enable IRQ Interrupts
	\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
	Can only be executed in Privileged modes.
	*/
	__STATIC_FORCEINLINE void __enable_irq(void)
	{
	__ASM volatile ("cpsie i" : : : "memory");
	}


	/**
	\brief Disable IRQ Interrupts
	\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
	Can only be executed in Privileged modes.
	*/
	__STATIC_FORCEINLINE void __disable_irq(void)
	{
	__ASM volatile ("cpsid i" : : : "memory");
	}

	#if (__ARM_ARCH_ISA_THUMB >= 2)
	/**
	\brief Enable FIQ
	\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
	Can only be executed in Privileged modes.
	*/
	__STATIC_FORCEINLINE void __enable_fault_irq(void)
	{
	__ASM volatile ("cpsie f" : : : "memory");
	}


	/**
	\brief Disable FIQ
	\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
	Can only be executed in Privileged modes.
	*/
	__STATIC_FORCEINLINE void __disable_fault_irq(void)
	{
	__ASM volatile ("cpsid f" : : : "memory");
	}
	#endif



	/**
	\brief Get FPSCR
	\details Returns the current value of the Floating Point Status/Control register.
	\return Floating Point Status/Control register value
	*/
	__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
	{
	#if (defined(__ARM_FP) && (__ARM_FP >= 1))
	return (__builtin_arm_get_fpscr());
	#else
	return (0U);
	#endif
	}


	/**
	\brief Set FPSCR
	\details Assigns the given value to the Floating Point Status/Control register.
	\param [in] fpscr Floating Point Status/Control value to set
	*/
	__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
	{
	#if (defined(__ARM_FP) && (__ARM_FP >= 1))
	__builtin_arm_set_fpscr(fpscr);
	#else
	(void)fpscr;
	#endif
	}

	/** @} end of CMSIS_Core_RegAccFunctions */

	// Include the profile specific settings:
	#if __ARM_ARCH_PROFILE == 'A'
	#include "./a-profile/cmsis_clang_a.h"
	#elif __ARM_ARCH_PROFILE == 'R'
	#include "./r-profile/cmsis_clang_r.h"
	#elif __ARM_ARCH_PROFILE == 'M'
	#include "./m-profile/cmsis_clang_m.h"
	#else
	#error "Unknown Arm architecture profile"
	#endif

	#endif /* __CMSIS_CLANG_H */