| /* |
| * Copyright (c) 2009-2024 Arm Limited. All rights reserved. |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| * |
| * Licensed under the Apache License, Version 2.0 (the License); you may |
| * not use this file except in compliance with the License. |
| * You may obtain a copy of the License at |
| * |
| * www.apache.org/licenses/LICENSE-2.0 |
| * |
| * Unless required by applicable law or agreed to in writing, software |
| * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| * See the License for the specific language governing permissions and |
| * limitations under the License. |
| */ |
| |
| /* |
| * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File |
| */ |
| |
| #if defined ( __ICCARM__ ) |
| #pragma system_include /* treat file as system include file for MISRA check */ |
| #elif defined (__clang__) |
| #pragma clang system_header /* treat file as system include file */ |
| #elif defined ( __GNUC__ ) |
| #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ |
| #endif |
| |
| #ifndef __CORE_CM0PLUS_H_GENERIC |
| #define __CORE_CM0PLUS_H_GENERIC |
| |
| #include <stdint.h> |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| /** |
| \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
| CMSIS violates the following MISRA-C:2004 rules: |
| |
| \li Required Rule 8.5, object/function definition in header file.<br> |
| Function definitions in header files are used to allow 'inlining'. |
| |
| \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
| Unions are used for effective representation of core registers. |
| |
| \li Advisory Rule 19.7, Function-like macro defined.<br> |
| Function-like macros are used to allow more efficient code. |
| */ |
| |
| |
| /******************************************************************************* |
| * CMSIS definitions |
| ******************************************************************************/ |
| /** |
| \ingroup Cortex-M0+ |
| @{ |
| */ |
| |
| #include "cmsis_version.h" |
| |
| /* CMSIS CM0+ definitions */ |
| |
| #define __CORTEX_M (0U) /*!< Cortex-M Core */ |
| |
| /** __FPU_USED indicates whether an FPU is used or not. |
| This core does not support an FPU at all |
| */ |
| #define __FPU_USED 0U |
| |
| #if defined ( __CC_ARM ) |
| #if defined (__TARGET_FPU_VFP) |
| #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| #endif |
| |
| #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
| #if defined (__ARM_FP) |
| #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| #endif |
| |
| #elif defined (__ti__) |
| #if defined (__ARM_FP) |
| #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| #endif |
| |
| #elif defined ( __GNUC__ ) |
| #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
| #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| #endif |
| |
| #elif defined ( __ICCARM__ ) |
| #if defined (__ARMVFP__) |
| #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| #endif |
| |
| #elif defined ( __TI_ARM__ ) |
| #if defined (__TI_VFP_SUPPORT__) |
| #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| #endif |
| |
| #elif defined ( __TASKING__ ) |
| #if defined (__FPU_VFP__) |
| #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| #endif |
| |
| #elif defined ( __CSMC__ ) |
| #if ( __CSMC__ & 0x400U) |
| #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| #endif |
| |
| #endif |
| |
| #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ |
| |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| |
| #endif /* __CORE_CM0PLUS_H_GENERIC */ |
| |
| #ifndef __CMSIS_GENERIC |
| |
| #ifndef __CORE_CM0PLUS_H_DEPENDANT |
| #define __CORE_CM0PLUS_H_DEPENDANT |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| /* check device defines and use defaults */ |
| #if defined __CHECK_DEVICE_DEFINES |
| #ifndef __CM0PLUS_REV |
| #define __CM0PLUS_REV 0x0000U |
| #warning "__CM0PLUS_REV not defined in device header file; using default!" |
| #endif |
| |
| #ifndef __MPU_PRESENT |
| #define __MPU_PRESENT 0U |
| #warning "__MPU_PRESENT not defined in device header file; using default!" |
| #endif |
| |
| #ifndef __VTOR_PRESENT |
| #define __VTOR_PRESENT 0U |
| #warning "__VTOR_PRESENT not defined in device header file; using default!" |
| #endif |
| |
| #ifndef __NVIC_PRIO_BITS |
| #define __NVIC_PRIO_BITS 2U |
| #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
| #endif |
| |
| #ifndef __Vendor_SysTickConfig |
| #define __Vendor_SysTickConfig 0U |
| #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
| #endif |
| #endif |
| |
| /* IO definitions (access restrictions to peripheral registers) */ |
| /** |
| \defgroup CMSIS_glob_defs CMSIS Global Defines |
| |
| <strong>IO Type Qualifiers</strong> are used |
| \li to specify the access to peripheral variables. |
| \li for automatic generation of peripheral register debug information. |
| */ |
| #ifdef __cplusplus |
| #define __I volatile /*!< Defines 'read only' permissions */ |
| #else |
| #define __I volatile const /*!< Defines 'read only' permissions */ |
| #endif |
| #define __O volatile /*!< Defines 'write only' permissions */ |
| #define __IO volatile /*!< Defines 'read / write' permissions */ |
| |
| /* following defines should be used for structure members */ |
| #define __IM volatile const /*! Defines 'read only' structure member permissions */ |
| #define __OM volatile /*! Defines 'write only' structure member permissions */ |
| #define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
| |
| /*@} end of group Cortex-M0+ */ |
| |
| |
| |
| /******************************************************************************* |
| * Register Abstraction |
| Core Register contain: |
| - Core Register |
| - Core NVIC Register |
| - Core SCB Register |
| - Core SysTick Register |
| - Core MPU Register |
| ******************************************************************************/ |
| /** |
| \defgroup CMSIS_core_register Defines and Type Definitions |
| \brief Type definitions and defines for Cortex-M processor based devices. |
| */ |
| |
| /** |
| \ingroup CMSIS_core_register |
| \defgroup CMSIS_CORE Status and Control Registers |
| \brief Core Register type definitions. |
| @{ |
| */ |
| |
| /** |
| \brief Union type to access the Application Program Status Register (APSR). |
| */ |
| typedef union |
| { |
| struct |
| { |
| uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
| uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| } b; /*!< Structure used for bit access */ |
| uint32_t w; /*!< Type used for word access */ |
| } APSR_Type; |
| |
| /** \brief APSR Register Definitions */ |
| #define APSR_N_Pos 31U /*!< APSR: N Position */ |
| #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
| |
| #define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
| |
| #define APSR_C_Pos 29U /*!< APSR: C Position */ |
| #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
| |
| #define APSR_V_Pos 28U /*!< APSR: V Position */ |
| #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
| |
| |
| /** |
| \brief Union type to access the Interrupt Program Status Register (IPSR). |
| */ |
| typedef union |
| { |
| struct |
| { |
| uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
| } b; /*!< Structure used for bit access */ |
| uint32_t w; /*!< Type used for word access */ |
| } IPSR_Type; |
| |
| /** \brief IPSR Register Definitions */ |
| #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
| |
| |
| /** |
| \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
| */ |
| typedef union |
| { |
| struct |
| { |
| uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
| uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
| uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
| uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| } b; /*!< Structure used for bit access */ |
| uint32_t w; /*!< Type used for word access */ |
| } xPSR_Type; |
| |
| /** \brief xPSR Register Definitions */ |
| #define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
| |
| #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
| |
| #define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
| |
| #define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
| |
| #define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
| |
| #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
| |
| |
| /** |
| \brief Union type to access the Control Registers (CONTROL). |
| */ |
| typedef union |
| { |
| struct |
| { |
| uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
| uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
| uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
| } b; /*!< Structure used for bit access */ |
| uint32_t w; /*!< Type used for word access */ |
| } CONTROL_Type; |
| |
| /** \brief CONTROL Register Definitions */ |
| #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
| |
| #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ |
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ |
| |
| /*@} end of group CMSIS_CORE */ |
| |
| |
| /** |
| \ingroup CMSIS_core_register |
| \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
| \brief Type definitions for the NVIC Registers |
| @{ |
| */ |
| |
| /** |
| \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
| */ |
| typedef struct |
| { |
| __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
| uint32_t RESERVED0[31U]; |
| __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
| uint32_t RESERVED1[31U]; |
| __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
| uint32_t RESERVED2[31U]; |
| __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
| uint32_t RESERVED3[31U]; |
| uint32_t RESERVED4[64U]; |
| __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
| } NVIC_Type; |
| |
| /*@} end of group CMSIS_NVIC */ |
| |
| |
| /** |
| \ingroup CMSIS_core_register |
| \defgroup CMSIS_SCB System Control Block (SCB) |
| \brief Type definitions for the System Control Block Registers |
| @{ |
| */ |
| |
| /** |
| \brief Structure type to access the System Control Block (SCB). |
| */ |
| typedef struct |
| { |
| __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
| __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
| #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) |
| __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
| #else |
| uint32_t RESERVED0; |
| #endif |
| __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
| __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
| __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
| uint32_t RESERVED1; |
| __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
| __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
| } SCB_Type; |
| |
| /** \brief SCB CPUID Register Definitions */ |
| #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
| |
| #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
| |
| #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
| |
| #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
| |
| #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
| |
| /** \brief SCB Interrupt Control State Register Definitions */ |
| #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
| |
| #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
| |
| #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
| |
| #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
| |
| #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
| |
| #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
| |
| #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
| |
| #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
| |
| #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
| |
| #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) |
| /** \brief SCB Vector Table Offset Register Definitions */ |
| #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ |
| #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
| #endif |
| |
| /** \brief SCB Application Interrupt and Reset Control Register Definitions */ |
| #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
| |
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
| |
| #define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ |
| #define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ |
| |
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
| |
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
| |
| /** \brief SCB System Control Register Definitions */ |
| #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
| |
| #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
| |
| #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
| |
| /** \brief SCB Configuration Control Register Definitions */ |
| #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
| |
| #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
| |
| /** \brief SCB System Handler Control and State Register Definitions */ |
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
| |
| /*@} end of group CMSIS_SCB */ |
| |
| |
| /** |
| \ingroup CMSIS_core_register |
| \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
| \brief Type definitions for the System Timer Registers. |
| @{ |
| */ |
| |
| /** |
| \brief Structure type to access the System Timer (SysTick). |
| */ |
| typedef struct |
| { |
| __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
| __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
| __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
| __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
| } SysTick_Type; |
| |
| /** \brief SysTick Control / Status Register Definitions */ |
| #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
| |
| #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
| |
| #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
| |
| #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
| |
| /** \brief SysTick Reload Register Definitions */ |
| #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
| |
| /** \brief SysTick Current Register Definitions */ |
| #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
| |
| /** \brief SysTick Calibration Register Definitions */ |
| #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
| |
| #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
| |
| #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
| |
| /*@} end of group CMSIS_SysTick */ |
| |
| #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
| /** |
| \ingroup CMSIS_core_register |
| \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
| \brief Type definitions for the Memory Protection Unit (MPU) |
| @{ |
| */ |
| |
| /** |
| \brief Structure type to access the Memory Protection Unit (MPU). |
| */ |
| typedef struct |
| { |
| __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
| __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
| __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ |
| __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
| __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
| } MPU_Type; |
| |
| #define MPU_TYPE_RALIASES 1U |
| |
| /** \brief MPU Type Register Definitions */ |
| #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ |
| #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
| |
| #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ |
| #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
| |
| #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ |
| #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
| |
| /** \brief MPU Control Register Definitions */ |
| #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ |
| #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
| |
| #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ |
| #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
| |
| #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ |
| #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
| |
| /** \brief MPU Region Number Register Definitions */ |
| #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ |
| #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
| |
| /** \brief MPU Region Base Address Register Definitions */ |
| #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ |
| #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
| |
| #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ |
| #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
| |
| #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ |
| #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
| |
| /** \brief MPU Region Attribute and Size Register Definitions */ |
| #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ |
| #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
| |
| #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ |
| #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
| |
| #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ |
| #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
| |
| #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ |
| #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
| |
| #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ |
| #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
| |
| #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ |
| #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
| |
| #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ |
| #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
| |
| #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ |
| #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
| |
| #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ |
| #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
| |
| #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ |
| #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
| |
| /*@} end of group CMSIS_MPU */ |
| #endif |
| |
| |
| /** |
| \ingroup CMSIS_core_register |
| \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
| \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
| Therefore they are not covered by the Cortex-M0+ header file. |
| @{ |
| */ |
| /*@} end of group CMSIS_CoreDebug */ |
| |
| |
| /** |
| \ingroup CMSIS_core_register |
| \defgroup CMSIS_core_bitfield Core register bit field macros |
| \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
| @{ |
| */ |
| |
| /** |
| \brief Mask and shift a bit field value for use in a register bit range. |
| \param[in] field Name of the register bit field. |
| \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. |
| \return Masked and shifted value. |
| */ |
| #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
| |
| /** |
| \brief Mask and shift a register value to extract a bit filed value. |
| \param[in] field Name of the register bit field. |
| \param[in] value Value of register. This parameter is interpreted as an uint32_t type. |
| \return Masked and shifted bit field value. |
| */ |
| #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
| |
| /*@} end of group CMSIS_core_bitfield */ |
| |
| |
| /** |
| \ingroup CMSIS_core_register |
| \defgroup CMSIS_core_base Core Definitions |
| \brief Definitions for base addresses, unions, and structures. |
| @{ |
| */ |
| |
| /* Memory mapping of Core Hardware */ |
| #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
| #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
| #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
| #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
| |
| #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
| #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
| #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
| |
| #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
| #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
| #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
| #endif |
| |
| /*@} */ |
| |
| |
| /** |
| \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases |
| \brief Alias definitions present for backwards compatibility for deprecated symbols. |
| @{ |
| */ |
| |
| #ifndef CMSIS_DISABLE_DEPRECATED |
| |
| #define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos |
| #define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk |
| |
| #endif // CMSIS_DISABLE_DEPRECATED |
| |
| /*@} */ |
| |
| |
| /******************************************************************************* |
| * Hardware Abstraction Layer |
| Core Function Interface contains: |
| - Core NVIC Functions |
| - Core SysTick Functions |
| - Core Register Access Functions |
| ******************************************************************************/ |
| /** |
| \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
| */ |
| |
| |
| |
| /* ########################## NVIC functions #################################### */ |
| /** |
| \ingroup CMSIS_Core_FunctionInterface |
| \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
| \brief Functions that manage interrupts and exceptions via the NVIC. |
| @{ |
| */ |
| |
| #ifdef CMSIS_NVIC_VIRTUAL |
| #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE |
| #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" |
| #endif |
| #include CMSIS_NVIC_VIRTUAL_HEADER_FILE |
| #else |
| #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping |
| #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping |
| #define NVIC_EnableIRQ __NVIC_EnableIRQ |
| #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ |
| #define NVIC_DisableIRQ __NVIC_DisableIRQ |
| #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ |
| #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ |
| #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ |
| /* NVIC_GetActive not available for Cortex-M0+ */ |
| #define NVIC_SetPriority __NVIC_SetPriority |
| #define NVIC_GetPriority __NVIC_GetPriority |
| #define NVIC_SystemReset __NVIC_SystemReset |
| #endif /* CMSIS_NVIC_VIRTUAL */ |
| |
| #ifdef CMSIS_VECTAB_VIRTUAL |
| #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
| #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" |
| #endif |
| #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
| #else |
| #define NVIC_SetVector __NVIC_SetVector |
| #define NVIC_GetVector __NVIC_GetVector |
| #endif /* (CMSIS_VECTAB_VIRTUAL) */ |
| |
| #define NVIC_USER_IRQ_OFFSET 16 |
| |
| |
| /* The following EXC_RETURN values are saved the LR on exception entry */ |
| #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ |
| #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ |
| #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ |
| |
| |
| /* Interrupt Priorities are WORD accessible only under Armv6-M */ |
| /* The following MACROS handle generation of the register offset and byte masks */ |
| #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
| #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
| #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
| |
| #define __NVIC_SetPriorityGrouping(X) (void)(X) |
| #define __NVIC_GetPriorityGrouping() (0U) |
| |
| /** |
| \brief Enable Interrupt |
| \details Enables a device specific interrupt in the NVIC interrupt controller. |
| \param [in] IRQn Device specific interrupt number. |
| \note IRQn must not be negative. |
| */ |
| __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) |
| { |
| if ((int32_t)(IRQn) >= 0) |
| { |
| __COMPILER_BARRIER(); |
| NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
| __COMPILER_BARRIER(); |
| } |
| } |
| |
| |
| /** |
| \brief Get Interrupt Enable status |
| \details Returns a device specific interrupt enable status from the NVIC interrupt controller. |
| \param [in] IRQn Device specific interrupt number. |
| \return 0 Interrupt is not enabled. |
| \return 1 Interrupt is enabled. |
| \note IRQn must not be negative. |
| */ |
| __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) |
| { |
| if ((int32_t)(IRQn) >= 0) |
| { |
| return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| } |
| else |
| { |
| return(0U); |
| } |
| } |
| |
| |
| /** |
| \brief Disable Interrupt |
| \details Disables a device specific interrupt in the NVIC interrupt controller. |
| \param [in] IRQn Device specific interrupt number. |
| \note IRQn must not be negative. |
| */ |
| __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) |
| { |
| if ((int32_t)(IRQn) >= 0) |
| { |
| NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
| __DSB(); |
| __ISB(); |
| } |
| } |
| |
| |
| /** |
| \brief Get Pending Interrupt |
| \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. |
| \param [in] IRQn Device specific interrupt number. |
| \return 0 Interrupt status is not pending. |
| \return 1 Interrupt status is pending. |
| \note IRQn must not be negative. |
| */ |
| __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) |
| { |
| if ((int32_t)(IRQn) >= 0) |
| { |
| return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| } |
| else |
| { |
| return(0U); |
| } |
| } |
| |
| |
| /** |
| \brief Set Pending Interrupt |
| \details Sets the pending bit of a device specific interrupt in the NVIC pending register. |
| \param [in] IRQn Device specific interrupt number. |
| \note IRQn must not be negative. |
| */ |
| __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) |
| { |
| if ((int32_t)(IRQn) >= 0) |
| { |
| NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
| } |
| } |
| |
| |
| /** |
| \brief Clear Pending Interrupt |
| \details Clears the pending bit of a device specific interrupt in the NVIC pending register. |
| \param [in] IRQn Device specific interrupt number. |
| \note IRQn must not be negative. |
| */ |
| __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
| { |
| if ((int32_t)(IRQn) >= 0) |
| { |
| NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
| } |
| } |
| |
| |
| /** |
| \brief Set Interrupt Priority |
| \details Sets the priority of a device specific interrupt or a processor exception. |
| The interrupt number can be positive to specify a device specific interrupt, |
| or negative to specify a processor exception. |
| \param [in] IRQn Interrupt number. |
| \param [in] priority Priority to set. |
| \note The priority cannot be set for every processor exception. |
| */ |
| __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
| { |
| if ((int32_t)(IRQn) >= 0) |
| { |
| NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
| (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
| } |
| else |
| { |
| SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
| (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
| } |
| } |
| |
| |
| /** |
| \brief Get Interrupt Priority |
| \details Reads the priority of a device specific interrupt or a processor exception. |
| The interrupt number can be positive to specify a device specific interrupt, |
| or negative to specify a processor exception. |
| \param [in] IRQn Interrupt number. |
| \return Interrupt Priority. |
| Value is aligned automatically to the implemented priority bits of the microcontroller. |
| */ |
| __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) |
| { |
| |
| if ((int32_t)(IRQn) >= 0) |
| { |
| return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
| } |
| else |
| { |
| return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
| } |
| } |
| |
| |
| /** |
| \brief Encode Priority |
| \details Encodes the priority for an interrupt with the given priority group, |
| preemptive priority value, and subpriority value. |
| In case of a conflict between priority grouping and available |
| priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
| \param [in] PriorityGroup Used priority group. |
| \param [in] PreemptPriority Preemptive priority value (starting from 0). |
| \param [in] SubPriority Subpriority value (starting from 0). |
| \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). |
| */ |
| __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
| { |
| uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
| uint32_t PreemptPriorityBits; |
| uint32_t SubPriorityBits; |
| |
| PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
| SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
| |
| return ( |
| ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | |
| ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) |
| ); |
| } |
| |
| |
| /** |
| \brief Decode Priority |
| \details Decodes an interrupt priority value with a given priority group to |
| preemptive priority value and subpriority value. |
| In case of a conflict between priority grouping and available |
| priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
| \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). |
| \param [in] PriorityGroup Used priority group. |
| \param [out] pPreemptPriority Preemptive priority value (starting from 0). |
| \param [out] pSubPriority Subpriority value (starting from 0). |
| */ |
| __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) |
| { |
| uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
| uint32_t PreemptPriorityBits; |
| uint32_t SubPriorityBits; |
| |
| PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
| SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
| |
| *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); |
| *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); |
| } |
| |
| |
| /** |
| \brief Set Interrupt Vector |
| \details Sets an interrupt vector in SRAM based interrupt vector table. |
| The interrupt number can be positive to specify a device specific interrupt, |
| or negative to specify a processor exception. |
| VTOR must been relocated to SRAM before. |
| If VTOR is not present address 0 must be mapped to SRAM. |
| \param [in] IRQn Interrupt number |
| \param [in] vector Address of interrupt handler function |
| */ |
| __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) |
| { |
| #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) |
| uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); |
| vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; |
| #else |
| uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ |
| *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ |
| #endif |
| /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ |
| } |
| |
| |
| /** |
| \brief Get Interrupt Vector |
| \details Reads an interrupt vector from interrupt vector table. |
| The interrupt number can be positive to specify a device specific interrupt, |
| or negative to specify a processor exception. |
| \param [in] IRQn Interrupt number. |
| \return Address of interrupt handler function |
| */ |
| __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) |
| { |
| #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) |
| uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); |
| return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; |
| #else |
| uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ |
| return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ |
| #endif |
| } |
| |
| |
| /** |
| \brief System Reset |
| \details Initiates a system reset request to reset the MCU. |
| */ |
| __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) |
| { |
| __DSB(); /* Ensure all outstanding memory accesses included |
| buffered write are completed before reset */ |
| SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
| SCB_AIRCR_SYSRESETREQ_Msk); |
| __DSB(); /* Ensure completion of memory access */ |
| |
| for(;;) /* wait until reset */ |
| { |
| __NOP(); |
| } |
| } |
| |
| /*@} end of CMSIS_Core_NVICFunctions */ |
| |
| /* ########################## MPU functions #################################### */ |
| |
| #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
| |
| #include "m-profile/armv7m_mpu.h" |
| |
| #endif |
| |
| /* ########################## FPU functions #################################### */ |
| /** |
| \ingroup CMSIS_Core_FunctionInterface |
| \defgroup CMSIS_Core_FpuFunctions FPU Functions |
| \brief Function that provides FPU type. |
| @{ |
| */ |
| |
| /** |
| \brief get FPU type |
| \details returns the FPU type |
| \returns |
| - \b 0: No FPU |
| - \b 1: Single precision FPU |
| - \b 2: Double + Single precision FPU |
| */ |
| __STATIC_INLINE uint32_t SCB_GetFPUType(void) |
| { |
| return 0U; /* No FPU */ |
| } |
| |
| |
| /*@} end of CMSIS_Core_FpuFunctions */ |
| |
| |
| |
| /* ################################## SysTick function ############################################ */ |
| /** |
| \ingroup CMSIS_Core_FunctionInterface |
| \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
| \brief Functions that configure the System. |
| @{ |
| */ |
| |
| #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) |
| |
| /** |
| \brief System Tick Configuration |
| \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
| Counter is in free running mode to generate periodic interrupts. |
| \param [in] ticks Number of ticks between two interrupts. |
| \return 0 Function succeeded. |
| \return 1 Function failed. |
| \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
| function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
| must contain a vendor-specific implementation of this function. |
| */ |
| __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
| { |
| if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
| { |
| return (1UL); /* Reload value impossible */ |
| } |
| |
| SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
| NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
| SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
| SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
| SysTick_CTRL_TICKINT_Msk | |
| SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
| return (0UL); /* Function successful */ |
| } |
| |
| #endif |
| |
| /*@} end of CMSIS_Core_SysTickFunctions */ |
| |
| |
| |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| |
| #endif /* __CORE_CM0PLUS_H_DEPENDANT */ |
| |
| #endif /* __CMSIS_GENERIC */ |
