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pigweed / third_party / github / raspberrypi / pico-sdk / efe2103f9b28458a1615ff096054479743ade236 / . / src / rp2_common / cmsis / stub / CMSIS / Device / RP2350 / Include / RP2350.h
blob: 8ae014e047f75e7aced9cde97b0e5a1f396a1652 [file] [log] [blame]
/*
* Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause
*
* @file src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h
* @brief CMSIS HeaderFile
* @version 0.1
* @date Thu Aug 8 04:04:02 2024
* @note Generated by SVDConv V3.3.47
* from File 'src/rp2_common/cmsis/../../rp2350/hardware_regs/RP2350.svd',
* last modified on Thu Aug 8 03:59:33 2024
*/
/** @addtogroup Raspberry Pi
* @{
*/
/** @addtogroup RP2350
* @{
*/
#ifndef RP2350_H
#define RP2350_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
typedef enum {
/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* =========================================== RP2350 Specific Interrupt Numbers =========================================== */
TIMER0_IRQ_0_IRQn = 0, /*!< 0 TIMER0_IRQ_0 */
TIMER0_IRQ_1_IRQn = 1, /*!< 1 TIMER0_IRQ_1 */
TIMER0_IRQ_2_IRQn = 2, /*!< 2 TIMER0_IRQ_2 */
TIMER0_IRQ_3_IRQn = 3, /*!< 3 TIMER0_IRQ_3 */
TIMER1_IRQ_0_IRQn = 4, /*!< 4 TIMER1_IRQ_0 */
TIMER1_IRQ_1_IRQn = 5, /*!< 5 TIMER1_IRQ_1 */
TIMER1_IRQ_2_IRQn = 6, /*!< 6 TIMER1_IRQ_2 */
TIMER1_IRQ_3_IRQn = 7, /*!< 7 TIMER1_IRQ_3 */
PWM_IRQ_WRAP_0_IRQn = 8, /*!< 8 PWM_IRQ_WRAP_0 */
PWM_IRQ_WRAP_1_IRQn = 9, /*!< 9 PWM_IRQ_WRAP_1 */
DMA_IRQ_0_IRQn = 10, /*!< 10 DMA_IRQ_0 */
DMA_IRQ_1_IRQn = 11, /*!< 11 DMA_IRQ_1 */
DMA_IRQ_2_IRQn = 12, /*!< 12 DMA_IRQ_2 */
DMA_IRQ_3_IRQn = 13, /*!< 13 DMA_IRQ_3 */
USBCTRL_IRQ_IRQn = 14, /*!< 14 USBCTRL_IRQ */
PIO0_IRQ_0_IRQn = 15, /*!< 15 PIO0_IRQ_0 */
PIO0_IRQ_1_IRQn = 16, /*!< 16 PIO0_IRQ_1 */
PIO1_IRQ_0_IRQn = 17, /*!< 17 PIO1_IRQ_0 */
PIO1_IRQ_1_IRQn = 18, /*!< 18 PIO1_IRQ_1 */
PIO2_IRQ_0_IRQn = 19, /*!< 19 PIO2_IRQ_0 */
PIO2_IRQ_1_IRQn = 20, /*!< 20 PIO2_IRQ_1 */
IO_IRQ_BANK0_IRQn = 21, /*!< 21 IO_IRQ_BANK0 */
IO_IRQ_BANK0_NS_IRQn = 22, /*!< 22 IO_IRQ_BANK0_NS */
IO_IRQ_QSPI_IRQn = 23, /*!< 23 IO_IRQ_QSPI */
IO_IRQ_QSPI_NS_IRQn = 24, /*!< 24 IO_IRQ_QSPI_NS */
SIO_IRQ_FIFO_IRQn = 25, /*!< 25 SIO_IRQ_FIFO */
SIO_IRQ_BELL_IRQn = 26, /*!< 26 SIO_IRQ_BELL */
SIO_IRQ_FIFO_NS_IRQn = 27, /*!< 27 SIO_IRQ_FIFO_NS */
SIO_IRQ_BELL_NS_IRQn = 28, /*!< 28 SIO_IRQ_BELL_NS */
SIO_IRQ_MTIMECMP_IRQn = 29, /*!< 29 SIO_IRQ_MTIMECMP */
CLOCKS_IRQ_IRQn = 30, /*!< 30 CLOCKS_IRQ */
SPI0_IRQ_IRQn = 31, /*!< 31 SPI0_IRQ */
SPI1_IRQ_IRQn = 32, /*!< 32 SPI1_IRQ */
UART0_IRQ_IRQn = 33, /*!< 33 UART0_IRQ */
UART1_IRQ_IRQn = 34, /*!< 34 UART1_IRQ */
ADC_IRQ_FIFO_IRQn = 35, /*!< 35 ADC_IRQ_FIFO */
I2C0_IRQ_IRQn = 36, /*!< 36 I2C0_IRQ */
I2C1_IRQ_IRQn = 37, /*!< 37 I2C1_IRQ */
OTP_IRQ_IRQn = 38, /*!< 38 OTP_IRQ */
TRNG_IRQ_IRQn = 39, /*!< 39 TRNG_IRQ */
PLL_SYS_IRQ_IRQn = 42, /*!< 42 PLL_SYS_IRQ */
PLL_USB_IRQ_IRQn = 43, /*!< 43 PLL_USB_IRQ */
POWMAN_IRQ_POW_IRQn = 44, /*!< 44 POWMAN_IRQ_POW */
POWMAN_IRQ_TIMER_IRQn = 45 /*!< 45 POWMAN_IRQ_TIMER */
} IRQn_Type;
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */
#define __CM33_REV 0x0100U /*!< CM33 Core Revision */
#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __MPU_PRESENT 1 /*!< MPU present */
#define __FPU_PRESENT 1 /*!< FPU present */
#define __FPU_DP 0 /*!< Double Precision FPU */
#define __DSP_PRESENT 1 /*!< DSP extension present */
#define __SAUREGION_PRESENT 1 /*!< SAU region present */
/** @} */ /* End of group Configuration_of_CMSIS */
#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
#include "system_RP2350.h" /*!< RP2350 System */
#ifndef __IM /*!< Fallback for older CMSIS versions */
#define __IM __I
#endif
#ifndef __OM /*!< Fallback for older CMSIS versions */
#define __OM __O
#endif
#ifndef __IOM /*!< Fallback for older CMSIS versions */
#define __IOM __IO
#endif
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Section ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripherals
* @{
*/
/* =========================================================================================================================== */
/* ================ RESETS ================ */
/* =========================================================================================================================== */
/**
* @brief RESETS (RESETS)
*/
typedef struct { /*!< RESETS Structure */
__IOM uint32_t RESET; /*!< RESET */
__IOM uint32_t WDSEL; /*!< WDSEL */
__IOM uint32_t RESET_DONE; /*!< RESET_DONE */
} RESETS_Type; /*!< Size = 12 (0xc) */
/* =========================================================================================================================== */
/* ================ PSM ================ */
/* =========================================================================================================================== */
/**
* @brief PSM (PSM)
*/
typedef struct { /*!< PSM Structure */
__IOM uint32_t FRCE_ON; /*!< Force block out of reset (i.e. power it on) */
__IOM uint32_t FRCE_OFF; /*!< Force into reset (i.e. power it off) */
__IOM uint32_t WDSEL; /*!< Set to 1 if the watchdog should reset this */
__IOM uint32_t DONE; /*!< Is the subsystem ready? */
} PSM_Type; /*!< Size = 16 (0x10) */
/* =========================================================================================================================== */
/* ================ CLOCKS ================ */
/* =========================================================================================================================== */
/**
* @brief CLOCKS (CLOCKS)
*/
typedef struct { /*!< CLOCKS Structure */
__IOM uint32_t CLK_GPOUT0_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */
__IOM uint32_t CLK_GPOUT0_DIV; /*!< CLK_GPOUT0_DIV */
__IOM uint32_t CLK_GPOUT0_SELECTED; /*!< Indicates which src is currently selected (one-hot) */
__IOM uint32_t CLK_GPOUT1_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */
__IOM uint32_t CLK_GPOUT1_DIV; /*!< CLK_GPOUT1_DIV */
__IOM uint32_t CLK_GPOUT1_SELECTED; /*!< Indicates which src is currently selected (one-hot) */
__IOM uint32_t CLK_GPOUT2_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */
__IOM uint32_t CLK_GPOUT2_DIV; /*!< CLK_GPOUT2_DIV */
__IOM uint32_t CLK_GPOUT2_SELECTED; /*!< Indicates which src is currently selected (one-hot) */
__IOM uint32_t CLK_GPOUT3_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */
__IOM uint32_t CLK_GPOUT3_DIV; /*!< CLK_GPOUT3_DIV */
__IOM uint32_t CLK_GPOUT3_SELECTED; /*!< Indicates which src is currently selected (one-hot) */
__IOM uint32_t CLK_REF_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */
__IOM uint32_t CLK_REF_DIV; /*!< CLK_REF_DIV */
__IOM uint32_t CLK_REF_SELECTED; /*!< Indicates which src is currently selected (one-hot) */
__IOM uint32_t CLK_SYS_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */
__IOM uint32_t CLK_SYS_DIV; /*!< CLK_SYS_DIV */
__IOM uint32_t CLK_SYS_SELECTED; /*!< Indicates which src is currently selected (one-hot) */
__IOM uint32_t CLK_PERI_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */
__IOM uint32_t CLK_PERI_DIV; /*!< CLK_PERI_DIV */
__IOM uint32_t CLK_PERI_SELECTED; /*!< Indicates which src is currently selected (one-hot) */
__IOM uint32_t CLK_HSTX_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */
__IOM uint32_t CLK_HSTX_DIV; /*!< CLK_HSTX_DIV */
__IOM uint32_t CLK_HSTX_SELECTED; /*!< Indicates which src is currently selected (one-hot) */
__IOM uint32_t CLK_USB_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */
__IOM uint32_t CLK_USB_DIV; /*!< CLK_USB_DIV */
__IOM uint32_t CLK_USB_SELECTED; /*!< Indicates which src is currently selected (one-hot) */
__IOM uint32_t CLK_ADC_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */
__IOM uint32_t CLK_ADC_DIV; /*!< CLK_ADC_DIV */
__IOM uint32_t CLK_ADC_SELECTED; /*!< Indicates which src is currently selected (one-hot) */
__IOM uint32_t DFTCLK_XOSC_CTRL; /*!< DFTCLK_XOSC_CTRL */
__IOM uint32_t DFTCLK_ROSC_CTRL; /*!< DFTCLK_ROSC_CTRL */
__IOM uint32_t DFTCLK_LPOSC_CTRL; /*!< DFTCLK_LPOSC_CTRL */
__IOM uint32_t CLK_SYS_RESUS_CTRL; /*!< CLK_SYS_RESUS_CTRL */
__IOM uint32_t CLK_SYS_RESUS_STATUS; /*!< CLK_SYS_RESUS_STATUS */
__IOM uint32_t FC0_REF_KHZ; /*!< Reference clock frequency in kHz */
__IOM uint32_t FC0_MIN_KHZ; /*!< Minimum pass frequency in kHz. This is optional. Set to 0 if
you are not using the pass/fail flags */
__IOM uint32_t FC0_MAX_KHZ; /*!< Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff
if you are not using the pass/fail flags */
__IOM uint32_t FC0_DELAY; /*!< Delays the start of frequency counting to allow the mux to settle
Delay is measured in multiples of the reference clock period */
__IOM uint32_t FC0_INTERVAL; /*!< The test interval is 0.98us * 2**interval, but let's call it
1us * 2**interval The default gives a test interval of
250us */
__IOM uint32_t FC0_SRC; /*!< Clock sent to frequency counter, set to 0 when not required
Writing to this register initiates the frequency count */
__IOM uint32_t FC0_STATUS; /*!< Frequency counter status */
__IOM uint32_t FC0_RESULT; /*!< Result of frequency measurement, only valid when status_done=1 */
__IOM uint32_t WAKE_EN0; /*!< enable clock in wake mode */
__IOM uint32_t WAKE_EN1; /*!< enable clock in wake mode */
__IOM uint32_t SLEEP_EN0; /*!< enable clock in sleep mode */
__IOM uint32_t SLEEP_EN1; /*!< enable clock in sleep mode */
__IOM uint32_t ENABLED0; /*!< indicates the state of the clock enable */
__IOM uint32_t ENABLED1; /*!< indicates the state of the clock enable */
__IOM uint32_t INTR; /*!< Raw Interrupts */
__IOM uint32_t INTE; /*!< Interrupt Enable */
__IOM uint32_t INTF; /*!< Interrupt Force */
__IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */
} CLOCKS_Type; /*!< Size = 212 (0xd4) */
/* =========================================================================================================================== */
/* ================ TICKS ================ */
/* =========================================================================================================================== */
/**
* @brief TICKS (TICKS)
*/
typedef struct { /*!< TICKS Structure */
__IOM uint32_t PROC0_CTRL; /*!< Controls the tick generator */
__IOM uint32_t PROC0_CYCLES; /*!< PROC0_CYCLES */
__IOM uint32_t PROC0_COUNT; /*!< PROC0_COUNT */
__IOM uint32_t PROC1_CTRL; /*!< Controls the tick generator */
__IOM uint32_t PROC1_CYCLES; /*!< PROC1_CYCLES */
__IOM uint32_t PROC1_COUNT; /*!< PROC1_COUNT */
__IOM uint32_t TIMER0_CTRL; /*!< Controls the tick generator */
__IOM uint32_t TIMER0_CYCLES; /*!< TIMER0_CYCLES */
__IOM uint32_t TIMER0_COUNT; /*!< TIMER0_COUNT */
__IOM uint32_t TIMER1_CTRL; /*!< Controls the tick generator */
__IOM uint32_t TIMER1_CYCLES; /*!< TIMER1_CYCLES */
__IOM uint32_t TIMER1_COUNT; /*!< TIMER1_COUNT */
__IOM uint32_t WATCHDOG_CTRL; /*!< Controls the tick generator */
__IOM uint32_t WATCHDOG_CYCLES; /*!< WATCHDOG_CYCLES */
__IOM uint32_t WATCHDOG_COUNT; /*!< WATCHDOG_COUNT */
__IOM uint32_t RISCV_CTRL; /*!< Controls the tick generator */
__IOM uint32_t RISCV_CYCLES; /*!< RISCV_CYCLES */
__IOM uint32_t RISCV_COUNT; /*!< RISCV_COUNT */
} TICKS_Type; /*!< Size = 72 (0x48) */
/* =========================================================================================================================== */
/* ================ PADS_BANK0 ================ */
/* =========================================================================================================================== */
/**
* @brief PADS_BANK0 (PADS_BANK0)
*/
typedef struct { /*!< PADS_BANK0 Structure */
__IOM uint32_t VOLTAGE_SELECT; /*!< Voltage select. Per bank control */
__IOM uint32_t GPIO0; /*!< GPIO0 */
__IOM uint32_t GPIO1; /*!< GPIO1 */
__IOM uint32_t GPIO2; /*!< GPIO2 */
__IOM uint32_t GPIO3; /*!< GPIO3 */
__IOM uint32_t GPIO4; /*!< GPIO4 */
__IOM uint32_t GPIO5; /*!< GPIO5 */
__IOM uint32_t GPIO6; /*!< GPIO6 */
__IOM uint32_t GPIO7; /*!< GPIO7 */
__IOM uint32_t GPIO8; /*!< GPIO8 */
__IOM uint32_t GPIO9; /*!< GPIO9 */
__IOM uint32_t GPIO10; /*!< GPIO10 */
__IOM uint32_t GPIO11; /*!< GPIO11 */
__IOM uint32_t GPIO12; /*!< GPIO12 */
__IOM uint32_t GPIO13; /*!< GPIO13 */
__IOM uint32_t GPIO14; /*!< GPIO14 */
__IOM uint32_t GPIO15; /*!< GPIO15 */
__IOM uint32_t GPIO16; /*!< GPIO16 */
__IOM uint32_t GPIO17; /*!< GPIO17 */
__IOM uint32_t GPIO18; /*!< GPIO18 */
__IOM uint32_t GPIO19; /*!< GPIO19 */
__IOM uint32_t GPIO20; /*!< GPIO20 */
__IOM uint32_t GPIO21; /*!< GPIO21 */
__IOM uint32_t GPIO22; /*!< GPIO22 */
__IOM uint32_t GPIO23; /*!< GPIO23 */
__IOM uint32_t GPIO24; /*!< GPIO24 */
__IOM uint32_t GPIO25; /*!< GPIO25 */
__IOM uint32_t GPIO26; /*!< GPIO26 */
__IOM uint32_t GPIO27; /*!< GPIO27 */
__IOM uint32_t GPIO28; /*!< GPIO28 */
__IOM uint32_t GPIO29; /*!< GPIO29 */
__IOM uint32_t GPIO30; /*!< GPIO30 */
__IOM uint32_t GPIO31; /*!< GPIO31 */
__IOM uint32_t GPIO32; /*!< GPIO32 */
__IOM uint32_t GPIO33; /*!< GPIO33 */
__IOM uint32_t GPIO34; /*!< GPIO34 */
__IOM uint32_t GPIO35; /*!< GPIO35 */
__IOM uint32_t GPIO36; /*!< GPIO36 */
__IOM uint32_t GPIO37; /*!< GPIO37 */
__IOM uint32_t GPIO38; /*!< GPIO38 */
__IOM uint32_t GPIO39; /*!< GPIO39 */
__IOM uint32_t GPIO40; /*!< GPIO40 */
__IOM uint32_t GPIO41; /*!< GPIO41 */
__IOM uint32_t GPIO42; /*!< GPIO42 */
__IOM uint32_t GPIO43; /*!< GPIO43 */
__IOM uint32_t GPIO44; /*!< GPIO44 */
__IOM uint32_t GPIO45; /*!< GPIO45 */
__IOM uint32_t GPIO46; /*!< GPIO46 */
__IOM uint32_t GPIO47; /*!< GPIO47 */
__IOM uint32_t SWCLK; /*!< SWCLK */
__IOM uint32_t SWD; /*!< SWD */
} PADS_BANK0_Type; /*!< Size = 204 (0xcc) */
/* =========================================================================================================================== */
/* ================ PADS_QSPI ================ */
/* =========================================================================================================================== */
/**
* @brief PADS_QSPI (PADS_QSPI)
*/
typedef struct { /*!< PADS_QSPI Structure */
__IOM uint32_t VOLTAGE_SELECT; /*!< Voltage select. Per bank control */
__IOM uint32_t GPIO_QSPI_SCLK; /*!< GPIO_QSPI_SCLK */
__IOM uint32_t GPIO_QSPI_SD0; /*!< GPIO_QSPI_SD0 */
__IOM uint32_t GPIO_QSPI_SD1; /*!< GPIO_QSPI_SD1 */
__IOM uint32_t GPIO_QSPI_SD2; /*!< GPIO_QSPI_SD2 */
__IOM uint32_t GPIO_QSPI_SD3; /*!< GPIO_QSPI_SD3 */
__IOM uint32_t GPIO_QSPI_SS; /*!< GPIO_QSPI_SS */
} PADS_QSPI_Type; /*!< Size = 28 (0x1c) */
/* =========================================================================================================================== */
/* ================ IO_QSPI ================ */
/* =========================================================================================================================== */
/**
* @brief IO_QSPI (IO_QSPI)
*/
typedef struct { /*!< IO_QSPI Structure */
__IOM uint32_t USBPHY_DP_STATUS; /*!< USBPHY_DP_STATUS */
__IOM uint32_t USBPHY_DP_CTRL; /*!< USBPHY_DP_CTRL */
__IOM uint32_t USBPHY_DM_STATUS; /*!< USBPHY_DM_STATUS */
__IOM uint32_t USBPHY_DM_CTRL; /*!< USBPHY_DM_CTRL */
__IOM uint32_t GPIO_QSPI_SCLK_STATUS; /*!< GPIO_QSPI_SCLK_STATUS */
__IOM uint32_t GPIO_QSPI_SCLK_CTRL; /*!< GPIO_QSPI_SCLK_CTRL */
__IOM uint32_t GPIO_QSPI_SS_STATUS; /*!< GPIO_QSPI_SS_STATUS */
__IOM uint32_t GPIO_QSPI_SS_CTRL; /*!< GPIO_QSPI_SS_CTRL */
__IOM uint32_t GPIO_QSPI_SD0_STATUS; /*!< GPIO_QSPI_SD0_STATUS */
__IOM uint32_t GPIO_QSPI_SD0_CTRL; /*!< GPIO_QSPI_SD0_CTRL */
__IOM uint32_t GPIO_QSPI_SD1_STATUS; /*!< GPIO_QSPI_SD1_STATUS */
__IOM uint32_t GPIO_QSPI_SD1_CTRL; /*!< GPIO_QSPI_SD1_CTRL */
__IOM uint32_t GPIO_QSPI_SD2_STATUS; /*!< GPIO_QSPI_SD2_STATUS */
__IOM uint32_t GPIO_QSPI_SD2_CTRL; /*!< GPIO_QSPI_SD2_CTRL */
__IOM uint32_t GPIO_QSPI_SD3_STATUS; /*!< GPIO_QSPI_SD3_STATUS */
__IOM uint32_t GPIO_QSPI_SD3_CTRL; /*!< GPIO_QSPI_SD3_CTRL */
__IM uint32_t RESERVED[112];
__IOM uint32_t IRQSUMMARY_PROC0_SECURE; /*!< IRQSUMMARY_PROC0_SECURE */
__IOM uint32_t IRQSUMMARY_PROC0_NONSECURE; /*!< IRQSUMMARY_PROC0_NONSECURE */
__IOM uint32_t IRQSUMMARY_PROC1_SECURE; /*!< IRQSUMMARY_PROC1_SECURE */
__IOM uint32_t IRQSUMMARY_PROC1_NONSECURE; /*!< IRQSUMMARY_PROC1_NONSECURE */
__IOM uint32_t IRQSUMMARY_DORMANT_WAKE_SECURE;/*!< IRQSUMMARY_DORMANT_WAKE_SECURE */
__IOM uint32_t IRQSUMMARY_DORMANT_WAKE_NONSECURE;/*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE */
__IOM uint32_t INTR; /*!< Raw Interrupts */
__IOM uint32_t PROC0_INTE; /*!< Interrupt Enable for proc0 */
__IOM uint32_t PROC0_INTF; /*!< Interrupt Force for proc0 */
__IOM uint32_t PROC0_INTS; /*!< Interrupt status after masking & forcing for proc0 */
__IOM uint32_t PROC1_INTE; /*!< Interrupt Enable for proc1 */
__IOM uint32_t PROC1_INTF; /*!< Interrupt Force for proc1 */
__IOM uint32_t PROC1_INTS; /*!< Interrupt status after masking & forcing for proc1 */
__IOM uint32_t DORMANT_WAKE_INTE; /*!< Interrupt Enable for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTF; /*!< Interrupt Force for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTS; /*!< Interrupt status after masking & forcing for dormant_wake */
} IO_QSPI_Type; /*!< Size = 576 (0x240) */
/* =========================================================================================================================== */
/* ================ IO_BANK0 ================ */
/* =========================================================================================================================== */
/**
* @brief IO_BANK0 (IO_BANK0)
*/
typedef struct { /*!< IO_BANK0 Structure */
__IOM uint32_t GPIO0_STATUS; /*!< GPIO0_STATUS */
__IOM uint32_t GPIO0_CTRL; /*!< GPIO0_CTRL */
__IOM uint32_t GPIO1_STATUS; /*!< GPIO1_STATUS */
__IOM uint32_t GPIO1_CTRL; /*!< GPIO1_CTRL */
__IOM uint32_t GPIO2_STATUS; /*!< GPIO2_STATUS */
__IOM uint32_t GPIO2_CTRL; /*!< GPIO2_CTRL */
__IOM uint32_t GPIO3_STATUS; /*!< GPIO3_STATUS */
__IOM uint32_t GPIO3_CTRL; /*!< GPIO3_CTRL */
__IOM uint32_t GPIO4_STATUS; /*!< GPIO4_STATUS */
__IOM uint32_t GPIO4_CTRL; /*!< GPIO4_CTRL */
__IOM uint32_t GPIO5_STATUS; /*!< GPIO5_STATUS */
__IOM uint32_t GPIO5_CTRL; /*!< GPIO5_CTRL */
__IOM uint32_t GPIO6_STATUS; /*!< GPIO6_STATUS */
__IOM uint32_t GPIO6_CTRL; /*!< GPIO6_CTRL */
__IOM uint32_t GPIO7_STATUS; /*!< GPIO7_STATUS */
__IOM uint32_t GPIO7_CTRL; /*!< GPIO7_CTRL */
__IOM uint32_t GPIO8_STATUS; /*!< GPIO8_STATUS */
__IOM uint32_t GPIO8_CTRL; /*!< GPIO8_CTRL */
__IOM uint32_t GPIO9_STATUS; /*!< GPIO9_STATUS */
__IOM uint32_t GPIO9_CTRL; /*!< GPIO9_CTRL */
__IOM uint32_t GPIO10_STATUS; /*!< GPIO10_STATUS */
__IOM uint32_t GPIO10_CTRL; /*!< GPIO10_CTRL */
__IOM uint32_t GPIO11_STATUS; /*!< GPIO11_STATUS */
__IOM uint32_t GPIO11_CTRL; /*!< GPIO11_CTRL */
__IOM uint32_t GPIO12_STATUS; /*!< GPIO12_STATUS */
__IOM uint32_t GPIO12_CTRL; /*!< GPIO12_CTRL */
__IOM uint32_t GPIO13_STATUS; /*!< GPIO13_STATUS */
__IOM uint32_t GPIO13_CTRL; /*!< GPIO13_CTRL */
__IOM uint32_t GPIO14_STATUS; /*!< GPIO14_STATUS */
__IOM uint32_t GPIO14_CTRL; /*!< GPIO14_CTRL */
__IOM uint32_t GPIO15_STATUS; /*!< GPIO15_STATUS */
__IOM uint32_t GPIO15_CTRL; /*!< GPIO15_CTRL */
__IOM uint32_t GPIO16_STATUS; /*!< GPIO16_STATUS */
__IOM uint32_t GPIO16_CTRL; /*!< GPIO16_CTRL */
__IOM uint32_t GPIO17_STATUS; /*!< GPIO17_STATUS */
__IOM uint32_t GPIO17_CTRL; /*!< GPIO17_CTRL */
__IOM uint32_t GPIO18_STATUS; /*!< GPIO18_STATUS */
__IOM uint32_t GPIO18_CTRL; /*!< GPIO18_CTRL */
__IOM uint32_t GPIO19_STATUS; /*!< GPIO19_STATUS */
__IOM uint32_t GPIO19_CTRL; /*!< GPIO19_CTRL */
__IOM uint32_t GPIO20_STATUS; /*!< GPIO20_STATUS */
__IOM uint32_t GPIO20_CTRL; /*!< GPIO20_CTRL */
__IOM uint32_t GPIO21_STATUS; /*!< GPIO21_STATUS */
__IOM uint32_t GPIO21_CTRL; /*!< GPIO21_CTRL */
__IOM uint32_t GPIO22_STATUS; /*!< GPIO22_STATUS */
__IOM uint32_t GPIO22_CTRL; /*!< GPIO22_CTRL */
__IOM uint32_t GPIO23_STATUS; /*!< GPIO23_STATUS */
__IOM uint32_t GPIO23_CTRL; /*!< GPIO23_CTRL */
__IOM uint32_t GPIO24_STATUS; /*!< GPIO24_STATUS */
__IOM uint32_t GPIO24_CTRL; /*!< GPIO24_CTRL */
__IOM uint32_t GPIO25_STATUS; /*!< GPIO25_STATUS */
__IOM uint32_t GPIO25_CTRL; /*!< GPIO25_CTRL */
__IOM uint32_t GPIO26_STATUS; /*!< GPIO26_STATUS */
__IOM uint32_t GPIO26_CTRL; /*!< GPIO26_CTRL */
__IOM uint32_t GPIO27_STATUS; /*!< GPIO27_STATUS */
__IOM uint32_t GPIO27_CTRL; /*!< GPIO27_CTRL */
__IOM uint32_t GPIO28_STATUS; /*!< GPIO28_STATUS */
__IOM uint32_t GPIO28_CTRL; /*!< GPIO28_CTRL */
__IOM uint32_t GPIO29_STATUS; /*!< GPIO29_STATUS */
__IOM uint32_t GPIO29_CTRL; /*!< GPIO29_CTRL */
__IOM uint32_t GPIO30_STATUS; /*!< GPIO30_STATUS */
__IOM uint32_t GPIO30_CTRL; /*!< GPIO30_CTRL */
__IOM uint32_t GPIO31_STATUS; /*!< GPIO31_STATUS */
__IOM uint32_t GPIO31_CTRL; /*!< GPIO31_CTRL */
__IOM uint32_t GPIO32_STATUS; /*!< GPIO32_STATUS */
__IOM uint32_t GPIO32_CTRL; /*!< GPIO32_CTRL */
__IOM uint32_t GPIO33_STATUS; /*!< GPIO33_STATUS */
__IOM uint32_t GPIO33_CTRL; /*!< GPIO33_CTRL */
__IOM uint32_t GPIO34_STATUS; /*!< GPIO34_STATUS */
__IOM uint32_t GPIO34_CTRL; /*!< GPIO34_CTRL */
__IOM uint32_t GPIO35_STATUS; /*!< GPIO35_STATUS */
__IOM uint32_t GPIO35_CTRL; /*!< GPIO35_CTRL */
__IOM uint32_t GPIO36_STATUS; /*!< GPIO36_STATUS */
__IOM uint32_t GPIO36_CTRL; /*!< GPIO36_CTRL */
__IOM uint32_t GPIO37_STATUS; /*!< GPIO37_STATUS */
__IOM uint32_t GPIO37_CTRL; /*!< GPIO37_CTRL */
__IOM uint32_t GPIO38_STATUS; /*!< GPIO38_STATUS */
__IOM uint32_t GPIO38_CTRL; /*!< GPIO38_CTRL */
__IOM uint32_t GPIO39_STATUS; /*!< GPIO39_STATUS */
__IOM uint32_t GPIO39_CTRL; /*!< GPIO39_CTRL */
__IOM uint32_t GPIO40_STATUS; /*!< GPIO40_STATUS */
__IOM uint32_t GPIO40_CTRL; /*!< GPIO40_CTRL */
__IOM uint32_t GPIO41_STATUS; /*!< GPIO41_STATUS */
__IOM uint32_t GPIO41_CTRL; /*!< GPIO41_CTRL */
__IOM uint32_t GPIO42_STATUS; /*!< GPIO42_STATUS */
__IOM uint32_t GPIO42_CTRL; /*!< GPIO42_CTRL */
__IOM uint32_t GPIO43_STATUS; /*!< GPIO43_STATUS */
__IOM uint32_t GPIO43_CTRL; /*!< GPIO43_CTRL */
__IOM uint32_t GPIO44_STATUS; /*!< GPIO44_STATUS */
__IOM uint32_t GPIO44_CTRL; /*!< GPIO44_CTRL */
__IOM uint32_t GPIO45_STATUS; /*!< GPIO45_STATUS */
__IOM uint32_t GPIO45_CTRL; /*!< GPIO45_CTRL */
__IOM uint32_t GPIO46_STATUS; /*!< GPIO46_STATUS */
__IOM uint32_t GPIO46_CTRL; /*!< GPIO46_CTRL */
__IOM uint32_t GPIO47_STATUS; /*!< GPIO47_STATUS */
__IOM uint32_t GPIO47_CTRL; /*!< GPIO47_CTRL */
__IM uint32_t RESERVED[32];
__IOM uint32_t IRQSUMMARY_PROC0_SECURE0; /*!< IRQSUMMARY_PROC0_SECURE0 */
__IOM uint32_t IRQSUMMARY_PROC0_SECURE1; /*!< IRQSUMMARY_PROC0_SECURE1 */
__IOM uint32_t IRQSUMMARY_PROC0_NONSECURE0; /*!< IRQSUMMARY_PROC0_NONSECURE0 */
__IOM uint32_t IRQSUMMARY_PROC0_NONSECURE1; /*!< IRQSUMMARY_PROC0_NONSECURE1 */
__IOM uint32_t IRQSUMMARY_PROC1_SECURE0; /*!< IRQSUMMARY_PROC1_SECURE0 */
__IOM uint32_t IRQSUMMARY_PROC1_SECURE1; /*!< IRQSUMMARY_PROC1_SECURE1 */
__IOM uint32_t IRQSUMMARY_PROC1_NONSECURE0; /*!< IRQSUMMARY_PROC1_NONSECURE0 */
__IOM uint32_t IRQSUMMARY_PROC1_NONSECURE1; /*!< IRQSUMMARY_PROC1_NONSECURE1 */
__IOM uint32_t IRQSUMMARY_DORMANT_WAKE_SECURE0;/*!< IRQSUMMARY_DORMANT_WAKE_SECURE0 */
__IOM uint32_t IRQSUMMARY_DORMANT_WAKE_SECURE1;/*!< IRQSUMMARY_DORMANT_WAKE_SECURE1 */
__IOM uint32_t IRQSUMMARY_DORMANT_WAKE_NONSECURE0;/*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE0 */
__IOM uint32_t IRQSUMMARY_DORMANT_WAKE_NONSECURE1;/*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE1 */
__IOM uint32_t INTR0; /*!< Raw Interrupts */
__IOM uint32_t INTR1; /*!< Raw Interrupts */
__IOM uint32_t INTR2; /*!< Raw Interrupts */
__IOM uint32_t INTR3; /*!< Raw Interrupts */
__IOM uint32_t INTR4; /*!< Raw Interrupts */
__IOM uint32_t INTR5; /*!< Raw Interrupts */
__IOM uint32_t PROC0_INTE0; /*!< Interrupt Enable for proc0 */
__IOM uint32_t PROC0_INTE1; /*!< Interrupt Enable for proc0 */
__IOM uint32_t PROC0_INTE2; /*!< Interrupt Enable for proc0 */
__IOM uint32_t PROC0_INTE3; /*!< Interrupt Enable for proc0 */
__IOM uint32_t PROC0_INTE4; /*!< Interrupt Enable for proc0 */
__IOM uint32_t PROC0_INTE5; /*!< Interrupt Enable for proc0 */
__IOM uint32_t PROC0_INTF0; /*!< Interrupt Force for proc0 */
__IOM uint32_t PROC0_INTF1; /*!< Interrupt Force for proc0 */
__IOM uint32_t PROC0_INTF2; /*!< Interrupt Force for proc0 */
__IOM uint32_t PROC0_INTF3; /*!< Interrupt Force for proc0 */
__IOM uint32_t PROC0_INTF4; /*!< Interrupt Force for proc0 */
__IOM uint32_t PROC0_INTF5; /*!< Interrupt Force for proc0 */
__IOM uint32_t PROC0_INTS0; /*!< Interrupt status after masking & forcing for proc0 */
__IOM uint32_t PROC0_INTS1; /*!< Interrupt status after masking & forcing for proc0 */
__IOM uint32_t PROC0_INTS2; /*!< Interrupt status after masking & forcing for proc0 */
__IOM uint32_t PROC0_INTS3; /*!< Interrupt status after masking & forcing for proc0 */
__IOM uint32_t PROC0_INTS4; /*!< Interrupt status after masking & forcing for proc0 */
__IOM uint32_t PROC0_INTS5; /*!< Interrupt status after masking & forcing for proc0 */
__IOM uint32_t PROC1_INTE0; /*!< Interrupt Enable for proc1 */
__IOM uint32_t PROC1_INTE1; /*!< Interrupt Enable for proc1 */
__IOM uint32_t PROC1_INTE2; /*!< Interrupt Enable for proc1 */
__IOM uint32_t PROC1_INTE3; /*!< Interrupt Enable for proc1 */
__IOM uint32_t PROC1_INTE4; /*!< Interrupt Enable for proc1 */
__IOM uint32_t PROC1_INTE5; /*!< Interrupt Enable for proc1 */
__IOM uint32_t PROC1_INTF0; /*!< Interrupt Force for proc1 */
__IOM uint32_t PROC1_INTF1; /*!< Interrupt Force for proc1 */
__IOM uint32_t PROC1_INTF2; /*!< Interrupt Force for proc1 */
__IOM uint32_t PROC1_INTF3; /*!< Interrupt Force for proc1 */
__IOM uint32_t PROC1_INTF4; /*!< Interrupt Force for proc1 */
__IOM uint32_t PROC1_INTF5; /*!< Interrupt Force for proc1 */
__IOM uint32_t PROC1_INTS0; /*!< Interrupt status after masking & forcing for proc1 */
__IOM uint32_t PROC1_INTS1; /*!< Interrupt status after masking & forcing for proc1 */
__IOM uint32_t PROC1_INTS2; /*!< Interrupt status after masking & forcing for proc1 */
__IOM uint32_t PROC1_INTS3; /*!< Interrupt status after masking & forcing for proc1 */
__IOM uint32_t PROC1_INTS4; /*!< Interrupt status after masking & forcing for proc1 */
__IOM uint32_t PROC1_INTS5; /*!< Interrupt status after masking & forcing for proc1 */
__IOM uint32_t DORMANT_WAKE_INTE0; /*!< Interrupt Enable for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTE1; /*!< Interrupt Enable for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTE2; /*!< Interrupt Enable for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTE3; /*!< Interrupt Enable for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTE4; /*!< Interrupt Enable for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTE5; /*!< Interrupt Enable for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTF0; /*!< Interrupt Force for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTF1; /*!< Interrupt Force for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTF2; /*!< Interrupt Force for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTF3; /*!< Interrupt Force for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTF4; /*!< Interrupt Force for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTF5; /*!< Interrupt Force for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTS0; /*!< Interrupt status after masking & forcing for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTS1; /*!< Interrupt status after masking & forcing for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTS2; /*!< Interrupt status after masking & forcing for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTS3; /*!< Interrupt status after masking & forcing for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTS4; /*!< Interrupt status after masking & forcing for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTS5; /*!< Interrupt status after masking & forcing for dormant_wake */
} IO_BANK0_Type; /*!< Size = 800 (0x320) */
/* =========================================================================================================================== */
/* ================ SYSINFO ================ */
/* =========================================================================================================================== */
/**
* @brief SYSINFO (SYSINFO)
*/
typedef struct { /*!< SYSINFO Structure */
__IOM uint32_t CHIP_ID; /*!< JEDEC JEP-106 compliant chip identifier. */
__IOM uint32_t PACKAGE_SEL; /*!< PACKAGE_SEL */
__IOM uint32_t PLATFORM; /*!< Platform register. Allows software to know what environment
it is running in during pre-production development. Post-production,
the PLATFORM is always ASIC, non-SIM. */
__IM uint32_t RESERVED[2];
__IOM uint32_t GITREF_RP2350; /*!< Git hash of the chip source. Used to identify chip version. */
} SYSINFO_Type; /*!< Size = 24 (0x18) */
/* =========================================================================================================================== */
/* ================ SHA256 ================ */
/* =========================================================================================================================== */
/**
* @brief SHA-256 hash function implementation (SHA256)
*/
typedef struct { /*!< SHA256 Structure */
__IOM uint32_t CSR; /*!< Control and status register */
__IOM uint32_t WDATA; /*!< Write data register */
__IOM uint32_t SUM0; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD
is 0. */
__IOM uint32_t SUM1; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD
is 0. */
__IOM uint32_t SUM2; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD
is 0. */
__IOM uint32_t SUM3; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD
is 0. */
__IOM uint32_t SUM4; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD
is 0. */
__IOM uint32_t SUM5; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD
is 0. */
__IOM uint32_t SUM6; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD
is 0. */
__IOM uint32_t SUM7; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD
is 0. */
} SHA256_Type; /*!< Size = 40 (0x28) */
/* =========================================================================================================================== */
/* ================ HSTX_FIFO ================ */
/* =========================================================================================================================== */
/**
* @brief FIFO status and write access for HSTX (HSTX_FIFO)
*/
typedef struct { /*!< HSTX_FIFO Structure */
__IOM uint32_t STAT; /*!< FIFO status */
__IOM uint32_t FIFO; /*!< Write access to FIFO */
} HSTX_FIFO_Type; /*!< Size = 8 (0x8) */
/* =========================================================================================================================== */
/* ================ HSTX_CTRL ================ */
/* =========================================================================================================================== */
/**
* @brief Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block. (HSTX_CTRL)
*/
typedef struct { /*!< HSTX_CTRL Structure */
__IOM uint32_t CSR; /*!< CSR */
__IOM uint32_t BIT0; /*!< Data control register for output bit 0 */
__IOM uint32_t BIT1; /*!< Data control register for output bit 1 */
__IOM uint32_t BIT2; /*!< Data control register for output bit 2 */
__IOM uint32_t BIT3; /*!< Data control register for output bit 3 */
__IOM uint32_t BIT4; /*!< Data control register for output bit 4 */
__IOM uint32_t BIT5; /*!< Data control register for output bit 5 */
__IOM uint32_t BIT6; /*!< Data control register for output bit 6 */
__IOM uint32_t BIT7; /*!< Data control register for output bit 7 */
__IOM uint32_t EXPAND_SHIFT; /*!< Configure the optional shifter inside the command expander */
__IOM uint32_t EXPAND_TMDS; /*!< Configure the optional TMDS encoder inside the command expander */
} HSTX_CTRL_Type; /*!< Size = 44 (0x2c) */
/* =========================================================================================================================== */
/* ================ EPPB ================ */
/* =========================================================================================================================== */
/**
* @brief Cortex-M33 EPPB vendor register block for RP2350 (EPPB)
*/
typedef struct { /*!< EPPB Structure */
__IOM uint32_t NMI_MASK0; /*!< NMI mask for IRQs 0 through 31. This register is core-local,
and is reset by a processor warm reset. */
__IOM uint32_t NMI_MASK1; /*!< NMI mask for IRQs 0 though 51. This register is core-local,
and is reset by a processor warm reset. */
__IOM uint32_t SLEEPCTRL; /*!< Nonstandard sleep control register */
} EPPB_Type; /*!< Size = 12 (0xc) */
/* =========================================================================================================================== */
/* ================ PPB ================ */
/* =========================================================================================================================== */
/**
* @brief TEAL registers accessible through the debug interface (PPB)
*/
typedef struct { /*!< PPB Structure */
__IOM uint32_t ITM_STIM0; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM1; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM2; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM3; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM4; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM5; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM6; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM7; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM8; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM9; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM10; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM11; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM12; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM13; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM14; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM15; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM16; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM17; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM18; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM19; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM20; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM21; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM22; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM23; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM24; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM25; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM26; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM27; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM28; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM29; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM30; /*!< Provides the interface for generating Instrumentation packets */
__IOM uint32_t ITM_STIM31; /*!< Provides the interface for generating Instrumentation packets */
__IM uint32_t RESERVED[864];
__IOM uint32_t ITM_TER0; /*!< Provide an individual enable bit for each ITM_STIM register */
__IM uint32_t RESERVED1[15];
__IOM uint32_t ITM_TPR; /*!< Controls which stimulus ports can be accessed by unprivileged
code */
__IM uint32_t RESERVED2[15];
__IOM uint32_t ITM_TCR; /*!< Configures and controls transfers through the ITM interface */
__IM uint32_t RESERVED3[27];
__IOM uint32_t INT_ATREADY; /*!< Integration Mode: Read ATB Ready */
__IM uint32_t RESERVED4;
__IOM uint32_t INT_ATVALID; /*!< Integration Mode: Write ATB Valid */
__IM uint32_t RESERVED5;
__IOM uint32_t ITM_ITCTRL; /*!< Integration Mode Control Register */
__IM uint32_t RESERVED6[46];
__IOM uint32_t ITM_DEVARCH; /*!< Provides CoreSight discovery information for the ITM */
__IM uint32_t RESERVED7[3];
__IOM uint32_t ITM_DEVTYPE; /*!< Provides CoreSight discovery information for the ITM */
__IOM uint32_t ITM_PIDR4; /*!< Provides CoreSight discovery information for the ITM */
__IOM uint32_t ITM_PIDR5; /*!< Provides CoreSight discovery information for the ITM */
__IOM uint32_t ITM_PIDR6; /*!< Provides CoreSight discovery information for the ITM */
__IOM uint32_t ITM_PIDR7; /*!< Provides CoreSight discovery information for the ITM */
__IOM uint32_t ITM_PIDR0; /*!< Provides CoreSight discovery information for the ITM */
__IOM uint32_t ITM_PIDR1; /*!< Provides CoreSight discovery information for the ITM */
__IOM uint32_t ITM_PIDR2; /*!< Provides CoreSight discovery information for the ITM */
__IOM uint32_t ITM_PIDR3; /*!< Provides CoreSight discovery information for the ITM */
__IOM uint32_t ITM_CIDR0; /*!< Provides CoreSight discovery information for the ITM */
__IOM uint32_t ITM_CIDR1; /*!< Provides CoreSight discovery information for the ITM */
__IOM uint32_t ITM_CIDR2; /*!< Provides CoreSight discovery information for the ITM */
__IOM uint32_t ITM_CIDR3; /*!< Provides CoreSight discovery information for the ITM */
__IOM uint32_t DWT_CTRL; /*!< Provides configuration and status information for the DWT unit,
and used to control features of the unit */
__IOM uint32_t DWT_CYCCNT; /*!< Shows or sets the value of the processor cycle counter, CYCCNT */
__IM uint32_t RESERVED8;
__IOM uint32_t DWT_EXCCNT; /*!< Counts the total cycles spent in exception processing */
__IM uint32_t RESERVED9;
__IOM uint32_t DWT_LSUCNT; /*!< Increments on the additional cycles required to execute all
load or store instructions */
__IOM uint32_t DWT_FOLDCNT; /*!< Increments on the additional cycles required to execute all
load or store instructions */
__IM uint32_t RESERVED10;
__IOM uint32_t DWT_COMP0; /*!< Provides a reference value for use by watchpoint comparator
0 */
__IM uint32_t RESERVED11;
__IOM uint32_t DWT_FUNCTION0; /*!< Controls the operation of watchpoint comparator 0 */
__IM uint32_t RESERVED12;
__IOM uint32_t DWT_COMP1; /*!< Provides a reference value for use by watchpoint comparator
1 */
__IM uint32_t RESERVED13;
__IOM uint32_t DWT_FUNCTION1; /*!< Controls the operation of watchpoint comparator 1 */
__IM uint32_t RESERVED14;
__IOM uint32_t DWT_COMP2; /*!< Provides a reference value for use by watchpoint comparator
2 */
__IM uint32_t RESERVED15;
__IOM uint32_t DWT_FUNCTION2; /*!< Controls the operation of watchpoint comparator 2 */
__IM uint32_t RESERVED16;
__IOM uint32_t DWT_COMP3; /*!< Provides a reference value for use by watchpoint comparator
3 */
__IM uint32_t RESERVED17;
__IOM uint32_t DWT_FUNCTION3; /*!< Controls the operation of watchpoint comparator 3 */
__IM uint32_t RESERVED18[984];
__IOM uint32_t DWT_DEVARCH; /*!< Provides CoreSight discovery information for the DWT */
__IM uint32_t RESERVED19[3];
__IOM uint32_t DWT_DEVTYPE; /*!< Provides CoreSight discovery information for the DWT */
__IOM uint32_t DWT_PIDR4; /*!< Provides CoreSight discovery information for the DWT */
__IOM uint32_t DWT_PIDR5; /*!< Provides CoreSight discovery information for the DWT */
__IOM uint32_t DWT_PIDR6; /*!< Provides CoreSight discovery information for the DWT */
__IOM uint32_t DWT_PIDR7; /*!< Provides CoreSight discovery information for the DWT */
__IOM uint32_t DWT_PIDR0; /*!< Provides CoreSight discovery information for the DWT */
__IOM uint32_t DWT_PIDR1; /*!< Provides CoreSight discovery information for the DWT */
__IOM uint32_t DWT_PIDR2; /*!< Provides CoreSight discovery information for the DWT */
__IOM uint32_t DWT_PIDR3; /*!< Provides CoreSight discovery information for the DWT */
__IOM uint32_t DWT_CIDR0; /*!< Provides CoreSight discovery information for the DWT */
__IOM uint32_t DWT_CIDR1; /*!< Provides CoreSight discovery information for the DWT */
__IOM uint32_t DWT_CIDR2; /*!< Provides CoreSight discovery information for the DWT */
__IOM uint32_t DWT_CIDR3; /*!< Provides CoreSight discovery information for the DWT */
__IOM uint32_t FP_CTRL; /*!< Provides FPB implementation information, and the global enable
for the FPB unit */
__IOM uint32_t FP_REMAP; /*!< Indicates whether the implementation supports Flash Patch remap
and, if it does, holds the target address for remap */
__IOM uint32_t FP_COMP0; /*!< Holds an address for comparison. The effect of the match depends
on the configuration of the FPB and whether the comparator
is an instruction address comparator or a literal address
comparator */
__IOM uint32_t FP_COMP1; /*!< Holds an address for comparison. The effect of the match depends
on the configuration of the FPB and whether the comparator
is an instruction address comparator or a literal address
comparator */
__IOM uint32_t FP_COMP2; /*!< Holds an address for comparison. The effect of the match depends
on the configuration of the FPB and whether the comparator
is an instruction address comparator or a literal address
comparator */
__IOM uint32_t FP_COMP3; /*!< Holds an address for comparison. The effect of the match depends
on the configuration of the FPB and whether the comparator
is an instruction address comparator or a literal address
comparator */
__IOM uint32_t FP_COMP4; /*!< Holds an address for comparison. The effect of the match depends
on the configuration of the FPB and whether the comparator
is an instruction address comparator or a literal address
comparator */
__IOM uint32_t FP_COMP5; /*!< Holds an address for comparison. The effect of the match depends
on the configuration of the FPB and whether the comparator
is an instruction address comparator or a literal address
comparator */
__IOM uint32_t FP_COMP6; /*!< Holds an address for comparison. The effect of the match depends
on the configuration of the FPB and whether the comparator
is an instruction address comparator or a literal address
comparator */
__IOM uint32_t FP_COMP7; /*!< Holds an address for comparison. The effect of the match depends
on the configuration of the FPB and whether the comparator
is an instruction address comparator or a literal address
comparator */
__IM uint32_t RESERVED20[997];
__IOM uint32_t FP_DEVARCH; /*!< Provides CoreSight discovery information for the FPB */
__IM uint32_t RESERVED21[3];
__IOM uint32_t FP_DEVTYPE; /*!< Provides CoreSight discovery information for the FPB */
__IOM uint32_t FP_PIDR4; /*!< Provides CoreSight discovery information for the FP */
__IOM uint32_t FP_PIDR5; /*!< Provides CoreSight discovery information for the FP */
__IOM uint32_t FP_PIDR6; /*!< Provides CoreSight discovery information for the FP */
__IOM uint32_t FP_PIDR7; /*!< Provides CoreSight discovery information for the FP */
__IOM uint32_t FP_PIDR0; /*!< Provides CoreSight discovery information for the FP */
__IOM uint32_t FP_PIDR1; /*!< Provides CoreSight discovery information for the FP */
__IOM uint32_t FP_PIDR2; /*!< Provides CoreSight discovery information for the FP */
__IOM uint32_t FP_PIDR3; /*!< Provides CoreSight discovery information for the FP */
__IOM uint32_t FP_CIDR0; /*!< Provides CoreSight discovery information for the FP */
__IOM uint32_t FP_CIDR1; /*!< Provides CoreSight discovery information for the FP */
__IOM uint32_t FP_CIDR2; /*!< Provides CoreSight discovery information for the FP */
__IOM uint32_t FP_CIDR3; /*!< Provides CoreSight discovery information for the FP */
__IM uint32_t RESERVED22[11265];
__IOM uint32_t ICTR; /*!< Provides information about the interrupt controller */
__IOM uint32_t ACTLR; /*!< Provides IMPLEMENTATION DEFINED configuration and control options */
__IM uint32_t RESERVED23;
__IOM uint32_t SYST_CSR; /*!< Use the SysTick Control and Status Register to enable the SysTick
features. */
__IOM uint32_t SYST_RVR; /*!< Use the SysTick Reload Value Register to specify the start value
to load into the current value register when the counter
reaches 0. It can be any value between 0 and 0x00FFFFFF.
A start value of 0 is possible, but has no effect because
the SysTick interrupt and COUNTFLAG are activated when
counting from 1 to 0. The reset value of this register
is UNKNOWN. To generate a multi-shot timer with a period
of N processor clock cycles, use a RELOAD value of N-1.
For example, if the SysTick interrupt is required every
100 clock pulses, set RELOAD to 99. */
__IOM uint32_t SYST_CVR; /*!< Use the SysTick Current Value Register to find the current value
in the register. The reset value of this register is UNKNOWN. */
__IOM uint32_t SYST_CALIB; /*!< Use the SysTick Calibration Value Register to enable software
to scale to any required speed using divide and multiply. */
__IM uint32_t RESERVED24[56];
__IOM uint32_t NVIC_ISER0; /*!< Enables or reads the enabled state of each group of 32 interrupts */
__IOM uint32_t NVIC_ISER1; /*!< Enables or reads the enabled state of each group of 32 interrupts */
__IM uint32_t RESERVED25[30];
__IOM uint32_t NVIC_ICER0; /*!< Clears or reads the enabled state of each group of 32 interrupts */
__IOM uint32_t NVIC_ICER1; /*!< Clears or reads the enabled state of each group of 32 interrupts */
__IM uint32_t RESERVED26[30];
__IOM uint32_t NVIC_ISPR0; /*!< Enables or reads the pending state of each group of 32 interrupts */
__IOM uint32_t NVIC_ISPR1; /*!< Enables or reads the pending state of each group of 32 interrupts */
__IM uint32_t RESERVED27[30];
__IOM uint32_t NVIC_ICPR0; /*!< Clears or reads the pending state of each group of 32 interrupts */
__IOM uint32_t NVIC_ICPR1; /*!< Clears or reads the pending state of each group of 32 interrupts */
__IM uint32_t RESERVED28[30];
__IOM uint32_t NVIC_IABR0; /*!< For each group of 32 interrupts, shows the active state of each
interrupt */
__IOM uint32_t NVIC_IABR1; /*!< For each group of 32 interrupts, shows the active state of each
interrupt */
__IM uint32_t RESERVED29[30];
__IOM uint32_t NVIC_ITNS0; /*!< For each group of 32 interrupts, determines whether each interrupt
targets Non-secure or Secure state */
__IOM uint32_t NVIC_ITNS1; /*!< For each group of 32 interrupts, determines whether each interrupt
targets Non-secure or Secure state */
__IM uint32_t RESERVED30[30];
__IOM uint32_t NVIC_IPR0; /*!< Sets or reads interrupt priorities */
__IOM uint32_t NVIC_IPR1; /*!< Sets or reads interrupt priorities */
__IOM uint32_t NVIC_IPR2; /*!< Sets or reads interrupt priorities */
__IOM uint32_t NVIC_IPR3; /*!< Sets or reads interrupt priorities */
__IOM uint32_t NVIC_IPR4; /*!< Sets or reads interrupt priorities */
__IOM uint32_t NVIC_IPR5; /*!< Sets or reads interrupt priorities */
__IOM uint32_t NVIC_IPR6; /*!< Sets or reads interrupt priorities */
__IOM uint32_t NVIC_IPR7; /*!< Sets or reads interrupt priorities */
__IOM uint32_t NVIC_IPR8; /*!< Sets or reads interrupt priorities */
__IOM uint32_t NVIC_IPR9; /*!< Sets or reads interrupt priorities */
__IOM uint32_t NVIC_IPR10; /*!< Sets or reads interrupt priorities */
__IOM uint32_t NVIC_IPR11; /*!< Sets or reads interrupt priorities */
__IOM uint32_t NVIC_IPR12; /*!< Sets or reads interrupt priorities */
__IOM uint32_t NVIC_IPR13; /*!< Sets or reads interrupt priorities */
__IOM uint32_t NVIC_IPR14; /*!< Sets or reads interrupt priorities */
__IOM uint32_t NVIC_IPR15; /*!< Sets or reads interrupt priorities */
__IM uint32_t RESERVED31[560];
__IOM uint32_t CPUID; /*!< Provides identification information for the PE, including an
implementer code for the device and a device ID number */
__IOM uint32_t ICSR; /*!< Controls and provides status information for NMI, PendSV, SysTick
and interrupts */
__IOM uint32_t VTOR; /*!< The VTOR indicates the offset of the vector table base address
from memory address 0x00000000. */
__IOM uint32_t AIRCR; /*!< Use the Application Interrupt and Reset Control Register to:
determine data endianness, clear all active state information
from debug halt mode, request a system reset. */
__IOM uint32_t SCR; /*!< System Control Register. Use the System Control Register for
power-management functions: signal to the system when the
processor can enter a low power state, control how the
processor enters and exits low power states. */
__IOM uint32_t CCR; /*!< Sets or returns configuration and control data */
__IOM uint32_t SHPR1; /*!< Sets or returns priority for system handlers 4 - 7 */
__IOM uint32_t SHPR2; /*!< Sets or returns priority for system handlers 8 - 11 */
__IOM uint32_t SHPR3; /*!< Sets or returns priority for system handlers 12 - 15 */
__IOM uint32_t SHCSR; /*!< Provides access to the active and pending status of system exceptions */
__IOM uint32_t CFSR; /*!< Contains the three Configurable Fault Status Registers. 31:16
UFSR: Provides information on UsageFault exceptions 15:8
BFSR: Provides information on BusFault exceptions 7:0 MMFSR:
Provides information on MemManage exceptions */
__IOM uint32_t HFSR; /*!< Shows the cause of any HardFaults */
__IOM uint32_t DFSR; /*!< Shows which debug event occurred */
__IOM uint32_t MMFAR; /*!< Shows the address of the memory location that caused an MPU
fault */
__IOM uint32_t BFAR; /*!< Shows the address associated with a precise data access BusFault */
__IM uint32_t RESERVED32;
__IOM uint32_t ID_PFR0; /*!< Gives top-level information about the instruction set supported
by the PE */
__IOM uint32_t ID_PFR1; /*!< Gives information about the programmers' model and Extensions
support */
__IOM uint32_t ID_DFR0; /*!< Provides top level information about the debug system */
__IOM uint32_t ID_AFR0; /*!< Provides information about the IMPLEMENTATION DEFINED features
of the PE */
__IOM uint32_t ID_MMFR0; /*!< Provides information about the implemented memory model and
memory management support */
__IOM uint32_t ID_MMFR1; /*!< Provides information about the implemented memory model and
memory management support */
__IOM uint32_t ID_MMFR2; /*!< Provides information about the implemented memory model and
memory management support */
__IOM uint32_t ID_MMFR3; /*!< Provides information about the implemented memory model and
memory management support */
__IOM uint32_t ID_ISAR0; /*!< Provides information about the instruction set implemented by
the PE */
__IOM uint32_t ID_ISAR1; /*!< Provides information about the instruction set implemented by
the PE */
__IOM uint32_t ID_ISAR2; /*!< Provides information about the instruction set implemented by
the PE */
__IOM uint32_t ID_ISAR3; /*!< Provides information about the instruction set implemented by
the PE */
__IOM uint32_t ID_ISAR4; /*!< Provides information about the instruction set implemented by
the PE */
__IOM uint32_t ID_ISAR5; /*!< Provides information about the instruction set implemented by
the PE */
__IM uint32_t RESERVED33;
__IOM uint32_t CTR; /*!< Provides information about the architecture of the caches. CTR
is RES0 if CLIDR is zero. */
__IM uint32_t RESERVED34[2];
__IOM uint32_t CPACR; /*!< Specifies the access privileges for coprocessors and the FP
Extension */
__IOM uint32_t NSACR; /*!< Defines the Non-secure access permissions for both the FP Extension
and coprocessors CP0 to CP7 */
__IOM uint32_t MPU_TYPE; /*!< The MPU Type Register indicates how many regions the MPU `FTSSS
supports */
__IOM uint32_t MPU_CTRL; /*!< Enables the MPU and, when the MPU is enabled, controls whether
the default memory map is enabled as a background region
for privileged accesses, and whether the MPU is enabled
for HardFaults, NMIs, and exception handlers when FAULTMASK
is set to 1 */
__IOM uint32_t MPU_RNR; /*!< Selects the region currently accessed by MPU_RBAR and MPU_RLAR */
__IOM uint32_t MPU_RBAR; /*!< Provides indirect read and write access to the base address
of the currently selected MPU region `FTSSS */
__IOM uint32_t MPU_RLAR; /*!< Provides indirect read and write access to the limit address
of the currently selected MPU region `FTSSS */
__IOM uint32_t MPU_RBAR_A1; /*!< Provides indirect read and write access to the base address
of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS */
__IOM uint32_t MPU_RLAR_A1; /*!< Provides indirect read and write access to the limit address
of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0])
`FTSSS */
__IOM uint32_t MPU_RBAR_A2; /*!< Provides indirect read and write access to the base address
of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS */
__IOM uint32_t MPU_RLAR_A2; /*!< Provides indirect read and write access to the limit address
of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0])
`FTSSS */
__IOM uint32_t MPU_RBAR_A3; /*!< Provides indirect read and write access to the base address
of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS */
__IOM uint32_t MPU_RLAR_A3; /*!< Provides indirect read and write access to the limit address
of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0])
`FTSSS */
__IM uint32_t RESERVED35;
__IOM uint32_t MPU_MAIR0; /*!< Along with MPU_MAIR1, provides the memory attribute encodings
corresponding to the AttrIndex values */
__IOM uint32_t MPU_MAIR1; /*!< Along with MPU_MAIR0, provides the memory attribute encodings
corresponding to the AttrIndex values */
__IM uint32_t RESERVED36[2];
__IOM uint32_t SAU_CTRL; /*!< Allows enabling of the Security Attribution Unit */
__IOM uint32_t SAU_TYPE; /*!< Indicates the number of regions implemented by the Security
Attribution Unit */
__IOM uint32_t SAU_RNR; /*!< Selects the region currently accessed by SAU_RBAR and SAU_RLAR */
__IOM uint32_t SAU_RBAR; /*!< Provides indirect read and write access to the base address
of the currently selected SAU region */
__IOM uint32_t SAU_RLAR; /*!< Provides indirect read and write access to the limit address
of the currently selected SAU region */
__IOM uint32_t SFSR; /*!< Provides information about any security related faults */
__IOM uint32_t SFAR; /*!< Shows the address of the memory location that caused a Security
violation */
__IM uint32_t RESERVED37;
__IOM uint32_t DHCSR; /*!< Controls halting debug */
__IOM uint32_t DCRSR; /*!< With the DCRDR, provides debug access to the general-purpose
registers, special-purpose registers, and the FP extension
registers. A write to the DCRSR specifies the register
to transfer, whether the transfer is a read or write, and
starts the transfer */
__IOM uint32_t DCRDR; /*!< With the DCRSR, provides debug access to the general-purpose
registers, special-purpose registers, and the FP Extension
registers. If the Main Extension is implemented, it can
also be used for message passing between an external debugger
and a debug agent running on the PE */
__IOM uint32_t DEMCR; /*!< Manages vector catch behavior and DebugMonitor handling when
debugging */
__IM uint32_t RESERVED38[2];
__IOM uint32_t DSCSR; /*!< Provides control and status information for Secure debug */
__IM uint32_t RESERVED39[61];
__IOM uint32_t STIR; /*!< Provides a mechanism for software to generate an interrupt */
__IM uint32_t RESERVED40[12];
__IOM uint32_t FPCCR; /*!< Holds control data for the Floating-point extension */
__IOM uint32_t FPCAR; /*!< Holds the location of the unpopulated floating-point register
space allocated on an exception stack frame */
__IOM uint32_t FPDSCR; /*!< Holds the default values for the floating-point status control
data that the PE assigns to the FPSCR when it creates a
new floating-point context */
__IOM uint32_t MVFR0; /*!< Describes the features provided by the Floating-point Extension */
__IOM uint32_t MVFR1; /*!< Describes the features provided by the Floating-point Extension */
__IOM uint32_t MVFR2; /*!< Describes the features provided by the Floating-point Extension */
__IM uint32_t RESERVED41[28];
__IOM uint32_t DDEVARCH; /*!< Provides CoreSight discovery information for the SCS */
__IM uint32_t RESERVED42[3];
__IOM uint32_t DDEVTYPE; /*!< Provides CoreSight discovery information for the SCS */
__IOM uint32_t DPIDR4; /*!< Provides CoreSight discovery information for the SCS */
__IOM uint32_t DPIDR5; /*!< Provides CoreSight discovery information for the SCS */
__IOM uint32_t DPIDR6; /*!< Provides CoreSight discovery information for the SCS */
__IOM uint32_t DPIDR7; /*!< Provides CoreSight discovery information for the SCS */
__IOM uint32_t DPIDR0; /*!< Provides CoreSight discovery information for the SCS */
__IOM uint32_t DPIDR1; /*!< Provides CoreSight discovery information for the SCS */
__IOM uint32_t DPIDR2; /*!< Provides CoreSight discovery information for the SCS */
__IOM uint32_t DPIDR3; /*!< Provides CoreSight discovery information for the SCS */
__IOM uint32_t DCIDR0; /*!< Provides CoreSight discovery information for the SCS */
__IOM uint32_t DCIDR1; /*!< Provides CoreSight discovery information for the SCS */
__IOM uint32_t DCIDR2; /*!< Provides CoreSight discovery information for the SCS */
__IOM uint32_t DCIDR3; /*!< Provides CoreSight discovery information for the SCS */
__IM uint32_t RESERVED43[51201];
__IOM uint32_t TRCPRGCTLR; /*!< Programming Control Register */
__IM uint32_t RESERVED44;
__IOM uint32_t TRCSTATR; /*!< The TRCSTATR indicates the ETM-Teal status */
__IOM uint32_t TRCCONFIGR; /*!< The TRCCONFIGR sets the basic tracing options for the trace
unit */
__IM uint32_t RESERVED45[3];
__IOM uint32_t TRCEVENTCTL0R; /*!< The TRCEVENTCTL0R controls the tracing of events in the trace
stream. The events also drive the ETM-Teal external outputs. */
__IOM uint32_t TRCEVENTCTL1R; /*!< The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R
behave */
__IM uint32_t RESERVED46;
__IOM uint32_t TRCSTALLCTLR; /*!< The TRCSTALLCTLR enables ETM-Teal to stall the processor if
the ETM-Teal FIFO goes over the programmed level to minimize
risk of overflow */
__IOM uint32_t TRCTSCTLR; /*!< The TRCTSCTLR controls the insertion of global timestamps into
the trace stream. A timestamp is always inserted into the
instruction trace stream */
__IOM uint32_t TRCSYNCPR; /*!< The TRCSYNCPR specifies the period of trace synchronization
of the trace streams. TRCSYNCPR defines a number of bytes
of trace between requests for trace synchronization. This
value is always a power of two */
__IOM uint32_t TRCCCCTLR; /*!< The TRCCCCTLR sets the threshold value for instruction trace
cycle counting. The threshold represents the minimum interval
between cycle count trace packets */
__IM uint32_t RESERVED47[17];
__IOM uint32_t TRCVICTLR; /*!< The TRCVICTLR controls instruction trace filtering */
__IM uint32_t RESERVED48[47];
__IOM uint32_t TRCCNTRLDVR0; /*!< The TRCCNTRLDVR defines the reload value for the reduced function
counter */
__IM uint32_t RESERVED49[15];
__IOM uint32_t TRCIDR8; /*!< TRCIDR8 */
__IOM uint32_t TRCIDR9; /*!< TRCIDR9 */
__IOM uint32_t TRCIDR10; /*!< TRCIDR10 */
__IOM uint32_t TRCIDR11; /*!< TRCIDR11 */
__IOM uint32_t TRCIDR12; /*!< TRCIDR12 */
__IOM uint32_t TRCIDR13; /*!< TRCIDR13 */
__IM uint32_t RESERVED50[10];
__IOM uint32_t TRCIMSPEC; /*!< The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC
features, and enables any features that are provided */
__IM uint32_t RESERVED51[7];
__IOM uint32_t TRCIDR0; /*!< TRCIDR0 */
__IOM uint32_t TRCIDR1; /*!< TRCIDR1 */
__IOM uint32_t TRCIDR2; /*!< TRCIDR2 */
__IOM uint32_t TRCIDR3; /*!< TRCIDR3 */
__IOM uint32_t TRCIDR4; /*!< TRCIDR4 */
__IOM uint32_t TRCIDR5; /*!< TRCIDR5 */
__IOM uint32_t TRCIDR6; /*!< TRCIDR6 */
__IOM uint32_t TRCIDR7; /*!< TRCIDR7 */
__IM uint32_t RESERVED52[2];
__IOM uint32_t TRCRSCTLR2; /*!< The TRCRSCTLR controls the trace resources */
__IOM uint32_t TRCRSCTLR3; /*!< The TRCRSCTLR controls the trace resources */
__IM uint32_t RESERVED53[36];
__IOM uint32_t TRCSSCSR; /*!< Controls the corresponding single-shot comparator resource */
__IM uint32_t RESERVED54[7];
__IOM uint32_t TRCSSPCICR; /*!< Selects the PE comparator inputs for Single-shot control */
__IM uint32_t RESERVED55[19];
__IOM uint32_t TRCPDCR; /*!< Requests the system to provide power to the trace unit */
__IOM uint32_t TRCPDSR; /*!< Returns the following information about the trace unit: - OS
Lock status. - Core power domain status. - Power interruption
status */
__IM uint32_t RESERVED56[755];
__IOM uint32_t TRCITATBIDR; /*!< Trace Integration ATB Identification Register */
__IM uint32_t RESERVED57[3];
__IOM uint32_t TRCITIATBINR; /*!< Trace Integration Instruction ATB In Register */
__IM uint32_t RESERVED58;
__IOM uint32_t TRCITIATBOUTR; /*!< Trace Integration Instruction ATB Out Register */
__IM uint32_t RESERVED59[40];
__IOM uint32_t TRCCLAIMSET; /*!< Claim Tag Set Register */
__IOM uint32_t TRCCLAIMCLR; /*!< Claim Tag Clear Register */
__IM uint32_t RESERVED60[4];
__IOM uint32_t TRCAUTHSTATUS; /*!< Returns the level of tracing that the trace unit can support */
__IOM uint32_t TRCDEVARCH; /*!< TRCDEVARCH */
__IM uint32_t RESERVED61[2];
__IOM uint32_t TRCDEVID; /*!< TRCDEVID */
__IOM uint32_t TRCDEVTYPE; /*!< TRCDEVTYPE */
__IOM uint32_t TRCPIDR4; /*!< TRCPIDR4 */
__IOM uint32_t TRCPIDR5; /*!< TRCPIDR5 */
__IOM uint32_t TRCPIDR6; /*!< TRCPIDR6 */
__IOM uint32_t TRCPIDR7; /*!< TRCPIDR7 */
__IOM uint32_t TRCPIDR0; /*!< TRCPIDR0 */
__IOM uint32_t TRCPIDR1; /*!< TRCPIDR1 */
__IOM uint32_t TRCPIDR2; /*!< TRCPIDR2 */
__IOM uint32_t TRCPIDR3; /*!< TRCPIDR3 */
__IOM uint32_t TRCCIDR0; /*!< TRCCIDR0 */
__IOM uint32_t TRCCIDR1; /*!< TRCCIDR1 */
__IOM uint32_t TRCCIDR2; /*!< TRCCIDR2 */
__IOM uint32_t TRCCIDR3; /*!< TRCCIDR3 */
__IOM uint32_t CTICONTROL; /*!< CTI Control Register */
__IM uint32_t RESERVED62[3];
__IOM uint32_t CTIINTACK; /*!< CTI Interrupt Acknowledge Register */
__IOM uint32_t CTIAPPSET; /*!< CTI Application Trigger Set Register */
__IOM uint32_t CTIAPPCLEAR; /*!< CTI Application Trigger Clear Register */
__IOM uint32_t CTIAPPPULSE; /*!< CTI Application Pulse Register */
__IOM uint32_t CTIINEN0; /*!< CTI Trigger to Channel Enable Registers */
__IOM uint32_t CTIINEN1; /*!< CTI Trigger to Channel Enable Registers */
__IOM uint32_t CTIINEN2; /*!< CTI Trigger to Channel Enable Registers */
__IOM uint32_t CTIINEN3; /*!< CTI Trigger to Channel Enable Registers */
__IOM uint32_t CTIINEN4; /*!< CTI Trigger to Channel Enable Registers */
__IOM uint32_t CTIINEN5; /*!< CTI Trigger to Channel Enable Registers */
__IOM uint32_t CTIINEN6; /*!< CTI Trigger to Channel Enable Registers */
__IOM uint32_t CTIINEN7; /*!< CTI Trigger to Channel Enable Registers */
__IM uint32_t RESERVED63[24];
__IOM uint32_t CTIOUTEN0; /*!< CTI Trigger to Channel Enable Registers */
__IOM uint32_t CTIOUTEN1; /*!< CTI Trigger to Channel Enable Registers */
__IOM uint32_t CTIOUTEN2; /*!< CTI Trigger to Channel Enable Registers */
__IOM uint32_t CTIOUTEN3; /*!< CTI Trigger to Channel Enable Registers */
__IOM uint32_t CTIOUTEN4; /*!< CTI Trigger to Channel Enable Registers */
__IOM uint32_t CTIOUTEN5; /*!< CTI Trigger to Channel Enable Registers */
__IOM uint32_t CTIOUTEN6; /*!< CTI Trigger to Channel Enable Registers */
__IOM uint32_t CTIOUTEN7; /*!< CTI Trigger to Channel Enable Registers */
__IM uint32_t RESERVED64[28];
__IOM uint32_t CTITRIGINSTATUS; /*!< CTI Trigger to Channel Enable Registers */
__IOM uint32_t CTITRIGOUTSTATUS; /*!< CTI Trigger In Status Register */
__IOM uint32_t CTICHINSTATUS; /*!< CTI Channel In Status Register */
__IM uint32_t RESERVED65;
__IOM uint32_t CTIGATE; /*!< Enable CTI Channel Gate register */
__IOM uint32_t ASICCTL; /*!< External Multiplexer Control register */
__IM uint32_t RESERVED66[871];
__IOM uint32_t ITCHOUT; /*!< Integration Test Channel Output register */
__IOM uint32_t ITTRIGOUT; /*!< Integration Test Trigger Output register */
__IM uint32_t RESERVED67[2];
__IOM uint32_t ITCHIN; /*!< Integration Test Channel Input register */
__IM uint32_t RESERVED68[2];
__IOM uint32_t ITCTRL; /*!< Integration Mode Control register */
__IM uint32_t RESERVED69[46];
__IOM uint32_t DEVARCH; /*!< Device Architecture register */
__IM uint32_t RESERVED70[2];
__IOM uint32_t DEVID; /*!< Device Configuration register */
__IOM uint32_t DEVTYPE; /*!< Device Type Identifier register */
__IOM uint32_t PIDR4; /*!< CoreSight Peripheral ID4 */
__IOM uint32_t PIDR5; /*!< CoreSight Peripheral ID5 */
__IOM uint32_t PIDR6; /*!< CoreSight Peripheral ID6 */
__IOM uint32_t PIDR7; /*!< CoreSight Peripheral ID7 */
__IOM uint32_t PIDR0; /*!< CoreSight Peripheral ID0 */
__IOM uint32_t PIDR1; /*!< CoreSight Peripheral ID1 */
__IOM uint32_t PIDR2; /*!< CoreSight Peripheral ID2 */
__IOM uint32_t PIDR3; /*!< CoreSight Peripheral ID3 */
__IOM uint32_t CIDR0; /*!< CoreSight Component ID0 */
__IOM uint32_t CIDR1; /*!< CoreSight Component ID1 */
__IOM uint32_t CIDR2; /*!< CoreSight Component ID2 */
__IOM uint32_t CIDR3; /*!< CoreSight Component ID3 */
} PPB_Type; /*!< Size = 274432 (0x43000) */
/* =========================================================================================================================== */
/* ================ QMI ================ */
/* =========================================================================================================================== */
/**
* @brief QSPI Memory Interface.
Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device. (QMI)
*/
typedef struct { /*!< QMI Structure */
__IOM uint32_t DIRECT_CSR; /*!< Control and status for direct serial mode Direct serial mode
allows the processor to send and receive raw serial frames,
for programming, configuration and control of the external
memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported. */
__IOM uint32_t DIRECT_TX; /*!< Transmit FIFO for direct mode */
__IOM uint32_t DIRECT_RX; /*!< Receive FIFO for direct mode */
__IOM uint32_t M0_TIMING; /*!< Timing configuration register for memory address window 0. */
__IOM uint32_t M0_RFMT; /*!< Read transfer format configuration for memory address window
0. Configure the bus width of each transfer phase individually,
and configure the length or presence of the command prefix,
command suffix and dummy/turnaround transfer phases. Only
24-bit addresses are supported. The reset value of the
M0_RFMT register is configured to support a basic 03h serial
read transfer with no additional configuration. */
__IOM uint32_t M0_RCMD; /*!< Command constants used for reads from memory address window
0. The reset value of the M0_RCMD register is configured
to support a basic 03h serial read transfer with no additional
configuration. */
__IOM uint32_t M0_WFMT; /*!< Write transfer format configuration for memory address window
0. Configure the bus width of each transfer phase individually,
and configure the length or presence of the command prefix,
command suffix and dummy/turnaround transfer phases. Only
24-bit addresses are supported. The reset value of the
M0_WFMT register is configured to support a basic 02h serial
write transfer. However, writes to this window must first
be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory
is read-only by default. */
__IOM uint32_t M0_WCMD; /*!< Command constants used for writes to memory address window 0.
The reset value of the M0_WCMD register is configured to
support a basic 02h serial write transfer with no additional
configuration. */
__IOM uint32_t M1_TIMING; /*!< Timing configuration register for memory address window 1. */
__IOM uint32_t M1_RFMT; /*!< Read transfer format configuration for memory address window
1. Configure the bus width of each transfer phase individually,
and configure the length or presence of the command prefix,
command suffix and dummy/turnaround transfer phases. Only
24-bit addresses are supported. The reset value of the
M1_RFMT register is configured to support a basic 03h serial
read transfer with no additional configuration. */
__IOM uint32_t M1_RCMD; /*!< Command constants used for reads from memory address window
1. The reset value of the M1_RCMD register is configured
to support a basic 03h serial read transfer with no additional
configuration. */
__IOM uint32_t M1_WFMT; /*!< Write transfer format configuration for memory address window
1. Configure the bus width of each transfer phase individually,
and configure the length or presence of the command prefix,
command suffix and dummy/turnaround transfer phases. Only
24-bit addresses are supported. The reset value of the
M1_WFMT register is configured to support a basic 02h serial
write transfer. However, writes to this window must first
be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory
is read-only by default. */
__IOM uint32_t M1_WCMD; /*!< Command constants used for writes to memory address window 1.
The reset value of the M1_WCMD register is configured to
support a basic 02h serial write transfer with no additional
configuration. */
__IOM uint32_t ATRANS0; /*!< Configure address translation for XIP virtual addresses 0x000000
through 0x3fffff (a 4 MiB window starting at +0 MiB). Address
translation allows a program image to be executed in place
at multiple physical flash addresses (for example, a double-buffered
flash image for over-the-air updates), without the overhead
of position-independent code. At reset, the address translation
registers are initialised to an identity mapping, so that
they can be ignored if address translation is not required.
Note that the XIP cache is fully virtually addressed, so
a cache flush is required after changing the address translation. */
__IOM uint32_t ATRANS1; /*!< Configure address translation for XIP virtual addresses 0x400000
through 0x7fffff (a 4 MiB window starting at +4 MiB). Address
translation allows a program image to be executed in place
at multiple physical flash addresses (for example, a double-buffered
flash image for over-the-air updates), without the overhead
of position-independent code. At reset, the address translation
registers are initialised to an identity mapping, so that
they can be ignored if address translation is not required.
Note that the XIP cache is fully virtually addressed, so
a cache flush is required after changing the address translation. */
__IOM uint32_t ATRANS2; /*!< Configure address translation for XIP virtual addresses 0x800000
through 0xbfffff (a 4 MiB window starting at +8 MiB). Address
translation allows a program image to be executed in place
at multiple physical flash addresses (for example, a double-buffered
flash image for over-the-air updates), without the overhead
of position-independent code. At reset, the address translation
registers are initialised to an identity mapping, so that
they can be ignored if address translation is not required.
Note that the XIP cache is fully virtually addressed, so
a cache flush is required after changing the address translation. */
__IOM uint32_t ATRANS3; /*!< Configure address translation for XIP virtual addresses 0xc00000
through 0xffffff (a 4 MiB window starting at +12 MiB).
Address translation allows a program image to be executed
in place at multiple physical flash addresses (for example,
a double-buffered flash image for over-the-air updates),
without the overhead of position-independent code. At reset,
the address translation registers are initialised to an
identity mapping, so that they can be ignored if address
translation is not required. Note that the XIP cache is
fully virtually addressed, so a cache flush is required
after changing the address translation. */
__IOM uint32_t ATRANS4; /*!< Configure address translation for XIP virtual addresses 0x1000000
through 0x13fffff (a 4 MiB window starting at +16 MiB).
Address translation allows a program image to be executed
in place at multiple physical flash addresses (for example,
a double-buffered flash image for over-the-air updates),
without the overhead of position-independent code. At reset,
the address translation registers are initialised to an
identity mapping, so that they can be ignored if address
translation is not required. Note that the XIP cache is
fully virtually addressed, so a cache flush is required
after changing the address translation. */
__IOM uint32_t ATRANS5; /*!< Configure address translation for XIP virtual addresses 0x1400000
through 0x17fffff (a 4 MiB window starting at +20 MiB).
Address translation allows a program image to be executed
in place at multiple physical flash addresses (for example,
a double-buffered flash image for over-the-air updates),
without the overhead of position-independent code. At reset,
the address translation registers are initialised to an
identity mapping, so that they can be ignored if address
translation is not required. Note that the XIP cache is
fully virtually addressed, so a cache flush is required
after changing the address translation. */
__IOM uint32_t ATRANS6; /*!< Configure address translation for XIP virtual addresses 0x1800000
through 0x1bfffff (a 4 MiB window starting at +24 MiB).
Address translation allows a program image to be executed
in place at multiple physical flash addresses (for example,
a double-buffered flash image for over-the-air updates),
without the overhead of position-independent code. At reset,
the address translation registers are initialised to an
identity mapping, so that they can be ignored if address
translation is not required. Note that the XIP cache is
fully virtually addressed, so a cache flush is required
after changing the address translation. */
__IOM uint32_t ATRANS7; /*!< Configure address translation for XIP virtual addresses 0x1c00000
through 0x1ffffff (a 4 MiB window starting at +28 MiB).
Address translation allows a program image to be executed
in place at multiple physical flash addresses (for example,
a double-buffered flash image for over-the-air updates),
without the overhead of position-independent code. At reset,
the address translation registers are initialised to an
identity mapping, so that they can be ignored if address
translation is not required. Note that the XIP cache is
fully virtually addressed, so a cache flush is required
after changing the address translation. */
} QMI_Type; /*!< Size = 84 (0x54) */
/* =========================================================================================================================== */
/* ================ XIP_CTRL ================ */
/* =========================================================================================================================== */
/**
* @brief QSPI flash execute-in-place block (XIP_CTRL)
*/
typedef struct { /*!< XIP_CTRL Structure */
__IOM uint32_t CTRL; /*!< Cache control register. Read-only from a Non-secure context. */
__IM uint32_t RESERVED;
__IOM uint32_t STAT; /*!< STAT */
__IOM uint32_t CTR_HIT; /*!< Cache Hit counter */
__IOM uint32_t CTR_ACC; /*!< Cache Access counter */
__IOM uint32_t STREAM_ADDR; /*!< FIFO stream address */
__IOM uint32_t STREAM_CTR; /*!< FIFO stream control */
__IOM uint32_t STREAM_FIFO; /*!< FIFO stream data */
} XIP_CTRL_Type; /*!< Size = 32 (0x20) */
/* =========================================================================================================================== */
/* ================ XIP_AUX ================ */
/* =========================================================================================================================== */
/**
* @brief Auxiliary DMA access to XIP FIFOs, via fast AHB bus access (XIP_AUX)
*/
typedef struct { /*!< XIP_AUX Structure */
__IOM uint32_t STREAM; /*!< Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) */
__IOM uint32_t QMI_DIRECT_TX; /*!< Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) */
__IOM uint32_t QMI_DIRECT_RX; /*!< Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) */
} XIP_AUX_Type; /*!< Size = 12 (0xc) */
/* =========================================================================================================================== */
/* ================ SYSCFG ================ */
/* =========================================================================================================================== */
/**
* @brief Register block for various chip control signals (SYSCFG)
*/
typedef struct { /*!< SYSCFG Structure */
__IOM uint32_t PROC_CONFIG; /*!< Configuration for processors */
__IOM uint32_t PROC_IN_SYNC_BYPASS; /*!< For each bit, if 1, bypass the input synchronizer between that
GPIO and the GPIO input register in the SIO. The input
synchronizers should generally be unbypassed, to avoid
injecting metastabilities into processors. If you're feeling
brave, you can bypass to save two cycles of input latency.
This register applies to GPIO 0...31. */
__IOM uint32_t PROC_IN_SYNC_BYPASS_HI; /*!< For each bit, if 1, bypass the input synchronizer between that
GPIO and the GPIO input register in the SIO. The input
synchronizers should generally be unbypassed, to avoid
injecting metastabilities into processors. If you're feeling
brave, you can bypass to save two cycles of input latency.
This register applies to GPIO 32...47. USB GPIO 56..57
QSPI GPIO 58..63 */
__IOM uint32_t DBGFORCE; /*!< Directly control the chip SWD debug port */
__IOM uint32_t MEMPOWERDOWN; /*!< Control PD pins to memories. Set high to put memories to a low
power state. In this state the memories will retain contents
but not be accessible Use with caution */
__IOM uint32_t AUXCTRL; /*!< Auxiliary system control register */
} SYSCFG_Type; /*!< Size = 24 (0x18) */
/* =========================================================================================================================== */
/* ================ XOSC ================ */
/* =========================================================================================================================== */
/**
* @brief Controls the crystal oscillator (XOSC)
*/
typedef struct { /*!< XOSC Structure */
__IOM uint32_t CTRL; /*!< Crystal Oscillator Control */
__IOM uint32_t STATUS; /*!< Crystal Oscillator Status */
__IOM uint32_t DORMANT; /*!< Crystal Oscillator pause control */
__IOM uint32_t STARTUP; /*!< Controls the startup delay */
__IOM uint32_t COUNT; /*!< A down counter running at the xosc frequency which counts to
zero and stops. Can be used for short software pauses when
setting up time sensitive hardware. To start the counter,
write a non-zero value. Reads will return 1 while the count
is running and 0 when it has finished. Minimum count value
is 4. Count values <4 will be treated as count value =4.
Note that synchronisation to the register clock domain
costs 2 register clock cycles and the counter cannot compensate
for that. */
} XOSC_Type; /*!< Size = 20 (0x14) */
/* =========================================================================================================================== */
/* ================ PLL_SYS ================ */
/* =========================================================================================================================== */
/**
* @brief PLL_SYS (PLL_SYS)
*/
typedef struct { /*!< PLL_SYS Structure */
__IOM uint32_t CS; /*!< Control and Status GENERAL CONSTRAINTS: Reference clock frequency
min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO
frequency min=750MHz, max=1600MHz */
__IOM uint32_t PWR; /*!< Controls the PLL power modes. */
__IOM uint32_t FBDIV_INT; /*!< Feedback divisor (note: this PLL does not support fractional
division) */
__IOM uint32_t PRIM; /*!< Controls the PLL post dividers for the primary output (note:
this PLL does not have a secondary output) the primary
output is driven from VCO divided by postdiv1*postdiv2 */
__IOM uint32_t INTR; /*!< Raw Interrupts */
__IOM uint32_t INTE; /*!< Interrupt Enable */
__IOM uint32_t INTF; /*!< Interrupt Force */
__IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */
} PLL_SYS_Type; /*!< Size = 32 (0x20) */
/* =========================================================================================================================== */
/* ================ ACCESSCTRL ================ */
/* =========================================================================================================================== */
/**
* @brief Hardware access control registers (ACCESSCTRL)
*/
typedef struct { /*!< ACCESSCTRL Structure */
__IOM uint32_t LOCK; /*!< Once a LOCK bit is written to 1, ACCESSCTRL silently ignores
writes from that master. LOCK is writable only by a Secure,
Privileged processor or debugger. LOCK bits are only writable
when their value is zero. Once set, they can never be cleared,
except by a full reset of ACCESSCTRL Setting the LOCK bit
does not affect whether an access raises a bus error. Unprivileged
writes, or writes from the DMA, will continue to raise
bus errors. All other accesses will continue not to. */
__IOM uint32_t FORCE_CORE_NS; /*!< Force core 1's bus accesses to always be Non-secure, no matter
the core's internal state. Useful for schemes where one
core is designated as the Non-secure core, since some peripherals
may filter individual registers internally based on security
state but not on master ID. */
__IOM uint32_t CFGRESET; /*!< Write 1 to reset all ACCESSCTRL configuration, except for the
LOCK and FORCE_CORE_NS registers. This bit is used in the
RP2350 bootrom to quickly restore ACCESSCTRL to a known
state during the boot path. Note that, like all registers
in ACCESSCTRL, this register is not writable when the writer's
corresponding LOCK bit is set, therefore a master which
has been locked out of ACCESSCTRL can not use the CFGRESET
register to disturb its contents. */
__IOM uint32_t GPIO_NSMASK0; /*!< Control whether GPIO0...31 are accessible to Non-secure code.
Writable only by a Secure, Privileged processor or debugger.
0 -> Secure access only 1 -> Secure + Non-secure access */
__IOM uint32_t GPIO_NSMASK1; /*!< Control whether GPIO32..47 are accessible to Non-secure code,
and whether QSPI and USB bitbang are accessible through
the Non-secure SIO. Writable only by a Secure, Privileged
processor or debugger. */
__IOM uint32_t ROM; /*!< Control whether debugger, DMA, core 0 and core 1 can access
ROM, and at what security/privilege levels they can do
so. Defaults to fully open access. This register is writable
only from a Secure, Privileged processor or debugger, with
the exception of the NSU bit, which becomes Non-secure-Privileged-writabl
when the NSP bit is set. */
__IOM uint32_t XIP_MAIN; /*!< Control whether debugger, DMA, core 0 and core 1 can access
XIP_MAIN, and at what security/privilege levels they can
do so. Defaults to fully open access. This register is
writable only from a Secure, Privileged processor or debugger,
with the exception of the NSU bit, which becomes Non-secure-Privileged-wr
table when the NSP bit is set. */
__IOM uint32_t SRAM0; /*!< Control whether debugger, DMA, core 0 and core 1 can access
SRAM0, and at what security/privilege levels they can do
so. Defaults to fully open access. This register is writable
only from a Secure, Privileged processor or debugger, with
the exception of the NSU bit, which becomes Non-secure-Privileged-writabl
when the NSP bit is set. */
__IOM uint32_t SRAM1; /*!< Control whether debugger, DMA, core 0 and core 1 can access
SRAM1, and at what security/privilege levels they can do
so. Defaults to fully open access. This register is writable
only from a Secure, Privileged processor or debugger, with
the exception of the NSU bit, which becomes Non-secure-Privileged-writabl
when the NSP bit is set. */
__IOM uint32_t SRAM2; /*!< Control whether debugger, DMA, core 0 and core 1 can access
SRAM2, and at what security/privilege levels they can do
so. Defaults to fully open access. This register is writable
only from a Secure, Privileged processor or debugger, with
the exception of the NSU bit, which becomes Non-secure-Privileged-writabl
when the NSP bit is set. */
__IOM uint32_t SRAM3; /*!< Control whether debugger, DMA, core 0 and core 1 can access
SRAM3, and at what security/privilege levels they can do
so. Defaults to fully open access. This register is writable
only from a Secure, Privileged processor or debugger, with
the exception of the NSU bit, which becomes Non-secure-Privileged-writabl
when the NSP bit is set. */
__IOM uint32_t SRAM4; /*!< Control whether debugger, DMA, core 0 and core 1 can access
SRAM4, and at what security/privilege levels they can do
so. Defaults to fully open access. This register is writable
only from a Secure, Privileged processor or debugger, with
the exception of the NSU bit, which becomes Non-secure-Privileged-writabl
when the NSP bit is set. */
__IOM uint32_t SRAM5; /*!< Control whether debugger, DMA, core 0 and core 1 can access
SRAM5, and at what security/privilege levels they can do
so. Defaults to fully open access. This register is writable
only from a Secure, Privileged processor or debugger, with
the exception of the NSU bit, which becomes Non-secure-Privileged-writabl
when the NSP bit is set. */
__IOM uint32_t SRAM6; /*!< Control whether debugger, DMA, core 0 and core 1 can access
SRAM6, and at what security/privilege levels they can do
so. Defaults to fully open access. This register is writable
only from a Secure, Privileged processor or debugger, with
the exception of the NSU bit, which becomes Non-secure-Privileged-writabl
when the NSP bit is set. */
__IOM uint32_t SRAM7; /*!< Control whether debugger, DMA, core 0 and core 1 can access
SRAM7, and at what security/privilege levels they can do
so. Defaults to fully open access. This register is writable
only from a Secure, Privileged processor or debugger, with
the exception of the NSU bit, which becomes Non-secure-Privileged-writabl
when the NSP bit is set. */
__IOM uint32_t SRAM8; /*!< Control whether debugger, DMA, core 0 and core 1 can access
SRAM8, and at what security/privilege levels they can do
so. Defaults to fully open access. This register is writable
only from a Secure, Privileged processor or debugger, with
the exception of the NSU bit, which becomes Non-secure-Privileged-writabl
when the NSP bit is set. */
__IOM uint32_t SRAM9; /*!< Control whether debugger, DMA, core 0 and core 1 can access
SRAM9, and at what security/privilege levels they can do
so. Defaults to fully open access. This register is writable
only from a Secure, Privileged processor or debugger, with
the exception of the NSU bit, which becomes Non-secure-Privileged-writabl
when the NSP bit is set. */
__IOM uint32_t DMA; /*!< Control whether debugger, DMA, core 0 and core 1 can access
DMA, and at what security/privilege levels they can do
so. Defaults to Secure access from any master. This register
is writable only from a Secure, Privileged processor or
debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t USBCTRL; /*!< Control whether debugger, DMA, core 0 and core 1 can access
USBCTRL, and at what security/privilege levels they can
do so. Defaults to Secure access from any master. This
register is writable only from a Secure, Privileged processor
or debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t PIO0; /*!< Control whether debugger, DMA, core 0 and core 1 can access
PIO0, and at what security/privilege levels they can do
so. Defaults to Secure access from any master. This register
is writable only from a Secure, Privileged processor or
debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t PIO1; /*!< Control whether debugger, DMA, core 0 and core 1 can access
PIO1, and at what security/privilege levels they can do
so. Defaults to Secure access from any master. This register
is writable only from a Secure, Privileged processor or
debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t PIO2; /*!< Control whether debugger, DMA, core 0 and core 1 can access
PIO2, and at what security/privilege levels they can do
so. Defaults to Secure access from any master. This register
is writable only from a Secure, Privileged processor or
debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t CORESIGHT_TRACE; /*!< Control whether debugger, DMA, core 0 and core 1 can access
CORESIGHT_TRACE, and at what security/privilege levels
they can do so. Defaults to Secure, Privileged processor
or debug access only. This register is writable only from
a Secure, Privileged processor or debugger, with the exception
of the NSU bit, which becomes Non-secure-Privileged-writable
when the NSP bit is set. */
__IOM uint32_t CORESIGHT_PERIPH; /*!< Control whether debugger, DMA, core 0 and core 1 can access
CORESIGHT_PERIPH, and at what security/privilege levels
they can do so. Defaults to Secure, Privileged processor
or debug access only. This register is writable only from
a Secure, Privileged processor or debugger, with the exception
of the NSU bit, which becomes Non-secure-Privileged-writable
when the NSP bit is set. */
__IOM uint32_t SYSINFO; /*!< Control whether debugger, DMA, core 0 and core 1 can access
SYSINFO, and at what security/privilege levels they can
do so. Defaults to fully open access. This register is
writable only from a Secure, Privileged processor or debugger,
with the exception of the NSU bit, which becomes Non-secure-Privileged-wr
table when the NSP bit is set. */
__IOM uint32_t RESETS; /*!< Control whether debugger, DMA, core 0 and core 1 can access
RESETS, and at what security/privilege levels they can
do so. Defaults to Secure access from any master. This
register is writable only from a Secure, Privileged processor
or debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t IO_BANK0; /*!< Control whether debugger, DMA, core 0 and core 1 can access
IO_BANK0, and at what security/privilege levels they can
do so. Defaults to Secure access from any master. This
register is writable only from a Secure, Privileged processor
or debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t IO_BANK1; /*!< Control whether debugger, DMA, core 0 and core 1 can access
IO_BANK1, and at what security/privilege levels they can
do so. Defaults to Secure access from any master. This
register is writable only from a Secure, Privileged processor
or debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t PADS_BANK0; /*!< Control whether debugger, DMA, core 0 and core 1 can access
PADS_BANK0, and at what security/privilege levels they
can do so. Defaults to Secure access from any master. This
register is writable only from a Secure, Privileged processor
or debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t PADS_QSPI; /*!< Control whether debugger, DMA, core 0 and core 1 can access
PADS_QSPI, and at what security/privilege levels they can
do so. Defaults to Secure access from any master. This
register is writable only from a Secure, Privileged processor
or debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t BUSCTRL; /*!< Control whether debugger, DMA, core 0 and core 1 can access
BUSCTRL, and at what security/privilege levels they can
do so. Defaults to Secure access from any master. This
register is writable only from a Secure, Privileged processor
or debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t ADC0; /*!< Control whether debugger, DMA, core 0 and core 1 can access
ADC0, and at what security/privilege levels they can do
so. Defaults to Secure access from any master. This register
is writable only from a Secure, Privileged processor or
debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t HSTX; /*!< Control whether debugger, DMA, core 0 and core 1 can access
HSTX, and at what security/privilege levels they can do
so. Defaults to Secure access from any master. This register
is writable only from a Secure, Privileged processor or
debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t I2C0; /*!< Control whether debugger, DMA, core 0 and core 1 can access
I2C0, and at what security/privilege levels they can do
so. Defaults to Secure access from any master. This register
is writable only from a Secure, Privileged processor or
debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t I2C1; /*!< Control whether debugger, DMA, core 0 and core 1 can access
I2C1, and at what security/privilege levels they can do
so. Defaults to Secure access from any master. This register
is writable only from a Secure, Privileged processor or
debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t PWM; /*!< Control whether debugger, DMA, core 0 and core 1 can access
PWM, and at what security/privilege levels they can do
so. Defaults to Secure access from any master. This register
is writable only from a Secure, Privileged processor or
debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t SPI0; /*!< Control whether debugger, DMA, core 0 and core 1 can access
SPI0, and at what security/privilege levels they can do
so. Defaults to Secure access from any master. This register
is writable only from a Secure, Privileged processor or
debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t SPI1; /*!< Control whether debugger, DMA, core 0 and core 1 can access
SPI1, and at what security/privilege levels they can do
so. Defaults to Secure access from any master. This register
is writable only from a Secure, Privileged processor or
debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t TIMER0; /*!< Control whether debugger, DMA, core 0 and core 1 can access
TIMER0, and at what security/privilege levels they can
do so. Defaults to Secure access from any master. This
register is writable only from a Secure, Privileged processor
or debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t TIMER1; /*!< Control whether debugger, DMA, core 0 and core 1 can access
TIMER1, and at what security/privilege levels they can
do so. Defaults to Secure access from any master. This
register is writable only from a Secure, Privileged processor
or debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t UART0; /*!< Control whether debugger, DMA, core 0 and core 1 can access
UART0, and at what security/privilege levels they can do
so. Defaults to Secure access from any master. This register
is writable only from a Secure, Privileged processor or
debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t UART1; /*!< Control whether debugger, DMA, core 0 and core 1 can access
UART1, and at what security/privilege levels they can do
so. Defaults to Secure access from any master. This register
is writable only from a Secure, Privileged processor or
debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t OTP; /*!< Control whether debugger, DMA, core 0 and core 1 can access
OTP, and at what security/privilege levels they can do
so. Defaults to Secure access from any master. This register
is writable only from a Secure, Privileged processor or
debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t TBMAN; /*!< Control whether debugger, DMA, core 0 and core 1 can access
TBMAN, and at what security/privilege levels they can do
so. Defaults to Secure access from any master. This register
is writable only from a Secure, Privileged processor or
debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t POWMAN; /*!< Control whether debugger, DMA, core 0 and core 1 can access
POWMAN, and at what security/privilege levels they can
do so. Defaults to Secure, Privileged processor or debug
access only. This register is writable only from a Secure,
Privileged processor or debugger, with the exception of
the NSU bit, which becomes Non-secure-Privileged-writable
when the NSP bit is set. */
__IOM uint32_t TRNG; /*!< Control whether debugger, DMA, core 0 and core 1 can access
TRNG, and at what security/privilege levels they can do
so. Defaults to Secure, Privileged processor or debug access
only. This register is writable only from a Secure, Privileged
processor or debugger, with the exception of the NSU bit,
which becomes Non-secure-Privileged-writable when the NSP
bit is set. */
__IOM uint32_t SHA256; /*!< Control whether debugger, DMA, core 0 and core 1 can access
SHA256, and at what security/privilege levels they can
do so. Defaults to Secure, Privileged access only. This
register is writable only from a Secure, Privileged processor
or debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
__IOM uint32_t SYSCFG; /*!< Control whether debugger, DMA, core 0 and core 1 can access
SYSCFG, and at what security/privilege levels they can
do so. Defaults to Secure, Privileged processor or debug
access only. This register is writable only from a Secure,
Privileged processor or debugger, with the exception of
the NSU bit, which becomes Non-secure-Privileged-writable
when the NSP bit is set. */
__IOM uint32_t CLOCKS; /*!< Control whether debugger, DMA, core 0 and core 1 can access
CLOCKS, and at what security/privilege levels they can
do so. Defaults to Secure, Privileged processor or debug
access only. This register is writable only from a Secure,
Privileged processor or debugger, with the exception of
the NSU bit, which becomes Non-secure-Privileged-writable
when the NSP bit is set. */
__IOM uint32_t XOSC; /*!< Control whether debugger, DMA, core 0 and core 1 can access
XOSC, and at what security/privilege levels they can do
so. Defaults to Secure, Privileged processor or debug access
only. This register is writable only from a Secure, Privileged
processor or debugger, with the exception of the NSU bit,
which becomes Non-secure-Privileged-writable when the NSP
bit is set. */
__IOM uint32_t ROSC; /*!< Control whether debugger, DMA, core 0 and core 1 can access
ROSC, and at what security/privilege levels they can do
so. Defaults to Secure, Privileged processor or debug access
only. This register is writable only from a Secure, Privileged
processor or debugger, with the exception of the NSU bit,
which becomes Non-secure-Privileged-writable when the NSP
bit is set. */
__IOM uint32_t PLL_SYS; /*!< Control whether debugger, DMA, core 0 and core 1 can access
PLL_SYS, and at what security/privilege levels they can
do so. Defaults to Secure, Privileged processor or debug
access only. This register is writable only from a Secure,
Privileged processor or debugger, with the exception of
the NSU bit, which becomes Non-secure-Privileged-writable
when the NSP bit is set. */
__IOM uint32_t PLL_USB; /*!< Control whether debugger, DMA, core 0 and core 1 can access
PLL_USB, and at what security/privilege levels they can
do so. Defaults to Secure, Privileged processor or debug
access only. This register is writable only from a Secure,
Privileged processor or debugger, with the exception of
the NSU bit, which becomes Non-secure-Privileged-writable
when the NSP bit is set. */
__IOM uint32_t TICKS; /*!< Control whether debugger, DMA, core 0 and core 1 can access
TICKS, and at what security/privilege levels they can do
so. Defaults to Secure, Privileged processor or debug access
only. This register is writable only from a Secure, Privileged
processor or debugger, with the exception of the NSU bit,
which becomes Non-secure-Privileged-writable when the NSP
bit is set. */
__IOM uint32_t WATCHDOG; /*!< Control whether debugger, DMA, core 0 and core 1 can access
WATCHDOG, and at what security/privilege levels they can
do so. Defaults to Secure, Privileged processor or debug
access only. This register is writable only from a Secure,
Privileged processor or debugger, with the exception of
the NSU bit, which becomes Non-secure-Privileged-writable
when the NSP bit is set. */
__IOM uint32_t RSM; /*!< Control whether debugger, DMA, core 0 and core 1 can access
RSM, and at what security/privilege levels they can do
so. Defaults to Secure, Privileged processor or debug access
only. This register is writable only from a Secure, Privileged
processor or debugger, with the exception of the NSU bit,
which becomes Non-secure-Privileged-writable when the NSP
bit is set. */
__IOM uint32_t XIP_CTRL; /*!< Control whether debugger, DMA, core 0 and core 1 can access
XIP_CTRL, and at what security/privilege levels they can
do so. Defaults to Secure, Privileged processor or debug
access only. This register is writable only from a Secure,
Privileged processor or debugger, with the exception of
the NSU bit, which becomes Non-secure-Privileged-writable
when the NSP bit is set. */
__IOM uint32_t XIP_QMI; /*!< Control whether debugger, DMA, core 0 and core 1 can access
XIP_QMI, and at what security/privilege levels they can
do so. Defaults to Secure, Privileged processor or debug
access only. This register is writable only from a Secure,
Privileged processor or debugger, with the exception of
the NSU bit, which becomes Non-secure-Privileged-writable
when the NSP bit is set. */
__IOM uint32_t XIP_AUX; /*!< Control whether debugger, DMA, core 0 and core 1 can access
XIP_AUX, and at what security/privilege levels they can
do so. Defaults to Secure, Privileged access only. This
register is writable only from a Secure, Privileged processor
or debugger, with the exception of the NSU bit, which becomes
Non-secure-Privileged-writable when the NSP bit is set. */
} ACCESSCTRL_Type; /*!< Size = 236 (0xec) */
/* =========================================================================================================================== */
/* ================ UART0 ================ */
/* =========================================================================================================================== */
/**
* @brief UART0 (UART0)
*/
typedef struct { /*!< UART0 Structure */
__IOM uint32_t UARTDR; /*!< Data Register, UARTDR */
__IOM uint32_t UARTRSR; /*!< Receive Status Register/Error Clear Register, UARTRSR/UARTECR */
__IM uint32_t RESERVED[4];
__IOM uint32_t UARTFR; /*!< Flag Register, UARTFR */
__IM uint32_t RESERVED1;
__IOM uint32_t UARTILPR; /*!< IrDA Low-Power Counter Register, UARTILPR */
__IOM uint32_t UARTIBRD; /*!< Integer Baud Rate Register, UARTIBRD */
__IOM uint32_t UARTFBRD; /*!< Fractional Baud Rate Register, UARTFBRD */
__IOM uint32_t UARTLCR_H; /*!< Line Control Register, UARTLCR_H */
__IOM uint32_t UARTCR; /*!< Control Register, UARTCR */
__IOM uint32_t UARTIFLS; /*!< Interrupt FIFO Level Select Register, UARTIFLS */
__IOM uint32_t UARTIMSC; /*!< Interrupt Mask Set/Clear Register, UARTIMSC */
__IOM uint32_t UARTRIS; /*!< Raw Interrupt Status Register, UARTRIS */
__IOM uint32_t UARTMIS; /*!< Masked Interrupt Status Register, UARTMIS */
__IOM uint32_t UARTICR; /*!< Interrupt Clear Register, UARTICR */
__IOM uint32_t UARTDMACR; /*!< DMA Control Register, UARTDMACR */
__IM uint32_t RESERVED2[997];
__IOM uint32_t UARTPERIPHID0; /*!< UARTPeriphID0 Register */
__IOM uint32_t UARTPERIPHID1; /*!< UARTPeriphID1 Register */
__IOM uint32_t UARTPERIPHID2; /*!< UARTPeriphID2 Register */
__IOM uint32_t UARTPERIPHID3; /*!< UARTPeriphID3 Register */
__IOM uint32_t UARTPCELLID0; /*!< UARTPCellID0 Register */
__IOM uint32_t UARTPCELLID1; /*!< UARTPCellID1 Register */
__IOM uint32_t UARTPCELLID2; /*!< UARTPCellID2 Register */
__IOM uint32_t UARTPCELLID3; /*!< UARTPCellID3 Register */
} UART0_Type; /*!< Size = 4096 (0x1000) */
/* =========================================================================================================================== */
/* ================ ROSC ================ */
/* =========================================================================================================================== */
/**
* @brief ROSC (ROSC)
*/
typedef struct { /*!< ROSC Structure */
__IOM uint32_t CTRL; /*!< Ring Oscillator control */
__IOM uint32_t FREQA; /*!< The FREQA & FREQB registers control the frequency by controlling
the drive strength of each stage The drive strength has
4 levels determined by the number of bits set Increasing
the number of bits set increases the drive strength and
increases the oscillation frequency 0 bits set is the default
drive strength 1 bit set doubles the drive strength 2 bits
set triples drive strength 3 bits set quadruples drive
strength For frequency randomisation set both DS0_RANDOM=1
& DS1_RANDOM=1 */
__IOM uint32_t FREQB; /*!< For a detailed description see freqa register */
__IOM uint32_t RANDOM; /*!< Loads a value to the LFSR randomiser */
__IOM uint32_t DORMANT; /*!< Ring Oscillator pause control */
__IOM uint32_t DIV; /*!< Controls the output divider */
__IOM uint32_t PHASE; /*!< Controls the phase shifted output */
__IOM uint32_t STATUS; /*!< Ring Oscillator Status */
__IOM uint32_t RANDOMBIT; /*!< This just reads the state of the oscillator output so randomness
is compromised if the ring oscillator is stopped or run
at a harmonic of the bus frequency */
__IOM uint32_t COUNT; /*!< A down counter running at the ROSC frequency which counts to
zero and stops. To start the counter write a non-zero value.
Can be used for short software pauses when setting up time
sensitive hardware. */
} ROSC_Type; /*!< Size = 40 (0x28) */
/* =========================================================================================================================== */
/* ================ POWMAN ================ */
/* =========================================================================================================================== */
/**
* @brief Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use (POWMAN)
*/
typedef struct { /*!< POWMAN Structure */
__IOM uint32_t BADPASSWD; /*!< Indicates a bad password has been used */
__IOM uint32_t VREG_CTRL; /*!< Voltage Regulator Control */
__IOM uint32_t VREG_STS; /*!< Voltage Regulator Status */
__IOM uint32_t VREG; /*!< Voltage Regulator Settings */
__IOM uint32_t VREG_LP_ENTRY; /*!< Voltage Regulator Low Power Entry Settings */
__IOM uint32_t VREG_LP_EXIT; /*!< Voltage Regulator Low Power Exit Settings */
__IOM uint32_t BOD_CTRL; /*!< Brown-out Detection Control */
__IOM uint32_t BOD; /*!< Brown-out Detection Settings */
__IOM uint32_t BOD_LP_ENTRY; /*!< Brown-out Detection Low Power Entry Settings */
__IOM uint32_t BOD_LP_EXIT; /*!< Brown-out Detection Low Power Exit Settings */
__IOM uint32_t LPOSC; /*!< Low power oscillator control register. */
__IOM uint32_t CHIP_RESET; /*!< Chip reset control and status */
__IOM uint32_t WDSEL; /*!< Allows a watchdog reset to reset the internal state of powman
in addition to the power-on state machine (PSM). Note that
powman ignores watchdog resets that do not select at least
the CLOCKS stage or earlier stages in the PSM. If using
these bits, it's recommended to set PSM_WDSEL to all-ones
in addition to the desired bits in this register. Failing
to select CLOCKS or earlier will result in the POWMAN_WDSEL
register having no effect. */
__IOM uint32_t SEQ_CFG; /*!< For configuration of the power sequencer Writes are ignored
while POWMAN_STATE_CHANGING=1 */
__IOM uint32_t STATE; /*!< This register controls the power state of the 4 power domains.
The current power state is indicated in POWMAN_STATE_CURRENT
which is read-only. To change the state, write to POWMAN_STATE_REQ.
The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds
to the power states defined in the datasheet: bit 3 = SWCORE
bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered
up 1 = powered down When POWMAN_STATE_REQ is written, the
POWMAN_STATE_WAITING flag is set while the Power Manager
determines what is required. If an invalid transition is
requested the Power Manager will still register the request
in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ
flag. It will then implement the power-up requests and
ignore the power down requests. To do nothing would risk
entering an unrecoverable lock-up state. Invalid requests
are: any combination of power up and power down requests
any request that results in swcore boing powered and xip
unpowered If the request is to power down the switched-core
domain then POWMAN_STATE_WAITING stays active until the
processors halt. During this time the POWMAN_STATE_REQ
field can be re-written to change or cancel the request.
When the power state transition begins the POWMAN_STATE_WAITING_flag
is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN
register writes are ignored until the transition completes. */
__IOM uint32_t POW_FASTDIV; /*!< POW_FASTDIV */
__IOM uint32_t POW_DELAY; /*!< power state machine delays */
__IOM uint32_t EXT_CTRL0; /*!< Configures a gpio as a power mode aware control output */
__IOM uint32_t EXT_CTRL1; /*!< Configures a gpio as a power mode aware control output */
__IOM uint32_t EXT_TIME_REF; /*!< Select a GPIO to use as a time reference, the source can be
used to drive the low power clock at 32kHz, or to provide
a 1ms tick to the timer, or provide a 1Hz tick to the timer.
The tick selection is controlled by the POWMAN_TIMER register. */
__IOM uint32_t LPOSC_FREQ_KHZ_INT; /*!< Informs the AON Timer of the integer component of the clock
frequency when running off the LPOSC. */
__IOM uint32_t LPOSC_FREQ_KHZ_FRAC; /*!< Informs the AON Timer of the fractional component of the clock
frequency when running off the LPOSC. */
__IOM uint32_t XOSC_FREQ_KHZ_INT; /*!< Informs the AON Timer of the integer component of the clock
frequency when running off the XOSC. */
__IOM uint32_t XOSC_FREQ_KHZ_FRAC; /*!< Informs the AON Timer of the fractional component of the clock
frequency when running off the XOSC. */
__IOM uint32_t SET_TIME_63TO48; /*!< SET_TIME_63TO48 */
__IOM uint32_t SET_TIME_47TO32; /*!< SET_TIME_47TO32 */
__IOM uint32_t SET_TIME_31TO16; /*!< SET_TIME_31TO16 */
__IOM uint32_t SET_TIME_15TO0; /*!< SET_TIME_15TO0 */
__IOM uint32_t READ_TIME_UPPER; /*!< READ_TIME_UPPER */
__IOM uint32_t READ_TIME_LOWER; /*!< READ_TIME_LOWER */
__IOM uint32_t ALARM_TIME_63TO48; /*!< ALARM_TIME_63TO48 */
__IOM uint32_t ALARM_TIME_47TO32; /*!< ALARM_TIME_47TO32 */
__IOM uint32_t ALARM_TIME_31TO16; /*!< ALARM_TIME_31TO16 */
__IOM uint32_t ALARM_TIME_15TO0; /*!< ALARM_TIME_15TO0 */
__IOM uint32_t TIMER; /*!< TIMER */
__IOM uint32_t PWRUP0; /*!< 4 GPIO powerup events can be configured to wake the chip up
from a low power state. The pwrups are level/edge sensitive
and can be set to trigger on a high/rising or low/falling
event The number of gpios available depends on the package
option. An invalid selection will be ignored source = 0
selects gpio0 . . source = 47 selects gpio47 source = 48
selects qspi_ss source = 49 selects qspi_sd0 source = 50
selects qspi_sd1 source = 51 selects qspi_sd2 source =
52 selects qspi_sd3 source = 53 selects qspi_sclk level
= 0 triggers the pwrup when the source is low level = 1
triggers the pwrup when the source is high */
__IOM uint32_t PWRUP1; /*!< 4 GPIO powerup events can be configured to wake the chip up
from a low power state. The pwrups are level/edge sensitive
and can be set to trigger on a high/rising or low/falling
event The number of gpios available depends on the package
option. An invalid selection will be ignored source = 0
selects gpio0 . . source = 47 selects gpio47 source = 48
selects qspi_ss source = 49 selects qspi_sd0 source = 50
selects qspi_sd1 source = 51 selects qspi_sd2 source =
52 selects qspi_sd3 source = 53 selects qspi_sclk level
= 0 triggers the pwrup when the source is low level = 1
triggers the pwrup when the source is high */
__IOM uint32_t PWRUP2; /*!< 4 GPIO powerup events can be configured to wake the chip up
from a low power state. The pwrups are level/edge sensitive
and can be set to trigger on a high/rising or low/falling
event The number of gpios available depends on the package
option. An invalid selection will be ignored source = 0
selects gpio0 . . source = 47 selects gpio47 source = 48
selects qspi_ss source = 49 selects qspi_sd0 source = 50
selects qspi_sd1 source = 51 selects qspi_sd2 source =
52 selects qspi_sd3 source = 53 selects qspi_sclk level
= 0 triggers the pwrup when the source is low level = 1
triggers the pwrup when the source is high */
__IOM uint32_t PWRUP3; /*!< 4 GPIO powerup events can be configured to wake the chip up
from a low power state. The pwrups are level/edge sensitive
and can be set to trigger on a high/rising or low/falling
event The number of gpios available depends on the package
option. An invalid selection will be ignored source = 0
selects gpio0 . . source = 47 selects gpio47 source = 48
selects qspi_ss source = 49 selects qspi_sd0 source = 50
selects qspi_sd1 source = 51 selects qspi_sd2 source =
52 selects qspi_sd3 source = 53 selects qspi_sclk level
= 0 triggers the pwrup when the source is low level = 1
triggers the pwrup when the source is high */
__IOM uint32_t CURRENT_PWRUP_REQ; /*!< Indicates current powerup request state pwrup events can be
cleared by removing the enable from the pwrup register.
The alarm pwrup req can be cleared by clearing timer.alarm_enab
0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET
1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup
6 = alarm_pwrup */
__IOM uint32_t LAST_SWCORE_PWRUP; /*!< Indicates which pwrup source triggered the last switched-core
power up 0 = chip reset, for the source of the last reset
see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2
4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup */
__IOM uint32_t DBG_PWRCFG; /*!< DBG_PWRCFG */
__IOM uint32_t BOOTDIS; /*!< Tell the bootrom to ignore the BOOT0..3 registers following
the next RSM reset (e.g. the next core power down/up).
If an early boot stage has soft-locked some OTP pages in
order to protect their contents from later stages, there
is a risk that Secure code running at a later stage can
unlock the pages by powering the core up and down. This
register can be used to ensure that the bootloader runs
as normal on the next power up, preventing Secure code
at a later stage from accessing OTP in its unlocked state.
Should be used in conjunction with the OTP BOOTDIS register. */
__IOM uint32_t DBGCONFIG; /*!< DBGCONFIG */
__IOM uint32_t SCRATCH0; /*!< Scratch register. Information persists in low power mode */
__IOM uint32_t SCRATCH1; /*!< Scratch register. Information persists in low power mode */
__IOM uint32_t SCRATCH2; /*!< Scratch register. Information persists in low power mode */
__IOM uint32_t SCRATCH3; /*!< Scratch register. Information persists in low power mode */
__IOM uint32_t SCRATCH4; /*!< Scratch register. Information persists in low power mode */
__IOM uint32_t SCRATCH5; /*!< Scratch register. Information persists in low power mode */
__IOM uint32_t SCRATCH6; /*!< Scratch register. Information persists in low power mode */
__IOM uint32_t SCRATCH7; /*!< Scratch register. Information persists in low power mode */
__IOM uint32_t BOOT0; /*!< Scratch register. Information persists in low power mode */
__IOM uint32_t BOOT1; /*!< Scratch register. Information persists in low power mode */
__IOM uint32_t BOOT2; /*!< Scratch register. Information persists in low power mode */
__IOM uint32_t BOOT3; /*!< Scratch register. Information persists in low power mode */
__IOM uint32_t INTR; /*!< Raw Interrupts */
__IOM uint32_t INTE; /*!< Interrupt Enable */
__IOM uint32_t INTF; /*!< Interrupt Force */
__IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */
} POWMAN_Type; /*!< Size = 240 (0xf0) */
/* =========================================================================================================================== */
/* ================ WATCHDOG ================ */
/* =========================================================================================================================== */
/**
* @brief WATCHDOG (WATCHDOG)
*/
typedef struct { /*!< WATCHDOG Structure */
__IOM uint32_t CTRL; /*!< Watchdog control The rst_wdsel register determines which subsystems
are reset when the watchdog is triggered. The watchdog
can be triggered in software. */
__IOM uint32_t LOAD; /*!< Load the watchdog timer. The maximum setting is 0xffffff which
corresponds to approximately 16 seconds. */
__IOM uint32_t REASON; /*!< Logs the reason for the last reset. Both bits are zero for the
case of a hardware reset. Additionally, as of RP2350, a
debugger warm reset of either core (SYSRESETREQ or hartreset)
will also clear the watchdog reason register, so that software
loaded under the debugger following a watchdog timeout
will not continue to see the timeout condition. */
__IOM uint32_t SCRATCH0; /*!< Scratch register. Information persists through soft reset of
the chip. */
__IOM uint32_t SCRATCH1; /*!< Scratch register. Information persists through soft reset of
the chip. */
__IOM uint32_t SCRATCH2; /*!< Scratch register. Information persists through soft reset of
the chip. */
__IOM uint32_t SCRATCH3; /*!< Scratch register. Information persists through soft reset of
the chip. */
__IOM uint32_t SCRATCH4; /*!< Scratch register. Information persists through soft reset of
the chip. */
__IOM uint32_t SCRATCH5; /*!< Scratch register. Information persists through soft reset of
the chip. */
__IOM uint32_t SCRATCH6; /*!< Scratch register. Information persists through soft reset of
the chip. */
__IOM uint32_t SCRATCH7; /*!< Scratch register. Information persists through soft reset of
the chip. */
} WATCHDOG_Type; /*!< Size = 44 (0x2c) */
/* =========================================================================================================================== */
/* ================ DMA ================ */
/* =========================================================================================================================== */
/**
* @brief DMA with separate read and write masters (DMA)
*/
typedef struct { /*!< DMA Structure */
__IOM uint32_t CH0_READ_ADDR; /*!< DMA Channel 0 Read Address pointer */
__IOM uint32_t CH0_WRITE_ADDR; /*!< DMA Channel 0 Write Address pointer */
__IOM uint32_t CH0_TRANS_COUNT; /*!< DMA Channel 0 Transfer Count */
__IOM uint32_t CH0_CTRL_TRIG; /*!< DMA Channel 0 Control and Status */
__IOM uint32_t CH0_AL1_CTRL; /*!< Alias for channel 0 CTRL register */
__IOM uint32_t CH0_AL1_READ_ADDR; /*!< Alias for channel 0 READ_ADDR register */
__IOM uint32_t CH0_AL1_WRITE_ADDR; /*!< Alias for channel 0 WRITE_ADDR register */
__IOM uint32_t CH0_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 0 TRANS_COUNT register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH0_AL2_CTRL; /*!< Alias for channel 0 CTRL register */
__IOM uint32_t CH0_AL2_TRANS_COUNT; /*!< Alias for channel 0 TRANS_COUNT register */
__IOM uint32_t CH0_AL2_READ_ADDR; /*!< Alias for channel 0 READ_ADDR register */
__IOM uint32_t CH0_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 0 WRITE_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH0_AL3_CTRL; /*!< Alias for channel 0 CTRL register */
__IOM uint32_t CH0_AL3_WRITE_ADDR; /*!< Alias for channel 0 WRITE_ADDR register */
__IOM uint32_t CH0_AL3_TRANS_COUNT; /*!< Alias for channel 0 TRANS_COUNT register */
__IOM uint32_t CH0_AL3_READ_ADDR_TRIG; /*!< Alias for channel 0 READ_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH1_READ_ADDR; /*!< DMA Channel 1 Read Address pointer */
__IOM uint32_t CH1_WRITE_ADDR; /*!< DMA Channel 1 Write Address pointer */
__IOM uint32_t CH1_TRANS_COUNT; /*!< DMA Channel 1 Transfer Count */
__IOM uint32_t CH1_CTRL_TRIG; /*!< DMA Channel 1 Control and Status */
__IOM uint32_t CH1_AL1_CTRL; /*!< Alias for channel 1 CTRL register */
__IOM uint32_t CH1_AL1_READ_ADDR; /*!< Alias for channel 1 READ_ADDR register */
__IOM uint32_t CH1_AL1_WRITE_ADDR; /*!< Alias for channel 1 WRITE_ADDR register */
__IOM uint32_t CH1_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 1 TRANS_COUNT register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH1_AL2_CTRL; /*!< Alias for channel 1 CTRL register */
__IOM uint32_t CH1_AL2_TRANS_COUNT; /*!< Alias for channel 1 TRANS_COUNT register */
__IOM uint32_t CH1_AL2_READ_ADDR; /*!< Alias for channel 1 READ_ADDR register */
__IOM uint32_t CH1_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 1 WRITE_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH1_AL3_CTRL; /*!< Alias for channel 1 CTRL register */
__IOM uint32_t CH1_AL3_WRITE_ADDR; /*!< Alias for channel 1 WRITE_ADDR register */
__IOM uint32_t CH1_AL3_TRANS_COUNT; /*!< Alias for channel 1 TRANS_COUNT register */
__IOM uint32_t CH1_AL3_READ_ADDR_TRIG; /*!< Alias for channel 1 READ_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH2_READ_ADDR; /*!< DMA Channel 2 Read Address pointer */
__IOM uint32_t CH2_WRITE_ADDR; /*!< DMA Channel 2 Write Address pointer */
__IOM uint32_t CH2_TRANS_COUNT; /*!< DMA Channel 2 Transfer Count */
__IOM uint32_t CH2_CTRL_TRIG; /*!< DMA Channel 2 Control and Status */
__IOM uint32_t CH2_AL1_CTRL; /*!< Alias for channel 2 CTRL register */
__IOM uint32_t CH2_AL1_READ_ADDR; /*!< Alias for channel 2 READ_ADDR register */
__IOM uint32_t CH2_AL1_WRITE_ADDR; /*!< Alias for channel 2 WRITE_ADDR register */
__IOM uint32_t CH2_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 2 TRANS_COUNT register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH2_AL2_CTRL; /*!< Alias for channel 2 CTRL register */
__IOM uint32_t CH2_AL2_TRANS_COUNT; /*!< Alias for channel 2 TRANS_COUNT register */
__IOM uint32_t CH2_AL2_READ_ADDR; /*!< Alias for channel 2 READ_ADDR register */
__IOM uint32_t CH2_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 2 WRITE_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH2_AL3_CTRL; /*!< Alias for channel 2 CTRL register */
__IOM uint32_t CH2_AL3_WRITE_ADDR; /*!< Alias for channel 2 WRITE_ADDR register */
__IOM uint32_t CH2_AL3_TRANS_COUNT; /*!< Alias for channel 2 TRANS_COUNT register */
__IOM uint32_t CH2_AL3_READ_ADDR_TRIG; /*!< Alias for channel 2 READ_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH3_READ_ADDR; /*!< DMA Channel 3 Read Address pointer */
__IOM uint32_t CH3_WRITE_ADDR; /*!< DMA Channel 3 Write Address pointer */
__IOM uint32_t CH3_TRANS_COUNT; /*!< DMA Channel 3 Transfer Count */
__IOM uint32_t CH3_CTRL_TRIG; /*!< DMA Channel 3 Control and Status */
__IOM uint32_t CH3_AL1_CTRL; /*!< Alias for channel 3 CTRL register */
__IOM uint32_t CH3_AL1_READ_ADDR; /*!< Alias for channel 3 READ_ADDR register */
__IOM uint32_t CH3_AL1_WRITE_ADDR; /*!< Alias for channel 3 WRITE_ADDR register */
__IOM uint32_t CH3_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 3 TRANS_COUNT register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH3_AL2_CTRL; /*!< Alias for channel 3 CTRL register */
__IOM uint32_t CH3_AL2_TRANS_COUNT; /*!< Alias for channel 3 TRANS_COUNT register */
__IOM uint32_t CH3_AL2_READ_ADDR; /*!< Alias for channel 3 READ_ADDR register */
__IOM uint32_t CH3_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 3 WRITE_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH3_AL3_CTRL; /*!< Alias for channel 3 CTRL register */
__IOM uint32_t CH3_AL3_WRITE_ADDR; /*!< Alias for channel 3 WRITE_ADDR register */
__IOM uint32_t CH3_AL3_TRANS_COUNT; /*!< Alias for channel 3 TRANS_COUNT register */
__IOM uint32_t CH3_AL3_READ_ADDR_TRIG; /*!< Alias for channel 3 READ_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH4_READ_ADDR; /*!< DMA Channel 4 Read Address pointer */
__IOM uint32_t CH4_WRITE_ADDR; /*!< DMA Channel 4 Write Address pointer */
__IOM uint32_t CH4_TRANS_COUNT; /*!< DMA Channel 4 Transfer Count */
__IOM uint32_t CH4_CTRL_TRIG; /*!< DMA Channel 4 Control and Status */
__IOM uint32_t CH4_AL1_CTRL; /*!< Alias for channel 4 CTRL register */
__IOM uint32_t CH4_AL1_READ_ADDR; /*!< Alias for channel 4 READ_ADDR register */
__IOM uint32_t CH4_AL1_WRITE_ADDR; /*!< Alias for channel 4 WRITE_ADDR register */
__IOM uint32_t CH4_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 4 TRANS_COUNT register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH4_AL2_CTRL; /*!< Alias for channel 4 CTRL register */
__IOM uint32_t CH4_AL2_TRANS_COUNT; /*!< Alias for channel 4 TRANS_COUNT register */
__IOM uint32_t CH4_AL2_READ_ADDR; /*!< Alias for channel 4 READ_ADDR register */
__IOM uint32_t CH4_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 4 WRITE_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH4_AL3_CTRL; /*!< Alias for channel 4 CTRL register */
__IOM uint32_t CH4_AL3_WRITE_ADDR; /*!< Alias for channel 4 WRITE_ADDR register */
__IOM uint32_t CH4_AL3_TRANS_COUNT; /*!< Alias for channel 4 TRANS_COUNT register */
__IOM uint32_t CH4_AL3_READ_ADDR_TRIG; /*!< Alias for channel 4 READ_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH5_READ_ADDR; /*!< DMA Channel 5 Read Address pointer */
__IOM uint32_t CH5_WRITE_ADDR; /*!< DMA Channel 5 Write Address pointer */
__IOM uint32_t CH5_TRANS_COUNT; /*!< DMA Channel 5 Transfer Count */
__IOM uint32_t CH5_CTRL_TRIG; /*!< DMA Channel 5 Control and Status */
__IOM uint32_t CH5_AL1_CTRL; /*!< Alias for channel 5 CTRL register */
__IOM uint32_t CH5_AL1_READ_ADDR; /*!< Alias for channel 5 READ_ADDR register */
__IOM uint32_t CH5_AL1_WRITE_ADDR; /*!< Alias for channel 5 WRITE_ADDR register */
__IOM uint32_t CH5_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 5 TRANS_COUNT register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH5_AL2_CTRL; /*!< Alias for channel 5 CTRL register */
__IOM uint32_t CH5_AL2_TRANS_COUNT; /*!< Alias for channel 5 TRANS_COUNT register */
__IOM uint32_t CH5_AL2_READ_ADDR; /*!< Alias for channel 5 READ_ADDR register */
__IOM uint32_t CH5_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 5 WRITE_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH5_AL3_CTRL; /*!< Alias for channel 5 CTRL register */
__IOM uint32_t CH5_AL3_WRITE_ADDR; /*!< Alias for channel 5 WRITE_ADDR register */
__IOM uint32_t CH5_AL3_TRANS_COUNT; /*!< Alias for channel 5 TRANS_COUNT register */
__IOM uint32_t CH5_AL3_READ_ADDR_TRIG; /*!< Alias for channel 5 READ_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH6_READ_ADDR; /*!< DMA Channel 6 Read Address pointer */
__IOM uint32_t CH6_WRITE_ADDR; /*!< DMA Channel 6 Write Address pointer */
__IOM uint32_t CH6_TRANS_COUNT; /*!< DMA Channel 6 Transfer Count */
__IOM uint32_t CH6_CTRL_TRIG; /*!< DMA Channel 6 Control and Status */
__IOM uint32_t CH6_AL1_CTRL; /*!< Alias for channel 6 CTRL register */
__IOM uint32_t CH6_AL1_READ_ADDR; /*!< Alias for channel 6 READ_ADDR register */
__IOM uint32_t CH6_AL1_WRITE_ADDR; /*!< Alias for channel 6 WRITE_ADDR register */
__IOM uint32_t CH6_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 6 TRANS_COUNT register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH6_AL2_CTRL; /*!< Alias for channel 6 CTRL register */
__IOM uint32_t CH6_AL2_TRANS_COUNT; /*!< Alias for channel 6 TRANS_COUNT register */
__IOM uint32_t CH6_AL2_READ_ADDR; /*!< Alias for channel 6 READ_ADDR register */
__IOM uint32_t CH6_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 6 WRITE_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH6_AL3_CTRL; /*!< Alias for channel 6 CTRL register */
__IOM uint32_t CH6_AL3_WRITE_ADDR; /*!< Alias for channel 6 WRITE_ADDR register */
__IOM uint32_t CH6_AL3_TRANS_COUNT; /*!< Alias for channel 6 TRANS_COUNT register */
__IOM uint32_t CH6_AL3_READ_ADDR_TRIG; /*!< Alias for channel 6 READ_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH7_READ_ADDR; /*!< DMA Channel 7 Read Address pointer */
__IOM uint32_t CH7_WRITE_ADDR; /*!< DMA Channel 7 Write Address pointer */
__IOM uint32_t CH7_TRANS_COUNT; /*!< DMA Channel 7 Transfer Count */
__IOM uint32_t CH7_CTRL_TRIG; /*!< DMA Channel 7 Control and Status */
__IOM uint32_t CH7_AL1_CTRL; /*!< Alias for channel 7 CTRL register */
__IOM uint32_t CH7_AL1_READ_ADDR; /*!< Alias for channel 7 READ_ADDR register */
__IOM uint32_t CH7_AL1_WRITE_ADDR; /*!< Alias for channel 7 WRITE_ADDR register */
__IOM uint32_t CH7_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 7 TRANS_COUNT register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH7_AL2_CTRL; /*!< Alias for channel 7 CTRL register */
__IOM uint32_t CH7_AL2_TRANS_COUNT; /*!< Alias for channel 7 TRANS_COUNT register */
__IOM uint32_t CH7_AL2_READ_ADDR; /*!< Alias for channel 7 READ_ADDR register */
__IOM uint32_t CH7_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 7 WRITE_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH7_AL3_CTRL; /*!< Alias for channel 7 CTRL register */
__IOM uint32_t CH7_AL3_WRITE_ADDR; /*!< Alias for channel 7 WRITE_ADDR register */
__IOM uint32_t CH7_AL3_TRANS_COUNT; /*!< Alias for channel 7 TRANS_COUNT register */
__IOM uint32_t CH7_AL3_READ_ADDR_TRIG; /*!< Alias for channel 7 READ_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH8_READ_ADDR; /*!< DMA Channel 8 Read Address pointer */
__IOM uint32_t CH8_WRITE_ADDR; /*!< DMA Channel 8 Write Address pointer */
__IOM uint32_t CH8_TRANS_COUNT; /*!< DMA Channel 8 Transfer Count */
__IOM uint32_t CH8_CTRL_TRIG; /*!< DMA Channel 8 Control and Status */
__IOM uint32_t CH8_AL1_CTRL; /*!< Alias for channel 8 CTRL register */
__IOM uint32_t CH8_AL1_READ_ADDR; /*!< Alias for channel 8 READ_ADDR register */
__IOM uint32_t CH8_AL1_WRITE_ADDR; /*!< Alias for channel 8 WRITE_ADDR register */
__IOM uint32_t CH8_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 8 TRANS_COUNT register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH8_AL2_CTRL; /*!< Alias for channel 8 CTRL register */
__IOM uint32_t CH8_AL2_TRANS_COUNT; /*!< Alias for channel 8 TRANS_COUNT register */
__IOM uint32_t CH8_AL2_READ_ADDR; /*!< Alias for channel 8 READ_ADDR register */
__IOM uint32_t CH8_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 8 WRITE_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH8_AL3_CTRL; /*!< Alias for channel 8 CTRL register */
__IOM uint32_t CH8_AL3_WRITE_ADDR; /*!< Alias for channel 8 WRITE_ADDR register */
__IOM uint32_t CH8_AL3_TRANS_COUNT; /*!< Alias for channel 8 TRANS_COUNT register */
__IOM uint32_t CH8_AL3_READ_ADDR_TRIG; /*!< Alias for channel 8 READ_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH9_READ_ADDR; /*!< DMA Channel 9 Read Address pointer */
__IOM uint32_t CH9_WRITE_ADDR; /*!< DMA Channel 9 Write Address pointer */
__IOM uint32_t CH9_TRANS_COUNT; /*!< DMA Channel 9 Transfer Count */
__IOM uint32_t CH9_CTRL_TRIG; /*!< DMA Channel 9 Control and Status */
__IOM uint32_t CH9_AL1_CTRL; /*!< Alias for channel 9 CTRL register */
__IOM uint32_t CH9_AL1_READ_ADDR; /*!< Alias for channel 9 READ_ADDR register */
__IOM uint32_t CH9_AL1_WRITE_ADDR; /*!< Alias for channel 9 WRITE_ADDR register */
__IOM uint32_t CH9_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 9 TRANS_COUNT register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH9_AL2_CTRL; /*!< Alias for channel 9 CTRL register */
__IOM uint32_t CH9_AL2_TRANS_COUNT; /*!< Alias for channel 9 TRANS_COUNT register */
__IOM uint32_t CH9_AL2_READ_ADDR; /*!< Alias for channel 9 READ_ADDR register */
__IOM uint32_t CH9_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 9 WRITE_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH9_AL3_CTRL; /*!< Alias for channel 9 CTRL register */
__IOM uint32_t CH9_AL3_WRITE_ADDR; /*!< Alias for channel 9 WRITE_ADDR register */
__IOM uint32_t CH9_AL3_TRANS_COUNT; /*!< Alias for channel 9 TRANS_COUNT register */
__IOM uint32_t CH9_AL3_READ_ADDR_TRIG; /*!< Alias for channel 9 READ_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH10_READ_ADDR; /*!< DMA Channel 10 Read Address pointer */
__IOM uint32_t CH10_WRITE_ADDR; /*!< DMA Channel 10 Write Address pointer */
__IOM uint32_t CH10_TRANS_COUNT; /*!< DMA Channel 10 Transfer Count */
__IOM uint32_t CH10_CTRL_TRIG; /*!< DMA Channel 10 Control and Status */
__IOM uint32_t CH10_AL1_CTRL; /*!< Alias for channel 10 CTRL register */
__IOM uint32_t CH10_AL1_READ_ADDR; /*!< Alias for channel 10 READ_ADDR register */
__IOM uint32_t CH10_AL1_WRITE_ADDR; /*!< Alias for channel 10 WRITE_ADDR register */
__IOM uint32_t CH10_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 10 TRANS_COUNT register This is a trigger
register (0xc). Writing a nonzero value will reload the
channel counter and start the channel. */
__IOM uint32_t CH10_AL2_CTRL; /*!< Alias for channel 10 CTRL register */
__IOM uint32_t CH10_AL2_TRANS_COUNT; /*!< Alias for channel 10 TRANS_COUNT register */
__IOM uint32_t CH10_AL2_READ_ADDR; /*!< Alias for channel 10 READ_ADDR register */
__IOM uint32_t CH10_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 10 WRITE_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH10_AL3_CTRL; /*!< Alias for channel 10 CTRL register */
__IOM uint32_t CH10_AL3_WRITE_ADDR; /*!< Alias for channel 10 WRITE_ADDR register */
__IOM uint32_t CH10_AL3_TRANS_COUNT; /*!< Alias for channel 10 TRANS_COUNT register */
__IOM uint32_t CH10_AL3_READ_ADDR_TRIG; /*!< Alias for channel 10 READ_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH11_READ_ADDR; /*!< DMA Channel 11 Read Address pointer */
__IOM uint32_t CH11_WRITE_ADDR; /*!< DMA Channel 11 Write Address pointer */
__IOM uint32_t CH11_TRANS_COUNT; /*!< DMA Channel 11 Transfer Count */
__IOM uint32_t CH11_CTRL_TRIG; /*!< DMA Channel 11 Control and Status */
__IOM uint32_t CH11_AL1_CTRL; /*!< Alias for channel 11 CTRL register */
__IOM uint32_t CH11_AL1_READ_ADDR; /*!< Alias for channel 11 READ_ADDR register */
__IOM uint32_t CH11_AL1_WRITE_ADDR; /*!< Alias for channel 11 WRITE_ADDR register */
__IOM uint32_t CH11_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 11 TRANS_COUNT register This is a trigger
register (0xc). Writing a nonzero value will reload the
channel counter and start the channel. */
__IOM uint32_t CH11_AL2_CTRL; /*!< Alias for channel 11 CTRL register */
__IOM uint32_t CH11_AL2_TRANS_COUNT; /*!< Alias for channel 11 TRANS_COUNT register */
__IOM uint32_t CH11_AL2_READ_ADDR; /*!< Alias for channel 11 READ_ADDR register */
__IOM uint32_t CH11_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 11 WRITE_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH11_AL3_CTRL; /*!< Alias for channel 11 CTRL register */
__IOM uint32_t CH11_AL3_WRITE_ADDR; /*!< Alias for channel 11 WRITE_ADDR register */
__IOM uint32_t CH11_AL3_TRANS_COUNT; /*!< Alias for channel 11 TRANS_COUNT register */
__IOM uint32_t CH11_AL3_READ_ADDR_TRIG; /*!< Alias for channel 11 READ_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH12_READ_ADDR; /*!< DMA Channel 12 Read Address pointer */
__IOM uint32_t CH12_WRITE_ADDR; /*!< DMA Channel 12 Write Address pointer */
__IOM uint32_t CH12_TRANS_COUNT; /*!< DMA Channel 12 Transfer Count */
__IOM uint32_t CH12_CTRL_TRIG; /*!< DMA Channel 12 Control and Status */
__IOM uint32_t CH12_AL1_CTRL; /*!< Alias for channel 12 CTRL register */
__IOM uint32_t CH12_AL1_READ_ADDR; /*!< Alias for channel 12 READ_ADDR register */
__IOM uint32_t CH12_AL1_WRITE_ADDR; /*!< Alias for channel 12 WRITE_ADDR register */
__IOM uint32_t CH12_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 12 TRANS_COUNT register This is a trigger
register (0xc). Writing a nonzero value will reload the
channel counter and start the channel. */
__IOM uint32_t CH12_AL2_CTRL; /*!< Alias for channel 12 CTRL register */
__IOM uint32_t CH12_AL2_TRANS_COUNT; /*!< Alias for channel 12 TRANS_COUNT register */
__IOM uint32_t CH12_AL2_READ_ADDR; /*!< Alias for channel 12 READ_ADDR register */
__IOM uint32_t CH12_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 12 WRITE_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH12_AL3_CTRL; /*!< Alias for channel 12 CTRL register */
__IOM uint32_t CH12_AL3_WRITE_ADDR; /*!< Alias for channel 12 WRITE_ADDR register */
__IOM uint32_t CH12_AL3_TRANS_COUNT; /*!< Alias for channel 12 TRANS_COUNT register */
__IOM uint32_t CH12_AL3_READ_ADDR_TRIG; /*!< Alias for channel 12 READ_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH13_READ_ADDR; /*!< DMA Channel 13 Read Address pointer */
__IOM uint32_t CH13_WRITE_ADDR; /*!< DMA Channel 13 Write Address pointer */
__IOM uint32_t CH13_TRANS_COUNT; /*!< DMA Channel 13 Transfer Count */
__IOM uint32_t CH13_CTRL_TRIG; /*!< DMA Channel 13 Control and Status */
__IOM uint32_t CH13_AL1_CTRL; /*!< Alias for channel 13 CTRL register */
__IOM uint32_t CH13_AL1_READ_ADDR; /*!< Alias for channel 13 READ_ADDR register */
__IOM uint32_t CH13_AL1_WRITE_ADDR; /*!< Alias for channel 13 WRITE_ADDR register */
__IOM uint32_t CH13_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 13 TRANS_COUNT register This is a trigger
register (0xc). Writing a nonzero value will reload the
channel counter and start the channel. */
__IOM uint32_t CH13_AL2_CTRL; /*!< Alias for channel 13 CTRL register */
__IOM uint32_t CH13_AL2_TRANS_COUNT; /*!< Alias for channel 13 TRANS_COUNT register */
__IOM uint32_t CH13_AL2_READ_ADDR; /*!< Alias for channel 13 READ_ADDR register */
__IOM uint32_t CH13_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 13 WRITE_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH13_AL3_CTRL; /*!< Alias for channel 13 CTRL register */
__IOM uint32_t CH13_AL3_WRITE_ADDR; /*!< Alias for channel 13 WRITE_ADDR register */
__IOM uint32_t CH13_AL3_TRANS_COUNT; /*!< Alias for channel 13 TRANS_COUNT register */
__IOM uint32_t CH13_AL3_READ_ADDR_TRIG; /*!< Alias for channel 13 READ_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH14_READ_ADDR; /*!< DMA Channel 14 Read Address pointer */
__IOM uint32_t CH14_WRITE_ADDR; /*!< DMA Channel 14 Write Address pointer */
__IOM uint32_t CH14_TRANS_COUNT; /*!< DMA Channel 14 Transfer Count */
__IOM uint32_t CH14_CTRL_TRIG; /*!< DMA Channel 14 Control and Status */
__IOM uint32_t CH14_AL1_CTRL; /*!< Alias for channel 14 CTRL register */
__IOM uint32_t CH14_AL1_READ_ADDR; /*!< Alias for channel 14 READ_ADDR register */
__IOM uint32_t CH14_AL1_WRITE_ADDR; /*!< Alias for channel 14 WRITE_ADDR register */
__IOM uint32_t CH14_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 14 TRANS_COUNT register This is a trigger
register (0xc). Writing a nonzero value will reload the
channel counter and start the channel. */
__IOM uint32_t CH14_AL2_CTRL; /*!< Alias for channel 14 CTRL register */
__IOM uint32_t CH14_AL2_TRANS_COUNT; /*!< Alias for channel 14 TRANS_COUNT register */
__IOM uint32_t CH14_AL2_READ_ADDR; /*!< Alias for channel 14 READ_ADDR register */
__IOM uint32_t CH14_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 14 WRITE_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH14_AL3_CTRL; /*!< Alias for channel 14 CTRL register */
__IOM uint32_t CH14_AL3_WRITE_ADDR; /*!< Alias for channel 14 WRITE_ADDR register */
__IOM uint32_t CH14_AL3_TRANS_COUNT; /*!< Alias for channel 14 TRANS_COUNT register */
__IOM uint32_t CH14_AL3_READ_ADDR_TRIG; /*!< Alias for channel 14 READ_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH15_READ_ADDR; /*!< DMA Channel 15 Read Address pointer */
__IOM uint32_t CH15_WRITE_ADDR; /*!< DMA Channel 15 Write Address pointer */
__IOM uint32_t CH15_TRANS_COUNT; /*!< DMA Channel 15 Transfer Count */
__IOM uint32_t CH15_CTRL_TRIG; /*!< DMA Channel 15 Control and Status */
__IOM uint32_t CH15_AL1_CTRL; /*!< Alias for channel 15 CTRL register */
__IOM uint32_t CH15_AL1_READ_ADDR; /*!< Alias for channel 15 READ_ADDR register */
__IOM uint32_t CH15_AL1_WRITE_ADDR; /*!< Alias for channel 15 WRITE_ADDR register */
__IOM uint32_t CH15_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 15 TRANS_COUNT register This is a trigger
register (0xc). Writing a nonzero value will reload the
channel counter and start the channel. */
__IOM uint32_t CH15_AL2_CTRL; /*!< Alias for channel 15 CTRL register */
__IOM uint32_t CH15_AL2_TRANS_COUNT; /*!< Alias for channel 15 TRANS_COUNT register */
__IOM uint32_t CH15_AL2_READ_ADDR; /*!< Alias for channel 15 READ_ADDR register */
__IOM uint32_t CH15_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 15 WRITE_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t CH15_AL3_CTRL; /*!< Alias for channel 15 CTRL register */
__IOM uint32_t CH15_AL3_WRITE_ADDR; /*!< Alias for channel 15 WRITE_ADDR register */
__IOM uint32_t CH15_AL3_TRANS_COUNT; /*!< Alias for channel 15 TRANS_COUNT register */
__IOM uint32_t CH15_AL3_READ_ADDR_TRIG; /*!< Alias for channel 15 READ_ADDR register This is a trigger register
(0xc). Writing a nonzero value will reload the channel
counter and start the channel. */
__IOM uint32_t INTR; /*!< Interrupt Status (raw) */
__IOM uint32_t INTE0; /*!< Interrupt Enables for IRQ 0 */
__IOM uint32_t INTF0; /*!< Force Interrupts */
__IOM uint32_t INTS0; /*!< Interrupt Status for IRQ 0 */
__IOM uint32_t INTR1; /*!< Interrupt Status (raw) */
__IOM uint32_t INTE1; /*!< Interrupt Enables for IRQ 1 */
__IOM uint32_t INTF1; /*!< Force Interrupts */
__IOM uint32_t INTS1; /*!< Interrupt Status for IRQ 1 */
__IOM uint32_t INTR2; /*!< Interrupt Status (raw) */
__IOM uint32_t INTE2; /*!< Interrupt Enables for IRQ 2 */
__IOM uint32_t INTF2; /*!< Force Interrupts */
__IOM uint32_t INTS2; /*!< Interrupt Status for IRQ 2 */
__IOM uint32_t INTR3; /*!< Interrupt Status (raw) */
__IOM uint32_t INTE3; /*!< Interrupt Enables for IRQ 3 */
__IOM uint32_t INTF3; /*!< Force Interrupts */
__IOM uint32_t INTS3; /*!< Interrupt Status for IRQ 3 */
__IOM uint32_t TIMER0; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ
assertions at a rate set by ((X/Y) * sys_clk). This equation
is evaluated every sys_clk cycles and therefore can only
generate TREQs at a rate of 1 per sys_clk (i.e. permanent
TREQ) or less. */
__IOM uint32_t TIMER1; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ
assertions at a rate set by ((X/Y) * sys_clk). This equation
is evaluated every sys_clk cycles and therefore can only
generate TREQs at a rate of 1 per sys_clk (i.e. permanent
TREQ) or less. */
__IOM uint32_t TIMER2; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ
assertions at a rate set by ((X/Y) * sys_clk). This equation
is evaluated every sys_clk cycles and therefore can only
generate TREQs at a rate of 1 per sys_clk (i.e. permanent
TREQ) or less. */
__IOM uint32_t TIMER3; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ
assertions at a rate set by ((X/Y) * sys_clk). This equation
is evaluated every sys_clk cycles and therefore can only
generate TREQs at a rate of 1 per sys_clk (i.e. permanent
TREQ) or less. */
__IOM uint32_t MULTI_CHAN_TRIGGER; /*!< Trigger one or more channels simultaneously */
__IOM uint32_t SNIFF_CTRL; /*!< Sniffer Control */
__IOM uint32_t SNIFF_DATA; /*!< Data accumulator for sniff hardware */
__IM uint32_t RESERVED;
__IOM uint32_t FIFO_LEVELS; /*!< Debug RAF, WAF, TDF levels */
__IOM uint32_t CHAN_ABORT; /*!< Abort an in-progress transfer sequence on one or more channels */
__IOM uint32_t N_CHANNELS; /*!< The number of channels this DMA instance is equipped with. This
DMA supports up to 16 hardware channels, but can be configured
with as few as one, to minimise silicon area. */
__IM uint32_t RESERVED1[5];
__IOM uint32_t SECCFG_CH0; /*!< Security configuration for channel 0. Control whether this channel
performs Secure/Non-secure and Privileged/Unprivileged
bus accesses. If this channel generates bus accesses of
some security level, an access of at least that level (in
the order S+P > S+U > NS+P > NS+U) is required to program,
trigger, abort, check the status of, interrupt on or acknowledge
the interrupt of this channel. This register automatically
locks down (becomes read-only) once software starts to
configure the channel. This register is world-readable,
but is writable only from a Secure, Privileged context. */
__IOM uint32_t SECCFG_CH1; /*!< Security configuration for channel 1. Control whether this channel
performs Secure/Non-secure and Privileged/Unprivileged
bus accesses. If this channel generates bus accesses of
some security level, an access of at least that level (in
the order S+P > S+U > NS+P > NS+U) is required to program,
trigger, abort, check the status of, interrupt on or acknowledge
the interrupt of this channel. This register automatically
locks down (becomes read-only) once software starts to
configure the channel. This register is world-readable,
but is writable only from a Secure, Privileged context. */
__IOM uint32_t SECCFG_CH2; /*!< Security configuration for channel 2. Control whether this channel
performs Secure/Non-secure and Privileged/Unprivileged
bus accesses. If this channel generates bus accesses of
some security level, an access of at least that level (in
the order S+P > S+U > NS+P > NS+U) is required to program,
trigger, abort, check the status of, interrupt on or acknowledge
the interrupt of this channel. This register automatically
locks down (becomes read-only) once software starts to
configure the channel. This register is world-readable,
but is writable only from a Secure, Privileged context. */
__IOM uint32_t SECCFG_CH3; /*!< Security configuration for channel 3. Control whether this channel
performs Secure/Non-secure and Privileged/Unprivileged
bus accesses. If this channel generates bus accesses of
some security level, an access of at least that level (in
the order S+P > S+U > NS+P > NS+U) is required to program,
trigger, abort, check the status of, interrupt on or acknowledge
the interrupt of this channel. This register automatically
locks down (becomes read-only) once software starts to
configure the channel. This register is world-readable,
but is writable only from a Secure, Privileged context. */
__IOM uint32_t SECCFG_CH4; /*!< Security configuration for channel 4. Control whether this channel
performs Secure/Non-secure and Privileged/Unprivileged
bus accesses. If this channel generates bus accesses of
some security level, an access of at least that level (in
the order S+P > S+U > NS+P > NS+U) is required to program,
trigger, abort, check the status of, interrupt on or acknowledge
the interrupt of this channel. This register automatically
locks down (becomes read-only) once software starts to
configure the channel. This register is world-readable,
but is writable only from a Secure, Privileged context. */
__IOM uint32_t SECCFG_CH5; /*!< Security configuration for channel 5. Control whether this channel
performs Secure/Non-secure and Privileged/Unprivileged
bus accesses. If this channel generates bus accesses of
some security level, an access of at least that level (in
the order S+P > S+U > NS+P > NS+U) is required to program,
trigger, abort, check the status of, interrupt on or acknowledge
the interrupt of this channel. This register automatically
locks down (becomes read-only) once software starts to
configure the channel. This register is world-readable,
but is writable only from a Secure, Privileged context. */
__IOM uint32_t SECCFG_CH6; /*!< Security configuration for channel 6. Control whether this channel
performs Secure/Non-secure and Privileged/Unprivileged
bus accesses. If this channel generates bus accesses of
some security level, an access of at least that level (in
the order S+P > S+U > NS+P > NS+U) is required to program,
trigger, abort, check the status of, interrupt on or acknowledge
the interrupt of this channel. This register automatically
locks down (becomes read-only) once software starts to
configure the channel. This register is world-readable,
but is writable only from a Secure, Privileged context. */
__IOM uint32_t SECCFG_CH7; /*!< Security configuration for channel 7. Control whether this channel
performs Secure/Non-secure and Privileged/Unprivileged
bus accesses. If this channel generates bus accesses of
some security level, an access of at least that level (in
the order S+P > S+U > NS+P > NS+U) is required to program,
trigger, abort, check the status of, interrupt on or acknowledge
the interrupt of this channel. This register automatically
locks down (becomes read-only) once software starts to
configure the channel. This register is world-readable,
but is writable only from a Secure, Privileged context. */
__IOM uint32_t SECCFG_CH8; /*!< Security configuration for channel 8. Control whether this channel
performs Secure/Non-secure and Privileged/Unprivileged
bus accesses. If this channel generates bus accesses of
some security level, an access of at least that level (in
the order S+P > S+U > NS+P > NS+U) is required to program,
trigger, abort, check the status of, interrupt on or acknowledge
the interrupt of this channel. This register automatically
locks down (becomes read-only) once software starts to
configure the channel. This register is world-readable,
but is writable only from a Secure, Privileged context. */
__IOM uint32_t SECCFG_CH9; /*!< Security configuration for channel 9. Control whether this channel
performs Secure/Non-secure and Privileged/Unprivileged
bus accesses. If this channel generates bus accesses of
some security level, an access of at least that level (in
the order S+P > S+U > NS+P > NS+U) is required to program,
trigger, abort, check the status of, interrupt on or acknowledge
the interrupt of this channel. This register automatically
locks down (becomes read-only) once software starts to
configure the channel. This register is world-readable,
but is writable only from a Secure, Privileged context. */
__IOM uint32_t SECCFG_CH10; /*!< Security configuration for channel 10. Control whether this
channel performs Secure/Non-secure and Privileged/Unprivileged
bus accesses. If this channel generates bus accesses of
some security level, an access of at least that level (in
the order S+P > S+U > NS+P > NS+U) is required to program,
trigger, abort, check the status of, interrupt on or acknowledge
the interrupt of this channel. This register automatically
locks down (becomes read-only) once software starts to
configure the channel. This register is world-readable,
but is writable only from a Secure, Privileged context. */
__IOM uint32_t SECCFG_CH11; /*!< Security configuration for channel 11. Control whether this
channel performs Secure/Non-secure and Privileged/Unprivileged
bus accesses. If this channel generates bus accesses of
some security level, an access of at least that level (in
the order S+P > S+U > NS+P > NS+U) is required to program,
trigger, abort, check the status of, interrupt on or acknowledge
the interrupt of this channel. This register automatically
locks down (becomes read-only) once software starts to
configure the channel. This register is world-readable,
but is writable only from a Secure, Privileged context. */
__IOM uint32_t SECCFG_CH12; /*!< Security configuration for channel 12. Control whether this