/*
 * Copyright (c) 2017, NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* SoC level DTS fixup file */

#define CONFIG_NUM_IRQ_PRIO_BITS		ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS

#define CONFIG_MCUX_CCM_BASE_ADDRESS		NXP_IMX_CCM_400FC000_BASE_ADDRESS
#define CONFIG_MCUX_CCM_NAME			NXP_IMX_CCM_400FC000_LABEL

#define CONFIG_MCUX_IGPIO_1_BASE_ADDRESS	NXP_IMX_GPIO_401B8000_BASE_ADDRESS
#define CONFIG_MCUX_IGPIO_1_NAME		NXP_IMX_GPIO_401B8000_LABEL
#define CONFIG_MCUX_IGPIO_1_IRQ_0		NXP_IMX_GPIO_401B8000_IRQ_0
#define CONFIG_MCUX_IGPIO_1_IRQ_0_PRI		NXP_IMX_GPIO_401B8000_IRQ_0_PRIORITY
#define CONFIG_MCUX_IGPIO_1_IRQ_1		NXP_IMX_GPIO_401B8000_IRQ_1
#define CONFIG_MCUX_IGPIO_1_IRQ_1_PRI		NXP_IMX_GPIO_401B8000_IRQ_1_PRIORITY

#define CONFIG_MCUX_IGPIO_5_BASE_ADDRESS	NXP_IMX_GPIO_400C0000_BASE_ADDRESS
#define CONFIG_MCUX_IGPIO_5_NAME		NXP_IMX_GPIO_400C0000_LABEL
#define CONFIG_MCUX_IGPIO_5_IRQ_0		NXP_IMX_GPIO_400C0000_IRQ_0
#define CONFIG_MCUX_IGPIO_5_IRQ_0_PRI		NXP_IMX_GPIO_400C0000_IRQ_0_PRIORITY
#define CONFIG_MCUX_IGPIO_5_IRQ_1		NXP_IMX_GPIO_400C0000_IRQ_1
#define CONFIG_MCUX_IGPIO_5_IRQ_1_PRI		NXP_IMX_GPIO_400C0000_IRQ_1_PRIORITY

#define CONFIG_UART_MCUX_LPUART_1_BASE_ADDRESS	NXP_KINETIS_LPUART_40184000_BASE_ADDRESS
#define CONFIG_UART_MCUX_LPUART_1_NAME		NXP_KINETIS_LPUART_40184000_LABEL
#define CONFIG_UART_MCUX_LPUART_1_IRQ		NXP_KINETIS_LPUART_40184000_IRQ_0
#define CONFIG_UART_MCUX_LPUART_1_IRQ_PRI	NXP_KINETIS_LPUART_40184000_IRQ_0_PRIORITY
#define CONFIG_UART_MCUX_LPUART_1_BAUD_RATE	NXP_KINETIS_LPUART_40184000_CURRENT_SPEED
#define CONFIG_UART_MCUX_LPUART_1_CLOCK_NAME	NXP_IMX_CCM_400FC000_LABEL
#define CONFIG_UART_MCUX_LPUART_1_CLOCK_SUBSYS	NXP_KINETIS_LPUART_40184000_CLOCK_NAME

/* End of SoC Level DTS fixup file */