/*
 * SPDX-License-Identifier: Apache-2.0
 *
 * GPIO & I/O controller registers and bit offsets for the
 * CC2650 System on Chip.
 */


#ifndef _CC2650_IOC_H_
#define _CC2650_IOC_H_

/* Registers */

enum CC2650_IOC_Registers {
	CC2650_IOC_IOCFG0 = 0x0,
	CC2650_IOC_IOCFG1 = 0x4,
	CC2650_IOC_IOCFG2 = 0x8,
	CC2650_IOC_IOCFG3 = 0xC,
	CC2650_IOC_IOCFG4 = 0x10,
	CC2650_IOC_IOCFG5 = 0x14,
	CC2650_IOC_IOCFG6 = 0x18,
	CC2650_IOC_IOCFG7 = 0x1C,
	CC2650_IOC_IOCFG8 = 0x20,
	CC2650_IOC_IOCFG9 = 0x24,
	CC2650_IOC_IOCFG10 = 0x28,
	CC2650_IOC_IOCFG11 = 0x2C,
	CC2650_IOC_IOCFG12 = 0x30,
	CC2650_IOC_IOCFG13 = 0x34,
	CC2650_IOC_IOCFG14 = 0x38,
	CC2650_IOC_IOCFG15 = 0x3C,
	CC2650_IOC_IOCFG16 = 0x40,
	CC2650_IOC_IOCFG17 = 0x44,
	CC2650_IOC_IOCFG18 = 0x48,
	CC2650_IOC_IOCFG19 = 0x4C,
	CC2650_IOC_IOCFG20 = 0x50,
	CC2650_IOC_IOCFG21 = 0x54,
	CC2650_IOC_IOCFG22 = 0x58,
	CC2650_IOC_IOCFG23 = 0x5C,
	CC2650_IOC_IOCFG24 = 0x60,
	CC2650_IOC_IOCFG25 = 0x64,
	CC2650_IOC_IOCFG26 = 0x68,
	CC2650_IOC_IOCFG27 = 0x6C,
	CC2650_IOC_IOCFG28 = 0x70,
	CC2650_IOC_IOCFG29 = 0x74,
	CC2650_IOC_IOCFG30 = 0x78,
	CC2650_IOC_IOCFG31 = 0x7C
};


/* Register-specific bits */

/* I/O Controller */
/* All IOCFGx registers are the same. */
enum CC2650_IOC_IOCFGX_POS {
	CC2650_IOC_IOCFGX_PORT_ID_POS		= 0,
	CC2650_IOC_IOCFGX_IOSTR_POS		= 8,
	CC2650_IOC_IOCFGX_IOCURR_POS		= 10,
	CC2650_IOC_IOCFGX_SLEW_RED_POS		= 12,
	CC2650_IOC_IOCFGX_PULL_CTL_POS		= 13,
	CC2650_IOC_IOCFGX_EDGE_DET_POS		= 16,
	CC2650_IOC_IOCFGX_EDGE_IRQ_EN_POS	= 18,
	CC2650_IOC_IOCFGX_IOMODE_POS		= 24,
	CC2650_IOC_IOCFGX_WU_CFG_POS		= 27,
	CC2650_IOC_IOCFGX_IE_POS		= 29,
	CC2650_IOC_IOCFGX_HYST_EN_POS		= 30
};

enum CC2650_IOC_IOCFGX_MASK {
	CC2650_IOC_IOCFGX_PORT_ID_MASK		= 0x0000003F,
	CC2650_IOC_IOCFGX_IOSTR_MASK		= 0x00000300,
	CC2650_IOC_IOCFGX_IOCURR_MASK		= 0x00000C00,
	CC2650_IOC_IOCFGX_SLEW_RED_MASK		= 0x00001000,
	CC2650_IOC_IOCFGX_PULL_CTL_MASK		= 0x00006000,
	CC2650_IOC_IOCFGX_EDGE_DET_MASK		= 0x00030000,
	CC2650_IOC_IOCFGX_EDGE_IRQ_EN_MASK	= 0x00040000,
	CC2650_IOC_IOCFGX_IOMODE_MASK		= 0x07000000,
	CC2650_IOC_IOCFGX_WU_CFG_MASK		= 0x18000000,
	CC2650_IOC_IOCFGX_IE_MASK		= 0x20000000,
	CC2650_IOC_IOCFGX_HYST_EN_MASK		= 0x40000000
};


/* Port-IDs available */
enum CC2650_IOC_PORTID {
	CC2650_IOC_GPIO =
		0 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_AON_SCS =
		1 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_AON_SCK =
		2 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_AON_SDI =
		3 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_AON_SDO =
		4 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	/* Reserved */
	CC2650_IOC_AON_CLK32K =
		7 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_AUX_IO =
		8 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_SSI0_RX =
		9 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_SSI0_TX =
		10 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_SSI0_FSS =
		11 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_SSI0_CLK =
		12 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_I2C_MSSDA =
		13 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_I2C_MSSCL =
		14 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_UART0_RX =
		15 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_UART0_TX =
		16 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_UART0_CTS =
		17 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_UART0_RTS =
		18 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	/* Reserved */
	CC2650_IOC_MCU_GPTM_GPTM0 =
		23 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_GPTM_GPTM1 =
		24 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_GPTM_GPTM2 =
		25 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_GPTM_GPTM3 =
		26 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_GPTM_GPTM4 =
		27 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_GPTM_GPTM5 =
		28 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_GPTM_GPTM6 =
		29 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_GPTM_GPTM7 =
		30 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	/* Reserved */
	CC2650_IOC_MCU_CM3_SWV =
		32 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_SSI1_RX =
		33 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_SSI1_TX =
		34 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_SSI1_FSS =
		35 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_SSI1_CLK =
		36 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_I2S_AD0 =
		37 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_I2S_AD1 =
		38 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_I2S_WCLK =
		39 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_I2S_BCLK =
		40 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_MCU_I2S_MCLK =
		41 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	/* Reserved */
	CC2650_IOC_RFC_GP0 =
		47 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_RFC_GP1 =
		48 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_RFC_GP2 =
		49 << CC2650_IOC_IOCFGX_PORT_ID_POS,
	CC2650_IOC_RFC_GP3 =
		50 << CC2650_IOC_IOCFGX_PORT_ID_POS
	/* Reserved */
};

/* IOSTR (drive strength) values available */
enum CC2650_IOC_IOSTR {
	CC2650_IOC_AUTO_DRIVE_STRENGTH =
		0 << CC2650_IOC_IOCFGX_IOSTR_POS,
	CC2650_IOC_MIN_DRIVE_STRENGTH =
		1 << CC2650_IOC_IOCFGX_IOSTR_POS,
	CC2650_IOC_MED_DRIVE_STRENGTH =
		2 << CC2650_IOC_IOCFGX_IOSTR_POS,
	CC2650_IOC_MAX_DRIVE_STRENGTH =
		3 << CC2650_IOC_IOCFGX_IOSTR_POS
};

/* IOCURR (IO current) values available */
enum CC2650_IOC_IOCURR {
	CC2650_IOC_LOW_CURRENT_MODE =
		0 << CC2650_IOC_IOCFGX_IOCURR_POS,
	CC2650_IOC_HIGH_CURRENT_MODE =
		1 << CC2650_IOC_IOCFGX_IOCURR_POS,
	CC2650_IOC_EXTENDED_CURRENT_MODE =
		2 << CC2650_IOC_IOCFGX_IOCURR_POS
};

/* SLEW_RED (slew rate) values available */
enum CC2650_IOC_SLEW_RED {
	CC2650_IOC_NORMAL_SLEW_RATE =
		0 << CC2650_IOC_IOCFGX_SLEW_RED_POS,
	CC2650_IOC_REDUCED_SLEW_RATE =
		1 << CC2650_IOC_IOCFGX_SLEW_RED_POS
};

/* PULL_CTL (pull-* modes) values available */
enum CC2650_IOC_PULL_CTL {
	CC2650_IOC_PULL_DOWN =
		1 << CC2650_IOC_IOCFGX_PULL_CTL_POS,
	CC2650_IOC_PULL_UP =
		2 << CC2650_IOC_IOCFGX_PULL_CTL_POS,
	CC2650_IOC_NO_PULL =
		3 << CC2650_IOC_IOCFGX_PULL_CTL_POS
};

/* EDGE_DET (edge detection) values available */
enum CC2650_IOC_EDGE_DET {
	CC2650_IOC_NO_EDGE_DET =
		0 << CC2650_IOC_IOCFGX_EDGE_DET_POS,
	CC2650_IOC_NEG_EDGE_DET =
		1 << CC2650_IOC_IOCFGX_EDGE_DET_POS,
	CC2650_IOC_POS_EDGE_DET =
		2 << CC2650_IOC_IOCFGX_EDGE_DET_POS,
	CC2650_IOC_NEG_AND_POS_EDGE_DET =
		3 << CC2650_IOC_IOCFGX_EDGE_DET_POS
};

/* IOMODE values available */
enum CC2650_IOC_IOMODE {
	CC2650_IOC_NORMAL_IO =
		0 << CC2650_IOC_IOCFGX_IOMODE_POS,
	CC2650_IOC_INVERTED_IO =
		1 << CC2650_IOC_IOCFGX_IOMODE_POS,
	CC2650_IOC_OPEN_DRAIN_IO =
		4 << CC2650_IOC_IOCFGX_IOMODE_POS,
	CC2650_IOC_OPEN_DRAIN_INVERTED_IO =
		5 << CC2650_IOC_IOCFGX_IOMODE_POS,
	CC2650_IOC_OPEN_SOURCE_IO =
		6 << CC2650_IOC_IOCFGX_IOMODE_POS,
	CC2650_IOC_OPEN_SOURCE_INVERTED_IO =
		7 << CC2650_IOC_IOCFGX_IOMODE_POS
};

/* WU_CFG (Wake-up control) values available */
enum CC2650_IOC_WU_CFG {
/* Values' meaning change with PORT_ID, so here we only
 * give very generic names...
 */
	CC2650_IOC_WAKE_UP_0 =
		0 << CC2650_IOC_IOCFGX_WU_CFG_POS,
	CC2650_IOC_WAKE_UP_1 =
		1 << CC2650_IOC_IOCFGX_WU_CFG_POS,
	CC2650_IOC_WAKE_UP_2 =
		2 << CC2650_IOC_IOCFGX_WU_CFG_POS,
	CC2650_IOC_WAKE_UP_3 =
		3 << CC2650_IOC_IOCFGX_WU_CFG_POS
};

/* IE (Input control) values available */
enum CC2650_IOC_IE {
	CC2650_IOC_INPUT_DISABLED =
		0 << CC2650_IOC_IOCFGX_IE_POS,
	CC2650_IOC_INPUT_ENABLED =
		1 << CC2650_IOC_IOCFGX_IE_POS
};

/* HYST_EN (Hysteresis control) values available */
enum CC2650_IOC_HYST_EN {
	CC2650_IOC_HYSTERESIS_DISABLED =
		0 << CC2650_IOC_IOCFGX_HYST_EN_POS,
	CC2650_IOC_HYSTERESIS_ENABLED =
		1 << CC2650_IOC_IOCFGX_HYST_EN_POS
};

#endif /* _CC2650_IOC_H_ */