# Kconfig - STM32L4 MCU clock control driver config
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 BayLibre, SAS
#
# SPDX-License-Identifier: Apache-2.0
#

if SOC_SERIES_STM32L4X

menuconfig CLOCK_CONTROL_STM32L4X
	bool
	prompt "STM32L4x Reset & Clock Control"
	depends on CLOCK_CONTROL && SOC_SERIES_STM32L4X
	default y if SOC_SERIES_STM32L4X
	help
	  Enable driver for Reset & Clock Control subsystem found
	  in STM32L4 family of MCUs

config CLOCK_CONTROL_STM32L4X_DEVICE_INIT_PRIORITY
	int "Clock Control Device Priority"
	default 1
	depends on CLOCK_CONTROL_STM32L4X
	help
	  This option controls the priority of clock control
	  device initialization. Higher priority ensures that the device
	  is initialized earlier in the startup cycle. If unsure, leave
	  at default value 1

choice
prompt "STM32L4X System Clock Source"
depends on CLOCK_CONTROL_STM32L4X
default CLOCK_STM32L4X_SYSCLK_SRC_PLL

config CLOCK_STM32L4X_SYSCLK_SRC_HSE
	bool "HSE"
	help
	  Use HSE as source of SYSCLK

config CLOCK_STM32L4X_SYSCLK_SRC_PLL
	bool "PLL"
	help
	  Use PLL as source of SYSCLK

endchoice

choice
prompt "STM32L4X PLL Clock Source"
depends on CLOCK_CONTROL_STM32L4X && CLOCK_STM32L4X_SYSCLK_SRC_PLL
default CLOCK_STM32L4X_PLL_SRC_HSI

config CLOCK_STM32L4X_PLL_SRC_MSI
	bool "MSI"
	help
	  Use MSI as source of PLL

config CLOCK_STM32L4X_PLL_SRC_HSI
	bool "HSI"
	help
	  Use HSI as source of PLL

endchoice

config CLOCK_STM32L4X_HSE_BYPASS
	bool "HSE bypass"
	depends on CLOCK_CONTROL_STM32L4X && CLOCK_STM32L4X_SYSCLK_SRC_HSE
	help
	  Enable this option to bypass external high-speed clock (HSE).

config CLOCK_STM32L4X_PLL_DIVISOR
	int "PLL divisor"
	depends on CLOCK_CONTROL_STM32L4X && CLOCK_STM32L4X_SYSCLK_SRC_PLL
	default 1
	range 1 8
	help
	  PLL divisor, allowed values: 1-8. With this ensure that the PLL
	  VCO input frequency ranges from 4 to 16MHz.

config CLOCK_STM32L4X_PLL_MULTIPLIER
	int "PLL multiplier"
	depends on CLOCK_CONTROL_STM32L4X && CLOCK_STM32L4X_SYSCLK_SRC_PLL
	default 20
	range 8 86
	help
	  PLL multiplier, allowed values: 2-16. PLL output must not
	  exceed 344MHz.

config CLOCK_STM32L4X_PLL_P_DIVISOR
	int "PLL P Divisor"
	depends on CLOCK_CONTROL_STM32L4X
	default 7
	range 0 17
	help
	  PLL P Output divisor, allowed values: 0, 7, 17.

config CLOCK_STM32L4X_PLL_Q_DIVISOR
	int "PLL Q Divisor"
	depends on CLOCK_CONTROL_STM32L4X
	default 2
	range 0 8
	help
	  PLL Q Output divisor, allowed values: 0, 2, 4, 6, 8.

config CLOCK_STM32L4X_PLL_R_DIVISOR
	int "PLL R Divisor"
	depends on CLOCK_CONTROL_STM32L4X
	default 4
	range 0 8
	help
	  PLL R Output divisor, allowed values: 0, 2, 4, 6, 8.

config CLOCK_STM32L4X_AHB_PRESCALER
	int "AHB prescaler"
	depends on CLOCK_CONTROL_STM32L4X
	default 0
	range 0 512
	help
	  AHB prescaler, allowed values: 0, 2, 4, 8, 16, 64, 128,
	  256, 512.

config CLOCK_STM32L4X_APB1_PRESCALER
	int "APB1 prescaler"
	depends on CLOCK_CONTROL_STM32L4X
	default 0
	range 0 16
	help
	  APB1 Low speed clock (PCLK1) prescaler, allowed values:
	  0, 2, 4, 8, 16

config CLOCK_STM32L4X_APB2_PRESCALER
	int "APB2 prescaler"
	depends on CLOCK_CONTROL_STM32L4X
	default 0
	range 0 16
	help
	  APB2 High speed clock (PCLK2) prescaler, allowed values:
	  0, 2, 4, 8, 16

endif