tree b456a563b80af871c28b807b6e3c25df354f8aab
parent ae082064ffa5746ed4ca9139420199afaaa2e362
author Evgeniy Paltsev <PaltsevEvgeniy@gmail.com> 1715701142 +0100
committer Carles Cufí <carles.cufi@nordicsemi.no> 1715942452 +0200

ARC: nSIM: west: launch cores in direct order for simulation run

We've reversed core launch order to workaround issue of
ARConnect initialization interfere with secondary cores
startup (we don't want to workaround it in runtime as it's
only possible in case of debug session).

However it bring us new issues with the simulation run:
 - mismatch arcnum (core ID) with ARConnect ID
 - mismatch arcnum (core ID) with CPU name in nSIM instruction traces

To avoid these issues let's use direct core order for simulation
runs.

Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>