/*
 * Copyright (c) 2023 STMicroelectronics
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <st/f0/stm32f031.dtsi>

/ {
	soc {
		compatible = "st,stm32f042", "st,stm32f0", "simple-bus";

		clocks {
			clk_hsi48: clk-hsi48 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <DT_FREQ_M(48)>;
				status = "disabled";
			};
		};

		usart2: serial@40004400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
			resets = <&rctl STM32_RESET(APB1, 17U)>;
			interrupts = <28 0>;
			status = "disabled";
		};

		spi2: spi@40003800 {
			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
			interrupts = <26 3>;
			status = "disabled";
		};

		can1: can@40006400 {
			compatible = "st,stm32-bxcan";
			reg = <0x40006400 0x400>;
			interrupts = <30 0>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
			status = "disabled";
		};

		timers15: timers@40014000 {
			compatible = "st,stm32-timers";
			reg = <0x40014000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
			resets = <&rctl STM32_RESET(APB2, 16U)>;
			interrupts = <20 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		usb: usb@40005c00 {
			compatible = "st,stm32-usb";
			reg = <0x40005c00 0x400>;
			interrupts = <31 0>;
			interrupt-names = "usb";
			num-bidir-endpoints = <8>;
			ram-size = <1024>;
			phys = <&usb_fs_phy>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>,
				 <&rcc STM32_SRC_PLLCLK USB_SEL(1)>;
			status = "disabled";
		};
	};

	usb_fs_phy: usbphy {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};
};