/*
 * Copyright (c) 2021 The Chromium OS Authors
 * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */


#include <arm/armv7-m.dtsi>
#include <zephyr/dt-bindings/clock/stm32g4_clock.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
#include <zephyr/dt-bindings/dma/stm32_dma.h>
#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
#include <zephyr/dt-bindings/reset/stm32g4_l4_5_reset.h>
#include <freq.h>

/ {
	chosen {
		zephyr,entropy = &rng;
		zephyr,flash-controller = &flash;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m4f";
			reg = <0>;
			cpu-power-states = <&stop0 &stop1>;
		};

		power-states {
			stop0: state0 {
					compatible = "zephyr,power-state";
					power-state-name = "suspend-to-idle";
					substate-id = <1>;
					min-residency-us = <20>;
				};
			stop1: state1 {
					compatible = "zephyr,power-state";
					power-state-name = "suspend-to-idle";
					substate-id = <2>;
					min-residency-us = <100>;
				};
		};
	};

	sram0: memory@20000000 {
		compatible = "mmio-sram";
	};

	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "st,stm32-hse-clock";
			status = "disabled";
		};

		clk_hsi: clk-hsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_M(16)>;
			status = "disabled";
		};

		clk_hsi48: clk-hsi48 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_M(48)>;
			status = "disabled";
		};

		clk_lse: clk-lse {
			#clock-cells = <0>;
			compatible = "st,stm32-lse-clock";
			clock-frequency = <32768>;
			driving-capability = <0>;
			status = "disabled";
		};

		clk_lsi: clk-lsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_K(32)>;
			status = "disabled";
		};

		pll: pll {
			#clock-cells = <0>;
			compatible = "st,stm32g4-pll-clock";
			status = "disabled";
		};
	};

	soc {
		/*
		 * Both adc instances cannot be used in parallel right now.
		 */
		adc1: adc@50000000 {
			compatible = "st,stm32-adc";
			reg = <0x50000000 0x100>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
			interrupts = <18 0>;
			status = "disabled";
			#io-channel-cells = <1>;
			resolutions = <STM32_ADC_RES(12, 0x00)
				       STM32_ADC_RES(10, 0x01)
				       STM32_ADC_RES(8, 0x02)
				       STM32_ADC_RES(6, 0x03)>;
			sampling-times = <3 7 13 25 48 93 248 641>;
			st,adc-sequencer = <FULLY_CONFIGURABLE>;
		};

		adc2: adc@50000100 {
			compatible = "st,stm32-adc";
			reg = <0x50000100 0x100>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
			interrupts = <18 0>;
			status = "disabled";
			#io-channel-cells = <1>;
			resolutions = <STM32_ADC_RES(12, 0x00)
				       STM32_ADC_RES(10, 0x01)
				       STM32_ADC_RES(8, 0x02)
				       STM32_ADC_RES(6, 0x03)>;
			sampling-times = <3 7 13 25 48 93 248 641>;
			st,adc-sequencer = <FULLY_CONFIGURABLE>;
		};

		dac1: dac@50000800 {
			compatible = "st,stm32-dac";
			reg = <0x50000800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
			status = "disabled";
			#io-channel-cells = <1>;
		};

		dac3: dac@50001000 {
			compatible = "st,stm32-dac";
			reg = <0x50001000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>;
			status = "disabled";
			#io-channel-cells = <1>;
		};

		flash: flash-controller@40022000 {
			compatible = "st,stm32-flash-controller", "st,stm32g4-flash-controller";
			reg = <0x40022000 0x400>;
			interrupts = <3 0>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;

			#address-cells = <1>;
			#size-cells = <1>;

			flash0: flash@8000000 {
				compatible = "st,stm32-nv-flash", "soc-nv-flash";

				write-block-size = <8>;
				erase-block-size = <2048>;
				/* maximum erase time(ms) for a 2K sector */
				max-erase-time = <25>;
			};
		};

		rcc: rcc@40021000 {
			compatible = "st,stm32-rcc";
			#clock-cells = <2>;
			reg = <0x40021000 0x400>;
			undershoot-prevention;

			rctl: reset-controller {
				compatible = "st,stm32-rcc-rctl";
				#reset-cells = <1>;
			};
		};

		exti: interrupt-controller@40010400 {
			compatible = "st,stm32-exti";
			interrupt-controller;
			#interrupt-cells = <1>;
			#address-cells = <1>;
			reg = <0x40010400 0x400>;
			num-lines = <16>;
			interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
				     <10 0>, <23 0>, <40 0>;
			interrupt-names = "line0", "line1", "line2-TSC", "line3",
					  "line4", "line5-9", "line10-15";
			line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
				      <4 1>, <5 5>, <10 6>;
		};

		pinctrl: pin-controller@48000000 {
			compatible = "st,stm32-pinctrl";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x48000000 0x2000>;

			gpioa: gpio@48000000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x48000000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
			};

			gpiob: gpio@48000400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x48000400 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
			};

			gpioc: gpio@48000800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x48000800 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
			};

			gpiod: gpio@48000c00 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x48000c00 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
			};

			gpioe: gpio@48001000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x48001000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
			};

			gpiof: gpio@48001400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x48001400 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
			};

			gpiog: gpio@48001800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x48001800 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
			};
		};

		usart1: serial@40013800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40013800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
			resets = <&rctl STM32_RESET(APB2, 14U)>;
			interrupts = <37 0>;
			status = "disabled";
		};

		usart2: serial@40004400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
			resets = <&rctl STM32_RESET(APB1L, 17U)>;
			interrupts = <38 0>;
			status = "disabled";
		};

		usart3: serial@40004800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
			resets = <&rctl STM32_RESET(APB1L, 18U)>;
			interrupts = <39 0>;
			status = "disabled";
		};

		uart4: serial@40004c00 {
			compatible = "st,stm32-uart";
			reg = <0x40004c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
			resets = <&rctl STM32_RESET(APB1L, 19U)>;
			interrupts = <52 0>;
			status = "disabled";
		};

		lpuart1: serial@40008000 {
			compatible = "st,stm32-lpuart", "st,stm32-uart";
			reg = <0x40008000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
			resets = <&rctl STM32_RESET(APB1H, 0U)>;
			interrupts = <91 0>;
			status = "disabled";
		};

		iwdg: watchdog@40003000 {
			compatible = "st,stm32-watchdog";
			reg = <0x40003000 0x400>;
			status = "disabled";
		};

		wwdg: watchdog@40002c00 {
			compatible = "st,stm32-window-watchdog";
			reg = <0x40002C00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
			interrupts = <0 7>;
			status = "disabled";
		};

		i2c1: i2c@40005400 {
			compatible = "st,stm32-i2c-v2";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40005400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
			interrupts = <31 0>, <32 0>;
			interrupt-names = "event", "error";
			status = "disabled";
		};

		i2c2: i2c@40005800 {
			compatible = "st,stm32-i2c-v2";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40005800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
			interrupts = <33 0>, <34 0>;
			interrupt-names = "event", "error";
			status = "disabled";
		};

		i2c3: i2c@40007800 {
			compatible = "st,stm32-i2c-v2";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40007800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
			interrupts = <92 0>, <93 0>;
			interrupt-names = "event", "error";
			status = "disabled";
		};

		spi1: spi@40013000 {
			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40013000 0x400>;
			interrupts = <35 5>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
			status = "disabled";
		};

		spi2: spi@40003800 {
			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
			interrupts = <36 5>;
			status = "disabled";
		};

		spi3: spi@40003c00 {
			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
			interrupts = <51 5>;
			status = "disabled";
		};

		fdcan1: can@40006400 {
			compatible = "st,stm32-fdcan";
			reg = <0x40006400 0x400>, <0x4000a400 0x350>;
			reg-names = "m_can", "message_ram";
			interrupts = <21 0>, <22 0>;
			interrupt-names = "int0", "int1";
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
			bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
			status = "disabled";
		};

		lptim1: timers@40007c00 {
			compatible = "st,stm32-lptim";
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40007c00 0x400>;
			interrupts = <49 1>;
			interrupt-names = "wakeup";
			status = "disabled";
		};

		timers1: timers@40012c00 {
			compatible = "st,stm32-timers";
			reg = <0x40012c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
			resets = <&rctl STM32_RESET(APB2, 11U)>;
			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
			interrupt-names = "brk", "up", "trgcom", "cc";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timers2: timers@40000000 {
			compatible = "st,stm32-timers";
			reg = <0x40000000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
			resets = <&rctl STM32_RESET(APB1L, 0U)>;
			interrupts = <28 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timers3: timers@40000400 {
			compatible = "st,stm32-timers";
			reg = <0x40000400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
			resets = <&rctl STM32_RESET(APB1L, 1U)>;
			interrupts = <29 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timers4: timers@40000800 {
			compatible = "st,stm32-timers";
			reg = <0x40000800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
			resets = <&rctl STM32_RESET(APB1L, 2U)>;
			interrupts = <30 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timers6: timers@40001000 {
			compatible = "st,stm32-timers";
			reg = <0x40001000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
			resets = <&rctl STM32_RESET(APB1L, 4U)>;
			interrupts = <54 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";
		};

		timers7: timers@40001400 {
			compatible = "st,stm32-timers";
			reg = <0x40001400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
			resets = <&rctl STM32_RESET(APB1L, 5U)>;
			interrupts = <55 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";
		};

		timers8: timers@40013400 {
			compatible = "st,stm32-timers";
			reg = <0x40013400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
			resets = <&rctl STM32_RESET(APB2, 13U)>;
			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
			interrupt-names = "brk", "up", "trgcom", "cc";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timers15: timers@40014000 {
			compatible = "st,stm32-timers";
			reg = <0x40014000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
			resets = <&rctl STM32_RESET(APB2, 16U)>;
			interrupts = <24 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers16: timers@40014400 {
			compatible = "st,stm32-timers";
			reg = <0x40014400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
			resets = <&rctl STM32_RESET(APB2, 17U)>;
			interrupts = <25 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers17: timers@40014800 {
			compatible = "st,stm32-timers";
			reg = <0x40014800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
			resets = <&rctl STM32_RESET(APB2, 18U)>;
			interrupts = <26 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		rtc: rtc@40002800 {
			compatible = "st,stm32-rtc";
			reg = <0x40002800 0x400>;
			interrupts = <41 0>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
			prescaler = <32768>;
			status = "disabled";
		};

		rng: rng@50060800 {
			compatible = "st,stm32-rng";
			reg = <0x50060800 0x400>;
			interrupts = <90 0>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x04000000>;
			status = "disabled";
		};

		usb: usb@40005c00 {
			compatible = "st,stm32-usb";
			reg = <0x40005c00 0x400>;
			interrupts = <20 0>, <19 0>;
			interrupt-names = "usb", "usbhp";
			num-bidir-endpoints = <8>;
			ram-size = <1024>;
			phys = <&usb_fs_phy>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>,
				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
			status = "disabled";
		};

		dma1: dma@40020000 {
			compatible = "st,stm32-dma-v2";
			#dma-cells = <3>;
			reg = <0x40020000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
			dma-offset = <0>;
			status = "disabled";
		};

		dma2: dma@40020400 {
			compatible = "st,stm32-dma-v2";
			#dma-cells = <3>;
			reg = <0x40020400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
			status = "disabled";
		};

		dmamux1: dmamux@40020800 {
			compatible = "st,stm32-dmamux";
			#dma-cells = <3>;
			reg = <0x40020800 0x400>;
			interrupts = <94 0>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>;
			dma-generators = <4>;
			dma-requests= <111>;
			status = "disabled";
		};

		ucpd1: ucpd@4000a000 {
			compatible = "st,stm32-ucpd";
			reg = <0x4000a000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
			interrupts = <63 0>;
			status = "disabled";
		};
	};

	die_temp: dietemp {
		compatible = "st,stm32-temp-cal";
		ts-cal1-addr = <0x1FFF75A8>;
		ts-cal2-addr = <0x1FFF75CA>;
		ts-cal1-temp = <30>;
		ts-cal2-temp = <130>;
		ts-cal-vrefanalog = <3000>;
		io-channels = <&adc1 16>;
		status = "disabled";
	};

	vref: vref {
		compatible = "st,stm32-vref";
		vrefint-cal-addr = <0x1FFF75AA>;
		vrefint-cal-mv = <3000>;
		io-channels = <&adc1 18>;
		status = "disabled";
	};

	vbat: vbat {
		compatible = "st,stm32-vbat";
		ratio = <3>;
		io-channels = <&adc1 17>;
		status = "disabled";
	};

	usb_fs_phy: usbphy {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};

	smbus1: smbus1 {
		compatible = "st,stm32-smbus";
		#address-cells = <1>;
		#size-cells = <0>;
		i2c = <&i2c1>;
		status = "disabled";
	};

	smbus2: smbus2 {
		compatible = "st,stm32-smbus";
		#address-cells = <1>;
		#size-cells = <0>;
		i2c = <&i2c2>;
		status = "disabled";
	};

	smbus3: smbus3 {
		compatible = "st,stm32-smbus";
		#address-cells = <1>;
		#size-cells = <0>;
		i2c = <&i2c3>;
		status = "disabled";
	};
};

&nvic {
	arm,num-irq-priority-bits = <4>;
};