# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0

description: |
  PLL node binding for STM32G0 devices

  It can take one of clk_hse or clk_hsi as input clock, with
  an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
  clock in this acceptable range.

  PLL can have up to 3 output clocks and for each output clock, the
  frequency can be computed with the following formulae:

    f(PLL_P) = f(VCO clock) / PLLP  --> to I2S
    f(PLL_Q) = f(VCO clock) / PLLQ  --> to RNG
    f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)

      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)

  The PLL output frequency must not exceed 64 MHz.

compatible: "st,stm32g0-pll-clock"

include: [clock-controller.yaml, base.yaml]

properties:
  "#clock-cells":
    const: 0

  clocks:
    required: true

  div-m:
    type: int
    required: true
    description: |
        Division factor for PLL input clock
        Valid range: 1 - 8

  mul-n:
    type: int
    required: true
    description: |
        Main PLL multiplication factor for VCO
        Valid range: 8 - 86

  div-p:
    type: int
    description: |
        PLL division factor for PLL P output
        Valid range: 2 - 32

  div-q:
    type: int
    description: |
        PLL division factor for PLL Q output
        Valid range: 2 - 8

  div-r:
    type: int
    required: true
    description: |
        PLL division factor for PLLCLK (system clock)
        Valid range: 2 - 8