/*
 * Copyright (c) 2023 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <xtensa/xtensa.dtsi>
#include <mem.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "cdns,tensilica-xtensa-lx7";
			reg = <0>;
		};
	};

	sram0: memory@8e000000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0x8e000000 DT_SIZE_K(512)>;
	};

	sram1: memory@8e800000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0x8e800000 DT_SIZE_K(512)>;
	};
};