# Copyright (c) 2021 Andes Technology Corporation
# SPDX-License-Identifier: Apache-2.0

choice
prompt "Andes V5 SoC Selection"
depends on SOC_SERIES_RISCV_ANDES_V5

config SOC_RISCV_ANDES_AE350
	bool "Andes AE350 SoC implementation"
	select ATOMIC_OPERATIONS_BUILTIN
	select INCLUDE_RESET_VECTOR

endchoice

if SOC_SERIES_RISCV_ANDES_V5

choice
prompt "Base CPU ISA options"
default RV32I_CPU

config RV32I_CPU
	bool "RISCV32 CPU ISA"

config RV64I_CPU
	bool "RISCV64 CPU ISA"
	select 64BIT

endchoice

choice
prompt "FPU options"
default NO_FPU

config NO_FPU
	bool "No FPU"

config SINGLE_PRECISION_FPU
	bool "Single precision FPU"
	select CPU_HAS_FPU

config DOUBLE_PRECISION_FPU
	bool "Double precision FPU"
	select CPU_HAS_FPU_DOUBLE_PRECISION

endchoice

config CACHE_ENABLE
	bool "Enable cache"
	default n

config SOC_ANDES_V5_L2_CACHE
	bool "Enable Andes V5 L2 cache controller"
	depends on CACHE_ENABLE
	default y

config SOC_ANDES_V5_HWDSP
	bool "Enable AndeStar V5 DSP ISA"
	select RISCV_SOC_CONTEXT_SAVE
	depends on !RISCV_GENERIC_TOOLCHAIN
	help
		This option enables the AndeStar v5 hardware DSP, in order to
		support using the DSP instructions.

config SOC_ANDES_V5_PFT
	bool "Enable Andes V5 PowerBrake extension"
	default y
	select RISCV_SOC_CONTEXT_SAVE
	help
		The PowerBrake extension throttles performance by reducing instruction
		executing rate.

config SOC_ANDES_V5_PMA
	bool "Enable Andes V5 Physical Memory Attribute (PMA)"
	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT
	help
		This option enables the Andes V5 PMA, in order to support SW to
		configure physical memory attribute by PMA CSRs. The address
		matching of Andes V5 PMA is like RISC-V PMP NAPOT mode
		(power-of-two alignment).

config SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE
	int
	depends on SOC_ANDES_V5_PMA
	default 4096
	help
		Minimum size (and alignment) of an PMA region. Use this symbol
		to guarantee minimum size and alignment of PMA regions.

endif # SOC_SERIES_RISCV_ANDES_V5