/*
 * Copyright (c) 2017, NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include <mem.h>

/ {
	aliases{
		gpio-0 = &gpio0;
		gpio-1 = &gpio1;
		mailbox-0 = &mailbox0;
	};

	chosen {
		zephyr,flash-controller = &iap;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-m4f";
			reg = <0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-m0+";
			reg = <1>;
		};
	};

	soc {
		syscon: syscon@40000000 {
			compatible = "nxp,lpc-syscon";
			reg = <0x40000000 0x4000>;
			label = "SYSCON";
			#clock-cells = <1>;
		};

		sram0:memory@20000000 {
			compatible = "mmio-sram";
			reg = <0x20000000 DT_SIZE_K(64)>;
		};

		sram1:memory@20010000 {
			compatible = "mmio-sram";
			reg = <0x20010000 DT_SIZE_K(64)>;
		};

		sram2:memory@20020000 {
			compatible = "mmio-sram";
			reg = <0x20020000 DT_SIZE_K(32)>;
		};

		sramx:memory@4000000{
			compatible = "mmio-sram";
			reg = <0x4000000 DT_SIZE_K(32)>;
		};

		iap: flash-controller@4009c000 {
			compatible = "nxp,lpc-iap";
			label = "FLASH_IAP";
			reg = <0x4009c000 0x18>;
			#address-cells = <1>;
			#size-cells = <1>;
			flash0: flash@0 {
				compatible = "soc-nv-flash";
				reg = <0 DT_SIZE_K(256)>;
				label = "LPC_FLASH";
				erase-block-size = <256>;
				write-block-size = <256>;
			};
		};

		gpio0: gpio@0 {
			compatible = "nxp,lpc-gpio";
			reg = <0x4008c000 0x2488>;
			interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
			label = "GPIO_0";
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpio1: gpio@1 {
			compatible = "nxp,lpc-gpio";
			reg = <0x4008C000 0x2488>;
			interrupts = <32 2>,<33 2>,<34 2>,<35 2>;
			label = "GPIO_1";
			gpio-controller;
			#gpio-cells = <2>;
		};

		mailbox0:mailbox@4008b000 {
			compatible = "nxp,lpc-mailbox";
			reg = <0x4008b000 0xEC>;
			interrupts = <31 0>;
			label = "MAILBOX_0";
			status = "disabled";
		};

		flexcomm0: flexcomm@40086000 {
			compatible = "nxp,lpc-flexcomm";
			reg = <0x40086000 0x1000>;
			interrupts = <14 0>;
			clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
			label = "FLEXCOMM_0";
			status = "disabled";
		};

		flexcomm1: flexcomm@40087000 {
			compatible = "nxp,lpc-flexcomm";
			reg = <0x40087000 0x1000>;
			interrupts = <15 0>;
			clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
			label = "FLEXCOMM_1";
			status = "disabled";
		};

		flexcomm2: flexcomm@40088000 {
			compatible = "nxp,lpc-flexcomm";
			reg = <0x40088000 0x1000>;
			interrupts = <16 0>;
			clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
			label = "FLEXCOMM_2";
			status = "disabled";
		};

		flexcomm3: flexcomm@40089000 {
			compatible = "nxp,lpc-flexcomm";
			reg = <0x40089000 0x1000>;
			interrupts = <17 0>;
			clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
			label = "FLEXCOMM_3";
			status = "disabled";
		};

		flexcomm4: flexcomm@4008a000 {
			compatible = "nxp,lpc-flexcomm";
			reg = <0x4008a000 0x1000>;
			interrupts = <18 0>;
			clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
			label = "FLEXCOMM_4";
			status = "disabled";
		};

		flexcomm5: flexcomm@40096000 {
			compatible = "nxp,lpc-flexcomm";
			reg = <0x40096000 0x1000>;
			interrupts = <19 0>;
			clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
			label = "FLEXCOMM_5";
			status = "disabled";
		};

		flexcomm6: flexcomm@40097000 {
			compatible = "nxp,lpc-flexcomm";
			reg = <0x40097000 0x1000>;
			interrupts = <20 0>;
			clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
			label = "FLEXCOMM_6";
			status = "disabled";
		};

		flexcomm7: flexcomm@40098000 {
			compatible = "nxp,lpc-flexcomm";
			reg = <0x40098000 0x1000>;
			interrupts = <21 0>;
			clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
			label = "FLEXCOMM_7";
			status = "disabled";
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <3>;
};