)]}'
{
  "commit": "14e9e7a814ef510e4d72521bb7eb8cab0f3ebbea",
  "tree": "dc153b1f29d8517894e8ab5a152908b750612af3",
  "parents": [
    "256ca5547645843ede6f4c7c5c88f30d79b75bcf"
  ],
  "author": {
    "name": "Tim Lin",
    "email": "tim2.lin@ite.corp-partner.google.com",
    "time": "Tue Apr 20 16:40:13 2021 +0800"
  },
  "committer": {
    "name": "Anas Nashif",
    "email": "anas.nashif@intel.com",
    "time": "Fri Apr 23 07:03:10 2021 -0400"
  },
  "message": "soc: riscv/riscv-ite: chip_chipregs: add chip register address\n\nAdd register address including external timer and watchdog(ETWD),\ngeneral control(GCTRL), serial peripheral interface(SPI).\n\n\nSigned-off-by: Tim Lin \u003ctim2.lin@ite.corp-partner.google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3c3ad6102dde464c34588d3e3a25cdf4707358c7",
      "old_mode": 33188,
      "old_path": "soc/riscv/riscv-ite/common/chip_chipregs.h",
      "new_id": "44d55c0afacb832046dbc23b24ea366e9bef64a3",
      "new_mode": 33188,
      "new_path": "soc/riscv/riscv-ite/common/chip_chipregs.h"
    }
  ]
}