tree 8f4dae4f97574ceb21643d41460d10f968ea21d5
parent 61e2c29e9f106fb102f6d399be8e01f0d9b1c0f3
author Thomas Stranger <thomas.stranger@outlook.com> 1656439961 +0200
committer Carles Cufí <carles.cufi@nordicsemi.no> 1656945684 +0200

drivers/clock_control: stm32 common pll src support(g0,g4,l4,l5,wb,wl)

This commit adds support to select pll outputs as peripheral clock
sources to the stm32 common driver.
With this commit they are only available on
STM32G0, STM32G4, STM32L4, STM32L5, STM32WB, and STM32WL.

Support for STM32F2, and STM32F4, which also have p,q,r dividers,
is not enabled in this commit.

Also, stm32_clock_control_get_subsys_rate is extended to return
the configured frequency in case they are enabled, otherwise 0.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>