/*
 * Copyright (c) 2021 Thomas Stranger
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;
#include <seeed_studio/lora-e5.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>

/ {
	model = "Seeed Studio LoRa-E5 Dev Board";
	compatible = "seeed,lora-e5-dev-board";

	chosen {
		zephyr,console = &usart1;
		zephyr,shell-uart = &usart1;
		zephyr,sram = &sram0;
		zephyr,flash = &flash0;
		zephyr,code-partition = &slot0_partition;
	};

	leds {
		compatible = "gpio-leds";
		red_led_1: led_0 {
			gpios = <&gpiob 5 GPIO_ACTIVE_LOW>;
			label = "User LED1";
			/* the led can be disconnected, using J16 (D5) */
		};
	};

	gpio_keys {
		compatible = "gpio-keys";
		boot_button: button_0 {
			label = "SW1";
			gpios = <&gpiob 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
			zephyr,code = <INPUT_KEY_0>;
		};

		user_button: button_1 {
			label = "SW2";
			gpios = <&gpioa 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
			/* user_button can be disconnected, using J14 (D0) */
			zephyr,code = <INPUT_KEY_1>;
		};
	};

	aliases {
		led0 = &red_led_1;
		sw0 = &boot_button;
		sw1 = &user_button;
		lora0 = &lora;
		watchdog0 = &iwdg;
	};

	pwr_3v3: pwr-3v3-ctrl {
		/*
		 * PWR rail for SPI-flash, Temp-Sensor, RS-485 Transceiver,
		 * and for external devices(Grove, header).
		 * Requires closed J15 (D9)
		 */
		compatible = "regulator-fixed";
		regulator-name = "pwr-3v3-ctrl";
		enable-gpios = <&gpioa 9 GPIO_ACTIVE_HIGH>;
		regulator-boot-on;
		status = "okay";
	};

	pwr_5v: pwr-5v-ctrl {
		/*
		 * Available for external devices on header J2
		 * Requires closed J6 (D10)
		 */
		compatible = "regulator-fixed";
		regulator-name = "pwr-5v-ctrl";
		enable-gpios = <&gpiob 10 GPIO_ACTIVE_HIGH>;
		regulator-boot-on;
		status = "okay";
	};
};

stm32_lp_tick_source: &lptim1 {
	status = "okay";
	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
		 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
};

&clk_lsi {
	status = "okay";
};

&clk_msi {
	status = "okay";
	msi-range = <11>;
};

&rcc {
	clocks = <&clk_msi>;
	clock-frequency = <DT_FREQ_M(48)>;
	cpu1-prescaler = <1>;
	ahb3-prescaler = <1>;
	apb1-prescaler = <1>;
	apb2-prescaler = <1>;
};

&lpuart1 {
	pinctrl-0 = <&lpuart1_tx_pc1 &lpuart1_rx_pc0>;
	pinctrl-names = "default";
	current-speed = <115200>;
	status = "okay";
};

&usart1 {
	pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
	pinctrl-names = "default";
	current-speed = <115200>;
	status = "okay";
};

&usart2 {
	pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
	pinctrl-names = "default";
	current-speed = <115200>;
	status = "okay";
	/* PB4 can select RS-485 TX, when J17 (A4) is closed */
};

&i2c2 {
	pinctrl-0 = <&i2c2_scl_pb15 &i2c2_sda_pa15>;
	pinctrl-names = "default";
	status = "okay";
	clock-frequency = <I2C_BITRATE_FAST>;

	/* LM75ADP temperature sensor on addr 0x48 */
};

/* Attention!: the spi-sck pin is in conflict with the boot_button on pb13 */
&spi2 {
	pinctrl-0 = <&spi2_nss_pb9 &spi2_sck_pb13
		     &spi2_miso_pb14 &spi2_mosi_pa10>;
	pinctrl-names = "default";
	status = "okay";

	/* unpopulated footprint for spi flash */
};

&rtc {
	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
	status = "okay";
};

&iwdg {
	status = "okay";
};

&adc1 {
	pinctrl-0 = <&adc_in2_pb3>;
	pinctrl-names = "default";
	st,adc-clock-source = <SYNC>;
	st,adc-prescaler = <4>;
	status = "okay";
};

&aes {
	status = "okay";
};

/* connectors: */
grove_serial: &usart1 {};
grove_i2c: &i2c2 {};

&flash0 {
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		boot_partition: partition@0 {
			label = "mcuboot";
			reg = <0x00000000 DT_SIZE_K(32)>;
			read-only;
		};
		slot0_partition: partition@8000 {
			label = "image-0";
			reg = <0x00008000 DT_SIZE_K(104)>;
		};
		slot1_partition: partition@22000 {
			label = "image-1";
			reg = <0x00022000 DT_SIZE_K(104)>;
		};
		/* 16KB (8x2kB pages) of storage at the end of the flash */
		storage_partition: partition@3c000 {
			label = "storage";
			reg = <0x0003c000 DT_SIZE_K(16)>;
		};
	};
};

/*
 * Other Pins:
 * Not assigned:  None
 * Debug:         PA13(swdio), PA14(swclk)
 */