/*
 * Copyright (c) 2020 TriaGnoSys GmbH
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <arm/armv8-m.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include <arm/silabs/gpio_gecko.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/pinctrl/gecko-pinctrl.h>
#include <dt-bindings/adc/adc.h>
#include <dt-bindings/clock/silabs/xg24-clock.h>
#include <freq.h>

/ {
	chosen {
		zephyr,flash-controller = &msc;
		zephyr,entropy = &se;
	};

	clocks {
		hfxort: hfxort {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&hfxo>;
		};
		hfrcodpllrt: hfrcodpllrt {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&hfrcodpll>;
		};
		sysclk: sysclk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&hfrcodpll>;
		};
		hclk: hclk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&sysclk>;
			/* Divider 1, 2, 4, 8, or 16 */
			clock-div = <1>;
		};
		pclk: pclk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&hclk>;
			/* Divider 1 or 2 */
			clock-div = <2>;
		};
		lspclk: lspclk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&pclk>;
			/* Fixed divider of 2 */
			clock-div = <2>;
		};
		hclkdiv1024: hclkdiv1024 {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&hclk>;
			/* Fixed divider of 1024 */
			clock-div = <1024>;
		};
		traceclk: traceclk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&sysclk>;
			/* Divider 1, 2, 3 or 4 */
			clock-div = <1>;
		};
		em01grpaclk: em01grpaclk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&hfrcodpll>;
		};
		em01grpcclk: em01grpcclk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&hfrcodpll>;
		};
		iadcclk: iadcclk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&em01grpaclk>;
		};
		em23grpaclk: em23grpaclk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&lfrco>;
		};
		em4grpaclk: em4grpaclk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&lfrco>;
		};
		sysrtcclk: sysrtcclk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&lfrco>;
		};
		wdog0clk: wdog0clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&lfrco>;
		};
		wdog1clk: wdog1clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&lfrco>;
		};
		pcnt0clk: pcnt0clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&em23grpaclk>;
		};
		eusart0clk: eusart0clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&em01grpcclk>;
		};
		systickclk: systickclk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&hclk>;
		};
		vdac0clk: vdac0clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&em01grpaclk>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m33";
			reg = <0>;
			cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>;
		};

		power-states {
			/*
			 * EM1 is a basic "CPU WFI idle", all high-freq clocks remain
			 * enabled.
			 */
			pstate_em1: em1 {
				compatible = "zephyr,power-state";
				power-state-name = "runtime-idle";
				min-residency-us = <4>;
				/* HFXO remains active */
				exit-latency-us = <2>;
			};

			/*
			 * EM2 is a deepsleep with HF clocks disabled by HW, voltages
			 * scaled down, etc.
			 */
			pstate_em2: em2 {
				compatible = "zephyr,power-state";
				power-state-name = "suspend-to-idle";
				min-residency-us = <260>;
				exit-latency-us = <250>;
			};

			/*
			 * EM3 seems to be exactly the same as EM2 except that
			 * LFXO & LFRCO should be disabled, so you must use ULFRCO
			 * as BURTC clock for the system to not lose track of time and
			 * wake up.
			 */
			pstate_em3: em3 {
				compatible = "zephyr,power-state";
				power-state-name = "standby";
				min-residency-us = <20000>;
				exit-latency-us = <2000>;
			};
		};
	};

	sram0: memory@20000000 {
		device_type = "memory";
		compatible = "mmio-sram";
	};

	soc {
		cmu: clock@50008000 {
			compatible = "silabs,series-clock";
			reg = <0x50008000 0x4000>;
			interrupts = <47 0>;
			interrupt-names = "cmu";
			status = "okay";
			#clock-cells = <2>;
		};

		fsrco: fsrco@50018000 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			reg = <0x50018000 0x4000>;
			clock-frequency = <DT_FREQ_M(20)>;
		};

		clk_hfxo: hfxo: hfxo@5a004000 {
			#clock-cells = <0>;
			compatible = "silabs,hfxo";
			reg = <0x5a004000 0x4000>;
			interrupts = <44 0>;
			interrupt-names = "hfxo";
			clock-frequency = <DT_FREQ_M(39)>;
			ctune = <140>;
			precision = <50>;
			status = "disabled";
		};

		lfxo: lfxo@50020000 {
			#clock-cells = <0>;
			compatible = "silabs,series2-lfxo";
			reg = <0x50020000 0x4000>;
			clock-frequency = <32768>;
			ctune = <63>;
			precision = <50>;
			timeout = <4096>;
			status = "disabled";
		};

		hfrcodpll: hfrcodpll@50010000 {
			#clock-cells = <0>;
			compatible = "silabs,series2-hfrcodpll";
			reg = <0x50010000 0x4000>;
			clock-frequency = <DT_FREQ_M(19)>;
		};

		hfrcoem23: hfrcoem23@5a000000 {
			#clock-cells = <0>;
			compatible = "silabs,series2-hfrcoem23";
			reg = <0x5a000000 0x4000>;
			clock-frequency = <DT_FREQ_M(19)>;
		};

		lfrco: lfrco@50024000 {
			#clock-cells = <0>;
			compatible = "silabs,series2-lfrco";
			reg = <0x50024000 0x4000>;
			clock-frequency = <32768>;
		};

		ulfrco: ulfrco@50028000 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			reg = <0x50028000 0x4000>;
			clock-frequency = <1000>;
		};

		clkin0: clkin0@5003c46c {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			reg = <0x5003c46c 0x4>;
			clock-frequency = <DT_FREQ_M(38)>;
		};

		msc: flash-controller@50030000 {
			compatible = "silabs,gecko-flash-controller";
			reg = <0x50030000 0x3148>;
			interrupts = <50 0>;

			#address-cells = <1>;
			#size-cells = <1>;

			flash0: flash@0 {
				compatible = "soc-nv-flash";
				write-block-size = <4>;
				erase-block-size = <8192>;
			};
		};

		usart0: usart@5005c000 {
			compatible = "silabs,gecko-usart";
			reg = <0x5005C000 0x306c>;
			interrupts = <9 0>, <10 0>;
			interrupt-names = "rx", "tx";
			peripheral-id = <0>;
			clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
			status = "disabled";
		};

		eusart0: eusart@5b010000 {
			compatible = "silabs,gecko-spi-eusart";
			reg = <0x5B010000 0x4000>;
			interrupts = <11 0>, <12 0>;
			interrupt-names = "rx", "tx";
			clocks = <&cmu CLOCK_EUSART0 CLOCK_BRANCH_EUSART0CLK>;
			status = "disabled";
		};

		eusart1: eusart@500a0000 {
			compatible = "silabs,gecko-spi-eusart";
			reg = <0x500A0000 0x4000>;
			interrupts = <13 0>, <14 0>;
			interrupt-names = "rx", "tx";
			clocks = <&cmu CLOCK_EUSART1 CLOCK_BRANCH_EM01GRPCCLK>;
			status = "disabled";
		};

		burtc0: burtc@50064000 {
			compatible = "silabs,gecko-burtc";
			reg = <0x50064000 0x3034>;
			interrupts = <17 0>;
			clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
			status = "disabled";
		};

		se: semailbox@5c021000 {
			compatible = "silabs,gecko-semailbox";
			reg = <0x5c021000 0x1000>;
			status = "disabled";
			interrupts = <64 3>, <65 3>, <66 3>;
			interrupt-names = "SETAMPERHOST", "SEMBRX", "SEMBTX";
		};

		i2c0: i2c@5b000000 {
			compatible = "silabs,gecko-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x5b000000 0x3044>;
			interrupts = <27 0>;
			clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
			status = "disabled";
		};

		sysrtc0: stimer0: sysrtc@500a8000 {
			compatible = "silabs,gecko-stimer";
			reg = <0x500a8000 0x3054>;
			interrupts = <67 0>, <68 0>;
			interrupt-names = "sysrtc_app", "sysrtc_seq";
			clock-frequency = <32768>;
			prescaler = <1>;
			clocks = <&cmu CLOCK_SYSRTC0 CLOCK_BRANCH_SYSRTCCLK>;
			status = "disabled";
		};

		gpio: gpio@5003c000 {
			compatible = "silabs,gecko-gpio";
			reg = <0x5003c000 0x4000>;
			interrupts = <26 2>, <25 2>;
			interrupt-names = "GPIO_EVEN", "GPIO_ODD";
			clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;

			ranges;
			#address-cells = <1>;
			#size-cells = <1>;

			gpioa: gpio@5003c030 {
				compatible = "silabs,gecko-gpio-port";
				reg = <0x5003c030 0x30>;
				peripheral-id = <0>;
				gpio-controller;
				#gpio-cells = <2>;
				status = "disabled";
			};

			gpiob: gpio@5003c060 {
				compatible = "silabs,gecko-gpio-port";
				reg = <0x5003c060 0x30>;
				peripheral-id = <1>;
				gpio-controller;
				#gpio-cells = <2>;
				status = "disabled";
			};

			gpioc: gpio@5003c090 {
				compatible = "silabs,gecko-gpio-port";
				reg = <0x5003c090 0x30>;
				peripheral-id = <2>;
				gpio-controller;
				#gpio-cells = <2>;
				status = "disabled";
			};

			gpiod: gpio@5003c0C0 {
				compatible = "silabs,gecko-gpio-port";
				reg = <0x5003c0C0 0x30>;
				peripheral-id = <3>;
				gpio-controller;
				#gpio-cells = <2>;
				status = "disabled";
			};
		};

		wdog0: wdog@5b004000 {
			compatible = "silabs,gecko-wdog";
			reg = <0x5b004000 0x2C>;
			peripheral-id = <0>;
			interrupts = <42 0>;
			clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>;
			status = "disabled";
		};

		wdog1: wdog@5b008000 {
			compatible = "silabs,gecko-wdog";
			reg = <0x5b008000 0x2C>;
			peripheral-id = <1>;
			interrupts = <43 0>;
			clocks = <&cmu CLOCK_WDOG1 CLOCK_BRANCH_WDOG1CLK>;
			status = "disabled";
		};

		adc0: adc@59004000 {
			compatible = "silabs,gecko-iadc";
			reg = <0x59004000 0x4000>;
			interrupts = <49 0>;
			clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>;
			status = "disabled";
			#io-channel-cells = <1>;
		};

		dcdc: dcdc@50094000 {
			compatible = "silabs,series2-dcdc";
			reg = <0x50094000 0x4000>;
			interrupts = <53 0>;
			status = "disabled";
		};
	};


	bt_hci_silabs: bt_hci_silabs {
		compatible = "silabs,bt-hci-efr32";
		status = "disabled";
	};
};

/ {
	pinctrl: pin-controller {
		/* Pin controller is a "virtual" device since SiLabs SoCs do pin
		 * control in a distributed way (GPIO registers and PSEL
		 * registers on each peripheral).
		 */
		compatible = "silabs,gecko-pinctrl";
	};

	hwinfo: hwinfo {
		compatible = "silabs,gecko-hwinfo";
		status = "disabled";
	};

};

&nvic {
	arm,num-irq-priority-bits = <4>;
};