#
# Copyright (c) 2024 Charles Dias <charlesdias.cd@outlook.com>
#
# SPDX-License-Identifier: Apache-2.0
#

description: |
    STMicroelectronics STM32 Digital Camera Memory Interface (DCMI).
    Example of node configuration at board level:

    &dcmi {
      status = "okay";
      sensor = <&ov2640>;
      pinctrl-0 = <&dcmi_hsync_pa4 &dcmi_pixclk_pa6 &dcmi_vsync_pb7
                  &dcmi_d0_pc6 &dcmi_d1_pc7 &dcmi_d2_pe0 &dcmi_d3_pe1
                  &dcmi_d4_pe4 &dcmi_d5_pd3 &dcmi_d6_pe5 &dcmi_d7_pe6>;
      pinctrl-names = "default";
      bus-width = <8>;
      hsync-active = <0>;
      vsync-active = <0>;
      pixelclk-active = <1>;
      capture-rate = <1>;
      dmas = <&dma1 0 75 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC |
              STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS |
              STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>;

      port {
        dcmi_ep_in: endpoint {
          remote-endpoint = <&ov2640_ep_out>;
        };
      };
    };

compatible: "st,stm32-dcmi"

include: [base.yaml, pinctrl-device.yaml]

properties:
  interrupts:
    required: true

  sensor:
    required: true
    type: phandle
    description: phandle of connected sensor device

  bus-width:
    type: int
    required: true
    enum:
      - 8
      - 10
      - 12
      - 14
    default: 8
    description: |
      Number of data lines actively used, valid for the parallel busses.

  hsync-active:
    type: int
    required: true
    enum:
      - 0
      - 1
    description: |
      Polarity of horizontal synchronization (DCMI_HSYNC_Polarity).
      0 Horizontal synchronization active Low.
      1 Horizontal synchronization active High.

      For example, if DCMI_HSYNC_Polarity is programmed active high:
      When HSYNC is low, the data is valid.
      When HSYNC is high, the data is not valid (horizontal blanking).

  vsync-active:
    type: int
    required: true
    enum:
      - 0
      - 1
    description: |
      Polarity of vertical synchronization (DCMI_VSYNC_Polarity).
      0 Vertical synchronization active Low.
      1 Vertical synchronization active High.

      For example, if DCMI_VSYNC_Polarity is programmed active high:
      When VSYNC is low, the data is valid.
      When VSYNC is high, the data is not valid (vertical blanking).

  pixelclk-active:
    type: int
    required: true
    enum:
      - 0
      - 1
    description: |
      Polarity of pixel clock (DCMI_PIXCK_Polarity).
      0 Pixel clock active on Falling edge.
      1 Pixel clock active on Rising edge.

  capture-rate:
    type: int
    enum:
      - 1
      - 2
      - 4
    default: 1
    description: |
      The DCMI can capture all frames or alternate frames. If it is not specified,
      the default is all frames.
      1 Capture all frames.
      2 Capture alternate frames.
      4 Capture one frame every 4 frames.

  dmas:
    required: true
    description: |
      phandle of DMA controller. The DMA controller should be compatible with
      DMA channel specifier. Specifies a phandle reference to the dma controller,
      the channel number, the slot number, channel configuration and finally features.

      dmas = <&dma1 0 75 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC |
              STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS |
              STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>;