)]}'
{
  "commit": "1c7c4506d85cf0f2bdacdbd6e4dfc9dc45badbde",
  "tree": "d4fd536bee30870f51de71a66f6dbf08fc2a7bde",
  "parents": [
    "7f4471c84e044b3b495f422fee49b143f119b29a"
  ],
  "author": {
    "name": "Francois Ramu",
    "email": "francois.ramu@st.com",
    "time": "Mon Feb 28 16:23:14 2022 +0100"
  },
  "committer": {
    "name": "Maureen Helm",
    "email": "maureen.helm@intel.com",
    "time": "Mon Mar 14 08:56:19 2022 -0500"
  },
  "message": "drivers: clock_control of the stm32l0x or stm32l1x devices\n\nFix register bit field when clock source is MSI\non the stm32L0x or stm32L1x mcus\nUse RCC_CR_MSIRGSEL bit field instead of not soc stm32wbx serie\nThat bit of the RCC CR is common to several stm32 mcus\n\nSigned-off-by: Francois Ramu \u003cfrancois.ramu@st.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "700817184236868b9ab763b782da54328c40b662",
      "old_mode": 33188,
      "old_path": "drivers/clock_control/clock_stm32_ll_common.c",
      "new_id": "c83851d8fa1868ed33274577daba1286196be3e1",
      "new_mode": 33188,
      "new_path": "drivers/clock_control/clock_stm32_ll_common.c"
    }
  ]
}