tree 9dbc45e0a03660e067fdc5b756f81da0c54e12d0
parent 94f39e5a80a4208cc7f5bf26743fb811e2d2d5a0
author Nicolas Pitre <npitre@baylibre.com> 1645556995 -0500
committer Anas Nashif <anas.nashif@intel.com> 1647862085 -0400

riscv: better abstraction for register-wide load/store opcodes

Those are prominent enough that having RV_OP_LOADREG and RV_OP_STOREREG
shouting at you all over the place is rather unpleasant and bad taste.

Let's create pseudo-instructions of our own with assembler macros
rather than preprocessor defines and only in assembly scope.
This makes the asm code way more uniform and readable.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>