/*
 * Copyright (c) 2020 Thomas Stranger
 * Copyright (c) 2021 G-Technologies Sdn. Bhd.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <st/g0/stm32g071.dtsi>

/ {
	soc {
		compatible = "st,stm32g0b1", "st,stm32g0", "simple-bus";

		clocks {
			clk_hsi48: clk-hsi48 {
				#clock-cells = <0>;
				compatible = "st,stm32-hsi48-clock";
				clock-frequency = <DT_FREQ_M(48)>;
				status = "disabled";
			};
		};

		pinctrl: pin-controller@50000000 {
			gpioe: gpio@50001000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x50001000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000010>;
			};
		};

		fdcan1: can@40006400 {
			compatible = "st,stm32-fdcan";
			reg = <0x40006400 0x400>, <0x4000b400 0x350>;
			reg-names = "m_can", "message_ram";
			interrupts = <21 0>, <22 0>;
			interrupt-names = "int0", "int1";
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>;
			bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
			status = "disabled";
		};

		fdcan2: can@40006800 {
			compatible = "st,stm32-fdcan";
			reg = <0x40006800 0x400>, <0x4000b750 0x350>;
			reg-names = "m_can", "message_ram";
			interrupts = <21 0>, <22 0>;
			interrupt-names = "int0", "int1";
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>;
			bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
			status = "disabled";
		};

		usart5: serial@40005000 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40005000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
			resets = <&rctl STM32_RESET(APB1L, 8U)>;
			interrupts = <29 0>;
			status = "disabled";
		};

		usart6: serial@40013c00 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40013c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>;
			resets = <&rctl STM32_RESET(APB1L, 9U)>;
			interrupts = <29 0>;
			status = "disabled";
		};

		lpuart2: serial@40008400 {
			compatible = "st,stm32-lpuart", "st,stm32-uart";
			reg = <0x40008400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
			resets = <&rctl STM32_RESET(APB1L, 7U)>;
			interrupts = <28 0>;
			status = "disabled";
		};

		timers4: timers@40000800 {
			compatible = "st,stm32-timers";
			reg = <0x40000800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
			resets = <&rctl STM32_RESET(APB1L, 2U)>;
			interrupts = <16 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		i2c3: i2c@40008800 {
			compatible = "st,stm32-i2c-v2";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40008800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
			interrupts = <24 0>;
			interrupt-names = "combined";
			status = "disabled";
		};

		spi3: spi@40003c00 {
			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
			interrupts = <26 3>;
			status = "disabled";
		};

		dma2: dma@40020400 {
			compatible = "st,stm32-dma-v2";
			#dma-cells = <3>;
			reg = <0x40020400 0x400>;
			interrupts = <11 0 11 0 11 0 11 0 11 0>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
			dma-requests = <5>;
			dma-offset = <7>;
			status = "disabled";
		};

		dmamux1: dmamux@40020800 {
			dma-channels = <12>;
			dma-requests = <73>;
		};

		usb: usb@40005c00 {
			compatible = "st,stm32-usb";
			reg = <0x40005c00 0x400>;
			interrupts = <8 0>;
			interrupt-names = "usb";
			num-bidir-endpoints = <8>;
			ram-size = <2048>;
			phys = <&usb_fs_phy>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00002000>,
				 <&rcc STM32_SRC_HSI48 USB_SEL(0)>;
			status = "disabled";
		};
	};

	usb_fs_phy: usbphy {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};

	smbus3: smbus3 {
		compatible = "st,stm32-smbus";
		#address-cells = <1>;
		#size-cells = <0>;
		i2c = <&i2c3>;
		status = "disabled";
	};
};