/*
 * Copyright (c) 2022 Nordic Semiconductor
 * SPDX-License-Identifier: Apache-2.0
 */

&pinctrl {
	uart0_default: uart0_default {
		group1 {
			psels = <NRF_PSEL(UART_TX, 0, 25)>,
				<NRF_PSEL(UART_RX, 0, 24)>;
		};
	};

	uart0_sleep: uart0_sleep {
		group1 {
			psels = <NRF_PSEL(UART_TX, 0, 25)>,
				<NRF_PSEL(UART_RX, 0, 24)>;
			low-power-enable;
		};
	};

	i2c0_default: i2c0_default {
		group1 {
			psels = <NRF_PSEL(TWIM_SDA, 0, 12)>,
				<NRF_PSEL(TWIM_SCL, 0, 11)>;
		};
	};

	i2c0_sleep: i2c0_sleep {
		group1 {
			psels = <NRF_PSEL(TWIM_SDA, 0, 12)>,
				<NRF_PSEL(TWIM_SCL, 0, 11)>;
			low-power-enable;
		};
	};

	spi1_default: spi1_default {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 0, 14)>,
				<NRF_PSEL(SPIM_MOSI, 0, 13)>,
				<NRF_PSEL(SPIM_MISO, 0, 15)>;
		};
	};

	spi1_sleep: spi1_sleep {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 0, 14)>,
				<NRF_PSEL(SPIM_MOSI, 0, 13)>,
				<NRF_PSEL(SPIM_MISO, 0, 15)>;
			low-power-enable;
		};
	};

	qspi_default: qspi_default {
		group1 {
			psels = <NRF_PSEL(QSPI_SCK, 0, 19)>,
				<NRF_PSEL(QSPI_IO0, 0, 17)>,
				<NRF_PSEL(QSPI_IO1, 0, 22)>,
				<NRF_PSEL(QSPI_IO2, 0, 23)>,
				<NRF_PSEL(QSPI_IO3, 0, 21)>,
				<NRF_PSEL(QSPI_CSN, 0, 20)>;
		};
	};

	qspi_sleep: qspi_sleep {
		group1 {
			psels = <NRF_PSEL(QSPI_SCK, 0, 19)>,
				<NRF_PSEL(QSPI_IO0, 0, 17)>,
				<NRF_PSEL(QSPI_IO1, 0, 22)>,
				<NRF_PSEL(QSPI_IO2, 0, 23)>,
				<NRF_PSEL(QSPI_IO3, 0, 21)>,
				<NRF_PSEL(QSPI_CSN, 0, 20)>;
			low-power-enable;
		};
	};

};