tree fbfdd656e8d58398d00346fec430c8e24a9794dd
parent 1c4889e4021dab4d4c67662dcf374b0ccd9c06bb
author Tyler Ng <tkng@rivosinc.com> 1683671833 -0700
committer Anas Nashif <anas.nashif@intel.com> 1685108725 -0400

soc: riscv: riscv-privilege: opentitan: Enable watchdog reset function

Adds watchdog reset as a reset source at SoC init. This is achieved by:

1. Writing 0x2 to the RESET_EN bitfield register to indicate watchdog
reset is enabled.
2. Writing 0x1 to the CFG_CDC_SYNC register to commit the change.
3. Polling the CFG_CDC_SYNC register until reading 0 to confirm the
change has been processed.

This patch is part of the OpenTitan watchdog (AON Timer) support patch
series. It is needed to ensure that the watchdog reset functionality
is enabled. Note that the timer itself is not enabled here, only the
reset function.

Signed-off-by: Tyler Ng <tkng@rivosinc.com>