/*
 * Copyright (c) 2021 Nuvoton Technology Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* NPCX9 series pinmux mapping table */
#include "npcx/npcx9/npcx9-alts-map.dtsi"
/* NPCX9 series mapping table between MIWU wui bits and source device */
#include "npcx/npcx9/npcx9-miwus-wui-map.dtsi"
/* NPCX9 series mapping table between MIWU groups and interrupts */
#include "npcx/npcx9/npcx9-miwus-int-map.dtsi"
/* NPCX9 series eSPI VW mapping table */
#include "npcx/npcx9/npcx9-espi-vws-map.dtsi"
/* NPCX9 series low-voltage io controls mapping table */
#include "npcx/npcx9/npcx9-lvol-ctrl-map.dtsi"
/* NPCX9 series power-switch-logic (PSL) io controls mapping table */
#include "npcx/npcx9/npcx9-psl-ctrl-map.dtsi"

/* Device tree declarations of npcx soc family */
#include "npcx.dtsi"

/ {
	def-io-conf-list {
		pinctrl-0 = <&alt0_gpio_no_spip
			   &alt0_gpio_no_fpip
			   &alt1_no_pwrgd
			   &alt1_no_lpc_espi
			   &alta_no_peci_en
			   &altd_npsl_in1_sl
			   &altd_npsl_in2_sl
			   &altd_psl_in3_sl
			   &altd_psl_in4_sl
			   &alt7_no_ksi0_sl
			   &alt7_no_ksi1_sl
			   &alt7_no_ksi2_sl
			   &alt7_no_ksi3_sl
			   &alt7_no_ksi4_sl
			   &alt7_no_ksi5_sl
			   &alt7_no_ksi6_sl
			   &alt7_no_ksi7_sl
			   &alt8_no_kso00_sl
			   &alt8_no_kso01_sl
			   &alt8_no_kso02_sl
			   &alt8_no_kso03_sl
			   &alt8_no_kso04_sl
			   &alt8_no_kso05_sl
			   &alt8_no_kso06_sl
			   &alt8_no_kso07_sl
			   &alt9_no_kso08_sl
			   &alt9_no_kso09_sl
			   &alt9_no_kso10_sl
			   &alt9_no_kso11_sl
			   &alt9_no_kso12_sl
			   &alt9_no_kso13_sl
			   &alt9_no_kso14_sl
			   &alt9_no_kso15_sl
			   &alta_no_kso16_sl
			   &alta_no_kso17_sl
			   &altg_psl_gpo_sl>;
	};

	soc {
		/* Specific soc devices in npcx9 series */
		itims: timer@400b0000 {
			compatible = "nuvoton,npcx-itim-timer";
			reg = <0x400b0000 0x2000
			       0x400be000 0x2000>;
			reg-names = "evt_itim", "sys_itim";
			clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0
				  &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>;
			interrupts = <28 1>; /* Event timer interrupt */
			label = "ITIM";
		};

		uart1: serial@400e0000 {
			compatible = "nuvoton,npcx-uart";
			reg = <0x400E0000 0x2000>;
			interrupts = <33 3>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL1 4>;
			pinctrl-0 = <&altj_cr_sin1_sl1 &altj_cr_sout1_sl1>; /* PIN10.11 */
			uart-rx = <&wui_cr_sin1>;
			status = "disabled";
			label = "UART_1";
		};

		uart2: serial@400e2000 {
			compatible = "nuvoton,npcx-uart";
			reg = <0x400E2000 0x2000>;
			interrupts = <32 3>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 6>;
			pinctrl-0 = <&altj_cr_sin2_sl &altj_cr_sout2_sl>; /* PIN75.86 */
			uart-rx = <&wui_cr_sin2>;
			status = "disabled";
			label = "UART_2";
		};

		uart3: serial@400e4000 {
			compatible = "nuvoton,npcx-uart";
			reg = <0x400E4000 0x2000>;
			interrupts = <38 3>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 4>;
			pinctrl-0 = <&altj_cr_sin3_sl &altj_cr_sout3_sl>; /* PIND3.D6 */
			uart-rx = <&wui_cr_sin3>;
			status = "disabled";
			label = "UART_3";
		};

		uart4: serial@400e6000 {
			compatible = "nuvoton,npcx-uart";
			reg = <0x400E6000 0x2000>;
			interrupts = <39 3>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 3>;
			pinctrl-0 = <&alte_cr_sin4_sl &alte_cr_sout4_sl>; /* PIN17.35 */
			uart-rx = <&wui_cr_sin4>;
			status = "disabled";
			label = "UART_4";
		};

		/* Default clock and power settings in npcx9 series */
		pcc: clock-controller@4000d000 {
			clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
			core-prescaler = <6>; /* CORE_CLK runs at 15MHz */
			apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
			apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
			apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
			apb4-prescaler = <6>; /* APB4_CLK runs at 15MHz */
			ram-pd-depth = <15>; /* Valid bit-depth of RAM_PDn reg */
		};

		/* Wake-up input source mapping for GPIOs in npcx9 series */
		gpio0: gpio@40081000 {
			wui-maps = <&wui_io00 &wui_io01 &wui_io02 &wui_io03
				    &wui_io04 &wui_io05 &wui_io06 &wui_io07>;
		};

		gpio1: gpio@40083000 {
			wui-maps = <&wui_io10 &wui_io11 &wui_none &wui_none
				    &wui_io14 &wui_io15 &wui_io16 &wui_io17>;
		};

		gpio2: gpio@40085000 {
			wui-maps = <&wui_io20 &wui_io21 &wui_io22 &wui_io23
				    &wui_io24 &wui_io25 &wui_io26 &wui_io27>;
		};

		gpio3: gpio@40087000 {
			wui-maps = <&wui_io30 &wui_io31 &wui_none &wui_io33
				    &wui_io34 &wui_none &wui_io36 &wui_io37>;
		};

		gpio4: gpio@40089000 {
			wui-maps = <&wui_io40 &wui_io41 &wui_io42 &wui_io43
				    &wui_io44 &wui_io45 &wui_io46 &wui_io47>;
		};

		gpio5: gpio@4008b000 {
			wui-maps = <&wui_io50 &wui_io51 &wui_io52 &wui_io53
				    &wui_io54 &wui_io55 &wui_io56 &wui_io57>;
		};

		gpio6: gpio@4008d000 {
			wui-maps = <&wui_io60 &wui_io61 &wui_io62 &wui_io63
				    &wui_io64 &wui_none &wui_io66 &wui_io67>;
		};

		gpio7: gpio@4008f000 {
			wui-maps = <&wui_io70 &wui_none &wui_io72 &wui_io73
				    &wui_io74 &wui_io75 &wui_io76 &wui_none>;
		};

		gpio8: gpio@40091000 {
			wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83
				    &wui_none &wui_none &wui_none &wui_io87>;
		};

		gpio9: gpio@40093000 {
			wui-maps = <&wui_io90 &wui_io91 &wui_io92 &wui_io93
				    &wui_io94 &wui_io95 &wui_io96 &wui_io97>;
		};

		gpioa: gpio@40095000 {
			wui-maps = <&wui_ioa0 &wui_ioa1 &wui_ioa2 &wui_ioa3
				    &wui_ioa4 &wui_ioa5 &wui_ioa6 &wui_ioa7>;
		};

		gpiob: gpio@40097000 {
			wui-maps = <&wui_iob0 &wui_iob1 &wui_iob2 &wui_iob3
				    &wui_iob4 &wui_iob5 &wui_iob6 &wui_iob7>;
		};

		gpioc: gpio@40099000 {
			wui-maps = <&wui_ioc0 &wui_ioc1 &wui_ioc2 &wui_ioc3
				    &wui_ioc4 &wui_ioc5 &wui_ioc6 &wui_ioc7>;
		};

		gpiod: gpio@4009b000 {
			wui-maps = <&wui_iod0 &wui_iod1 &wui_iod2 &wui_iod3
				    &wui_iod4 &wui_iod5 &wui_none &wui_none>;
		};

		gpioe: gpio@4009d000 {
			wui-maps = <&wui_ioe0 &wui_ioe1 &wui_ioe2 &wui_ioe3
				    &wui_ioe4 &wui_ioe5 &wui_none &wui_none>;
		};

		gpiof: gpio@4009f000 {
			wui-maps = <&wui_iof0 &wui_iof1 &wui_iof2 &wui_iof3
				    &wui_iof4 &wui_iof5 &wui_none &wui_none>;
		};

		/* Supported channels for ADC0 in npcx9 series */
		adc0: adc@400d1000 {
			pinctrl-0 = <&alt6_adc0_sl    /* ADC0 - PIN45 */
				     &alt6_adc1_sl    /* ADC1 - PIN44 */
				     &alt6_adc2_sl    /* ADC2 - PIN43 */
				     &alt6_adc3_sl    /* ADC3 - PIN42 */
				     &alt6_adc4_sl    /* ADC4 - PIN41 */
				     &altf_adc5_sl    /* ADC5 - PIN37 */
				     &altf_adc6_sl    /* ADC6 - PIN34 */
				     &altf_adc7_sl    /* ADC7 - PINE1 */
				     &altf_adc8_sl    /* ADC8 - PINF1 */
				     &altf_adc9_sl    /* ADC9 - PINF0 */
				     &altf_adc10_sl   /* ADC10 - PINE0 */
				     &altf_adc11_sl>; /* ADC11 - PINC7 */
			threshold-reg-offset = <0x60>;
		};
	};

	soc-id {
		chip-id = <0x09>;
		revision-reg = <0x0000FFFC 4>;
	};
};