/*
 * Copyright (c) 2021, Kwon Tae-young
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/imx_ccm.h>
#include <dt-bindings/rdc/imx_rdc.h>
#include <dt-bindings/gpio/gpio.h>
#include <mem.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m4";
			reg = <0>;
		};
	};

	soc {
		tcml_code: code@1ffe0000 {
			compatible = "nxp,imx-itcm";
			reg = <0x1ffe0000 DT_SIZE_K(128)>;
			label = "TCML CODE";
		};

		tcmu_sys: memory@20000000 {
			compatible = "nxp,imx-dtcm";
			reg = <0x20000000 DT_SIZE_K(128)>;
			label = "TCMU SYSTEM";
		};

		ocram_code: code@900000 {
			compatible = "nxp,imx-code-bus";
			reg = <0x00900000 DT_SIZE_K(256)>;
			label = "OCRAM CODE";
		};

		ocram_sys: memory@20200000 {
			device_type = "memory";
			compatible = "nxp,imx-sys-bus";
			reg = <0x20200000 DT_SIZE_K(256)>;
			label = "OCRAM SYSTEM";
		};

		ocram_s_code: code@180000 {
			compatible = "nxp,imx-code-bus";
			reg = <0x00180000 DT_SIZE_K(32)>;
			label = "OCRAM_S CODE";
		};

		ocram_s_sys: memory@20180000 {
			device_type = "memory";
			compatible = "nxp,imx-sys-bus";
			reg = <0x20180000 DT_SIZE_K(32)>;
			label = "OCRAM_S SYSTEM";
		};

		gpio1: gpio@30200000 {
			compatible = "nxp,imx-gpio";
			reg = <0x30200000 DT_SIZE_K(64)>;
			interrupts = <64 0>, <65 0>;
			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
					       RDC_DOMAIN_PERM_RW)|\
			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
					       RDC_DOMAIN_PERM_RW))>;
			label = "GPIO_1";
			gpio-controller;
			#gpio-cells = <2>;
			status = "disabled";
		};

		gpio2: gpio@30210000 {
			compatible = "nxp,imx-gpio";
			reg = <0x30210000 DT_SIZE_K(64)>;
			interrupts = <66 0>, <67 0>;
			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
					       RDC_DOMAIN_PERM_RW)|\
			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
					       RDC_DOMAIN_PERM_RW))>;
			label = "GPIO_2";
			gpio-controller;
			#gpio-cells = <2>;
			status = "disabled";
		};

		gpio3: gpio@30220000 {
			compatible = "nxp,imx-gpio";
			reg = <0x30220000 DT_SIZE_K(64)>;
			interrupts = <68 0>, <69 0>;
			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
					       RDC_DOMAIN_PERM_RW)|\
			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
					       RDC_DOMAIN_PERM_RW))>;
			label = "GPIO_3";
			gpio-controller;
			#gpio-cells = <2>;
			status = "disabled";
		};

		gpio4: gpio@30230000 {
			compatible = "nxp,imx-gpio";
			reg = <0x30230000 DT_SIZE_K(64)>;
			interrupts = <70 0>, <71 0>;
			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
					       RDC_DOMAIN_PERM_RW)|\
			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
					       RDC_DOMAIN_PERM_RW))>;
			label = "GPIO_4";
			gpio-controller;
			#gpio-cells = <2>;
			status = "disabled";
		};

		gpio5: gpio@30240000 {
			compatible = "nxp,imx-gpio";
			reg = <0x30240000 DT_SIZE_K(64)>;
			interrupts = <72 0>, <73 0>;
			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
					       RDC_DOMAIN_PERM_RW)|\
			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
					       RDC_DOMAIN_PERM_RW))>;
			label = "GPIO_5";
			gpio-controller;
			#gpio-cells = <2>;
			status = "disabled";
		};

		ccm: ccm@30380000 {
			compatible = "nxp,imx-ccm";
			reg = <0x30380000 DT_SIZE_K(64)>;
			label = "CCM";
			#clock-cells = <3>;
		};

		uart1: uart@30860000 {
			compatible = "nxp,imx-iuart";
			reg = <0x30860000 0x10000>;
			interrupts = <26 3>;
			clocks = <&ccm IMX_CCM_UART1_CLK 0x7c 24>;
			label = "UART_1";
			status = "disabled";
		};

		uart2: uart@30890000 {
			compatible = "nxp,imx-iuart";
			reg = <0x30890000 0x10000>;
			interrupts = <27 3>;
			clocks = <&ccm IMX_CCM_UART2_CLK 0x68 28>;
			label = "UART_2";
			status = "disabled";
		};

		uart3: uart@30880000 {
			compatible = "nxp,imx-iuart";
			reg = <0x30880000 0x10000>;
			interrupts = <28 3>;
			clocks = <&ccm IMX_CCM_UART3_CLK 0x68 12>;
			label = "UART_3";
			status = "disabled";
		};

		uart4: uart@30a60000 {
			compatible = "nxp,imx-iuart";
			reg = <0x30a60000 0x10000>;
			interrupts = <29 3>;
			clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>;
			label = "UART_4";
			status = "disabled";
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <4>;
};