/*
 * Copyright (c) 2020 Alexander Kozhinov <AlexanderKozhinov@yandex.com>
 * SPDX-License-Identifier: Apache-2.0
 */

#include <st/h7/stm32h7.dtsi>

/ {
	soc {
		flash-controller@52002000 {
			flash0: flash@8000000 {
				write-block-size = <32>;
				erase-block-size = <DT_SIZE_K(128)>;
			};
		};

		uart9: serial@40011800 {
			compatible = "st,stm32-uart";
			reg = <0x40011800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
			interrupts = <155 0>;
			status = "disabled";
			label = "UART_9";
		};

		usart10: serial@40011c00 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40011c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
			interrupts = <156 0>;
			status = "disabled";
			label = "UART_10";
		};

		dmamux1: dmamux@40020800 {
			dma-requests= <129>;
		};

		rng: rng@48021800 {
			health-test-magic = <0x17590abc>;
			health-test-config = <0xaa74>;
		};

		ltdc: display-controller@50001000 {
			compatible = "st,stm32-ltdc";
			reg = <0x50001000 0x200>;
			interrupts = <88 0>, <89 0>;
			interrupt-names = "ltdc", "ltdc_er";
			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x000000008>;
			label = "LTDC";
			status = "disabled";
		};
	};

	/* DTCM memory directly coupled to CPU */
	dtcm: memory@20000000 {
		compatible = "zephyr,memory-region", "arm,dtcm";
		reg = <0x20000000 DT_SIZE_K(128)>;
		zephyr,memory-region = "DTCM";
	};

	/* AXI SRAM in D1 domain (AXI bus) */
	sram0: memory@24000000 {
		reg = <0x24000000 DT_SIZE_K(128)>;
		compatible = "mmio-sram";
	};
};