/*
 * Copyright 2020 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <freq.h>
#include <arm64/armv8-a.dtsi>
#include <dt-bindings/clock/imx_ccm.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	chosen {
		zephyr,console = &uart2;
		zephyr,shell-uart = &uart2;
		zephyr,sram = &sram0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <1>;
		};
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>;
		label = "arch_timer";
		interrupt-parent = <&gic>;
	};

	gic: interrupt-controller@38800000 {
		compatible = "arm,gic";
		reg = <0x38800000 0x10000>, /* GIC Dist */
		      <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
		interrupt-controller;
		#interrupt-cells = <4>;
		label = "GIC";
		status = "okay";
	};

	soc {
		ana_pll: ana_pll@30360000 {
			compatible = "nxp,imx-ana";
			reg = <0x30360000 DT_SIZE_K(64)>;
			label = "ANA_PLL";
		};

		ccm: ccm@30380000 {
			compatible = "nxp,imx-ccm";
			reg = <0x30380000 DT_SIZE_K(64)>;
			label = "CCM";
			#clock-cells = <3>;
		};

		uart2: uart@30890000 {
			compatible = "nxp,imx-iuart";
			reg = <0x30890000 DT_SIZE_K(64)>;
			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL 0>;
			interrupt-names = "irq_0";
			interrupt-parent = <&gic>;
			label = "UART_2";
			status = "disabled";
		};

		uart4: uart@30a60000 {
			compatible = "nxp,imx-iuart";
			reg = <0x30a60000 DT_SIZE_K(64)>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL 0>;
			interrupt-names = "irq_0";
			interrupt-parent = <&gic>;
			label = "UART_4";
			status = "disabled";
		};
	};
};