)]}'
{
  "commit": "3754bb27f86bb5c6ee183abe3db672297f4f3e71",
  "tree": "956aee60d8a46f5bdb182e0dc14bea5d71a2705d",
  "parents": [
    "ed8dd0fa63d571f31a64bfb4a4535ff3253c353c"
  ],
  "author": {
    "name": "Yong Cong Sin",
    "email": "ycsin@meta.com",
    "time": "Wed Aug 14 15:01:31 2024 +0800"
  },
  "committer": {
    "name": "Anas Nashif",
    "email": "anas.nashif@intel.com",
    "time": "Mon Sep 02 12:33:36 2024 -0400"
  },
  "message": "Revert \"arch: riscv: ARCH_STACK_PTR_ALIGN should be 4 for RV32E\"\n\nThis reverts commit 87b95be52a62628f19263c738ea2907469fba71c.\n\nSigned-off-by: Yong Cong Sin \u003cycsin@meta.com\u003e\nSigned-off-by: Yong Cong Sin \u003cyongcong.sin@gmail.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2bd19c5f267b47ee851bbd2145b34840cbba7ad5",
      "old_mode": 33188,
      "old_path": "include/zephyr/arch/riscv/arch.h",
      "new_id": "4cdedb700d3261b5446a469c0674bfcf1aabc9df",
      "new_mode": 33188,
      "new_path": "include/zephyr/arch/riscv/arch.h"
    }
  ]
}