| /* SPDX-License-Identifier: Apache-2.0 */ |
| |
| /* SoC level DTS fixup file */ |
| |
| #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS |
| |
| /* CMSDK AHB General Purpose Input/Output (GPIO) */ |
| #define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_40010000_BASE_ADDRESS |
| #define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_40010000_IRQ_0 |
| |
| #define DT_CMSDK_AHB_GPIO1 DT_ARM_CMSDK_GPIO_40011000_BASE_ADDRESS |
| #define DT_IRQ_PORT1_ALL DT_ARM_CMSDK_GPIO_40011000_IRQ_0 |
| |
| #define DT_CMSDK_AHB_GPIO2 DT_ARM_CMSDK_GPIO_40012000_BASE_ADDRESS |
| #define DT_IRQ_PORT2_ALL DT_ARM_CMSDK_GPIO_40012000_IRQ_0 |
| |
| #define DT_CMSDK_AHB_GPIO3 DT_ARM_CMSDK_GPIO_40013000_BASE_ADDRESS |
| #define DT_IRQ_PORT3_ALL DT_ARM_CMSDK_GPIO_40013000_IRQ_0 |
| |
| /* End of SoC Level DTS fixup file */ |
