)]}'
{
  "commit": "3eedfcc21c24ef1a3102f2855b8e728f397f646d",
  "tree": "dbd5413307ef22e7f781bffff32a3147e64ada65",
  "parents": [
    "db54c4c179d524b3cf5e6e890358ac8f9b8b3673"
  ],
  "author": {
    "name": "Fabrice DJIATSA",
    "email": "fabrice.djiatsa-ext@st.com",
    "time": "Thu Oct 16 15:39:39 2025 +0200"
  },
  "committer": {
    "name": "Chris Friedt",
    "email": "chrisfriedt@gmail.com",
    "time": "Wed Oct 22 18:09:14 2025 -0400"
  },
  "message": "drivers: clock_control: stm32: enable clocks for SRAM1 and SRAM2\n\nenables the AHB2 peripheral clocks for SRAM1 and SRAM2\non STM32H7RSX series using LL_AHB2_GRP1_EnableClock.\n\nThese clocks are required to access the corresponding SRAM regions\nduring runtime.\n\nFixes potential access faults when using SRAM1 and SRAM2.\n\nSigned-off-by: Fabrice DJIATSA \u003cfabrice.djiatsa-ext@st.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3b99555d1eead0352d05197b82d7085dc748bf06",
      "old_mode": 33188,
      "old_path": "drivers/clock_control/clock_stm32_ll_h7.c",
      "new_id": "2f0a581d24bec5a71dcba10c27932240d71886cb",
      "new_mode": 33188,
      "new_path": "drivers/clock_control/clock_stm32_ll_h7.c"
    }
  ]
}