)]}'
{
  "commit": "3f5af0052921c061589a255edc7ecee3807f8494",
  "tree": "b37dfdaf0053a7fc5d586f50fcba5d2bf83fd3bf",
  "parents": [
    "14482f09402435dbf087b17522c4e28f8e1ad5fb"
  ],
  "author": {
    "name": "Maciek Borzecki",
    "email": "maciek.borzecki@gmail.com",
    "time": "Thu Mar 03 15:33:04 2016 +0100"
  },
  "committer": {
    "name": "Daniel Kalowsky",
    "email": "daniel.kalowsky@intel.com",
    "time": "Wed Mar 16 18:11:18 2016 +0000"
  },
  "message": "clock_control/stm32f10x: introduce driver for STM32F10x RCC\n\nThe patch adds a driver for STM32F10x series RCC (Reset and Clock\nControl) subsystem.\n\nThe module is primarily responsible for setting up of MCU\u0027s clock\ntree. In particular the driver sets up SYSCLK, PLL (with source\nconfiguration), AHB prescaler, and APB1/APB2 prescalers. As part of this\nfunctionality, the subsystem can enable/disable clock signal for\nparticular peripherals, thus reducing the power consumption of the MCU.\n\nThe driver implements clock control driver API. However, subsystem IDs\nbeing HW specific are exposed in driver public header that must be\nincluded by callers. The driver registers a single device using a common\nname STM32_CLOCK_CONTROL_NAME. The device is initialized at\nthe PRIMARY level with priority 1. This allows the initialization to\ntake place right after SoC initialization routine.\n\nThe driver depends on selection of SOC_STM32F1X config option and is MCU\nspecific.\n\nChange-Id: I8bea5db20726a24bce7b7ffe0b95de543240429a\nOrigin: Original\nSigned-off-by: Maciej Borzecki \u003cmaciek.borzecki@gmail.com\u003e\n",
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