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github
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zephyrproject-rtos
/
zephyr
/
4004475e7fbc93f9e845eca7d4bdf36599260d6c
/
.
/
samples
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modules
/
sof
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boards
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intel_adsp_cavs25.conf
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CONFIG_TIGERLAKE
=
y
CONFIG_INTEL_DMIC
=
y
CONFIG_INTEL_SSP
=
y
CONFIG_INTEL_ALH
=
y
CONFIG_LP_MEMORY_BANKS
=
1
CONFIG_HP_MEMORY_BANKS
=
30
CONFIG_RIMAGE_SIGNING_SCHEMA
=
"tgl"
