)]}'
{
  "commit": "453ee5e782caba77fcd76f3ca1464f7dce88642a",
  "tree": "43685de5b14055270a94807373cba2d1d52f728e",
  "parents": [
    "ea366e9aa317785d25ba61b9147b67cdbb4cdd96"
  ],
  "author": {
    "name": "Alex Porosanu",
    "email": "alexandru.porosanu@nxp.com",
    "time": "Fri Jul 05 11:01:30 2019 +0300"
  },
  "committer": {
    "name": "Maureen Helm",
    "email": "maureen.helm@nxp.com",
    "time": "Wed Aug 07 07:27:51 2019 -0500"
  },
  "message": "soc: riscv32: fix zero-riscy zephyr,flash node\n\nFor OpenVega board, in the case of the Zero Riscy core,\nthe flash partition used for the code and data is the\nM0 ARM core\u0027s 256KB flash region. This is closest to\nthe RISC core.\nThe m0_flash node defines where the interrupt vector\nis located for the Zero Riscy core, and one needs to\nrestrict the application so its interrupt vector is\nplaced accordingly.\n\nFixes: 34b05164662d (\"boards: riscv32: rv32m1_vega:\n                      enable MCUboot for ri5cy core\")\n\nSigned-off-by: Alex Porosanu \u003calexandru.porosanu@nxp.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "5059a00d56dc4b33409dc19bfeae714391e60c0e",
      "old_mode": 33188,
      "old_path": "boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.dts",
      "new_id": "aba70a3273891ed5695ccced6660511b191f6f4b",
      "new_mode": 33188,
      "new_path": "boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.dts"
    }
  ]
}