| /* |
| * Copyright (c) 2017 RnDity Sp. z o.o. |
| * Copyright (c) 2019 Centaur Analytics, Inc |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv6-m.dtsi> |
| #include <zephyr/dt-bindings/clock/stm32f0_clock.h> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| #include <zephyr/dt-bindings/pwm/pwm.h> |
| #include <zephyr/dt-bindings/pwm/stm32_pwm.h> |
| #include <zephyr/dt-bindings/dma/stm32_dma.h> |
| #include <zephyr/dt-bindings/reset/stm32f0_1_3_reset.h> |
| #include <zephyr/dt-bindings/adc/adc.h> |
| #include <freq.h> |
| |
| / { |
| chosen { |
| zephyr,flash-controller = &flash; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m0"; |
| reg = <0>; |
| }; |
| }; |
| |
| sram0: memory@20000000 { |
| compatible = "mmio-sram"; |
| }; |
| |
| clocks { |
| clk_hse: clk-hse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-hse-clock"; |
| status = "disabled"; |
| }; |
| |
| clk_hsi: clk-hsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(8)>; |
| status = "disabled"; |
| }; |
| |
| clk_lse: clk-lse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-lse-clock"; |
| clock-frequency = <32768>; |
| driving-capability = <0>; |
| status = "disabled"; |
| }; |
| |
| clk_lsi: clk-lsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_K(40)>; |
| status = "disabled"; |
| }; |
| |
| pll: pll { |
| #clock-cells = <0>; |
| compatible = "st,stm32f0-pll-clock"; |
| status = "disabled"; |
| }; |
| }; |
| |
| soc { |
| flash: flash-controller@40022000 { |
| compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller"; |
| reg = <0x40022000 0x400>; |
| interrupts = <3 0>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@8000000 { |
| compatible = "st,stm32-nv-flash", "soc-nv-flash"; |
| |
| write-block-size = <2>; |
| /* maximum erase time for a 2K sector */ |
| max-erase-time = <40>; |
| }; |
| }; |
| |
| rcc: rcc@40021000 { |
| compatible = "st,stm32f0-rcc"; |
| #clock-cells = <2>; |
| reg = <0x40021000 0x400>; |
| |
| rctl: reset-controller { |
| compatible = "st,stm32-rcc-rctl"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| exti: interrupt-controller@40010400 { |
| compatible = "st,stm32-exti"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| reg = <0x40010400 0x400>; |
| num-lines = <16>; |
| interrupts = <5 0>, <6 0>, <7 0>; |
| interrupt-names = "line0-1", "line2-3", "line4-15"; |
| line-ranges = <0 2>, <2 2>, <4 12>; |
| }; |
| |
| pinctrl: pin-controller@48000000 { |
| compatible = "st,stm32-pinctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x48000000 0x1800>; |
| |
| gpioa: gpio@48000000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48000000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00020000>; |
| }; |
| |
| gpiob: gpio@48000400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48000400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>; |
| }; |
| |
| gpioc: gpio@48000800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48000800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00080000>; |
| }; |
| |
| gpiod: gpio@48000c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48000c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>; |
| }; |
| |
| gpiof: gpio@48001400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48001400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00400000>; |
| }; |
| }; |
| |
| usart1: serial@40013800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40013800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>; |
| resets = <&rctl STM32_RESET(APB2, 14U)>; |
| interrupts = <27 0>; |
| status = "disabled"; |
| }; |
| |
| usart2: serial@40004400 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; |
| resets = <&rctl STM32_RESET(APB1, 17U)>; |
| interrupts = <28 0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@40005400 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>, |
| /* I2C1 clock source should always be defined, |
| * even for the default value |
| */ |
| <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>; |
| interrupts = <23 0>; |
| interrupt-names = "combined"; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@40005800 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>; |
| interrupts = <24 0>; |
| interrupt-names = "combined"; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@40013000 { |
| compatible = "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>; |
| interrupts = <25 3>; |
| status = "disabled"; |
| }; |
| |
| rtc: rtc@40002800 { |
| compatible = "st,stm32-rtc"; |
| reg = <0x40002800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>; |
| interrupts = <2 0>; |
| prescaler = <32768>; |
| status = "disabled"; |
| }; |
| |
| iwdg: watchdog@40003000 { |
| compatible = "st,stm32-watchdog"; |
| reg = <0x40003000 0x400>; |
| }; |
| |
| wwdg: watchdog@40002c00 { |
| compatible = "st,stm32-window-watchdog"; |
| reg = <0x40002C00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; |
| interrupts = <0 2>; |
| status = "disabled"; |
| }; |
| |
| timers1: timers@40012c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40012c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>; |
| resets = <&rctl STM32_RESET(APB2, 11U)>; |
| interrupts = <13 0>, <14 0>; |
| interrupt-names = "brk_up_trg_com", "cc"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers3: timers@40000400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>; |
| resets = <&rctl STM32_RESET(APB1, 1U)>; |
| interrupts = <16 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers6: timers@40001000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40001000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>; |
| resets = <&rctl STM32_RESET(APB1, 4U)>; |
| interrupts = <17 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| }; |
| |
| timers7: timers@40001400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40001400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>; |
| resets = <&rctl STM32_RESET(APB1, 5U)>; |
| interrupts = <18 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| }; |
| |
| timers14: timers@40002000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40002000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>; |
| resets = <&rctl STM32_RESET(APB1, 8U)>; |
| interrupts = <19 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers15: timers@40014000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>; |
| resets = <&rctl STM32_RESET(APB2, 16U)>; |
| interrupts = <20 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers16: timers@40014400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>; |
| resets = <&rctl STM32_RESET(APB2, 17U)>; |
| interrupts = <21 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers17: timers@40014800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>; |
| resets = <&rctl STM32_RESET(APB2, 18U)>; |
| interrupts = <22 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| adc1: adc@40012400 { |
| compatible = "st,stm32-adc"; |
| reg = <0x40012400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>; |
| interrupts = <12 0>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| temp-channel = <16>; |
| vref-channel = <17>; |
| }; |
| |
| dma1: dma@40020000 { |
| compatible = "st,stm32-dma-v2bis"; |
| #dma-cells = <2>; |
| reg = <0x40020000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>; |
| interrupts = <9 0 10 0 10 0 11 0 11 0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| die_temp: dietemp { |
| compatible = "st,stm32-temp-cal"; |
| ts-cal1-addr = <0x1FFFF7B8>; |
| ts-cal2-addr = <0x1FFFF7C2>; |
| ts-cal1-temp = <30>; |
| ts-cal2-temp = <110>; |
| ts-cal-vrefanalog = <3300>; |
| io-channels = <&adc1 16>; |
| status = "disabled"; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <2>; |
| }; |
