| /* |
| * Copyright (c) 2018 Pushpal Sidhu |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <mem.h> |
| #include <st/l4/stm32l4.dtsi> |
| #include <zephyr/dt-bindings/flash_controller/ospi.h> |
| |
| /delete-node/ &quadspi; |
| |
| / { |
| sram0: memory@20000000 { |
| reg = <0x20000000 DT_SIZE_K(640)>; |
| }; |
| |
| soc { |
| clocks { |
| clk_hsi48: clk-hsi48 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(48)>; |
| status = "disabled"; |
| }; |
| }; |
| |
| flash-controller@40022000 { |
| flash0: flash@8000000 { |
| erase-block-size = <4096>; |
| }; |
| }; |
| |
| rcc: rcc@40021000 { |
| undershoot-prevention; |
| }; |
| |
| rng: rng@50060800 { |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>, |
| <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; |
| }; |
| |
| pinctrl: pin-controller@48000000 { |
| gpiod: gpio@48000c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48000c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>; |
| }; |
| |
| gpioe: gpio@48001000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48001000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>; |
| }; |
| |
| gpiof: gpio@48001400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48001400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>; |
| }; |
| |
| gpiog: gpio@48001800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48001800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>; |
| }; |
| }; |
| |
| usart3: serial@40004800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; |
| resets = <&rctl STM32_RESET(APB1L, 18U)>; |
| interrupts = <39 0>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@40004c00 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40004c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; |
| resets = <&rctl STM32_RESET(APB1L, 19U)>; |
| interrupts = <52 0>; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@40005000 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40005000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>; |
| resets = <&rctl STM32_RESET(APB1L, 20U)>; |
| interrupts = <53 0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@40005800 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>; |
| interrupts = <33 0>, <34 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@40008400 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40008400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>; |
| interrupts = <83 0>, <84 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@40003800 { |
| compatible = "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40003800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>; |
| interrupts = <36 5>; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@40003c00 { |
| compatible = "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40003c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>; |
| interrupts = <51 5>; |
| status = "disabled"; |
| }; |
| |
| timers3: timers@40000400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>; |
| resets = <&rctl STM32_RESET(APB1L, 1U)>; |
| interrupts = <29 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers4: timers@40000800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>; |
| resets = <&rctl STM32_RESET(APB1L, 2U)>; |
| interrupts = <30 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers5: timers@40000c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>; |
| resets = <&rctl STM32_RESET(APB1L, 3U)>; |
| interrupts = <50 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers7: timers@40001400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40001400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>; |
| resets = <&rctl STM32_RESET(APB1L, 5U)>; |
| interrupts = <55 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers8: timers@40013400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40013400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>; |
| resets = <&rctl STM32_RESET(APB2, 13U)>; |
| interrupts = <43 0>, <44 0>, <45 0>, <46 0>; |
| interrupt-names = "brk", "up", "trgcom", "cc"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers17: timers@40014800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>; |
| resets = <&rctl STM32_RESET(APB2, 18U)>; |
| interrupts = <26 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| can1: can@40006400 { |
| compatible = "st,stm32-can"; |
| reg = <0x40006400 0x400>; |
| interrupts = <19 0>, <20 0>, <21 0>, <22 0>; |
| interrupt-names = "TX", "RX0", "RX1", "SCE"; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN |
| status = "disabled"; |
| sjw = <1>; |
| sample-point = <875>; |
| }; |
| |
| usbotg_fs: otgfs@50000000 { |
| compatible = "st,stm32-otgfs"; |
| reg = <0x50000000 0x40000>; |
| interrupts = <67 0>; |
| interrupt-names = "otgfs"; |
| num-bidir-endpoints = <6>; |
| ram-size = <1280>; |
| maximum-speed = "full-speed"; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00001000>, |
| <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; |
| phys = <&otgfs_phy>; |
| status = "disabled"; |
| }; |
| |
| dma1: dma@40020000 { |
| dma-offset = <0>; |
| }; |
| |
| dma2: dma@40020400 { |
| dma-offset = <7>; |
| }; |
| |
| dmamux1: dmamux@40020800 { |
| compatible = "st,stm32-dmamux"; |
| #dma-cells = <3>; |
| reg = <0x40020800 0x400>; |
| interrupts = <94 0>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>; |
| dma-channels = <14>; |
| dma-generators = <4>; |
| dma-requests= <89>; |
| status = "disabled"; |
| }; |
| |
| sdmmc1: sdmmc@50062400 { |
| compatible = "st,stm32-sdmmc"; |
| reg = <0x50062400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x400000>, |
| <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; |
| resets = <&rctl STM32_RESET(AHB2, 22U)>; |
| interrupts = <49 0>; |
| status = "disabled"; |
| }; |
| |
| dac1: dac@40007400 { |
| compatible = "st,stm32-dac"; |
| reg = <0x40007400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| }; |
| |
| octospi1: octospi@a0001000 { |
| compatible = "st,stm32-ospi"; |
| reg = <0xa0001000 0x400>; |
| interrupts = <71 0>; |
| clock-names = "ospix", "ospi-ker", "ospi-mgr"; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>, |
| <&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>, |
| <&rcc STM32_CLOCK_BUS_AHB2 0x00100000>; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| octospi2: octospi@a0001400 { |
| compatible = "st,stm32-ospi"; |
| reg = <0xa0001400 0x400>; |
| interrupts = <76 0>; |
| clock-names = "ospix", "ospi-ker", "ospi-mgr"; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000200>, |
| <&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>, |
| <&rcc STM32_CLOCK_BUS_AHB2 0x00100000>; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| rtc@40002800 { |
| bbram: backup_regs { |
| compatible = "st,stm32-bbram"; |
| st,backup-regs = <32>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| otgfs_phy: otgfs_phy { |
| compatible = "usb-nop-xceiv"; |
| #phy-cells = <0>; |
| }; |
| }; |
