# Copyright (c) 2017 Intel Corporation
# SPDX-License-Identifier: Apache-2.0

config SOC_ESP32
	bool "ESP32"
	select XTENSA
	select CLOCK_CONTROL
	select DYNAMIC_INTERRUPTS
	select ARCH_HAS_GDBSTUB
	select ARCH_SUPPORTS_COREDUMP
	select PINCTRL
	select XIP
	select HAS_ESPRESSIF_HAL
	select CPU_HAS_FPU

if SOC_ESP32

config IDF_TARGET_ESP32
	bool "ESP32 as target board"
	default y

config ESPTOOLPY_FLASHFREQ_80M
	bool
	default y

config FLASH_SIZE
	int
	default $(dt_node_reg_size_int,/soc/flash-controller@3ff42000/flash@0,0)

config FLASH_BASE_ADDRESS
	hex
	default $(dt_node_reg_addr_hex,/soc/flash-controller@3ff42000/flash@0)

config ESP32_NETWORK_CORE
	bool "Uses the ESP32 APP_CPU as Network dedicated core"

config ESP32_BT_RESERVE_DRAM
	hex "Bluetooth controller reserved RAM region"
	default 0xdb5c if BT
	default 0

config ESP_HEAP_MEM_POOL_REGION_1_SIZE
	int "Internal DRAM region 1 mempool size"
	default 1024 if ESP32_NETWORK_CORE
	default 49152
	help
	  ESP32 has two banks of size 192K and 128K which can be used
	  as DRAM, system heap allocates area from region 0.
	  This configuration can be used to add memory from region 1
	  to heap and can be allocated using k_malloc.

config ESP_SPIRAM
	bool "Support for external, SPI-connected RAM"
	help
	  This enables support for an external SPI RAM chip, connected in
	  parallel with the main SPI flash chip.

config ESP_HEAP_MIN_EXTRAM_THRESHOLD
	int "Minimum threshold for external RAM allocation"
	default 8192
	range 1024 131072
	depends on ESP_SPIRAM
	help
	  Threshold to decide if memory will be allocated from DRAM
	  or SPIRAM. If value of allocation size is less than this value,
	  memory will be allocated from internal RAM.

config ESP_HEAP_SEARCH_ALL_REGIONS
	bool "Search for all available heap regions"
	depends on ESP_SPIRAM
	default y
	help
	  This configuration enables searching all available heap
	  regions. If the region of desired capability is exhausted,
	  memory will be allocated from other available region.

menu "SPI RAM config"
	depends on ESP_SPIRAM

choice SPIRAM_TYPE
	prompt "Type of SPI RAM chip in use"
	default SPIRAM_TYPE_ESPPSRAM16

config SPIRAM_TYPE_ESPPSRAM16
	bool "ESP-PSRAM16 or APS1604"

config SPIRAM_TYPE_ESPPSRAM32
	bool "ESP-PSRAM32 or IS25WP032"

config SPIRAM_TYPE_ESPPSRAM64
	bool "ESP-PSRAM64 or LY68L6400"

endchoice # SPIRAM_TYPE

config ESP_SPIRAM_SIZE
	int "Size of SPIRAM part"
	default 2097152 if SPIRAM_TYPE_ESPPSRAM16
	default 4194304 if SPIRAM_TYPE_ESPPSRAM32
	default 8388608 if SPIRAM_TYPE_ESPPSRAM64
	help
	  Specify size of SPIRAM part.
	  NOTE: If SPIRAM size is greater than 4MB, only
	  lower 4MB can be allocated using k_malloc().

choice SPIRAM_SPEED
	prompt "Set RAM clock speed"
	default SPIRAM_SPEED_40M
	help
	  Select the speed for the SPI RAM chip.
	  If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now:

	  1. Flash SPI running at 40MHz and RAM SPI running at 40MHz
	  2. Flash SPI running at 80MHz and RAM SPI running at 40MHz
	  3. Flash SPI running at 80MHz and RAM SPI running at 80MHz

	  Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host
	  will be occupied by the system. Which SPI host to use can be selected by the config item
	  SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The
	  option to select 80MHz will only be visible if the flash SPI speed is also 80MHz.
	  (ESPTOOLPY_FLASHFREQ_79M is true)

config SPIRAM_SPEED_40M
	bool "40MHz clock speed"

config SPIRAM_SPEED_80M
	depends on ESPTOOLPY_FLASHFREQ_80M
	bool "80MHz clock speed"

endchoice # SPIRAM_SPEED

menu "PSRAM clock and cs IO for ESP32-DOWD"

config D0WD_PSRAM_CLK_IO
	int "PSRAM CLK IO number"
	range 0 33
	default 17
	help
	  The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
	  1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.

config D0WD_PSRAM_CS_IO
	int "PSRAM CS IO number"
	range 0 33
	default 16
	help
	  The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
	  1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.

endmenu # PSRAM clock and cs IO for ESP32-DOWD

menu "PSRAM clock and cs IO for ESP32-D2WD"

config D2WD_PSRAM_CLK_IO
	int "PSRAM CLK IO number"
	range 0 33
	default 9
	help
	  User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
	  so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.

config D2WD_PSRAM_CS_IO
	int "PSRAM CS IO number"
	range 0 33
	default 10
	help
	  User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
	  so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.

endmenu # PSRAM clock and cs IO for ESP32-D2WD

menu "PSRAM clock and cs IO for ESP32-PICO"

config PICO_PSRAM_CS_IO
	int "PSRAM CS IO number"
	range 0 33
	default 10
	help
	  The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.

	  For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
	  IO.
	  For the reference hardware design, please refer to
	  https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf

endmenu # PSRAM clock and cs IO for ESP32-PICO

config SPIRAM_CUSTOM_SPIWP_SD3_PIN
	bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
	default y if SPIRAM_SPIWP_SD3_PIN != 7  # backwards compatibility, can remove in IDF 5
	default n
	help
	  This setting is only used if the SPI flash pins have been overridden by setting the eFuses
	  SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT.

	  When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
	  ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
	  mode, so a WP pin setting is necessary.

	  If this config item is set to N (default), the correct WP pin will be automatically used for any
	  Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
	  to Y and specify the GPIO number connected to the WP pin.

	  When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin
	  configured in the bootloader.

config SPIRAM_SPIWP_SD3_PIN
	int "Custom SPI PSRAM WP(SD3) Pin"
	range 0 33
	default 7
	help
	  The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored

	  If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this
	  value to the GPIO number of the SPIRAM WP pin.

config SPIRAM
	bool
	default y

endmenu # SPI RAM config

config ESP_SYSTEM_RTC_EXT_XTAL
	bool

config ESP_SYSTEM_RTC_EXT_OSC
	bool

choice ESP32_RTC_CLK_SRC
	prompt "RTC clock source"
	default ESP32_RTC_CLK_SRC_INT_RC
	help
	  Choose which clock is used as RTC clock source.

	  - "Internal 150kHz oscillator" option provides lowest deep sleep current
	  consumption, and does not require extra external components. However
	  frequency stability with respect to temperature is poor, so time may
	  drift in deep/light sleep modes.
	  - "External 32kHz crystal" provides better frequency stability, at the
	  expense of slightly higher (1uA) deep sleep current consumption.
	  - "External 32kHz oscillator" allows using 32kHz clock generated by an
	  external circuit. In this case, external clock signal must be connected
	  to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal,
	  and <1V in case of square wave signal. Common mode voltage should be
	  0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude.
	  Additionally, 1nF capacitor must be connected between 32K_XP pin and
	  ground. 32K_XP pin can not be used as a GPIO in this case.
	  - "Internal 8.5MHz oscillator divided by 256" option results in higher
	  deep sleep current (by 5uA) but has better frequency stability than
	  the internal 150kHz oscillator. It does not require external components.

config ESP32_RTC_CLK_SRC_INT_RC
	bool "Internal 150kHz RC oscillator"

config ESP32_RTC_CLK_SRC_EXT_CRYS
	bool "External 32kHz crystal"
	select ESP_SYSTEM_RTC_EXT_XTAL

config ESP32_RTC_CLK_SRC_EXT_OSC
	bool "External 32kHz oscillator at 32K_XN pin"
	select ESP_SYSTEM_RTC_EXT_OSC

config ESP32_RTC_CLK_SRC_INT_8MD256
	bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)"

endchoice # ESP32_RTC_CLK_SRC

config ESP32_RTC_CLK_CAL_CYCLES
	int "Number of cycles for RTC_SLOW_CLK calibration"
	default 3000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256
	default 1024 if ESP32_RTC_CLK_SRC_INT_RC
	range 0 27000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256
	range 0 32766 if ESP32_RTC_CLK_SRC_INT_RC
	help
	  When the startup code initializes RTC_SLOW_CLK, it can perform
	  calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
	  frequency. This option sets the number of RTC_SLOW_CLK cycles measured
	  by the calibration routine. Higher numbers increase calibration
	  precision, which may be important for applications which spend a lot of
	  time in deep sleep. Lower numbers reduce startup time.

	  When this option is set to 0, clock calibration will not be performed at
	  startup, and approximate clock frequencies will be assumed:

	  - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
	  - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
	  In case more value will help improve the definition of the launch of the crystal.
	  If the crystal could not start, it will be switched to internal RC.

config ESP32_RTC_XTAL_CAL_RETRY
	int "Number of attempts to repeat 32k XTAL calibration"
	default 1
	depends on ESP32_RTC_CLK_SRC_EXT_CRYS
	help
	  Number of attempts to repeat 32k XTAL calibration
	  before giving up and switching to the internal RC.
	  Increase this option if the 32k crystal oscillator
	  does not start and switches to internal RC.

config ESP32_DEEP_SLEEP_WAKEUP_DELAY
	int "Extra delay in deep sleep wake stub (in us)"
	default 2000
	range 0 5000
	help
	  When ESP32 exits deep sleep, the CPU and the flash chip are powered on
	  at the same time. CPU will run deep sleep stub first, and then
	  proceed to load code from flash. Some flash chips need sufficient
	  time to pass between power on and first read operation. By default,
	  without any extra delay, this time is approximately 900us, although
	  some flash chip types need more than that.

	  By default extra delay is set to 2000us. When optimizing startup time
	  for applications which require it, this value may be reduced.

	  If you are seeing "flash read err, 1000" message printed to the
	  console after deep sleep reset, try increasing this value.

choice ESP32_UNIVERSAL_MAC_ADDRESSES
	bool "Number of universally administered (by IEEE) MAC address"
	default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
	help
	  Configure the number of universally administered (by IEEE) MAC addresses.
	  During initialization, MAC addresses for each network interface are generated or
	  derived from a single base MAC address. If the number of universal MAC addresses is four,
	  all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally
	  administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively)
	  to the final octet of the base MAC address. If the number of universal MAC addresses is two,
	  only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address.
	  These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address.
	  The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses.
	  These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively.
	  When using the default (Espressif-assigned) base MAC address, either setting can be used.
	  When using a custom universal MAC address range, the correct setting will depend on the
	  allocation of MAC addresses in this range (either 2 or 4 per device.)

config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
	bool "Two"
	select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
	select ESP_MAC_ADDR_UNIVERSE_BT

config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
	bool "Four"
	select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
	select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
	select ESP_MAC_ADDR_UNIVERSE_BT
	select ESP_MAC_ADDR_UNIVERSE_ETH

endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES

config ESP_MAC_ADDR_UNIVERSE_WIFI_AP
	bool

config ESP_MAC_ADDR_UNIVERSE_WIFI_STA
	bool

config ESP_MAC_ADDR_UNIVERSE_BT
	bool

config ESP_MAC_ADDR_UNIVERSE_ETH
	bool

config ESP32_UNIVERSAL_MAC_ADDRESSES
	int
	default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
	default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR

config ESP32_PHY_MAX_WIFI_TX_POWER
	int "Max WiFi/BLE TX power (dBm)"
	range 10 20
	default 20
	help
	  Set maximum transmit power for WiFi radio. Actual transmit power for high
	  data rates may be lower than this setting.

config ESP32_PHY_MAX_TX_POWER
	int
	default ESP32_PHY_MAX_WIFI_TX_POWER

config ESP32_EMAC
	bool
	default y if ETH_ESP32
	default y if MDIO_ESP32
	default n
	help
	  Hidden option to enable the ESP32 Ethernet MAC driver.
	  Both Ethernet and MDIO depend on this driver.
	  This option allows enabling MDIO independently of Ethernet.

if ESP32_EMAC

config ETH_DMA_BUFFER_SIZE
	int "Ethernet DMA buffer size (Byte)"
	range 256 1600
	default 512
	help
	  Set the size of each buffer used by Ethernet MAC DMA.

config ETH_DMA_RX_BUFFER_NUM
	int "Amount of Ethernet DMA Rx buffers"
	range 3 30
	default 10
	help
	  Number of DMA receive buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE.
	  Larger number of buffers could increase throughput somehow.

config ETH_DMA_TX_BUFFER_NUM
	int "Amount of Ethernet DMA Tx buffers"
	range 3 30
	default 10
	help
	  Number of DMA transmit buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE.
	  Larger number of buffers could increase throughput somehow.

endif # ESP32_EMAC

endif # SOC_ESP32