/*
 * Copyright (c) 2021 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Warning: This overlay performs configuration from clean sheet.
 * It is assumed that it is applied after clear_clocks.overlay file.
 */

&clk_hsi {
	hsi-div = <1>;		/* HSI RC: 64MHz, hsi_clk = 64MHz */
	status = "okay";
};

&rcc {
	clocks = <&clk_hsi>;
	clock-frequency = <DT_FREQ_M(64)>;
	d1cpre = <1>;
	hpre = <1>;
	d1ppre = <1>;
	d2ppre1 = <1>;
	d2ppre2 = <1>;
	d3ppre = <1>;
};