)]}'
{
  "commit": "4c6ab7cfcd84e28e2804435dc331b5ccdbb96148",
  "tree": "7cd9bd400c10bdbe635bdedad285160d0c69e04b",
  "parents": [
    "cd83e85edc5d741f6b52c6b5995303c30bda443a"
  ],
  "author": {
    "name": "Jean-Paul Etienne",
    "email": "fractalclone@gmail.com",
    "time": "Wed Jan 11 00:24:30 2017 +0100"
  },
  "committer": {
    "name": "Andrew Boie",
    "email": "andrew.p.boie@intel.com",
    "time": "Fri Jan 13 19:53:57 2017 +0000"
  },
  "message": "unified: added _MOVE_INSTR for RISCV32 architecture\n\nadded _MOVE_INSTR for RISCV32 architecture\n\nThe store instruction has a different syntax in RISC-V,\ncompared to the other architectures. Hence, for each\narchitecture, specify the entire load instruction within\nthe _MOVE_INSTR variable.\n\nChange-Id: Iedc421e73411876abd8b698f7d4b46081b473d79\nSigned-off-by: Jean-Paul Etienne \u003cfractalclone@gmail.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "617f0acd0640017b25c88542176669bca9acb6c3",
      "old_mode": 33188,
      "old_path": "kernel/init.c",
      "new_id": "ced665eb53487d26b06eeb52c2c55601781bf86a",
      "new_mode": 33188,
      "new_path": "kernel/init.c"
    }
  ]
}