# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0

if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3

config ESP_SPIRAM
	bool "Support for external, SPI-connected RAM"
	default n if MCUBOOT
	default n if ESP32_USE_UNSUPPORTED_REVISION && SOC_SERIES_ESP32
	select SHARED_MULTI_HEAP
	help
	  This enables support for an external SPI RAM chip, connected in
	  parallel with the main SPI flash chip.

menu "SPI RAM config"
	depends on ESP_SPIRAM

config ESP_HEAP_SEARCH_ALL_REGIONS
	bool "Search for all available heap regions"
	default y
	help
	  This configuration enables searching all available heap
	  regions. If the region of desired capability is exhausted,
	  memory will be allocated from other available region.

config ESP_SPIRAM_HEAP_SIZE
	int "Size of SPIRAM heap"
	default 262134 if SYS_HEAP_SMALL_ONLY
	default 1048576 if !SYS_HEAP_SMALL_ONLY
	help
	  Specify size of SPIRAM heap.

config ESP_SPIRAM_MEMTEST
	bool "Run memory test on SPI RAM initialization"
	default y
	help
	  Runs a memory test on initialization. Disable this for faster startup.

choice SPIRAM_MODE
	prompt "Mode (QUAD/OCT) of SPI RAM chip in use"
	default SPIRAM_MODE_QUAD

	config SPIRAM_MODE_QUAD
		bool "Quad Mode PSRAM"

	config SPIRAM_MODE_OCT
		bool "Octal Mode PSRAM"
		depends on SOC_SERIES_ESP32S3

endchoice # SPIRAM_MODE

choice SPIRAM_TYPE
	prompt "Type of SPI RAM chip in use"
	default SPIRAM_TYPE_ESPPSRAM16 if SPIRAM_MODE_QUAD
	default SPIRAM_TYPE_ESPPSRAM64

config SPIRAM_TYPE_ESPPSRAM16
	bool "ESP-PSRAM16 or APS1604"
	depends on SPIRAM_MODE_QUAD

config SPIRAM_TYPE_ESPPSRAM32
	bool "ESP-PSRAM32 or IS25WP032"
	depends on SPIRAM_MODE_QUAD

config SPIRAM_TYPE_ESPPSRAM64
	bool "ESP-PSRAM64, LY68L6400 or APS6408"

endchoice # SPIRAM_TYPE

config ESP_SPIRAM_SIZE
	int "Size of SPIRAM part"
	default 2097152 if SPIRAM_TYPE_ESPPSRAM16
	default 4194304 if SPIRAM_TYPE_ESPPSRAM32
	default 8388608 if SPIRAM_TYPE_ESPPSRAM64
	help
	  Specify size of SPIRAM part.
	  NOTE: If SPIRAM size is greater than 4MB, only
	  lower 4MB can be allocated using k_malloc().

choice SPIRAM_SPEED
	prompt "Set RAM clock speed"
	default SPIRAM_SPEED_40M
	help
	  Select the speed for the SPI RAM chip.

config SPIRAM_SPEED_20M
	bool "20MHz clock speed"
	depends on SOC_SERIES_ESP32S2

config SPIRAM_SPEED_26M
	bool "26MHz clock speed"
	depends on SOC_SERIES_ESP32S2

config SPIRAM_SPEED_40M
	bool "40MHz clock speed"

config SPIRAM_SPEED_80M
	bool "80MHz clock speed"
	depends on ESPTOOLPY_FLASHFREQ_80M

config SPIRAM_SPEED_120M
	bool "120MHz clock speed"
	depends on SPIRAM_MODE_QUAD && SOC_SERIES_ESP32S3

endchoice # SPIRAM_SPEED

config SPIRAM_SPEED
	int
	default 120 if SPIRAM_SPEED_120M
	default 80 if SPIRAM_SPEED_80M
	default 40 if SPIRAM_SPEED_40M || SPIRAM_SPEED_26M || SPIRAM_SPEED_20M

config SPIRAM_CLK_IO
	int
	depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
	default 30

config SPIRAM_CS_IO
	int
	depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
	default 26

config SPIRAM_FETCH_INSTRUCTIONS
	bool "Move Instructions in Flash to PSRAM"
	depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
	default n
	help
	  If enabled, instructions in flash will be moved into PSRAM on startup.
	  If SPIRAM_RODATA is also enabled, code that requires execution during an SPI1 Flash operation
	  can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation
	  for more details).

config SPIRAM_RODATA
	bool "Move Read-Only Data in Flash to PSRAM"
	depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
	default n
	help
	  If enabled, rodata in flash will be moved into PSRAM on startup.
	  If SPIRAM_FETCH_INSTRUCTIONS is also enabled, code that requires execution during an SPI1 Flash operation
	  can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation
	  for more details).

config SPIRAM_ECC_ENABLE
	bool "Allow enabling SPI RAM ECC"
	default n
	depends on SPIRAM_MODE_OCT && SOC_SERIES_ESP32S3
	help
	  Enable MSPI Error-Correcting Code function when accessing SPIRAM.
	  If enabled, 1/16 of the SPI RAM total size will be reserved for error-correcting code.

if SOC_SERIES_ESP32

menu "PSRAM clock and cs IO for ESP32-DOWD"

config D0WD_PSRAM_CLK_IO
	int "PSRAM CLK IO number"
	range 0 33
	default 17
	help
	  The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
	  1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.

config D0WD_PSRAM_CS_IO
	int "PSRAM CS IO number"
	range 0 33
	default 16
	help
	  The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
	  1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.

endmenu # PSRAM clock and cs IO for ESP32-DOWD

menu "PSRAM clock and cs IO for ESP32-D2WD"

config D2WD_PSRAM_CLK_IO
	int "PSRAM CLK IO number"
	range 0 33
	default 9
	help
	  User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
	  so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.

config D2WD_PSRAM_CS_IO
	int "PSRAM CS IO number"
	range 0 33
	default 10
	help
	  User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
	  so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.

endmenu # PSRAM clock and cs IO for ESP32-D2WD

menu "PSRAM clock and cs IO for ESP32-PICO"

config PICO_PSRAM_CS_IO
	int "PSRAM CS IO number"
	range 0 33
	default 10
	help
	  The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.

	  For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
	  IO For the reference hardware design, please refer to
	  https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf

endmenu # PSRAM clock and cs IO for ESP32-PICO

config SPIRAM_CUSTOM_SPIWP_SD3_PIN
	bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
	depends on ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT
	default n
	help
	  This setting is only used if the SPI flash pins have been overridden by setting the eFuses
	  SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT.

	  When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
	  ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
	  mode, so a WP pin setting is necessary.

	  If this config item is set to N (default), the correct WP pin will be automatically used for any
	  Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
	  to Y and specify the GPIO number connected to the WP pin.

	  When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin
	  configured in the bootloader.

config SPIRAM_SPIWP_SD3_PIN
	int "Custom SPI PSRAM WP(SD3) Pin"
	depends on SPIRAM_CUSTOM_SPIWP_SD3_PIN
	range 0 33
	default 7
	help
	  The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored

	  If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this
	  value to the GPIO number of the SPIRAM WP pin.

endif # SOC_SERIES_ESP32

endmenu # ESP_SPIRAM

endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3