)]}'
{
  "commit": "5a11caba336c57445585911b52a231de9fdfc6cb",
  "tree": "58e78040fbcefaa436f124e5456f40732d0e3bdb",
  "parents": [
    "0ee896117cb55c5d83ba069f30cf97c22e9d4ce3"
  ],
  "author": {
    "name": "Daniel Leung",
    "email": "daniel.leung@intel.com",
    "time": "Wed Feb 03 14:30:27 2021 -0800"
  },
  "committer": {
    "name": "Anas Nashif",
    "email": "anas.nashif@intel.com",
    "time": "Fri Feb 05 07:45:07 2021 -0500"
  },
  "message": "xtensa: fix rsr/wsr assembly for XCC\n\nXCC doesn\u0027t like the \"rsr.\u003creg name\u003e\" style assembly\nso fix that to the other style.\n\nAlso, XCC doesn\u0027t like _CONCAT() with the EPC/EPS\nregisters so need to spell out all of them.\n\nSigned-off-by: Daniel Leung \u003cdaniel.leung@intel.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0c4a25614e8bc15eb6235a418a79c3cf448ee409",
      "old_mode": 33188,
      "old_path": "arch/xtensa/core/xtensa-asm2-util.S",
      "new_id": "a6e50cc2d0c549a865b3b832414e735ff8c76895",
      "new_mode": 33188,
      "new_path": "arch/xtensa/core/xtensa-asm2-util.S"
    }
  ]
}