/*
 * Copyright (c) 2019 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;
#include <st/h7/stm32h747Xi_m7.dtsi>
#include <st/h7/stm32h747xihx-pinctrl.dtsi>
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
#include "stm32h747i_disco.dtsi"

/ {
	model = "STMicroelectronics STM32H747I DISCOVERY board";
	compatible = "st,stm32h747i-disco";

	/* HW resources are split between CM7 and CM4 */
	chosen {
		zephyr,console = &usart1;
		zephyr,shell-uart = &usart1;
		zephyr,sram = &sram0;
		zephyr,flash = &flash0;
		zephyr,flash-controller = &mt25ql512ab1;
	};

	sdram2: sdram@d0000000 {
		compatible = "zephyr,memory-region", "mmio-sram";
		device_type = "memory";
		reg = <0xd0000000 DT_SIZE_M(32)>;
		zephyr,memory-region = "SDRAM2";
		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
	};

	leds {
		green_led_1:led_1 {
			status = "okay";
		};
		orange_led_2:led_2 {
			status = "okay";
		};
	};

	gpio_keys {
		wake_up: button {
			status = "okay";
		};
	};

	otghs_ulpi_phy: otghs_ulpis_phy {
		compatible = "usb-ulpi-phy";
		#phy-cells = <0>;
	};

	aliases {
		led0 = &green_led_1;
		led1 = &orange_led_2;
		sw0 = &wake_up;
		spi-flash0 = &mt25ql512ab1;
	};
};

&clk_hse {
	clock-frequency = <DT_FREQ_M(25)>;
	status = "okay";
};

&clk_hsi48 {
	status = "okay";
};

&pll {
	div-m = <5>;
	mul-n = <160>;
	div-p = <2>;
	div-q = <4>;
	div-r = <2>;
	clocks = <&clk_hse>;
	status = "okay";
};

&pll2 {
	div-m = <5>;
	mul-n = <96>;
	div-p = <2>;
	div-q = <4>;
	div-r = <10>;
	clocks = <&clk_hse>;  /* Assuming 25MHz HSE */
	status = "okay";
};

&rcc {
	clocks = <&pll>;
	clock-frequency = <DT_FREQ_M(400)>;
};

&usart1 {
	status = "okay";
};

&uart8 {
	/* status = "okay"; */
};

&spi5 {
	status = "okay";
};

&flash0 {
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		/* Set 2KB of storage at the end of first 1MB flash */
		storage_partition: partition@ff800 {
			label = "storage";
			reg = <0x000ff800 DT_SIZE_K(2)>;
		};
	};
};

&mac {
	/*
	 * From UM2411 Rev 4:
	 * With the default setting, the Ethernet feature is not working due
	 * of a pin conflict between ETH_MDC and SAI4_D1 of the MEMs digital
	 * microphone.
	 * Cf Ethernet section in board documentation for more information on
	 * the hw modification to be done to enable it.
	 */
	status = "okay";
	pinctrl-0 = <&eth_ref_clk_pa1
		     &eth_mdio_pa2
		     &eth_crs_dv_pa7
		     &eth_mdc_pc1
		     &eth_rxd0_pc4
		     &eth_rxd1_pc5
		     &eth_tx_en_pg11
		     &eth_txd0_pg13
		     &eth_txd1_pg12>;
	pinctrl-names = "default";
};

&rng {
	status = "okay";
};

&fmc {
	status = "okay";
	pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4 &fmc_nbl3_pi5
		     &fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke1_ph7
		     &fmc_sdne1_ph6 &fmc_sdnras_pf11 &fmc_sdncas_pg15
		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
		     &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
		     &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 &fmc_a12_pg2
		     &fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
		     &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
		     &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
		     &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
		     &fmc_d15_pd10 &fmc_d16_ph8 &fmc_d17_ph9 &fmc_d18_ph10
		     &fmc_d19_ph11 &fmc_d20_ph12 &fmc_d21_ph13 &fmc_d22_ph14
		     &fmc_d23_ph15 &fmc_d24_pi0 &fmc_d25_pi1 &fmc_d26_pi2
		     &fmc_d27_pi3 &fmc_d28_pi6 &fmc_d29_pi7 &fmc_d30_pi9
		     &fmc_d31_pi10>;
	pinctrl-names = "default";

	sdram {
		status = "okay";

		power-up-delay = <100>;
		num-auto-refresh = <8>;
		mode-register = <0x220>;
		refresh-rate = <603>;

		bank@1 {
			reg = <1>;

			st,sdram-control = <STM32_FMC_SDRAM_NC_9
					    STM32_FMC_SDRAM_NR_12
					    STM32_FMC_SDRAM_MWID_32
					    STM32_FMC_SDRAM_NB_4
					    STM32_FMC_SDRAM_CAS_2
					    STM32_FMC_SDRAM_SDCLK_PERIOD_2
					    STM32_FMC_SDRAM_RBURST_ENABLE
					    STM32_FMC_SDRAM_RPIPE_0>;
			st,sdram-timing = <2 6 4 6 2 2 2>;
		};
	};
};

zephyr_udc0: &usbotg_hs {
	pinctrl-0 = <&usb_otg_hs_ulpi_ck_pa5
			&usb_otg_hs_ulpi_d0_pa3
			&usb_otg_hs_ulpi_d1_pb0
			&usb_otg_hs_ulpi_d2_pb1
			&usb_otg_hs_ulpi_d3_pb10
			&usb_otg_hs_ulpi_d4_pb11
			&usb_otg_hs_ulpi_d5_pb12
			&usb_otg_hs_ulpi_d6_pb13
			&usb_otg_hs_ulpi_d7_pb5
			&usb_otg_hs_ulpi_stp_pc0
			&usb_otg_hs_ulpi_dir_pi11
			&usb_otg_hs_ulpi_nxt_ph4>;
	pinctrl-names = "default";
	maximum-speed = "high-speed";
	/* Include the USB1ULPIEN clock enable bit */
	clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x06000000>,
		 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
	phys = <&otghs_ulpi_phy>;
	status = "okay";
};

&sdmmc1 {
	status = "okay";
	clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00010000>,
			<&rcc STM32_SRC_PLL2_R SDMMC_SEL(1)>;
	pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
			&sdmmc1_d2_pc10 &sdmmc1_d3_pc11
			&sdmmc1_d4_pb8 &sdmmc1_d5_pb9
			&sdmmc1_d6_pc6 &sdmmc1_d7_pc7
			&sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
	pinctrl-names = "default";
	cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;
};

&quadspi {
	pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pg6
		     &quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pf9
		     &quadspi_bk1_io2_pf7 &quadspi_bk1_io3_pf6
		     &quadspi_bk2_io0_ph2 &quadspi_bk2_io1_ph3
		     &quadspi_bk2_io2_pg9 &quadspi_bk2_io3_pg14>;
	pinctrl-names = "default";
	status = "okay";

	mt25ql512ab1: qspi-nor-flash-1@90000000 {
		compatible = "st,stm32-qspi-nor";
		reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
		qspi-max-frequency = <72000000>;
		spi-bus-width = <4>;
		status = "okay";

		partitions {
			   compatible = "fixed-partitions";
			   #address-cells = <1>;
			   #size-cells = <1>;

			   partition@0 {
			       reg = <0x0 DT_SIZE_M(64)>;
			   };
		};
	};

	mt25ql512ab2: qspi-nor-flash-2@90000000 {
		compatible = "st,stm32-qspi-nor";
		reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
		qspi-max-frequency = <72000000>;
		status = "okay";
	};
};

arduino_spi: &spi5 {};