/*
 * Copyright 2022-2024 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
#include <dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/power/nxp_rw_pmu.h>

/ {
	chosen {
		zephyr,entropy = &trng;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-m33f";
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <1>;

			mpu: mpu@e000ed90 {
				compatible = "arm,armv8m-mpu";
				reg = <0xe000ed90 0x40>;
			};
		};
	};
};

&sram {
	#address-cells = <1>;
	#size-cells = <1>;

	sram_data: memory@20000000 {
		compatible = "mmio-sram";
		reg = <0x20040000 DT_SIZE_K(960)>;
	};

	sram_code: memory@0 {
		compatible = "mmio-sram";
		reg = <0x00000000 DT_SIZE_K(256)>;
	};
};

&peripheral {
	#address-cells = <1>;
	#size-cells = <1>;

	clkctl0: clkctl@1000 {
		compatible = "nxp,lpc-syscon";
		reg = <0x1000 0x1000>;
		#clock-cells = <1>;
	};

	pinctrl: mci_iomux@4000 {
		compatible = "nxp,mci-io-mux";
		reg = <0x4000 0x1000>;
		status = "okay";
	};

	clkctl1: clkctl@21000 {
		compatible = "nxp,lpc-syscon";
		reg = <0x21000 0x1000>;
		#clock-cells = <1>;
	};

	pmu: pmu@31000 {
		reg = <0x31000 0x130>;
		compatible = "nxp,rw-pmu";
	};

	trng: random@14000 {
		compatible = "nxp,kinetis-trng";
		reg = <0x14000 0x1000>;
		status = "okay";
		interrupts = <123 0>;
	};

	wwdt: watchdog@e000 {
		compatible = "nxp,lpc-wwdt";
		reg = <0xe000 0x1000>;
		interrupts = <0 0>;
		status = "disabled";
		clk-divider = <1>;
	};

	hsgpio0: hsgpio@0 {
		compatible = "nxp,lpc-gpio";
		reg = <0x100000 0x4000>;
		gpio-controller;
		#gpio-cells = <2>;
		port = <0>;
		int-source = "pint";
	};

	hsgpio1: hsgpio@1 {
		compatible = "nxp,lpc-gpio";
		reg = <0x100000 0x4000>;
		gpio-controller;
		#gpio-cells = <2>;
		port = <1>;
		int-source = "pint";
	};

	flexcomm0: flexcomm@106000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x106000 0x1000>;
		interrupts = <14 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>;
		dmas = <&dma0 0>, <&dma0 1>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	flexcomm1: flexcomm@107000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x107000 0x1000>;
		interrupts = <15 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>;
		dmas = <&dma0 2>, <&dma0 3>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	flexcomm2: flexcomm@108000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x108000 0x1000>;
		interrupts = <16 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK>;
		dmas = <&dma0 4>, <&dma0 5>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	flexcomm3: flexcomm@109000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x109000 0x1000>;
		interrupts = <17 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>;
		dmas = <&dma0 6>, <&dma0 7>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	flexcomm14: flexcom@126000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x126000 0x2000>;
		interrupts = <20 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM14_CLK>;
		dmas = <&dma0 26>, <&dma0 27>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	aon_soc_ctrl: aon_soc_ctrl@5000800 {
		compatible = "nxp,rw-soc-ctrl";
		reg = <0x5000800 0x1000>;
		status = "okay";
	};

	soc_ctrl: soc_ctrl@5001000 {
		compatible = "nxp,rw-soc-ctrl";
		reg = <0x5001000 0x1000>;
		status = "okay";
	};

	pint: pint@25000 {
		compatible = "nxp,pint";
		reg = <0x25000 0x1000>;
		interrupt-controller;
		#interrupt-cells = <1>;
		#address-cells = <0>;
		interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
			<35 2>, <36 2>, <37 2>, <38 2>;
		num-lines = <8>;
		num-inputs = <64>;
	};

	dma0: dma-controller@104000 {
		compatible = "nxp,lpc-dma";
		reg = <0x104000 0x1000>;
		interrupts = <1 0>;
		status = "disabled";
		#dma-cells = <1>;
		dma-channels = <33>;
	};

	ctimer0: ctimer@28000 {
		compatible = "nxp,lpc-ctimer";
		reg = <0x28000 0x1000>;
		interrupts = <10 0>;
		status = "disabled";
		clk-source = <1>;
		clocks = <&clkctl1 MCUX_CTIMER0_CLK>;
		mode = <0>;
		input = <0>;
		prescale = <0>;
	};

	ctimer1: ctimer@29000 {
		compatible = "nxp,lpc-ctimer";
		reg = <0x29000 0x1000>;
		interrupts = <11 0>;
		status = "disabled";
		clk-source = <1>;
		clocks = <&clkctl1 MCUX_CTIMER1_CLK>;
		mode = <0>;
		input = <0>;
		prescale = <0>;
	};

	ctimer2: ctimer@2a000 {
		compatible = "nxp,lpc-ctimer";
		reg = <0x2a000 0x1000>;
		interrupts = <39 0>;
		status = "disabled";
		clk-source = <1>;
		clocks = <&clkctl1 MCUX_CTIMER2_CLK>;
		mode = <0>;
		input = <0>;
		prescale = <0>;
	};

	ctimer3: ctimer@2b000 {
		compatible = "nxp,lpc-ctimer";
		reg = <0x2b000 0x1000>;
		interrupts = <13 0>;
		status = "disabled";
		clk-source = <1>;
		clocks = <&clkctl1 MCUX_CTIMER3_CLK>;
		mode = <0>;
		input = <0>;
		prescale = <0>;
	};

	mrt0: mrt@2d000 {
		compatible = "nxp,mrt";
		reg = <0x2d000 0x100>;
		interrupts = <9 0>;
		num-channels = <4>;
		num-bits = <24>;
		clocks = <&clkctl1 MCUX_MRT_CLK>;
		#address-cells = <1>;
		#size-cells = <0>;

		mrt0_channel0: mrt0_channel@0 {
			compatible = "nxp,mrt-channel";
			reg = <0>;
			status = "disabled";
		};
		mrt0_channel1: mrt0_channel@1 {
			compatible = "nxp,mrt-channel";
			reg = <1>;
			status = "disabled";
		};
		mrt0_channel2: mrt0_channel@2 {
			compatible = "nxp,mrt-channel";
			reg = <2>;
			status = "disabled";
		};
		mrt0_channel3: mrt0_channel@3 {
			compatible = "nxp,mrt-channel";
			reg = <3>;
			status = "disabled";
		};
	};

	mrt1: mrt@3f000 {
		compatible = "nxp,mrt";
		reg = <0x3f000 0x100>;
		interrupts = <23 0>;
		num-channels = <4>;
		num-bits = <24>;
		clocks = <&clkctl1 MCUX_FREEMRT_CLK>;
		#address-cells = <1>;
		#size-cells = <0>;

		mrt1_channel0: mrt1_channel@0 {
			compatible = "nxp,mrt-channel";
			reg = <0>;
			status = "disabled";
		};
		mrt1_channel1: mrt1_channel@1 {
			compatible = "nxp,mrt-channel";
			reg = <1>;
			status = "disabled";
		};
		mrt1_channel2: mrt1_channel@2 {
			compatible = "nxp,mrt-channel";
			reg = <2>;
			status = "disabled";
		};
		mrt1_channel3: mrt1_channel@3 {
			compatible = "nxp,mrt-channel";
			reg = <3>;
			status = "disabled";
		};
	};

	dmic0: dmic@121000 {
		#address-cells=<1>;
		#size-cells=<0>;
		compatible = "nxp,dmic";
		reg = <0x121000 0x1000>;
		interrupts = <25 0>;
		status = "disabled";
		clocks = <&clkctl1 MCUX_DMIC_CLK>;

		pdmc0: dmic-channel@0 {
			reg = <0>;
			compatible = "nxp,dmic-channel";
			dmas = <&dma0 16>;
			status = "disabled";
		};

		pdmc1: dmic-channel@1 {
			reg = <1>;
			compatible = "nxp,dmic-channel";
			dmas = <&dma0 17>;
			status = "disabled";
		};

		pdmc2: dmic-channel@2 {
			reg = <2>;
			compatible = "nxp,dmic-channel";
			dmas = <&dma0 18>;
			status = "disabled";
		};

		pdmc3: dmic-channel@3 {
			reg = <3>;
			compatible = "nxp,dmic-channel";
			dmas = <&dma0 19>;
			status = "disabled";
		};
	};

};

&flexspi {
	compatible = "nxp,imx-flexspi";
	status = "disabled";
	interrupts = <42 0>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&clkctl1 MCUX_FLEXSPI_CLK>;
};

&nvic {
	arm,num-irq-priority-bits = <3>;
};