)]}'
{
  "commit": "627fa91e42fb3d1cd0b156c1a89f9600a455dc35",
  "tree": "0eb4ee67893cccaa45ffea77e9c218f50bbbdd23",
  "parents": [
    "62b1e1c28d0dc14047ec32764a3983016877513a"
  ],
  "author": {
    "name": "Etienne Carriere",
    "email": "etienne.carriere@st.com",
    "time": "Fri Oct 24 12:34:19 2025 +0200"
  },
  "committer": {
    "name": "Chris Friedt",
    "email": "chrisfriedt@gmail.com",
    "time": "Fri Oct 31 10:38:25 2025 -0400"
  },
  "message": "boards: st: correct RAM and/or Flash size in YAML board description\n\nFix several RAM size that are wrong regarding what is defined in the\nrelated board device tree.\n\nIn many cases, SoC DTSI files have been changed to split internal RAMs\nand related boards YAML file was not updated accordingly. This is the\ncase of H5xx, H7xx\n\nIn the case of stm32g081b_eval, polarity bytes are not default enabled\nhence the internal SRAM size of 36kB, not 32kB.\n\nStm32mp135f was wrongly set with 256KB RAM and Flash whereas the board\nassigns 256MB for each.\n\nStm32mp157c_dk2 assigned SRAM1, SRAM2 and SRAM3 to Zephyr hence\nproviding 320kB of system RAM.\n\nFix several typos setting RAM size to 786 whereas 768 is expected.\n\nSigned-off-by: Etienne Carriere \u003cetienne.carriere@st.com\u003e\n",
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