| /* |
| * Copyright (c) 2024 Analog Devices, Inc. |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv7-m.dtsi> |
| #include <adi/max32/max32xxx.dtsi> |
| #include <zephyr/dt-bindings/dma/max32672_dma.h> |
| |
| &sram0 { |
| reg = <0x20000000 DT_SIZE_K(16)>; |
| }; |
| |
| &clk_inro { |
| clock-frequency = <DT_FREQ_K(80)>; |
| }; |
| |
| &i2c2 { |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS1 21>; |
| }; |
| |
| /delete-node/ &clk_iso; |
| |
| /delete-node/ &rtc_counter; |
| |
| &adc { |
| compatible = "adi,max32-adc-sar", "adi,max32-adc"; |
| clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; |
| clock-divider = <16>; |
| channel-count = <16>; |
| track-count = <4>; |
| idle-count = <0>; |
| vref-mv = <1250>; |
| resolution = <12>; |
| }; |
| |
| /* MAX32672 extra peripherals. */ |
| / { |
| soc { |
| sram1: memory@20004000 { |
| compatible = "mmio-sram"; |
| reg = <0x20004000 DT_SIZE_K(16)>; |
| }; |
| |
| sram2: memory@20008000 { |
| compatible = "mmio-sram"; |
| reg = <0x20008000 DT_SIZE_K(64)>; |
| }; |
| |
| sram3: memory@20018000 { |
| compatible = "mmio-sram"; |
| reg = <0x20018000 DT_SIZE_K(64)>; |
| }; |
| |
| sram4: memory@20028000 { |
| compatible = "mmio-sram"; |
| reg = <0x20028000 DT_SIZE_K(4)>; |
| }; |
| |
| sram5: memory@20029000 { |
| compatible = "mmio-sram"; |
| reg = <0x20029000 DT_SIZE_K(4)>; |
| }; |
| |
| sram6: memory@2002a000 { |
| compatible = "mmio-sram"; |
| reg = <0x2002a000 DT_SIZE_K(16)>; |
| }; |
| |
| sram7: memory@2002e000 { |
| compatible = "mmio-sram"; |
| reg = <0x2002e000 DT_SIZE_K(16)>; |
| }; |
| |
| flc1: flash_controller@40029400 { |
| compatible = "adi,max32-flash-controller"; |
| reg = <0x40029400 0x400>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| status = "okay"; |
| |
| flash1: flash@10080000 { |
| compatible = "soc-nv-flash"; |
| reg = <0x10080000 DT_SIZE_K(512)>; |
| write-block-size = <16>; |
| erase-block-size = <8192>; |
| }; |
| }; |
| |
| uart3: serial@40145000 { |
| compatible = "adi,max32-uart"; |
| reg = <0x40145000 0x1000>; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS2 2>; |
| clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; |
| interrupts = <88 0>; |
| status = "disabled"; |
| }; |
| |
| dma0: dma@40028000 { |
| compatible = "adi,max32-dma"; |
| reg = <0x40028000 0x1000>; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>; |
| interrupts = <28 0>, <29 0>, <30 0>, <31 0>, <68 0>, <69 0>, <70 0>, <71 0>, |
| <72 0>, <73 0>, <74 0>, <75 0>; |
| dma-channels = <12>; |
| status = "disabled"; |
| #dma-cells = <2>; |
| }; |
| |
| wdt1: watchdog@40003400 { |
| compatible = "adi,max32-watchdog"; |
| reg = <0x40003400 0x400>; |
| interrupts = <57 0>; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS1 5>; |
| clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; |
| status = "disabled"; |
| }; |
| |
| spi0: spi@40046000 { |
| compatible = "adi,max32-spi"; |
| reg = <0x40046000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>; |
| interrupts = <16 0>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@40047000 { |
| compatible = "adi,max32-spi"; |
| reg = <0x40047000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>; |
| interrupts = <17 0>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@40048000 { |
| compatible = "adi,max32-spi"; |
| reg = <0x40048000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS0 8>; |
| interrupts = <18 0>; |
| status = "disabled"; |
| }; |
| |
| lptimer0: timer@40114000 { |
| compatible = "adi,max32-timer"; |
| reg = <0x40114000 0x1000>; |
| interrupts = <9 0>; |
| status = "disabled"; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>; |
| clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; |
| prescaler = <1>; |
| |
| counter { |
| compatible = "adi,max32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| lptimer1: timer@40115000 { |
| compatible = "adi,max32-timer"; |
| reg = <0x40115000 0x1000>; |
| interrupts = <10 0>; |
| status = "disabled"; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS2 1>; |
| clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; |
| prescaler = <1>; |
| |
| counter { |
| compatible = "adi,max32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| rtc_counter: rtc_counter@40106000 { |
| compatible = "adi,max32-rtc-counter"; |
| reg = <0x40106000 0x400>; |
| interrupts = <3 0>; |
| status = "disabled"; |
| }; |
| }; |
| }; |