/* SoC level DTS fixup file */

#define CONFIG_UART_QMSI_0_BAUDRATE	INTEL_QMSI_UART_B0002000_CURRENT_SPEED
#define CONFIG_UART_QMSI_0_NAME		INTEL_QMSI_UART_B0002000_LABEL
#define CONFIG_UART_QMSI_0_IRQ		INTEL_QMSI_UART_B0002000_IRQ_0
#define CONFIG_UART_QMSI_0_IRQ_PRI	INTEL_QMSI_UART_B0002000_IRQ_0_PRIORITY

#define CONFIG_UART_QMSI_1_BAUDRATE	INTEL_QMSI_UART_B0002400_CURRENT_SPEED
#define CONFIG_UART_QMSI_1_NAME		INTEL_QMSI_UART_B0002400_LABEL
#define CONFIG_UART_QMSI_1_IRQ		INTEL_QMSI_UART_B0002400_IRQ_0
#define CONFIG_UART_QMSI_1_IRQ_PRI	INTEL_QMSI_UART_B0002400_IRQ_0_PRIORITY

#define SRAM_START			CONFIG_SRAM_BASE_ADDRESS
#define SRAM_SIZE			CONFIG_SRAM_SIZE

#define FLASH_START			CONFIG_FLASH_BASE_ADDRESS
#define FLASH_SIZE      		CONFIG_FLASH_SIZE

#define CONFIG_DCCM_BASE_ADDRESS       ARC_DCCM_80000000_BASE_ADDRESS
#define CONFIG_DCCM_SIZE               (ARC_DCCM_80000000_SIZE >> 10)

#define CONFIG_I2C_SS_0_NAME		INTEL_QMSI_SS_I2C_80012000_LABEL
#define CONFIG_I2C_SS_0_ERR_IRQ		INTEL_QMSI_SS_I2C_80012000_IRQ_ERROR
#define CONFIG_I2C_SS_0_ERR_IRQ_PRI	INTEL_QMSI_SS_I2C_80012000_IRQ_ERROR_PRIORITY
#define CONFIG_I2C_SS_0_RX_IRQ		INTEL_QMSI_SS_I2C_80012000_IRQ_RX
#define CONFIG_I2C_SS_0_RX_IRQ_PRI	INTEL_QMSI_SS_I2C_80012000_IRQ_RX_PRIORITY
#define CONFIG_I2C_SS_0_TX_IRQ		INTEL_QMSI_SS_I2C_80012000_IRQ_TX
#define CONFIG_I2C_SS_0_TX_IRQ_PRI	INTEL_QMSI_SS_I2C_80012000_IRQ_TX_PRIORITY
#define CONFIG_I2C_SS_0_STOP_IRQ	INTEL_QMSI_SS_I2C_80012000_IRQ_STOP
#define CONFIG_I2C_SS_0_STOP_IRQ_PRI	INTEL_QMSI_SS_I2C_80012000_IRQ_STOP_PRIORITY
#define CONFIG_I2C_SS_0_BITRATE		INTEL_QMSI_SS_I2C_80012000_CLOCK_FREQUENCY
#define CONFIG_I2C_SS_1_NAME		INTEL_QMSI_SS_I2C_80012100_LABEL
#define CONFIG_I2C_SS_1_ERR_IRQ		INTEL_QMSI_SS_I2C_80012100_IRQ_ERROR
#define CONFIG_I2C_SS_1_ERR_IRQ_PRI	INTEL_QMSI_SS_I2C_80012100_IRQ_ERROR_PRIORITY
#define CONFIG_I2C_SS_1_RX_IRQ		INTEL_QMSI_SS_I2C_80012100_IRQ_RX
#define CONFIG_I2C_SS_1_RX_IRQ_PRI	INTEL_QMSI_SS_I2C_80012100_IRQ_RX_PRIORITY
#define CONFIG_I2C_SS_1_TX_IRQ		INTEL_QMSI_SS_I2C_80012100_IRQ_TX
#define CONFIG_I2C_SS_1_TX_IRQ_PRI	INTEL_QMSI_SS_I2C_80012100_IRQ_TX_PRIORITY
#define CONFIG_I2C_SS_1_STOP_IRQ	INTEL_QMSI_SS_I2C_80012100_IRQ_STOP
#define CONFIG_I2C_SS_1_STOP_IRQ_PRI	INTEL_QMSI_SS_I2C_80012100_IRQ_STOP_PRIORITY
#define CONFIG_I2C_SS_1_BITRATE		INTEL_QMSI_SS_I2C_80012100_CLOCK_FREQUENCY

#define CONFIG_I2C_0_NAME		INTEL_QMSI_I2C_B0002800_LABEL
#define CONFIG_I2C_0_BITRATE		INTEL_QMSI_I2C_B0002800_CLOCK_FREQUENCY
#define CONFIG_I2C_0_IRQ		INTEL_QMSI_I2C_B0002800_IRQ_0
#define CONFIG_I2C_0_IRQ_PRI		INTEL_QMSI_I2C_B0002800_IRQ_0_PRIORITY
#define CONFIG_I2C_1_NAME		INTEL_QMSI_I2C_B0002C00_LABEL
#define CONFIG_I2C_1_BITRATE		INTEL_QMSI_I2C_B0002C00_CLOCK_FREQUENCY
#define CONFIG_I2C_1_IRQ		INTEL_QMSI_I2C_B0002C00_IRQ_0
#define CONFIG_I2C_1_IRQ_PRI		INTEL_QMSI_I2C_B0002C00_IRQ_0_PRIORITY

#define CONFIG_RTC_0_NAME		INTEL_QMSI_RTC_B0000400_LABEL
#define CONFIG_RTC_0_IRQ		INTEL_QMSI_RTC_B0000400_IRQ_0
#define CONFIG_RTC_0_IRQ_PRI		INTEL_QMSI_RTC_B0000400_IRQ_0_PRIORITY

#define CONFIG_GPIO_QMSI_SS_0_NAME	INTEL_QMSI_SS_GPIO_80017800_LABEL
#define CONFIG_GPIO_QMSI_SS_0_IRQ	INTEL_QMSI_SS_GPIO_80017800_IRQ_0
#define CONFIG_GPIO_QMSI_SS_0_IRQ_PRI	INTEL_QMSI_SS_GPIO_80017800_IRQ_0_PRIORITY

#define CONFIG_GPIO_QMSI_SS_1_NAME	INTEL_QMSI_SS_GPIO_80017900_LABEL
#define CONFIG_GPIO_QMSI_SS_1_IRQ	INTEL_QMSI_SS_GPIO_80017900_IRQ_0
#define CONFIG_GPIO_QMSI_SS_1_IRQ_PRI	INTEL_QMSI_SS_GPIO_80017900_IRQ_0_PRIORITY

#define CONFIG_GPIO_QMSI_0_NAME		INTEL_QMSI_GPIO_B0000C00_LABEL
#define CONFIG_GPIO_QMSI_0_IRQ		INTEL_QMSI_GPIO_B0000C00_IRQ_0
#define CONFIG_GPIO_QMSI_0_IRQ_PRI	INTEL_QMSI_GPIO_B0000C00_IRQ_0_PRIORITY
#define CONFIG_GPIO_QMSI_1_NAME		INTEL_QMSI_GPIO_B0800B00_LABEL
#define CONFIG_GPIO_QMSI_1_IRQ		INTEL_QMSI_GPIO_B0800B00_IRQ_0
#define CONFIG_GPIO_QMSI_1_IRQ_PRI	INTEL_QMSI_GPIO_B0800B00_IRQ_0_PRIORITY

/* End of SoC Level DTS fixup file */