diff --git a/drivers/gpio/gpio_ifx_cat1.c b/drivers/gpio/gpio_ifx_cat1.c
index 29a3079..5cc8981 100644
--- a/drivers/gpio/gpio_ifx_cat1.c
+++ b/drivers/gpio/gpio_ifx_cat1.c
@@ -19,6 +19,7 @@
 #include <zephyr/drivers/gpio/gpio_utils.h>
 #include <zephyr/irq.h>
 
+#include <infineon_kconfig.h>
 #include <cy_gpio.h>
 
 #include <zephyr/logging/log.h>
diff --git a/drivers/pinctrl/pinctrl_ifx_cat1.c b/drivers/pinctrl/pinctrl_ifx_cat1.c
index 87370c1..fe80dc5 100644
--- a/drivers/pinctrl/pinctrl_ifx_cat1.c
+++ b/drivers/pinctrl/pinctrl_ifx_cat1.c
@@ -10,9 +10,11 @@
  */
 
 #include <zephyr/drivers/pinctrl.h>
+
+#include <infineon_kconfig.h>
 #include <cy_gpio.h>
 
-#define GPIO_PORT_OR_NULL(node_id) \
+#define GPIO_PORT_OR_NULL(node_id)                                                                 \
 	COND_CODE_1(DT_NODE_EXISTS(node_id), ((GPIO_PRT_Type *)DT_REG_ADDR(node_id)), (NULL))
 
 /* @brief Array containing pointers to each GPIO port.
@@ -40,40 +42,40 @@
 static uint32_t soc_gpio_get_drv_mode(uint32_t flags)
 {
 	uint32_t drv_mode = CY_GPIO_DM_ANALOG;
-	uint32_t _flags;
+	uint32_t flags_masked;
 
-	_flags = ((flags & SOC_GPIO_FLAGS_MASK) >> SOC_GPIO_FLAGS_POS);
+	flags_masked = ((flags & SOC_GPIO_FLAGS_MASK) >> SOC_GPIO_FLAGS_POS);
 
-	if (_flags & SOC_GPIO_OPENDRAIN) {
+	if (flags_masked & SOC_GPIO_OPENDRAIN) {
 		/* drive_open_drain */
-		drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_OD_DRIVESLOW
+		drv_mode = (flags_masked & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_OD_DRIVESLOW
 							   : CY_GPIO_DM_OD_DRIVESLOW_IN_OFF;
 
-	} else if (_flags & SOC_GPIO_OPENSOURCE) {
+	} else if (flags_masked & SOC_GPIO_OPENSOURCE) {
 		/* drive_open_source */
-		drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_OD_DRIVESHIGH
+		drv_mode = (flags_masked & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_OD_DRIVESHIGH
 							   : CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF;
 
-	} else if (_flags & SOC_GPIO_PUSHPULL) {
+	} else if (flags_masked & SOC_GPIO_PUSHPULL) {
 		/* drive_push_pull */
-		drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_STRONG
+		drv_mode = (flags_masked & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_STRONG
 							   : CY_GPIO_DM_STRONG_IN_OFF;
 
-	} else if ((_flags & SOC_GPIO_PULLUP) && (_flags & SOC_GPIO_PULLDOWN)) {
+	} else if ((flags_masked & SOC_GPIO_PULLUP) && (flags_masked & SOC_GPIO_PULLDOWN)) {
 		/* bias_pull_up and bias_pull_down */
-		drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLUP_DOWN
+		drv_mode = (flags_masked & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLUP_DOWN
 							   : CY_GPIO_DM_PULLUP_DOWN_IN_OFF;
 
-	} else if (_flags & SOC_GPIO_PULLUP) {
+	} else if (flags_masked & SOC_GPIO_PULLUP) {
 		/* bias_pull_up */
-		drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLUP
+		drv_mode = (flags_masked & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLUP
 							   : CY_GPIO_DM_PULLUP_IN_OFF;
 
-	} else if (_flags & SOC_GPIO_PULLDOWN) {
+	} else if (flags_masked & SOC_GPIO_PULLDOWN) {
 		/* bias_pull_down */
-		drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLDOWN
+		drv_mode = (flags_masked & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLDOWN
 							   : CY_GPIO_DM_PULLDOWN_IN_OFF;
-	} else if ((_flags & SOC_GPIO_HIGHZ) | (_flags & SOC_GPIO_INPUTENABLE)) {
+	} else if ((flags_masked & SOC_GPIO_HIGHZ) | (flags_masked & SOC_GPIO_INPUTENABLE)) {
 		/* bias_pull_down */
 		drv_mode = CY_GPIO_DM_HIGHZ;
 	} else {
@@ -83,6 +85,39 @@
 	return drv_mode;
 }
 
+#if defined(CONFIG_SOC_SERIES_PSE84)
+static uint32_t soc_gpio_get_drv_strength(uint32_t flags)
+{
+	uint32_t drv_strength_idx = 0;
+	uint32_t drv_strength = CY_GPIO_DRIVE_1_8;
+	uint32_t flags_masked;
+
+	flags_masked = ((flags & SOC_GPIO_FLAGS_MASK) >> SOC_GPIO_FLAGS_POS);
+	drv_strength_idx = (flags_masked & SOC_GPIO_DRIVESTRENGTH) >> SOC_GPIO_DRIVESTRENGTH_POS;
+
+	switch (drv_strength_idx) {
+	case 0:
+		drv_strength = CY_GPIO_DRIVE_FULL;
+		break;
+	case 1:
+		drv_strength = CY_GPIO_DRIVE_1_2;
+		break;
+	case 2:
+		drv_strength = CY_GPIO_DRIVE_1_4;
+		break;
+	case 3:
+		drv_strength = CY_GPIO_DRIVE_1_8;
+		break;
+
+	default:
+		drv_strength = CY_GPIO_DRIVE_1_8;
+		break;
+	}
+
+	return drv_strength;
+}
+#endif
+
 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
 {
 	ARG_UNUSED(reg);
@@ -94,7 +129,7 @@
 		uint32_t pin_num = CAT1_PINMUX_GET_PIN_NUM(pins[i].pinmux);
 
 		/* Initialize pin */
-#if defined(COMPONENT_SECURE_DEVICE) || defined(CY_PDL_TZ_ENABLED)
+#if defined(CY_PDL_TZ_ENABLED)
 		Cy_GPIO_Pin_SecFastInit(gpio_ports[port_num], pin_num, drv_mode, 1, hsiom);
 #else
 		Cy_GPIO_Pin_FastInit(gpio_ports[port_num], pin_num, drv_mode, 1, hsiom);
@@ -109,9 +144,14 @@
 			Cy_GPIO_Write(gpio_ports[port_num], pin_num, 0);
 			break;
 		default:
-			/* do nothing */
+			/* Do nothing */
 			break;
 		}
+
+#if defined(CONFIG_SOC_SERIES_PSE84)
+		Cy_GPIO_SetDriveSel(gpio_ports[port_num], pin_num,
+				    soc_gpio_get_drv_strength(pins[i].pincfg));
+#endif
 	}
 
 	return 0;
diff --git a/dts/bindings/pinctrl/infineon,cat1-pinctrl.yaml b/dts/bindings/pinctrl/infineon,cat1-pinctrl.yaml
index d2345bd..3c9e896 100644
--- a/dts/bindings/pinctrl/infineon,cat1-pinctrl.yaml
+++ b/dts/bindings/pinctrl/infineon,cat1-pinctrl.yaml
@@ -120,3 +120,12 @@
         Encodes port/pin and alternate function.
       required: true
       type: int
+    drive-strength:
+      type: string
+      enum:
+        - "full"
+        - "half"
+        - "one-fourth"
+        - "one-eighth"
+      description: |
+        Pin output drive strength.